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https://github.com/holub/mame
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Merge pull request #1632 from npwoods/dasmstream_unsp
Changed the UNSP disassembler to use 'std::ostream &' internally
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commit
ea4e761f9b
@ -11,17 +11,6 @@
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#include "emu.h"
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#include <stdarg.h>
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static char *output;
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static void ATTR_PRINTF(1,2) print(const char *fmt, ...)
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{
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va_list vl;
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va_start(vl, fmt);
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vsprintf(output, fmt, vl);
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va_end(vl);
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}
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/*****************************************************************************/
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static const char *reg[] =
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@ -57,20 +46,16 @@ static const char *alu[] =
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#define UNSP_DASM_OK ((OP2X ? 2 : 1) | DASMFLAG_SUPPORTED)
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CPU_DISASSEMBLE( unsp )
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static offs_t internal_disasm_unsp(cpu_device *device, std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, int options)
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{
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uint16_t op = *(uint16_t *)oprom;
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uint16_t imm16 = *(uint16_t *)(oprom + 2);
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op = big_endianize_int16(op);
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imm16 = big_endianize_int16(imm16);
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output = buffer;
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print("<inv>");
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if(OP0 < 0xf && OPA == 0x7 && OP1 < 2)
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{
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print("%s %04x", jmp[OP0], OP1 ? (pc - OPIMM + 1) : (pc + OPIMM + 1));
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util::stream_format(stream, "%s %04x", jmp[OP0], OP1 ? (pc - OPIMM + 1) : (pc + OPIMM + 1));
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return UNSP_DASM_OK;
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}
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@ -78,29 +63,29 @@ CPU_DISASSEMBLE( unsp )
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{
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// ALU, Indexed
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case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x06: case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d:
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print("%s %s, [bp+%02x]", alu[OP0], reg[OPA], OPIMM);
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util::stream_format(stream, "%s %s, [bp+%02x]", alu[OP0], reg[OPA], OPIMM);
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return UNSP_DASM_OK;
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// ALU, Immediate
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case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x16: case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c:
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print("%s %s, %02x", alu[OP0], reg[OPA], OPIMM);
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util::stream_format(stream, "%s %s, %02x", alu[OP0], reg[OPA], OPIMM);
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return UNSP_DASM_OK;
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// Pop / Interrupt return
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case 0x29:
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if(op == 0x9a90)
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{
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print("retf");
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util::stream_format(stream, "retf");
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return UNSP_DASM_OK;
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}
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else if(op == 0x9a98)
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{
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print("reti");
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util::stream_format(stream, "reti");
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return UNSP_DASM_OK;
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}
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else if((OPA + 1) < 8 && ((OPA + OPN) < 8))
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{
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print("pop %s, %s [%s]", reg[OPA+1], reg[OPA+OPN], reg[OPB]);
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util::stream_format(stream, "pop %s, %s [%s]", reg[OPA+1], reg[OPA+OPN], reg[OPB]);
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return UNSP_DASM_OK;
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}
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break;
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@ -109,7 +94,7 @@ CPU_DISASSEMBLE( unsp )
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case 0x2d:
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if((OPA + 1) >= OPN && OPA < (OPN + 7))
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{
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print("push %s, %s [%s]", reg[(OPA+1)-OPN], reg[OPA], reg[OPB]);
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util::stream_format(stream, "push %s, %s [%s]", reg[(OPA+1)-OPN], reg[OPA], reg[OPB]);
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return UNSP_DASM_OK;
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}
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break;
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@ -119,16 +104,16 @@ CPU_DISASSEMBLE( unsp )
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switch(OPN & 3)
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{
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case 0:
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print("%s %s, [%s%s]", alu[OP0], reg[OPA], (OPN & 4) ? "ds:" : "", reg[OPB]);
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util::stream_format(stream, "%s %s, [%s%s]", alu[OP0], reg[OPA], (OPN & 4) ? "ds:" : "", reg[OPB]);
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return UNSP_DASM_OK;
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case 1:
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print("%s %s, [%s%s--]", alu[OP0], reg[OPA], (OPN & 4) ? "ds:" : "", reg[OPB]);
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util::stream_format(stream, "%s %s, [%s%s--]", alu[OP0], reg[OPA], (OPN & 4) ? "ds:" : "", reg[OPB]);
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return UNSP_DASM_OK;
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case 2:
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print("%s %s, [%s%s++]", alu[OP0], reg[OPA], (OPN & 4) ? "ds:" : "", reg[OPB]);
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util::stream_format(stream, "%s %s, [%s%s++]", alu[OP0], reg[OPA], (OPN & 4) ? "ds:" : "", reg[OPB]);
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return UNSP_DASM_OK;
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case 3:
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print("%s %s, [%s++%s]", alu[OP0], reg[OPA], (OPN & 4) ? "ds:" : "", reg[OPB]);
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util::stream_format(stream, "%s %s, [%s++%s]", alu[OP0], reg[OPA], (OPN & 4) ? "ds:" : "", reg[OPB]);
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return UNSP_DASM_OK;
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}
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return UNSP_DASM_OK;
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@ -139,7 +124,7 @@ CPU_DISASSEMBLE( unsp )
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{
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// ALU, Register
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case 0:
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print("%s %s, %s", alu[OP0], reg[OPA], reg[OPB]);
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util::stream_format(stream, "%s %s, %s", alu[OP0], reg[OPA], reg[OPB]);
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return UNSP_DASM_OK;
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// ALU, 16-bit Immediate
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@ -148,12 +133,12 @@ CPU_DISASSEMBLE( unsp )
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{
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if(OP0 != 4 && OP0 != 12)
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{
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print("%s %s, %s, %04x", alu[OP0], reg[OPA], reg[OPB], imm16);
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util::stream_format(stream, "%s %s, %s, %04x", alu[OP0], reg[OPA], reg[OPB], imm16);
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return UNSP_DASM_OK;
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}
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else
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{
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print("%s %s, %04x", alu[OP0], reg[OPB], imm16);
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util::stream_format(stream, "%s %s, %04x", alu[OP0], reg[OPB], imm16);
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return UNSP_DASM_OK;
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}
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}
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@ -161,74 +146,71 @@ CPU_DISASSEMBLE( unsp )
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// ALU, Direct 16
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case 2:
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print("%s %s, [%04x]", alu[OP0], reg[OPA], imm16);
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util::stream_format(stream, "%s %s, [%04x]", alu[OP0], reg[OPA], imm16);
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return UNSP_DASM_OK;
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// ALU, Direct 16
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case 3:
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print("%s [%04x], %s, %s", alu[OP0], imm16, reg[OPA], reg[OPB]);
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util::stream_format(stream, "%s [%04x], %s, %s", alu[OP0], imm16, reg[OPA], reg[OPB]);
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return UNSP_DASM_OK;
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// ALU, Shifted
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default:
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print("%s %s, %s asr %d", alu[OP0], reg[OPA], reg[OPB], (OPN & 3) + 1);
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util::stream_format(stream, "%s %s, %s asr %d", alu[OP0], reg[OPA], reg[OPB], (OPN & 3) + 1);
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return UNSP_DASM_OK;
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}
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case 0x4d:
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if(OPN == 3)
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{
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if(OPA == OPB)
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{
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print("store [%04x], %s", imm16, reg[OPB]);
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}
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}
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if((OPN == 3) && (OPA == OPB))
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util::stream_format(stream, "store [%04x], %s", imm16, reg[OPB]);
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else
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util::stream_format(stream, "<inv>");
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return UNSP_DASM_OK;
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// ALU, Shifted
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case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x56: case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c:
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print("%s %s, %s %s %d", alu[OP0], reg[OPA], reg[OPB], (OPN & 4) ? ">>" : "<<", (OPN & 3) + 1);
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util::stream_format(stream, "%s %s, %s %s %d", alu[OP0], reg[OPA], reg[OPB], (OPN & 4) ? ">>" : "<<", (OPN & 3) + 1);
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return UNSP_DASM_OK;
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// ALU, Rotated
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case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x66: case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c:
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print("%s %s, %s %s %d", alu[OP0], reg[OPA], reg[OPB], (OPN & 4) ? "ror" : "rol", (OPN & 3) + 1);
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util::stream_format(stream, "%s %s, %s %s %d", alu[OP0], reg[OPA], reg[OPB], (OPN & 4) ? "ror" : "rol", (OPN & 3) + 1);
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return UNSP_DASM_OK;
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// ALU, Direct 8
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case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x76: case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c:
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print("%s %s, [%02x]", alu[OP0], reg[OPA], OPIMM);
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util::stream_format(stream, "%s %s, [%02x]", alu[OP0], reg[OPA], OPIMM);
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return UNSP_DASM_OK;
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// Call
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case 0x1f:
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if(OPA == 0)
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{
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print("call %06x", ((OPIMM << 16) | imm16) << 1);
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}
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util::stream_format(stream, "call %06x", ((OPIMM << 16) | imm16) << 1);
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else
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util::stream_format(stream, "<inv>");
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return UNSP_DASM_OK;
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// Far Jump
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case 0x2f: case 0x3f: case 0x6f: case 0x7f:
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if (OPA == 7 && OP1 == 2)
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{
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print("goto %06x", ((OPIMM << 16) | imm16) << 1);
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}
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util::stream_format(stream, "goto %06x", ((OPIMM << 16) | imm16) << 1);
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else
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util::stream_format(stream, "<inv>");
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return UNSP_DASM_OK;
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// Multiply, Unsigned * Signed
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case 0x0f:
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if(OPN == 1 && OPA != 7)
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{
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print("mulus %s, %s", reg[OPA], reg[OPB]);
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}
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util::stream_format(stream, "mulus %s, %s", reg[OPA], reg[OPB]);
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else
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util::stream_format(stream, "<inv>");
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return UNSP_DASM_OK;
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// Multiply, Signed * Signed
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case 0x4f:
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if(OPN == 1 && OPA != 7)
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{
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print("mulss %s, %s", reg[OPA], reg[OPB]);
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}
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util::stream_format(stream, "mulss %s, %s", reg[OPA], reg[OPB]);
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else
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util::stream_format(stream, "<inv>");
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return UNSP_DASM_OK;
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// Interrupt flags
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@ -238,35 +220,51 @@ CPU_DISASSEMBLE( unsp )
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switch(OPIMM)
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{
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case 0:
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print("int off");
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util::stream_format(stream, "int off");
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break;
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case 1:
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print("int irq");
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util::stream_format(stream, "int irq");
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break;
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case 2:
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print("int fiq");
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util::stream_format(stream, "int fiq");
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break;
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case 3:
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print("int irq,fiq");
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util::stream_format(stream, "int irq,fiq");
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break;
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case 8:
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print("irq off");
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util::stream_format(stream, "irq off");
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break;
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case 9:
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print("irq on");
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util::stream_format(stream, "irq on");
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break;
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case 12:
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print("fiq off");
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util::stream_format(stream, "fiq off");
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break;
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case 14:
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print("fiq on");
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util::stream_format(stream, "fiq on");
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break;
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case 37:
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print("nop");
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util::stream_format(stream, "nop");
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break;
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default:
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util::stream_format(stream, "<inv>");
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break;
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}
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}
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else
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util::stream_format(stream, "<inv>");
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return UNSP_DASM_OK;
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}
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util::stream_format(stream, "<inv>");
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return UNSP_DASM_OK;
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}
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CPU_DISASSEMBLE(unsp)
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{
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std::ostringstream stream;
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offs_t result = internal_disasm_unsp(device, stream, pc, oprom, opram, options);
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std::string stream_str = stream.str();
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strcpy(buffer, stream_str.c_str());
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return result;
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}
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