AICA: Hooked up AICA-to-SH-4 irqs [Angelo Salese]

This commit is contained in:
Angelo Salese 2013-08-29 14:06:10 +00:00
parent 5f680fe1d0
commit eaf78dc272
7 changed files with 90 additions and 20 deletions

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@ -172,6 +172,7 @@ struct aica_state
UINT32 AICARAM_LENGTH, RAM_MASK, RAM_MASK16; UINT32 AICARAM_LENGTH, RAM_MASK, RAM_MASK16;
char Master; char Master;
devcb_resolved_write_line IntARMCB; devcb_resolved_write_line IntARMCB;
devcb_resolved_write_line IntSH4CB;
sound_stream * stream; sound_stream * stream;
INT32 *buffertmpl, *buffertmpr; INT32 *buffertmpl, *buffertmpr;
@ -190,6 +191,8 @@ struct aica_state
int TimPris[3]; int TimPris[3];
int TimCnt[3]; int TimCnt[3];
UINT16 mcieb, mcipd;
// timers // timers
emu_timer *timerA, *timerB, *timerC; emu_timer *timerA, *timerB, *timerC;
@ -288,16 +291,28 @@ static void CheckPendingIRQ(aica_state *AICA)
} }
} }
static void CheckPendingIRQ_SH4(aica_state *AICA)
{
if(AICA->mcipd & AICA->mcieb)
AICA->IntSH4CB(1);
if((AICA->mcipd & AICA->mcieb) == 0)
AICA->IntSH4CB(0);
}
static TIMER_CALLBACK( timerA_cb ) static TIMER_CALLBACK( timerA_cb )
{ {
aica_state *AICA = (aica_state *)ptr; aica_state *AICA = (aica_state *)ptr;
AICA->TimCnt[0] = 0xFFFF; AICA->TimCnt[0] = 0xFFFF;
AICA->udata.data[0xa0/2]|=0x40; AICA->udata.data[0xa0/2]|=0x40;
AICA->mcipd |= 0x40;
AICA->udata.data[0x90/2]&=0xff00; AICA->udata.data[0x90/2]&=0xff00;
AICA->udata.data[0x90/2]|=AICA->TimCnt[0]>>8; AICA->udata.data[0x90/2]|=AICA->TimCnt[0]>>8;
CheckPendingIRQ(AICA); CheckPendingIRQ(AICA);
CheckPendingIRQ_SH4(AICA);
} }
static TIMER_CALLBACK( timerB_cb ) static TIMER_CALLBACK( timerB_cb )
@ -306,10 +321,12 @@ static TIMER_CALLBACK( timerB_cb )
AICA->TimCnt[1] = 0xFFFF; AICA->TimCnt[1] = 0xFFFF;
AICA->udata.data[0xa0/2]|=0x80; AICA->udata.data[0xa0/2]|=0x80;
AICA->mcipd |= 0x80;
AICA->udata.data[0x94/2]&=0xff00; AICA->udata.data[0x94/2]&=0xff00;
AICA->udata.data[0x94/2]|=AICA->TimCnt[1]>>8; AICA->udata.data[0x94/2]|=AICA->TimCnt[1]>>8;
CheckPendingIRQ(AICA); CheckPendingIRQ(AICA);
CheckPendingIRQ_SH4(AICA);
} }
static TIMER_CALLBACK( timerC_cb ) static TIMER_CALLBACK( timerC_cb )
@ -318,10 +335,12 @@ static TIMER_CALLBACK( timerC_cb )
AICA->TimCnt[2] = 0xFFFF; AICA->TimCnt[2] = 0xFFFF;
AICA->udata.data[0xa0/2]|=0x100; AICA->udata.data[0xa0/2]|=0x100;
AICA->mcipd |= 0x100;
AICA->udata.data[0x98/2]&=0xff00; AICA->udata.data[0x98/2]&=0xff00;
AICA->udata.data[0x98/2]|=AICA->TimCnt[2]>>8; AICA->udata.data[0x98/2]|=AICA->TimCnt[2]>>8;
CheckPendingIRQ(AICA); CheckPendingIRQ(AICA);
CheckPendingIRQ_SH4(AICA);
} }
static int Get_AR(aica_state *AICA,int base,int R) static int Get_AR(aica_state *AICA,int base,int R)
@ -802,6 +821,13 @@ static void AICA_UpdateReg(aica_state *AICA, address_space &space, int reg)
} }
} }
break; break;
case 0x9c: //SCIEB
case 0x9d:
if(AICA->udata.data[0x9c/2] & 0x631)
popmessage("AICA: SCIEB enabled %04x, contact MAME/MESSdev",AICA->udata.data[0x9c/2]);
break;
case 0xa4: //SCIRE case 0xa4: //SCIRE
case 0xa5: case 0xa5:
@ -840,14 +866,25 @@ static void AICA_UpdateReg(aica_state *AICA, address_space &space, int reg)
} }
break; break;
case 0xb4: case 0xb4: //MCIEB
case 0xb5: case 0xb5:
case 0xb6: if(AICA->udata.data[0xb4/2] & 0x7df)
case 0xb7: popmessage("AICA: MCIEB enabled %04x, contact MAME/MESSdev",AICA->udata.data[0xb4/2]);
if (MCIEB(AICA) & 0x20) AICA->mcieb = AICA->udata.data[0xb4/2];
{ CheckPendingIRQ_SH4(AICA);
logerror("AICA: Interrupt requested on SH-4!\n"); break;
}
case 0xb8:
case 0xb9:
if(AICA->udata.data[0xb8/2] & 0x20)
AICA->mcipd |= 0x20;
CheckPendingIRQ_SH4(AICA);
break;
case 0xbc:
case 0xbd:
AICA->mcipd &= ~AICA->udata.data[0xbc/2];
CheckPendingIRQ_SH4(AICA);
break; break;
} }
} }
@ -924,6 +961,10 @@ static void AICA_UpdateRegR(aica_state *AICA, address_space &space, int reg)
AICA->udata.data[0x14/2] = CA; AICA->udata.data[0x14/2] = CA;
} }
break; break;
case 0xb8:
case 0xb9:
AICA->udata.data[0xb8/2] = AICA->mcipd;
break;
} }
} }
@ -1371,8 +1412,9 @@ static void aica_exec_dma(aica_state *aica,address_space &space)
/* Job done, clear DEXE */ /* Job done, clear DEXE */
aica->udata.data[0x8c/2] &= ~1; aica->udata.data[0x8c/2] &= ~1;
/* request a dma end irq (TBD) */ /* request a dma end irq */
// ... aica->mcipd |= 0x10;
CheckPendingIRQ_SH4(aica);
} }
#ifdef UNUSED_FUNCTION #ifdef UNUSED_FUNCTION
@ -1406,6 +1448,7 @@ static DEVICE_START( aica )
// set up the IRQ callbacks // set up the IRQ callbacks
{ {
AICA->IntARMCB.resolve(intf->irq_callback,*device); AICA->IntARMCB.resolve(intf->irq_callback,*device);
AICA->IntSH4CB.resolve(intf->master_irq_callback,*device);
AICA->stream = device->machine().sound().stream_alloc(*device, 0, 2, 44100, AICA, AICA_Update); AICA->stream = device->machine().sound().stream_alloc(*device, 0, 2, 44100, AICA, AICA_Update);
} }

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@ -12,6 +12,7 @@ struct aica_interface
int master; int master;
int roffset; /* offset in the region */ int roffset; /* offset in the region */
devcb_write_line irq_callback; /* irq callback */ devcb_write_line irq_callback; /* irq callback */
devcb_write_line master_irq_callback;
}; };
void aica_set_ram_base(device_t *device, void *base, int size); void aica_set_ram_base(device_t *device, void *base, int size);

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@ -1799,12 +1799,22 @@ WRITE_LINE_MEMBER(naomi_state::aica_irq)
m_soundcpu->set_input_line(ARM7_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE); m_soundcpu->set_input_line(ARM7_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
} }
WRITE_LINE_MEMBER(naomi_state::sh4_aica_irq)
{
if(state)
dc_sysctrl_regs[SB_ISTEXT] |= IST_EXT_AICA;
else
dc_sysctrl_regs[SB_ISTEXT] &= ~IST_EXT_AICA;
dc_update_interrupt_status();
}
static const aica_interface aica_config = static const aica_interface aica_config =
{ {
TRUE, TRUE,
0, 0,
DEVCB_DRIVER_LINE_MEMBER(naomi_state,aica_irq) DEVCB_DRIVER_LINE_MEMBER(naomi_state,aica_irq),
DEVCB_DRIVER_LINE_MEMBER(naomi_state,sh4_aica_irq)
}; };

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@ -32,6 +32,7 @@ class naomi_state : public dc_state
optional_device<eeprom_serial_93cxx_device> m_eeprom; optional_device<eeprom_serial_93cxx_device> m_eeprom;
DECLARE_WRITE_LINE_MEMBER(aica_irq); DECLARE_WRITE_LINE_MEMBER(aica_irq);
DECLARE_WRITE_LINE_MEMBER(sh4_aica_irq);
DECLARE_MACHINE_RESET(naomi); DECLARE_MACHINE_RESET(naomi);
DECLARE_DRIVER_INIT(atomiswave); DECLARE_DRIVER_INIT(atomiswave);
DECLARE_DRIVER_INIT(naomigd); DECLARE_DRIVER_INIT(naomigd);

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@ -1426,14 +1426,17 @@ WRITE32_MEMBER( powervr2_device::ta_yuv_tex_ctrl_w )
logerror("%s: ta_yuv_tex_ctrl = %08x\n", tag(), ta_yuv_tex_ctrl); logerror("%s: ta_yuv_tex_ctrl = %08x\n", tag(), ta_yuv_tex_ctrl);
} }
#include "debugger.h"
/* TODO */ /* TODO */
READ32_MEMBER( powervr2_device::ta_yuv_tex_cnt_r ) READ32_MEMBER( powervr2_device::ta_yuv_tex_cnt_r )
{ {
debugger_break(machine());
return ta_yuv_tex_cnt; return ta_yuv_tex_cnt;
} }
WRITE32_MEMBER( powervr2_device::ta_yuv_tex_cnt_w ) WRITE32_MEMBER( powervr2_device::ta_yuv_tex_cnt_w )
{ {
debugger_break(machine());
COMBINE_DATA(&ta_yuv_tex_cnt); COMBINE_DATA(&ta_yuv_tex_cnt);
} }

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@ -115,7 +115,7 @@
TA_IPINT (0109): TA_IPINT (0109):
NG -> TA: Illegal parameter (error) NG -> TA: Illegal parameter (error)
YUV Converter (0201): YUV Converter (0201):
NG (I think) ok
DDT i/f TEST: DDT i/f TEST:
Sort, Normal DMA (1) (0101) Sort, Normal DMA (1) (0101)
hangs (wants Sort DMA irq, of course) hangs (wants Sort DMA irq, of course)
@ -148,11 +148,11 @@
ok ok
Register (02xx) Register (02xx)
CH Data (0201) CH Data (0201)
NG ok
EXT Input (0202) EXT Input (0202)
ok ok
DSP Data (0203) DSP Data (0203)
NG NG (ADDR=0xa0704000 W=0xff R=0x00)
S_Clock (03xx) S_Clock (03xx)
50MSEC (0301) 50MSEC (0301)
NG NG
@ -188,19 +188,19 @@
ok ok
Interrupt (06xx) Interrupt (06xx)
Sampling clock (0601) Sampling clock (0601)
NG NG (irq 0x400)
Timer A (0602) Timer A (0602)
NG randomly NG/ok
Timer B (0603) Timer B (0603)
NG ok
Timer C (0604) Timer C (0604)
NG ok
DMA End (0605) DMA End (0605)
NG ok
Midi Out (0606) Midi Out (0606)
NG NG
Main CPU (0607) Main CPU (0607)
NG ok
RTC (07xx) RTC (07xx)
Write Protect (0701) Write Protect (0701)
ok ok
@ -570,11 +570,22 @@ WRITE_LINE_MEMBER(dc_cons_state::aica_irq)
m_soundcpu->set_input_line(ARM7_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE); m_soundcpu->set_input_line(ARM7_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
} }
WRITE_LINE_MEMBER(dc_cons_state::sh4_aica_irq)
{
if(state)
dc_sysctrl_regs[SB_ISTEXT] |= IST_EXT_AICA;
else
dc_sysctrl_regs[SB_ISTEXT] &= ~IST_EXT_AICA;
dc_update_interrupt_status();
}
static const aica_interface dc_aica_interface = static const aica_interface dc_aica_interface =
{ {
TRUE, TRUE,
0, 0,
DEVCB_DRIVER_LINE_MEMBER(dc_cons_state,aica_irq) DEVCB_DRIVER_LINE_MEMBER(dc_cons_state,aica_irq),
DEVCB_DRIVER_LINE_MEMBER(dc_cons_state,sh4_aica_irq)
}; };
static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, CPU_CLOCK }; static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, CPU_CLOCK };

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@ -25,6 +25,7 @@ public:
DECLARE_READ64_MEMBER(dc_arm_r); DECLARE_READ64_MEMBER(dc_arm_r);
DECLARE_WRITE64_MEMBER(dc_arm_w); DECLARE_WRITE64_MEMBER(dc_arm_w);
DECLARE_WRITE_LINE_MEMBER(aica_irq); DECLARE_WRITE_LINE_MEMBER(aica_irq);
DECLARE_WRITE_LINE_MEMBER(sh4_aica_irq);
void gdrom_raise_irq(); void gdrom_raise_irq();
void gdrom_set_status(UINT8 flag,bool state); void gdrom_set_status(UINT8 flag,bool state);
void gdrom_set_error(UINT8 flag,bool state); void gdrom_set_error(UINT8 flag,bool state);