mirror of
https://github.com/holub/mame
synced 2025-05-04 21:43:05 +03:00
replace some space.device() calls (nw)
This commit is contained in:
parent
64385b268b
commit
eb746cb7d8
@ -516,9 +516,9 @@ ADDRESS_MAP_END
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READ16_MEMBER(namcos11_state::c76_speedup_r)
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{
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if ((space.device().safe_pc() == 0xc153) && (!(m_su_83 & 0xff00)))
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if ((m_mcu->pc() == 0xc153) && (!(m_su_83 & 0xff00)))
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{
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space.device().execute().spin_until_interrupt();
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m_mcu->spin_until_interrupt();
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}
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return m_su_83;
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@ -5444,9 +5444,9 @@ ROM_END
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// for MCU BIOS v1.41
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READ16_MEMBER(namcos22_state::mcu141_speedup_r)
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{
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if ((space.device().safe_pc() == 0xc12d) && (!(m_su_82 & 0xff00)))
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if ((m_mcu->pc() == 0xc12d) && (!(m_su_82 & 0xff00)))
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{
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space.device().execute().spin_until_interrupt();
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m_mcu->spin_until_interrupt();
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}
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return m_su_82;
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@ -5460,9 +5460,9 @@ WRITE16_MEMBER(namcos22_state::mcu_speedup_w)
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// for MCU BIOS v1.20/v1.30
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READ16_MEMBER(namcos22_state::mcu130_speedup_r)
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{
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if ((space.device().safe_pc() == 0xc12a) && (!(m_su_82 & 0xff00)))
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if ((m_mcu->pc() == 0xc12a) && (!(m_su_82 & 0xff00)))
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{
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space.device().execute().spin_until_interrupt();
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m_mcu->spin_until_interrupt();
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}
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return m_su_82;
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@ -5471,9 +5471,9 @@ READ16_MEMBER(namcos22_state::mcu130_speedup_r)
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// for NSTX7702 v1.00 (C74)
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READ16_MEMBER(namcos22_state::mcuc74_speedup_r)
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{
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if (((space.device().safe_pc() == 0xc0df) || (space.device().safe_pc() == 0xc101)) && (!(m_su_82 & 0xff00)))
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if (((m_mcu->pc() == 0xc0df) || (m_mcu->pc() == 0xc101)) && (!(m_su_82 & 0xff00)))
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{
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space.device().execute().spin_until_interrupt();
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m_mcu->spin_until_interrupt();
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}
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return m_su_82;
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@ -1997,7 +1997,7 @@ READ32_MEMBER(namcos23_state::c435_r)
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return 1; // Busy flag
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}
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logerror("c435_r %02x @ %08x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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logerror("c435_r %02x @ %08x (%08x, %08x)\n", offset, mem_mask, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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return 0;
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}
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@ -2015,7 +2015,7 @@ WRITE32_MEMBER(namcos23_state::c435_w)
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c435_dma(space, m_c435_address, m_c435_size);
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break;
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default:
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logerror("c435_w %02x, %08x @ %08x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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logerror("c435_w %02x, %08x @ %08x (%08x, %08x)\n", offset, data, mem_mask, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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break;
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}
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}
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@ -2492,7 +2492,7 @@ READ16_MEMBER(namcos23_state::c417_r)
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case 1:
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return m_c417.adr;
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case 4:
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//logerror("c417_r %04x = %04x (%08x, %08x)\n", c417.adr, c417.ram[c417.adr], space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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//logerror("c417_r %04x = %04x (%08x, %08x)\n", c417.adr, c417.ram[c417.adr], m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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return m_c417.ram[m_c417.adr];
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case 5:
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if(m_c417.pointrom_adr >= m_ptrom_limit)
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@ -2504,7 +2504,7 @@ READ16_MEMBER(namcos23_state::c417_r)
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return m_ptrom[m_c417.pointrom_adr];
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}
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logerror("c417_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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logerror("c417_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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return 0;
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}
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@ -2524,7 +2524,7 @@ WRITE16_MEMBER(namcos23_state::c417_w)
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m_c417.pointrom_adr = 0;
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break;
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case 4:
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//logerror("c417_w %04x = %04x (%08x, %08x)\n", m_c417.adr, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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//logerror("c417_w %04x = %04x (%08x, %08x)\n", m_c417.adr, data, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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COMBINE_DATA(m_c417.ram + m_c417.adr);
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break;
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case 7:
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@ -2532,7 +2532,7 @@ WRITE16_MEMBER(namcos23_state::c417_w)
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update_main_interrupts(m_main_irqcause & ~MAIN_C435_IRQ);
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break;
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default:
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logerror("c417_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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logerror("c417_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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break;
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}
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}
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@ -2543,7 +2543,7 @@ WRITE16_MEMBER(namcos23_state::c417_w)
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READ16_MEMBER(namcos23_state::c412_ram_r)
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{
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// logerror("c412_ram_r %06x (%08x, %08x)\n", offset, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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// logerror("c412_ram_r %06x (%08x, %08x)\n", offset, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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if(offset < 0x100000)
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return m_c412.sdram_a[offset & 0xfffff];
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else if(offset < 0x200000)
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@ -2558,7 +2558,7 @@ READ16_MEMBER(namcos23_state::c412_ram_r)
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WRITE16_MEMBER(namcos23_state::c412_ram_w)
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{
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// logerror("c412_ram_w %06x = %04x (%08x, %08x)\n", offset, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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// logerror("c412_ram_w %06x = %04x (%08x, %08x)\n", offset, data, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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if(offset < 0x100000)
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COMBINE_DATA(m_c412.sdram_a + (offset & 0xfffff));
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else if(offset < 0x200000)
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@ -2587,7 +2587,7 @@ READ16_MEMBER(namcos23_state::c412_r)
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return m_c412.status_c;
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}
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logerror("c412_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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logerror("c412_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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return 0;
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}
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@ -2609,7 +2609,7 @@ WRITE16_MEMBER(namcos23_state::c412_w)
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m_c412.adr += 2;
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break;
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default:
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logerror("c412_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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logerror("c412_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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break;
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}
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}
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@ -2620,7 +2620,7 @@ WRITE16_MEMBER(namcos23_state::c412_w)
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READ16_MEMBER(namcos23_state::c421_ram_r)
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{
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// logerror("c421_ram_r %06x (%08x, %08x)\n", offset, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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// logerror("c421_ram_r %06x (%08x, %08x)\n", offset, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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if(offset < 0x40000)
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return m_c421.dram_a[offset & 0x3ffff];
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else if(offset < 0x80000)
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@ -2633,7 +2633,7 @@ READ16_MEMBER(namcos23_state::c421_ram_r)
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WRITE16_MEMBER(namcos23_state::c421_ram_w)
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{
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// logerror("c421_ram_w %06x = %04x (%08x, %08x)\n", offset, data, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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// logerror("c421_ram_w %06x = %04x (%08x, %08x)\n", offset, data, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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if(offset < 0x40000)
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COMBINE_DATA(m_c421.dram_a + (offset & 0x3ffff));
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else if(offset < 0x80000)
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@ -2654,7 +2654,7 @@ READ16_MEMBER(namcos23_state::c421_r)
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return m_c421.adr;
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}
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logerror("c421_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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logerror("c421_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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return 0;
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}
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@ -2672,7 +2672,7 @@ WRITE16_MEMBER(namcos23_state::c421_w)
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m_c421.adr = (data & mem_mask) | (m_c421.adr & (0xffffffff ^ mem_mask));
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break;
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default:
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logerror("c421_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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logerror("c421_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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break;
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}
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}
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@ -2743,7 +2743,7 @@ WRITE16_MEMBER(namcos23_state::c361_w)
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break;
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default:
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logerror("c361_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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logerror("c361_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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break;
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}
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}
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@ -2761,7 +2761,7 @@ READ16_MEMBER(namcos23_state::c361_r)
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return m_screen->vblank() ? 1 : 0;
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}
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logerror("c361_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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logerror("c361_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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return 0xffff;
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}
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@ -2793,11 +2793,11 @@ WRITE16_MEMBER(namcos23_state::ctl_w)
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case 6: // gmen wars spams this heavily with 0 prior to starting the GMEN board test
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if(data != 0)
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logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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break;
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default:
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logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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break;
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}
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}
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@ -2815,7 +2815,7 @@ READ16_MEMBER(namcos23_state::ctl_r)
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}
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}
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logerror("ctl_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
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logerror("ctl_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
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return 0xffff;
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}
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@ -9518,14 +9518,14 @@ DRIVER_INIT_MEMBER(atomiswave_state,atomiswave)
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READ64_MEMBER(atomiswave_state::xtrmhnt2_hack_r)
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{
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// disable ALL.Net board check
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if (space.device().safe_pc() == 0xc03cb30)
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if (m_maincpu->pc() == 0xc03cb30)
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{
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dc_ram[0x357fe/8] |= (uint64_t)0x200 << 48;
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dc_ram[0x358e2/8] |= (uint64_t)0x200 << 16;
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dc_ram[0x38bb2/8] |= (uint64_t)0x200 << 16;
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dc_ram[0x38bee/8] |= (uint64_t)0x200 << 48;
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}
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if (space.device().safe_pc() == 0xc108240)
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if (m_maincpu->pc() == 0xc108240)
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dc_ram[0x9acc8/8] = (dc_ram[0x9acc8/8] & 0xffffffffffff0000U) | (uint64_t)0x0009;
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return 0;
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}
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@ -123,8 +123,8 @@ READ8_MEMBER(rmhaihai_state::keyboard_r)
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{
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static const char *const keynames[] = { "KEY0", "KEY1" };
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logerror("%04x: keyboard_r\n",space.device().safe_pc());
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switch(space.device().safe_pc())
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logerror("%04x: keyboard_r\n",m_maincpu->pc());
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switch(m_maincpu->pc())
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{
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/* read keyboard */
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case 0x0280:
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@ -173,7 +173,7 @@ READ8_MEMBER(rmhaihai_state::keyboard_r)
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WRITE8_MEMBER(rmhaihai_state::keyboard_w)
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{
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logerror("%04x: keyboard_w %02x\n",space.device().safe_pc(),data);
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logerror("%04x: keyboard_w %02x\n",m_maincpu->pc(),data);
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m_keyboard_cmd = data;
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}
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@ -450,7 +450,7 @@ READ8_MEMBER(witch_state::prot_read_700x)
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Otherwise later in game some I/O (controls) reads are skipped.
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*/
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switch(space.device().safe_pc())
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switch(m_subcpu->pc())
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{
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case 0x23f:
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case 0x246:
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@ -1697,7 +1697,7 @@ READ8_MEMBER( x1_state::x1_io_r )
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else if(offset >= 0x4000 && offset <= 0xffff) { return m_gfx_bitmap_ram[offset-0x4000+(m_scrn_reg.gfx_bank*0xc000)]; }
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else
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{
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//logerror("(PC=%06x) Read i/o address %04x\n",space.device().safe_pc(),offset);
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//logerror("(PC=%06x) Read i/o address %04x\n",m_maincpu->pc(),offset);
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}
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return 0xff;
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}
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@ -1740,7 +1740,7 @@ WRITE8_MEMBER( x1_state::x1_io_w )
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else if(offset >= 0x4000 && offset <= 0xffff) { m_gfx_bitmap_ram[offset-0x4000+(m_scrn_reg.gfx_bank*0xc000)] = data; }
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else
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{
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//logerror("(PC=%06x) Write %02x at i/o address %04x\n",space.device().safe_pc(),data,offset);
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//logerror("(PC=%06x) Write %02x at i/o address %04x\n",m_maincpu->pc(),data,offset);
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}
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}
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@ -1787,7 +1787,7 @@ READ8_MEMBER( x1_state::x1turbo_io_r )
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else if(offset >= 0x4000 && offset <= 0xffff) { return m_gfx_bitmap_ram[offset-0x4000+(m_scrn_reg.gfx_bank*0xc000)]; }
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else
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{
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//logerror("(PC=%06x) Read i/o address %04x\n",space.device().safe_pc(),offset);
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//logerror("(PC=%06x) Read i/o address %04x\n",m_maincpu->pc(),offset);
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}
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return 0xff;
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}
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@ -1843,7 +1843,7 @@ WRITE8_MEMBER( x1_state::x1turbo_io_w )
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else if(offset >= 0x4000 && offset <= 0xffff) { m_gfx_bitmap_ram[offset-0x4000+(m_scrn_reg.gfx_bank*0xc000)] = data; }
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else
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{
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//logerror("(PC=%06x) Write %02x at i/o address %04x\n",space.device().safe_pc(),data,offset);
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//logerror("(PC=%06x) Write %02x at i/o address %04x\n",m_maincpu->pc(),data,offset);
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}
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}
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@ -829,7 +829,7 @@ WRITE16_MEMBER(x68k_state::x68k_sysport_w)
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COMBINE_DATA(&m_sysport.sram_writeprotect);
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break;
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default:
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// logerror("SYS: [%08x] Wrote %04x to invalid or unimplemented system port %04x\n",space.device().safe_pc(),data,offset);
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// logerror("SYS: [%08x] Wrote %04x to invalid or unimplemented system port %04x\n",m_maincpu->pc(),data,offset);
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break;
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}
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}
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@ -224,7 +224,7 @@ WRITE16_MEMBER(xexex_state::spriteram_mirror_w)
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READ16_MEMBER(xexex_state::xexex_waitskip_r)
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{
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if (space.device().safe_pc() == 0x1158)
|
||||
if (m_maincpu->pc() == 0x1158)
|
||||
{
|
||||
space.device().execute().spin_until_trigger(m_resume_trigger);
|
||||
m_suspension_active = 1;
|
||||
|
@ -36,7 +36,7 @@ likewise a 2 screen game
|
||||
|
||||
WRITE16_MEMBER(xmen_state::eeprom_w)
|
||||
{
|
||||
logerror("%06x: write %04x to 108000\n",space.device().safe_pc(),data);
|
||||
logerror("%06x: write %04x to 108000\n", m_maincpu->pc(),data);
|
||||
if (ACCESSING_BITS_0_7)
|
||||
{
|
||||
/* bit 0 = coin counter */
|
||||
|
@ -86,7 +86,7 @@ void xyonix_state::handle_coins(int coin)
|
||||
|
||||
READ8_MEMBER(xyonix_state::io_r)
|
||||
{
|
||||
int regPC = space.device().safe_pc();
|
||||
int regPC = m_maincpu->pc();
|
||||
|
||||
if (regPC == 0x27ba)
|
||||
return 0x88;
|
||||
@ -137,7 +137,7 @@ READ8_MEMBER(xyonix_state::io_r)
|
||||
|
||||
WRITE8_MEMBER(xyonix_state::io_w)
|
||||
{
|
||||
//logerror ("xyonix_port_e0_w %02x - PC = %04x\n", data, space.device().safe_pc());
|
||||
//logerror ("xyonix_port_e0_w %02x - PC = %04x\n", data, m_maincpu->pc());
|
||||
m_e0_data = data;
|
||||
}
|
||||
|
||||
|
@ -53,7 +53,7 @@ WRITE8_MEMBER(yunsung8_state::bankswitch_w)
|
||||
membank("mainbank")->set_entry(data & 0x07);
|
||||
|
||||
if (data & ~0x37)
|
||||
logerror("CPU #0 - PC %04X: Bank %02X\n", space.device().safe_pc(), data);
|
||||
logerror("CPU #0 - PC %04X: Bank %02X\n", m_maincpu->pc(), data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(yunsung8_state::sound_command_r)
|
||||
|
@ -1647,7 +1647,7 @@ WRITE16_MEMBER(zn_state::bam2_mcu_w)
|
||||
|
||||
case 1:
|
||||
m_bam2_mcu_command = data;
|
||||
logerror("MCU command: %04x (PC %08x)\n", m_bam2_mcu_command, space.device().safe_pc());
|
||||
logerror("MCU command: %04x (PC %08x)\n", m_bam2_mcu_command, m_maincpu->pc());
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -1657,11 +1657,11 @@ READ16_MEMBER(zn_state::bam2_mcu_r)
|
||||
switch (offset)
|
||||
{
|
||||
case 0:
|
||||
logerror("MCU port 0 read @ PC %08x mask %08x\n", space.device().safe_pc(), mem_mask);
|
||||
logerror("MCU port 0 read @ PC %08x mask %08x\n", m_maincpu->pc(), mem_mask);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
logerror("MCU status read @ PC %08x mask %08x\n", space.device().safe_pc(), mem_mask);
|
||||
logerror("MCU status read @ PC %08x mask %08x\n", m_maincpu->pc(), mem_mask);
|
||||
|
||||
switch (m_bam2_mcu_command)
|
||||
{
|
||||
|
Loading…
Reference in New Issue
Block a user