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z80dart: Refactored dart_channel to be of device_t kin. (nw)

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This commit is contained in:
Curt Coder 2013-05-28 11:18:50 +00:00
parent c1eb234dc2
commit ebccb44079
6 changed files with 630 additions and 544 deletions
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589
src/emu/machine/z80dart.c
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File diff suppressed because it is too large Load Diff

479
src/emu/machine/z80dart.h
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@ -1,14 +1,58 @@
/*************************************************************************** /***************************************************************************
Z80-DART Dual Asynchronous Receiver/Transmitter emulation
Z80-SIO/0/1/2/3/4 Serial Input/Output Controller emulation
Intel 8274 Multi-Protocol Serial Controller emulation Intel 8274 Multi-Protocol Serial Controller emulation
NEC uPD7201 Multiprotocol Serial Communications Controller emulation NEC uPD7201 Multiprotocol Serial Communications Controller emulation
Z80-DART Dual Asynchronous Receiver/Transmitter emulation
Z80-SIO/0/1/2/3/4 Serial Input/Output Controller emulation
Copyright (c) 2008, The MESS Team. Copyright (c) 2008, The MESS Team.
Visit http://mamedev.org for licensing and usage restrictions. Visit http://mamedev.org for licensing and usage restrictions.
**************************************************************************** ****************************************************************************
_____ _____
CLK 1 |* \_/ | 40 Vcc
_RESET 2 | | 39 _CTSA
_CDA 3 | | 38 _RTSA
_RxCB 4 | | 37 TxDA
_CDB 5 | | 36 _TxCA
_CTSB 6 | | 35 _RxCA
_TxCB 7 | | 34 RxDA
TxDB 8 | | 33 _SYNDETA
RxDB 9 | | 32 RDYA/RxDRQA
_RTSB/_SYNDETB 10 | I8274 | 31 _DTRA
RDYB/_TxDRQA 11 | | 30 _IPO/TxDRQB
D7 12 | | 29 _IPI/RxDRQB
D6 13 | | 28 _INT
D5 14 | | 27 _INTA
D4 15 | | 26 _DTRB
D3 16 | | 25 A0
D2 17 | | 24 A1
D1 18 | | 23 _CS
D0 19 | | 22 _RD
Vss 20 |_____________| 21 _WR
_____ _____
CLK 1 |* \_/ | 40 Vcc
_RESET 2 | | 39 _CTSA
_DCDA 3 | | 38 _RTSA
_RxCB 4 | | 37 TxDA
_DCDB 5 | | 36 _TxCA
_CTSB 6 | | 35 _RxCA
_TxCB 7 | | 34 RxDA
TxDB 8 | | 33 _SYNCA
RxDB 9 | | 32 _WAITA/DRQRxA
_RTSB/_SYNCB 10 | UPD7201 | 31 _DTRA/_HAO
_WAITB/_DRQTxA 11 | | 30 _PRO/DRQTxB
D7 12 | | 29 _PRI/DRQRxB
D6 13 | | 28 _INT
D5 14 | | 27 _INTAK
D4 15 | | 26 _DTRB/_HAI
D3 16 | | 25 B/_A
D2 17 | | 24 C/_D
D1 18 | | 23 _CS
D0 19 | | 22 _RD
Vss 20 |_____________| 21 _WR
_____ _____ _____ _____
D1 1 |* \_/ | 40 D0 D1 1 |* \_/ | 40 D0
D3 2 | | 39 D2 D3 2 | | 39 D2
@ -97,50 +141,6 @@
_DCDA 19 | | 22 _DCDB _DCDA 19 | | 22 _DCDB
CLK 20 |_____________| 21 _RESET CLK 20 |_____________| 21 _RESET
_____ _____
CLK 1 |* \_/ | 40 Vcc
_RESET 2 | | 39 _CTSA
_CDA 3 | | 38 _RTSA
_RxCB 4 | | 37 TxDA
_CDB 5 | | 36 _TxCA
_CTSB 6 | | 35 _RxCA
_TxCB 7 | | 34 RxDA
TxDB 8 | | 33 _SYNDETA
RxDB 9 | | 32 RDYA/RxDRQA
_RTSB/_SYNDETB 10 | I8274 | 31 _DTRA
RDYB/_TxDRQA 11 | | 30 _IPO/TxDRQB
D7 12 | | 29 _IPI/RxDRQB
D6 13 | | 28 _INT
D5 14 | | 27 _INTA
D4 15 | | 26 _DTRB
D3 16 | | 25 A0
D2 17 | | 24 A1
D1 18 | | 23 _CS
D0 19 | | 22 _RD
Vss 20 |_____________| 21 _WR
_____ _____
CLK 1 |* \_/ | 40 Vcc
_RESET 2 | | 39 _CTSA
_DCDA 3 | | 38 _RTSA
_RxCB 4 | | 37 TxDA
_DCDB 5 | | 36 _TxCA
_CTSB 6 | | 35 _RxCA
_TxCB 7 | | 34 RxDA
TxDB 8 | | 33 _SYNCA
RxDB 9 | | 32 _WAITA/DRQRxA
_RTSB/_SYNCB 10 | UPD7201 | 31 _DTRA/_HAO
_WAITB/_DRQTxA 11 | | 30 _PRO/DRQTxB
D7 12 | | 29 _PRI/DRQRxB
D6 13 | | 28 _INT
D5 14 | | 27 _INTAK
D4 15 | | 26 _DTRB/_HAI
D3 16 | | 25 B/_A
D2 17 | | 24 C/_D
D1 18 | | 23 _CS
D0 19 | | 22 _RD
Vss 20 |_____________| 21 _WR
***************************************************************************/ ***************************************************************************/
#ifndef __Z80DART_H__ #ifndef __Z80DART_H__
@ -202,20 +202,18 @@
const z80dart_interface (_name) = const z80dart_interface (_name) =
//************************************************************************** //**************************************************************************
// TYPE DEFINITIONS // TYPE DEFINITIONS
//************************************************************************** //**************************************************************************
// ======================> z80dart_interface // ======================> z80dart_interface
struct z80dart_interface struct z80dart_interface
{ {
int m_rx_clock_a; // channel A receive clock int m_rxca;
int m_tx_clock_a; // channel A transmit clock int m_txca;
int m_rx_clock_b; // channel B receive clock int m_rxcb;
int m_tx_clock_b; // channel B transmit clock int m_txcb;
devcb_read_line m_in_rxda_cb; devcb_read_line m_in_rxda_cb;
devcb_write_line m_out_txda_cb; devcb_write_line m_out_txda_cb;
@ -239,97 +237,21 @@ struct z80dart_interface
}; };
// ======================> z80dart_device // ======================> z80dart_channel
class z80dart_device : public device_t, class z80dart_device;
public device_z80daisy_interface,
public z80dart_interface
{
friend class dart_channel;
public: class z80dart_channel : public device_t
// construction/destruction
z80dart_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
z80dart_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
DECLARE_READ8_MEMBER( cd_ba_r );
DECLARE_WRITE8_MEMBER( cd_ba_w );
DECLARE_READ8_MEMBER( ba_cd_r );
DECLARE_WRITE8_MEMBER( ba_cd_w );
// control register access
UINT8 control_read(int which) { return m_channel[which].control_read(); }
void control_write(int which, UINT8 data) { return m_channel[which].control_write(data); }
// data register access
UINT8 data_read(int which) { return m_channel[which].data_read(); }
void data_write(int which, UINT8 data) { return m_channel[which].data_write(data); }
// put data on the input lines
void receive_data(int which, UINT8 data) { m_channel[which].receive_data(data); }
// interrupt acknowledge
int m1_r();
// control line access
void cts_w(int which, int state) { m_channel[which].cts_w(state); }
void dcd_w(int which, int state) { m_channel[which].dcd_w(state); }
void ri_w(int which, int state) { m_channel[which].ri_w(state); }
void rx_w(int which, int state) { m_channel[which].rx_w(state); }
void tx_w(int which, int state) { m_channel[which].tx_w(state); }
void sync_w(int which, int state) { m_channel[which].sync_w(state); }
DECLARE_WRITE_LINE_MEMBER( ctsa_w ) { cts_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( ctsb_w ) { cts_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( dcda_w ) { dcd_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( dcdb_w ) { dcd_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( ria_w ) { ri_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( rib_w ) { ri_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( rxca_w ) { rx_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( rxcb_w ) { rx_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( txca_w ) { tx_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( txcb_w ) { tx_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( rxtxcb_w ) { rx_w(1, state); tx_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( synca_w ) { sync_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( syncb_w ) { sync_w(1, state); }
protected:
enum
{
TYPE_DART,
TYPE_SIO0,
TYPE_SIO1,
TYPE_SIO2,
TYPE_SIO3,
TYPE_SIO4,
TYPE_I8274,
TYPE_UPD7201
};
// device-level overrides
virtual void device_config_complete();
virtual void device_start();
virtual void device_reset();
// device_z80daisy_interface overrides
virtual int z80daisy_irq_state();
virtual int z80daisy_irq_ack();
virtual void z80daisy_irq_reti();
// internal interrupt management
void check_interrupts();
void take_interrupt(int priority);
// a single channel on the DART
class dart_channel
{ {
friend class z80dart_device; friend class z80dart_device;
public: public:
dart_channel(); z80dart_channel(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
void start(z80dart_device *device, int index, const devcb_read_line &in_rxd, const devcb_write_line &out_txd, const devcb_write_line &out_dtr, const devcb_write_line &out_rts, const devcb_write_line &out_wrdy, const devcb_write_line &out_sync, const devcb_write_line &out_rxdrq, const devcb_write_line &out_txdrq); // device-level overrides
void reset(); virtual void device_start();
virtual void device_reset();
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
UINT8 control_read(); UINT8 control_read();
void control_write(UINT8 data); void control_write(UINT8 data);
@ -342,11 +264,174 @@ protected:
void cts_w(int state); void cts_w(int state);
void dcd_w(int state); void dcd_w(int state);
void ri_w(int state); void ri_w(int state);
void rx_w(int state); void rxc_w(int state);
void tx_w(int state); void txc_w(int state);
void sync_w(int state); void sync_w(int state);
private: devcb_read_line m_in_rxd_cb;
devcb_write_line m_out_txd_cb;
devcb_write_line m_out_dtr_cb;
devcb_write_line m_out_rts_cb;
devcb_write_line m_out_wrdy_cb;
devcb_write_line m_out_sync_cb;
devcb_write_line m_out_rxdrq_cb;
devcb_write_line m_out_txdrq_cb;
int m_rxc;
int m_txc;
// register state
UINT8 m_rr[3]; // read register
UINT8 m_wr[6]; // write register
protected:
enum
{
TIMER_RX,
TIMER_TX
};
enum
{
STATE_START = 0,
STATE_DATA,
STATE_PARITY,
STATE_STOP,
STATE_STOP2
};
enum
{
INT_TRANSMIT = 0,
INT_EXTERNAL,
INT_RECEIVE,
INT_SPECIAL
};
enum
{
RR0_RX_CHAR_AVAILABLE = 0x01,
RR0_INTERRUPT_PENDING = 0x02,
RR0_TX_BUFFER_EMPTY = 0x04,
RR0_DCD = 0x08,
RR0_RI = 0x10,
RR0_SYNC_HUNT = 0x10, // not supported
RR0_CTS = 0x20,
RR0_TX_UNDERRUN = 0x40, // not supported
RR0_BREAK_ABORT = 0x80 // not supported
};
enum
{
RR1_ALL_SENT = 0x01,
RR1_RESIDUE_CODE_MASK = 0x0e, // not supported
RR1_PARITY_ERROR = 0x10,
RR1_RX_OVERRUN_ERROR = 0x20,
RR1_CRC_FRAMING_ERROR = 0x40,
RR1_END_OF_FRAME = 0x80 // not supported
};
enum
{
WR0_REGISTER_MASK = 0x07,
WR0_COMMAND_MASK = 0x38,
WR0_NULL = 0x00,
WR0_SEND_ABORT = 0x08, // not supported
WR0_RESET_EXT_STATUS = 0x10,
WR0_CHANNEL_RESET = 0x18,
WR0_ENABLE_INT_NEXT_RX = 0x20,
WR0_RESET_TX_INT = 0x28, // not supported
WR0_ERROR_RESET = 0x30,
WR0_RETURN_FROM_INT = 0x38, // not supported
WR0_CRC_RESET_CODE_MASK = 0xc0, // not supported
WR0_CRC_RESET_NULL = 0x00, // not supported
WR0_CRC_RESET_RX = 0x40, // not supported
WR0_CRC_RESET_TX = 0x80, // not supported
WR0_CRC_RESET_TX_UNDERRUN = 0xc0 // not supported
};
enum
{
WR1_EXT_INT_ENABLE = 0x01,
WR1_TX_INT_ENABLE = 0x02,
WR1_STATUS_VECTOR = 0x04,
WR1_RX_INT_MODE_MASK = 0x18,
WR1_RX_INT_DISABLE = 0x00,
WR1_RX_INT_FIRST = 0x08,
WR1_RX_INT_ALL_PARITY = 0x10, // not supported
WR1_RX_INT_ALL = 0x18,
WR1_WRDY_ON_RX_TX = 0x20, // not supported
WR1_WRDY_FUNCTION = 0x40, // not supported
WR1_WRDY_ENABLE = 0x80 // not supported
};
enum
{
WR2_DATA_XFER_INT = 0x00, // not supported
WR2_DATA_XFER_DMA_INT = 0x01, // not supported
WR2_DATA_XFER_DMA = 0x02, // not supported
WR2_DATA_XFER_ILLEGAL = 0x03, // not supported
WR2_DATA_XFER_MASK = 0x03, // not supported
WR2_PRIORITY = 0x04, // not supported
WR2_MODE_8085_1 = 0x00, // not supported
WR2_MODE_8085_2 = 0x08, // not supported
WR2_MODE_8086_8088 = 0x10, // not supported
WR2_MODE_ILLEGAL = 0x18, // not supported
WR2_MODE_MASK = 0x18, // not supported
WR2_VECTORED_INT = 0x20, // not supported
WR2_PIN10_SYNDETB_RTSB = 0x80 // not supported
};
enum
{
WR3_RX_ENABLE = 0x01,
WR3_SYNC_CHAR_LOAD_INHIBIT= 0x02, // not supported
WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported
WR3_RX_CRC_ENABLE = 0x08, // not supported
WR3_ENTER_HUNT_PHASE = 0x10, // not supported
WR3_AUTO_ENABLES = 0x20,
WR3_RX_WORD_LENGTH_MASK = 0xc0,
WR3_RX_WORD_LENGTH_5 = 0x00,
WR3_RX_WORD_LENGTH_7 = 0x40,
WR3_RX_WORD_LENGTH_6 = 0x80,
WR3_RX_WORD_LENGTH_8 = 0xc0
};
enum
{
WR4_PARITY_ENABLE = 0x01, // not supported
WR4_PARITY_EVEN = 0x02, // not supported
WR4_STOP_BITS_MASK = 0x0c,
WR4_STOP_BITS_1 = 0x04,
WR4_STOP_BITS_1_5 = 0x08, // not supported
WR4_STOP_BITS_2 = 0x0c,
WR4_SYNC_MODE_MASK = 0x30, // not supported
WR4_SYNC_MODE_8_BIT = 0x00, // not supported
WR4_SYNC_MODE_16_BIT = 0x10, // not supported
WR4_SYNC_MODE_SDLC = 0x20, // not supported
WR4_SYNC_MODE_EXT = 0x30, // not supported
WR4_CLOCK_RATE_MASK = 0xc0,
WR4_CLOCK_RATE_X1 = 0x00,
WR4_CLOCK_RATE_X16 = 0x40,
WR4_CLOCK_RATE_X32 = 0x80,
WR4_CLOCK_RATE_X64 = 0xc0
};
enum
{
WR5_TX_CRC_ENABLE = 0x01, // not supported
WR5_RTS = 0x02,
WR5_CRC16 = 0x04, // not supported
WR5_TX_ENABLE = 0x08,
WR5_SEND_BREAK = 0x10,
WR5_TX_WORD_LENGTH_MASK = 0x60,
WR5_TX_WORD_LENGTH_5 = 0x00,
WR5_TX_WORD_LENGTH_6 = 0x40,
WR5_TX_WORD_LENGTH_7 = 0x20,
WR5_TX_WORD_LENGTH_8 = 0x60,
WR5_DTR = 0x80
};
void take_interrupt(int level); void take_interrupt(int level);
int get_clock_mode(); int get_clock_mode();
float get_stop_bits(); float get_stop_bits();
@ -360,12 +445,6 @@ protected:
void receive(); void receive();
void transmit(); void transmit();
static TIMER_CALLBACK( static_rxc_tick ) { reinterpret_cast<dart_channel *>(ptr)->rx_w(1); }
static TIMER_CALLBACK( static_txc_tick ) { reinterpret_cast<dart_channel *>(ptr)->tx_w(1); }
z80dart_device *m_device;
int m_index;
devcb_resolved_read_line m_in_rxd_func; devcb_resolved_read_line m_in_rxd_func;
devcb_resolved_write_line m_out_txd_func; devcb_resolved_write_line m_out_txd_func;
devcb_resolved_write_line m_out_dtr_func; devcb_resolved_write_line m_out_dtr_func;
@ -375,10 +454,6 @@ protected:
devcb_resolved_write_line m_out_rxdrq_func; devcb_resolved_write_line m_out_rxdrq_func;
devcb_resolved_write_line m_out_txdrq_func; devcb_resolved_write_line m_out_txdrq_func;
// register state
UINT8 m_rr[3]; // read register
UINT8 m_wr[6]; // write register
// receiver state // receiver state
UINT8 m_rx_data_fifo[3]; // receive data FIFO UINT8 m_rx_data_fifo[3]; // receive data FIFO
UINT8 m_rx_error_fifo[3]; // receive error FIFO UINT8 m_rx_error_fifo[3]; // receive error FIFO
@ -412,19 +487,110 @@ protected:
// synchronous state // synchronous state
UINT16 m_sync; // sync character UINT16 m_sync; // sync character
emu_timer *m_rx_timer;
emu_timer *m_tx_timer;
int m_index;
z80dart_device *m_uart;
}; };
// ======================> z80dart_device
class z80dart_device : public device_t,
public device_z80daisy_interface,
public z80dart_interface
{
friend class z80dart_channel;
public:
// construction/destruction
z80dart_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
z80dart_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
DECLARE_READ8_MEMBER( cd_ba_r );
DECLARE_WRITE8_MEMBER( cd_ba_w );
DECLARE_READ8_MEMBER( ba_cd_r );
DECLARE_WRITE8_MEMBER( ba_cd_w );
// interrupt acknowledge
int m1_r();
DECLARE_WRITE_LINE_MEMBER( ctsa_w ) { cts_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( ctsb_w ) { cts_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( dcda_w ) { dcd_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( dcdb_w ) { dcd_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( ria_w ) { ri_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( rib_w ) { ri_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( rxca_w ) { rxc_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( rxcb_w ) { rxc_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( txca_w ) { txc_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( txcb_w ) { txc_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( rxtxcb_w ) { rxc_w(1, state); txc_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( synca_w ) { sync_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( syncb_w ) { sync_w(1, state); }
protected:
// device-level overrides
virtual void device_config_complete();
virtual void device_start();
virtual void device_reset();
virtual machine_config_constructor device_mconfig_additions() const;
// device_z80daisy_interface overrides
virtual int z80daisy_irq_state();
virtual int z80daisy_irq_ack();
virtual void z80daisy_irq_reti();
// internal interrupt management
void check_interrupts();
void reset_interrupts();
void trigger_interrupt(int index, int state);
z80dart_channel *get_channel(int chan) { return chan == 0 ? m_chanA : m_chanB; }
int get_channel_index(z80dart_channel *ch) { return (ch == m_chanA) ? 0 : 1; }
enum
{
TYPE_DART,
TYPE_SIO0,
TYPE_SIO1,
TYPE_SIO2,
TYPE_SIO3,
TYPE_SIO4,
TYPE_I8274,
TYPE_UPD7201
};
enum
{
CHANNEL_A = 0,
CHANNEL_B
};
// control register access
UINT8 control_read(int which) { return get_channel(which)->control_read(); }
void control_write(int which, UINT8 data) { return get_channel(which)->control_write(data); }
// data register access
UINT8 data_read(int which) { return get_channel(which)->data_read(); }
void data_write(int which, UINT8 data) { return get_channel(which)->data_write(data); }
// control line access
void cts_w(int which, int state) { get_channel(which)->cts_w(state); }
void dcd_w(int which, int state) { get_channel(which)->dcd_w(state); }
void ri_w(int which, int state) { get_channel(which)->ri_w(state); }
void rxc_w(int which, int state) { get_channel(which)->rxc_w(state); }
void txc_w(int which, int state) { get_channel(which)->txc_w(state); }
void sync_w(int which, int state) { get_channel(which)->sync_w(state); }
required_device<z80dart_channel> m_chanA;
required_device<z80dart_channel> m_chanB;
// internal state // internal state
devcb_resolved_write_line m_out_int_func; devcb_resolved_write_line m_out_int_func;
dart_channel m_channel[2]; // channels
int m_int_state[8]; // interrupt state int m_int_state[8]; // interrupt state
// timers
emu_timer * m_rxca_timer;
emu_timer * m_txca_timer;
emu_timer * m_rxcb_timer;
emu_timer * m_txcb_timer;
int m_variant; int m_variant;
}; };
@ -500,6 +666,7 @@ public:
// device type definition // device type definition
extern const device_type Z80DART_CHANNEL;
extern const device_type Z80DART; extern const device_type Z80DART;
extern const device_type Z80SIO0; extern const device_type Z80SIO0;
extern const device_type Z80SIO1; extern const device_type Z80SIO1;

8
src/mess/drivers/abc80x.c
View File

@ -1031,10 +1031,10 @@ void abc800_state::machine_reset()
m_fetch_charram = 0; m_fetch_charram = 0;
bankswitch(); bankswitch();
m_dart->ri_w(0, 1); m_dart->ria_w(1);
// 50/60 Hz // 50/60 Hz
m_dart->cts_w(1, 0); // 0 = 50Hz, 1 = 60Hz m_dart->ctsb_w(0); // 0 = 50Hz, 1 = 60Hz
m_dfd_in = 0; m_dfd_in = 0;
} }
@ -1170,10 +1170,10 @@ void abc806_state::machine_reset()
m_rtc->clk_w(1); m_rtc->clk_w(1);
m_rtc->dio_w(1); m_rtc->dio_w(1);
m_dart->ri_w(0, 1); m_dart->ria_w(1);
// 50/60 Hz // 50/60 Hz
m_dart->cts_w(1, 0); // 0 = 50Hz, 1 = 60Hz m_dart->ctsb_w(0); // 0 = 50Hz, 1 = 60Hz
m_dfd_in = 0; m_dfd_in = 0;
} }

26
src/mess/machine/wangpc_mcc.c
View File

@ -201,33 +201,21 @@ UINT16 wangpc_mcc_device::wangpcbus_iorc_r(address_space &space, offs_t offset,
{ {
case 0x00/2: case 0x00/2:
case 0x02/2: case 0x02/2:
if (ACCESSING_BITS_0_7)
{
data = 0xff00 | m_sio->data_read(offset & 0x01);
}
break;
case 0x04/2: case 0x04/2:
case 0x06/2: case 0x06/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
data = 0xff00 | m_sio->control_read(offset & 0x01); data = 0xff00 | m_sio->cd_ba_r(space, offset >> 1);
} }
break; break;
case 0x08/2: case 0x08/2:
case 0x0a/2: case 0x0a/2:
if (ACCESSING_BITS_0_7)
{
data = 0xff00 | m_dart->data_read(offset & 0x01);
}
break;
case 0x0c/2: case 0x0c/2:
case 0x0e/2: case 0x0e/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
data = 0xff00 | m_dart->control_read(offset & 0x01); data = 0xff00 | m_dart->cd_ba_r(space, offset >> 1);
} }
break; break;
@ -280,22 +268,16 @@ void wangpc_mcc_device::wangpcbus_aiowc_w(address_space &space, offs_t offset, U
{ {
case 0x00/2: case 0x00/2:
case 0x02/2: case 0x02/2:
m_sio->data_write(offset & 0x01, data & 0xff);
break;
case 0x04/2: case 0x04/2:
case 0x06/2: case 0x06/2:
m_sio->control_write(offset & 0x01, data & 0xff); m_sio->cd_ba_w(space, offset >> 1, data & 0xff);
break; break;
case 0x08/2: case 0x08/2:
case 0x0a/2: case 0x0a/2:
m_dart->data_write(offset & 0x01, data & 0xff);
break;
case 0x0c/2: case 0x0c/2:
case 0x0e/2: case 0x0e/2:
m_dart->control_write(offset & 0x01, data & 0xff); m_dart->cd_ba_w(space, offset >> 1, data & 0xff);
break; break;
case 0x12/2: case 0x12/2:

2
src/mess/video/abc802.c
View File

@ -179,7 +179,7 @@ WRITE_LINE_MEMBER( abc802_state::vs_w )
} }
// signal _DEW to DART // signal _DEW to DART
m_dart->ri_w(1, !state); m_dart->rib_w(!state);
} }

2
src/mess/video/abc806.c
View File

@ -387,7 +387,7 @@ WRITE_LINE_MEMBER( abc806_state::hs_w )
if (m_d_vsync != vsync) if (m_d_vsync != vsync)
{ {
// signal _DEW to DART // signal _DEW to DART
m_dart->ri_w(1, !vsync); m_dart->rib_w(!vsync);
} }
m_d_vsync = vsync; m_d_vsync = vsync;