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-scc68070: Moved Quizard MCU HLE from SCC68070 device to cdi.cpp and converted SCC68070 to use logmacro. [Ryan Holtz]

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This commit is contained in:
MooglyGuy 2019-07-24 19:11:59 +02:00
parent aa2f9428dc
commit ebfc11eff3
5 changed files with 461 additions and 330 deletions
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396
src/devices/machine/scc68070.cpp
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@ -24,34 +24,25 @@ TODO:
#include "emu.h" #include "emu.h"
#include "machine/scc68070.h" #include "machine/scc68070.h"
/*----------- debug defines -----------*/ #define LOG_I2C (1 << 0)
#define LOG_UART (1 << 1)
#define LOG_TIMERS (1 << 2)
#define LOG_TIMERS_HF (1 << 3)
#define LOG_DMA (1 << 4)
#define LOG_MMU (1 << 5)
#define LOG_IRQS (1 << 6)
#define LOG_UNKNOWN (1 << 7)
#define LOG_ALL (LOG_I2C | LOG_UART | LOG_TIMERS | LOG_DMA | LOG_MMU | LOG_IRQS | LOG_UNKNOWN)
#define VERBOSE_LEVEL (1) #define VERBOSE (LOG_UART)
#define ENABLE_VERBOSE_LOG (0) #include "logmacro.h"
#define ENABLE_UART_PRINTING (0) #define ENABLE_UART_PRINTING (0)
// device type definition // device type definition
DEFINE_DEVICE_TYPE(SCC68070, scc68070_device, "scc68070", "Philips SCC68070") DEFINE_DEVICE_TYPE(SCC68070, scc68070_device, "scc68070", "Philips SCC68070")
#if ENABLE_VERBOSE_LOG
static inline void ATTR_PRINTF(3,4) verboselog(device_t& device, int n_level, const char *s_fmt, ...)
{
if ( VERBOSE_LEVEL >= n_level )
{
va_list v;
char buf[ 32768 ];
va_start( v, s_fmt );
vsprintf( buf, s_fmt, v );
va_end( v );
device.logerror("%s: %s", device.machine().describe_context(), buf );
}
}
#else
#define verboselog(x,y,z, ...)
#endif
//************************************************************************** //**************************************************************************
// LIVE DEVICE // LIVE DEVICE
//************************************************************************** //**************************************************************************
@ -76,6 +67,7 @@ scc68070_device::scc68070_device(const machine_config &mconfig, const char *tag,
, m_iack4_callback(*this) , m_iack4_callback(*this)
, m_iack5_callback(*this) , m_iack5_callback(*this)
, m_iack7_callback(*this) , m_iack7_callback(*this)
, m_uart_tx_callback(*this)
, m_ipl(0) , m_ipl(0)
, m_in2_line(CLEAR_LINE) , m_in2_line(CLEAR_LINE)
, m_in4_line(CLEAR_LINE) , m_in4_line(CLEAR_LINE)
@ -101,6 +93,7 @@ void scc68070_device::device_resolve_objects()
m_iack4_callback.resolve_safe(autovector(4)); m_iack4_callback.resolve_safe(autovector(4));
m_iack5_callback.resolve_safe(autovector(5)); m_iack5_callback.resolve_safe(autovector(5));
m_iack7_callback.resolve_safe(autovector(7)); m_iack7_callback.resolve_safe(autovector(7));
m_uart_tx_callback.resolve_safe();
} }
//------------------------------------------------- //-------------------------------------------------
@ -275,11 +268,6 @@ void scc68070_device::device_reset()
m_mmu.desc[index].base = 0; m_mmu.desc[index].base = 0;
} }
memset(m_seeds, 0, 10 * sizeof(uint16_t));
memset(m_state, 0, 8 * sizeof(uint8_t));
m_mcu_value = 0;
m_mcu_ack = 0;
update_ipl(); update_ipl();
} }
@ -443,16 +431,6 @@ void scc68070_device::set_timer_callback(int channel)
} }
} }
void scc68070_device::set_quizard_mcu_ack(uint8_t ack)
{
m_mcu_ack = ack;
}
void scc68070_device::set_quizard_mcu_value(uint16_t value)
{
m_mcu_value = value;
}
TIMER_CALLBACK_MEMBER( scc68070_device::timer0_callback ) TIMER_CALLBACK_MEMBER( scc68070_device::timer0_callback )
{ {
m_timers.timer0 = m_timers.reload_register; m_timers.timer0 = m_timers.reload_register;
@ -536,7 +514,7 @@ TIMER_CALLBACK_MEMBER( scc68070_device::rx_callback )
if (m_uart.receive_pointer > -1) if (m_uart.receive_pointer > -1)
{ {
verboselog(*this, 2, "scc68070_rx_callback: Receiving %02x\n", m_uart.receive_holding_register); LOGMASKED(LOG_UART, "scc68070_rx_callback: Receiving %02x\n", m_uart.receive_holding_register);
m_uart_rx_int = true; m_uart_rx_int = true;
update_ipl(); update_ipl();
@ -558,173 +536,6 @@ TIMER_CALLBACK_MEMBER( scc68070_device::rx_callback )
uart_rx_check(); uart_rx_check();
} }
void scc68070_device::quizard_rx(uint8_t data)
{
uart_rx(0x5a);
uart_rx(data);
}
void scc68070_device::quizard_set_seeds(uint8_t *rx)
{
m_seeds[0] = (rx[1] << 8) | rx[0];
m_seeds[1] = (rx[3] << 8) | rx[2];
m_seeds[2] = (rx[5] << 8) | rx[4];
m_seeds[3] = (rx[7] << 8) | rx[6];
m_seeds[4] = (rx[9] << 8) | rx[8];
m_seeds[5] = (rx[11] << 8) | rx[10];
m_seeds[6] = (rx[13] << 8) | rx[12];
m_seeds[7] = (rx[15] << 8) | rx[14];
m_seeds[8] = (rx[17] << 8) | rx[16];
m_seeds[9] = (rx[19] << 8) | rx[18];
}
void scc68070_device::quizard_calculate_state()
{
//const uint16_t desired_bitfield = mcu_value;
const uint16_t field0 = 0x00ff;
const uint16_t field1 = m_mcu_value ^ 0x00ff;
uint16_t total0 = 0;
uint16_t total1 = 0;
for(int index = 0; index < 10; index++)
{
if (field0 & (1 << index))
{
total0 += m_seeds[index];
}
if (field1 & (1 << index))
{
total1 += m_seeds[index];
}
}
uint16_t hi0 = (total0 >> 8) + 0x40;
m_state[2] = hi0 / 2;
m_state[3] = hi0 - m_state[2];
uint16_t lo0 = (total0 & 0x00ff) + 0x40;
m_state[0] = lo0 / 2;
m_state[1] = lo0 - m_state[0];
uint16_t hi1 = (total1 >> 8) + 0x40;
m_state[6] = hi1 / 2;
m_state[7] = hi1 - m_state[6];
uint16_t lo1 = (total1 & 0x00ff) + 0x40;
m_state[4] = lo1 / 2;
m_state[5] = lo1 - m_state[4];
}
void scc68070_device::mcu_frame()
{
if (0)//mcu_active)
{
quizard_calculate_state();
uart_rx(0x5a);
for(auto & elem : m_state)
{
uart_rx(elem);
}
}
}
void scc68070_device::quizard_handle_byte_tx()
{
static int state = 0;
static uint8_t rx[0x100];
static uint8_t rx_ptr = 0xff;
uint8_t tx = m_uart.transmit_holding_register;
switch (state)
{
case 0: // Waiting for a leadoff byte
if (tx == m_mcu_ack) // Sequence end
{
//scc68070_uart_rx(machine, scc68070, 0x5a);
//scc68070_uart_rx(machine, scc68070, 0x42);
}
else
{
switch (tx)
{
case 0x44: // DATABASEPATH = **_DATABASE/
rx[0] = 0x44;
rx_ptr = 1;
state = 3;
break;
case 0x2e: // Unknown; ignored
break;
case 0x56: // Seed start
rx_ptr = 0;
state = 1;
break;
default:
//printf("Unknown leadoff byte: %02x\n", tx);
break;
}
}
break;
case 1: // Receiving the seed
rx[rx_ptr] = tx;
rx_ptr++;
if (rx_ptr == 20)
{
//printf("Calculating seeds\n");
quizard_set_seeds(rx);
quizard_calculate_state();
state = 2;
}
break;
case 2: // Receiving the seed acknowledge
case 4:
if (tx == m_mcu_ack)
{
if (state == 2)
{
state = 4;
}
else
{
state = 0;
}
//printf("Sending seed ack\n");
uart_rx(0x5a);
uart_rx(m_state[0]);
uart_rx(m_state[1]);
uart_rx(m_state[2]);
uart_rx(m_state[3]);
uart_rx(m_state[4]);
uart_rx(m_state[5]);
uart_rx(m_state[6]);
uart_rx(m_state[7]);
}
break;
case 3: // Receiving the database path
rx[rx_ptr] = tx;
rx_ptr++;
if (tx == 0x0a)
{
/*rx[rx_ptr] = 0;
//printf("Database path: %s\n", rx);
scc68070_uart_rx(machine, scc68070, 0x5a);
scc68070_uart_rx(machine, scc68070, g_state[0]);
scc68070_uart_rx(machine, scc68070, g_state[1]);
scc68070_uart_rx(machine, scc68070, g_state[2]);
scc68070_uart_rx(machine, scc68070, g_state[3]);
scc68070_uart_rx(machine, scc68070, g_state[4]);
scc68070_uart_rx(machine, scc68070, g_state[5]);
scc68070_uart_rx(machine, scc68070, g_state[6]);
scc68070_uart_rx(machine, scc68070, g_state[7]);*/
state = 0;
}
break;
}
}
TIMER_CALLBACK_MEMBER( scc68070_device::tx_callback ) TIMER_CALLBACK_MEMBER( scc68070_device::tx_callback )
{ {
if (((m_uart.command_register >> 2) & 3) == 1) if (((m_uart.command_register >> 2) & 3) == 1)
@ -735,9 +546,9 @@ TIMER_CALLBACK_MEMBER( scc68070_device::tx_callback )
if (m_uart.transmit_pointer > -1) if (m_uart.transmit_pointer > -1)
{ {
m_uart.transmit_holding_register = m_uart.transmit_buffer[0]; m_uart.transmit_holding_register = m_uart.transmit_buffer[0];
quizard_handle_byte_tx(); m_uart_tx_callback(m_uart.transmit_holding_register);
verboselog(*this, 2, "tx_callback: Transmitting %02x\n", m_uart.transmit_holding_register); LOGMASKED(LOG_UART, "tx_callback: Transmitting %02x\n", machine().describe_context(), m_uart.transmit_holding_register);
for(int index = 0; index < m_uart.transmit_pointer; index++) for(int index = 0; index < m_uart.transmit_pointer; index++)
{ {
m_uart.transmit_buffer[index] = m_uart.transmit_buffer[index+1]; m_uart.transmit_buffer[index] = m_uart.transmit_buffer[index+1];
@ -772,31 +583,31 @@ READ16_MEMBER( scc68070_device::periphs_r )
case 0x2000/2: case 0x2000/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: I2C Data Register: %04x & %04x\n", m_i2c.data_register, mem_mask); LOGMASKED(LOG_I2C, "%s: I2C Data Register Read: %04x & %04x\n", machine().describe_context(), m_i2c.data_register, mem_mask);
} }
return m_i2c.data_register; return m_i2c.data_register;
case 0x2002/2: case 0x2002/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: I2C Address Register: %04x & %04x\n", m_i2c.address_register, mem_mask); LOGMASKED(LOG_I2C, "%s: I2C Address Register Read: %04x & %04x\n", machine().describe_context(), m_i2c.address_register, mem_mask);
} }
return m_i2c.address_register; return m_i2c.address_register;
case 0x2004/2: case 0x2004/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: I2C Status Register: %04x & %04x\n", m_i2c.status_register, mem_mask); LOGMASKED(LOG_I2C, "%s: I2C Status Register Read: %04x & %04x\n", machine().describe_context(), m_i2c.status_register, mem_mask);
} }
return m_i2c.status_register & 0xef; // hack for magicard return m_i2c.status_register & 0xef; // hack for magicard
case 0x2006/2: case 0x2006/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: I2C Control Register: %04x & %04x\n", m_i2c.control_register, mem_mask); LOGMASKED(LOG_I2C, "%s: I2C Control Register Read: %04x & %04x\n", machine().describe_context(), m_i2c.control_register, mem_mask);
} }
return m_i2c.control_register; return m_i2c.control_register;
case 0x2008/2: case 0x2008/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: I2C Clock Control Register: %04x & %04x\n", m_i2c.clock_control_register, mem_mask); LOGMASKED(LOG_I2C, "%s: I2C Clock Control Register Read: %04x & %04x\n", machine().describe_context(), m_i2c.clock_control_register, mem_mask);
} }
return m_i2c.clock_control_register; return m_i2c.clock_control_register;
@ -804,22 +615,22 @@ READ16_MEMBER( scc68070_device::periphs_r )
case 0x2010/2: case 0x2010/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_r: UART Mode Register: %04x & %04x\n", m_uart.mode_register, mem_mask); LOGMASKED(LOG_UART, "%s: UART Mode Register Read: %04x & %04x\n", machine().describe_context(), m_uart.mode_register, mem_mask);
} }
else else
{ {
verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Read: %04x & %04x\n", machine().describe_context(), offset * 2, mem_mask);
} }
return m_uart.mode_register | 0x20; return m_uart.mode_register | 0x20;
case 0x2012/2: case 0x2012/2:
m_uart.status_register |= (1 << 1); m_uart.status_register |= (1 << 1);
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_r: UART Status Register: %04x & %04x\n", m_uart.status_register, mem_mask); LOGMASKED(LOG_UART, "%s: UART Status Register Read: %04x & %04x\n", machine().describe_context(), m_uart.status_register, mem_mask);
} }
else else
{ {
verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Read: %04x & %04x\n", machine().describe_context(), offset * 2, mem_mask);
} }
return m_uart.status_register | 0x08; // hack for magicard return m_uart.status_register | 0x08; // hack for magicard
@ -827,41 +638,41 @@ READ16_MEMBER( scc68070_device::periphs_r )
case 0x2014/2: case 0x2014/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_r: UART Clock Select: %04x & %04x\n", m_uart.clock_select, mem_mask); LOGMASKED(LOG_UART, "%s: UART Clock Select Read: %04x & %04x\n", machine().describe_context(), m_uart.clock_select, mem_mask);
} }
else else
{ {
verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Read: %04x & %04x\n", machine().describe_context(), offset * 2, mem_mask);
} }
return m_uart.clock_select | 0x08; return m_uart.clock_select | 0x08;
case 0x2016/2: case 0x2016/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_r: UART Command Register: %02x & %04x\n", m_uart.command_register, mem_mask); LOGMASKED(LOG_UART, "%s: UART Command Register Read: %02x & %04x\n", machine().describe_context(), m_uart.command_register, mem_mask);
} }
else else
{ {
verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Read: %04x & %04x\n", machine().describe_context(), offset * 2, mem_mask);
} }
return m_uart.command_register | 0x80; return m_uart.command_register | 0x80;
case 0x2018/2: case 0x2018/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_r: UART Transmit Holding Register: %02x & %04x\n", m_uart.transmit_holding_register, mem_mask); LOGMASKED(LOG_UART, "%s: UART Transmit Holding Register Read: %02x & %04x\n", machine().describe_context(), m_uart.transmit_holding_register, mem_mask);
} }
else else
{ {
verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Read: %04x & %04x\n", machine().describe_context(), offset * 2, mem_mask);
} }
return m_uart.transmit_holding_register; return m_uart.transmit_holding_register;
case 0x201a/2: case 0x201a/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_r: UART Receive Holding Register: %02x & %04x\n", m_uart.receive_holding_register, mem_mask); LOGMASKED(LOG_UART, "%s: UART Receive Holding Register Read: %02x & %04x\n", machine().describe_context(), m_uart.receive_holding_register, mem_mask);
} }
else else
{ {
verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Read: %04x & %04x\n", machine().describe_context(), offset * 2, mem_mask);
} }
if (m_uart_rx_int) if (m_uart_rx_int)
{ {
@ -878,38 +689,37 @@ READ16_MEMBER( scc68070_device::periphs_r )
} }
m_uart.receive_pointer--; m_uart.receive_pointer--;
} }
//printf("R: %02x\n", m_uart.receive_holding_register);
return m_uart.receive_holding_register; return m_uart.receive_holding_register;
// Timers: 80002020 to 80002029 // Timers: 80002020 to 80002029
case 0x2020/2: case 0x2020/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_r: Timer Control Register: %02x & %04x\n", m_timers.timer_control_register, mem_mask); LOGMASKED(LOG_TIMERS, "%s: Timer Control Register Read: %02x & %04x\n", machine().describe_context(), m_timers.timer_control_register, mem_mask);
} }
if (ACCESSING_BITS_8_15) if (ACCESSING_BITS_8_15)
{ {
verboselog(*this, 12, "periphs_r: Timer Status Register: %02x & %04x\n", m_timers.timer_status_register, mem_mask); LOGMASKED(LOG_TIMERS_HF, "%s: Timer Status Register Read: %02x & %04x\n", machine().describe_context(), m_timers.timer_status_register, mem_mask);
} }
return (m_timers.timer_status_register << 8) | m_timers.timer_control_register; return (m_timers.timer_status_register << 8) | m_timers.timer_control_register;
case 0x2022/2: case 0x2022/2:
verboselog(*this, 2, "periphs_r: Timer Reload Register: %04x & %04x\n", m_timers.reload_register, mem_mask); LOGMASKED(LOG_TIMERS, "%s: Timer Reload Register Read: %04x & %04x\n", machine().describe_context(), m_timers.reload_register, mem_mask);
return m_timers.reload_register; return m_timers.reload_register;
case 0x2024/2: case 0x2024/2:
verboselog(*this, 2, "periphs_r: Timer 0: %04x & %04x\n", m_timers.timer0, mem_mask); LOGMASKED(LOG_TIMERS, "%s: Timer 0 Read: %04x & %04x\n", machine().describe_context(), m_timers.timer0, mem_mask);
return m_timers.timer0; return m_timers.timer0;
case 0x2026/2: case 0x2026/2:
verboselog(*this, 2, "periphs_r: Timer 1: %04x & %04x\n", m_timers.timer1, mem_mask); LOGMASKED(LOG_TIMERS, "%s: Timer 1 Read: %04x & %04x\n", machine().describe_context(), m_timers.timer1, mem_mask);
return m_timers.timer1; return m_timers.timer1;
case 0x2028/2: case 0x2028/2:
verboselog(*this, 2, "periphs_r: Timer 2: %04x & %04x\n", m_timers.timer2, mem_mask); LOGMASKED(LOG_TIMERS, "%s: Timer 2 Read: %04x & %04x\n", machine().describe_context(), m_timers.timer2, mem_mask);
return m_timers.timer2; return m_timers.timer2;
// PICR1: 80002045 // PICR1: 80002045
case 0x2044/2: case 0x2044/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_r: Peripheral Interrupt Control Register 1: %02x & %04x\n", m_picr1, mem_mask); LOGMASKED(LOG_IRQS, "%s: Peripheral Interrupt Control Register 1 Read: %02x & %04x\n", machine().describe_context(), m_picr1, mem_mask);
} }
return m_picr1 & 0x77; return m_picr1 & 0x77;
@ -917,7 +727,7 @@ READ16_MEMBER( scc68070_device::periphs_r )
case 0x2046/2: case 0x2046/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_r: Peripheral Interrupt Control Register 2: %02x & %04x\n", m_picr2, mem_mask); LOGMASKED(LOG_IRQS, "%s: Peripheral Interrupt Control Register 2 Read: %02x & %04x\n", machine().describe_context(), m_picr2, mem_mask);
} }
return m_picr2 & 0x77; return m_picr2 & 0x77;
@ -926,65 +736,65 @@ READ16_MEMBER( scc68070_device::periphs_r )
case 0x4040/2: case 0x4040/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_r: DMA(%d) Error Register: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_error, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Error Register Read: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_error, mem_mask);
} }
if (ACCESSING_BITS_8_15) if (ACCESSING_BITS_8_15)
{ {
verboselog(*this, 2, "periphs_r: DMA(%d) Status Register: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_status, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Status Register Read: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_status, mem_mask);
} }
return (m_dma.channel[(offset - 0x2000) / 32].channel_status << 8) | m_dma.channel[(offset - 0x2000) / 32].channel_error; return (m_dma.channel[(offset - 0x2000) / 32].channel_status << 8) | m_dma.channel[(offset - 0x2000) / 32].channel_error;
case 0x4004/2: case 0x4004/2:
case 0x4044/2: case 0x4044/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_r: DMA(%d) Operation Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].operation_control, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Operation Control Register Read: %02x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].operation_control, mem_mask);
} }
if (ACCESSING_BITS_8_15) if (ACCESSING_BITS_8_15)
{ {
verboselog(*this, 2, "periphs_r: DMA(%d) Device Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].device_control, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Device Control Register Read: %02x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].device_control, mem_mask);
} }
return (m_dma.channel[(offset - 0x2000) / 32].device_control << 8) | m_dma.channel[(offset - 0x2000) / 32].operation_control; return (m_dma.channel[(offset - 0x2000) / 32].device_control << 8) | m_dma.channel[(offset - 0x2000) / 32].operation_control;
case 0x4006/2: case 0x4006/2:
case 0x4046/2: case 0x4046/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_r: DMA(%d) Channel Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_control, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Channel Control Register Read: %02x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_control, mem_mask);
} }
if (ACCESSING_BITS_8_15) if (ACCESSING_BITS_8_15)
{ {
verboselog(*this, 2, "periphs_r: DMA(%d) Sequence Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].sequence_control, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Sequence Control Register Read: %02x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].sequence_control, mem_mask);
} }
return (m_dma.channel[(offset - 0x2000) / 32].sequence_control << 8) | m_dma.channel[(offset - 0x2000) / 32].channel_control; return (m_dma.channel[(offset - 0x2000) / 32].sequence_control << 8) | m_dma.channel[(offset - 0x2000) / 32].channel_control;
case 0x400a/2: case 0x400a/2:
verboselog(*this, 2, "periphs_r: DMA(%d) Memory Transfer Counter: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].transfer_counter, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Memory Transfer Counter Read: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].transfer_counter, mem_mask);
return m_dma.channel[(offset - 0x2000) / 32].transfer_counter; return m_dma.channel[(offset - 0x2000) / 32].transfer_counter;
case 0x400c/2: case 0x400c/2:
case 0x404c/2: case 0x404c/2:
verboselog(*this, 2, "periphs_r: DMA(%d) Memory Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, (m_dma.channel[(offset - 0x2000) / 32].memory_address_counter >> 16), mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Memory Address Counter (High Word) Read: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, (m_dma.channel[(offset - 0x2000) / 32].memory_address_counter >> 16), mem_mask);
return (m_dma.channel[(offset - 0x2000) / 32].memory_address_counter >> 16); return (m_dma.channel[(offset - 0x2000) / 32].memory_address_counter >> 16);
case 0x400e/2: case 0x400e/2:
case 0x404e/2: case 0x404e/2:
verboselog(*this, 2, "periphs_r: DMA(%d) Memory Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].memory_address_counter, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Memory Address Counter (Low Word) Read: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].memory_address_counter, mem_mask);
return m_dma.channel[(offset - 0x2000) / 32].memory_address_counter; return m_dma.channel[(offset - 0x2000) / 32].memory_address_counter;
case 0x4014/2: case 0x4014/2:
case 0x4054/2: case 0x4054/2:
verboselog(*this, 2, "periphs_r: DMA(%d) Device Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, (m_dma.channel[(offset - 0x2000) / 32].device_address_counter >> 16), mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Device Address Counter (High Word) Read: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, (m_dma.channel[(offset - 0x2000) / 32].device_address_counter >> 16), mem_mask);
return (m_dma.channel[(offset - 0x2000) / 32].device_address_counter >> 16); return (m_dma.channel[(offset - 0x2000) / 32].device_address_counter >> 16);
case 0x4016/2: case 0x4016/2:
case 0x4056/2: case 0x4056/2:
verboselog(*this, 2, "periphs_r: DMA(%d) Device Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].device_address_counter, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Device Address Counter (Low Word) Read: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].device_address_counter, mem_mask);
return m_dma.channel[(offset - 0x2000) / 32].device_address_counter; return m_dma.channel[(offset - 0x2000) / 32].device_address_counter;
// MMU: 80008000 to 8000807f // MMU: 80008000 to 8000807f
case 0x8000/2: // Status / Control register case 0x8000/2: // Status / Control register
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ // Control { // Control
verboselog(*this, 2, "periphs_r: MMU Control: %02x & %04x\n", m_mmu.control, mem_mask); LOGMASKED(LOG_MMU, "%s: MMU Control Read: %02x & %04x\n", machine().describe_context(), m_mmu.control, mem_mask);
return m_mmu.control; return m_mmu.control;
} // Status } // Status
else else
{ {
verboselog(*this, 2, "periphs_r: MMU Status: %02x & %04x\n", m_mmu.status, mem_mask); LOGMASKED(LOG_MMU, "%s: MMU Status Read: %02x & %04x\n", machine().describe_context(), m_mmu.status, mem_mask);
return m_mmu.status; return m_mmu.status;
} }
case 0x8040/2: case 0x8040/2:
@ -995,7 +805,7 @@ READ16_MEMBER( scc68070_device::periphs_r )
case 0x8068/2: case 0x8068/2:
case 0x8070/2: case 0x8070/2:
case 0x8078/2: // Attributes (SD0-7) case 0x8078/2: // Attributes (SD0-7)
verboselog(*this, 2, "periphs_r: MMU descriptor %d attributes: %04x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].attr, mem_mask); LOGMASKED(LOG_MMU, "%s: MMU descriptor %d attributes Read: %04x & %04x\n", machine().describe_context(), (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].attr, mem_mask);
return m_mmu.desc[(offset - 0x4020) / 4].attr; return m_mmu.desc[(offset - 0x4020) / 4].attr;
case 0x8042/2: case 0x8042/2:
case 0x804a/2: case 0x804a/2:
@ -1005,7 +815,7 @@ READ16_MEMBER( scc68070_device::periphs_r )
case 0x806a/2: case 0x806a/2:
case 0x8072/2: case 0x8072/2:
case 0x807a/2: // Segment Length (SD0-7) case 0x807a/2: // Segment Length (SD0-7)
verboselog(*this, 2, "periphs_r: MMU descriptor %d length: %04x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].length, mem_mask); LOGMASKED(LOG_MMU, "%s: MMU descriptor %d length Read: %04x & %04x\n", machine().describe_context(), (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].length, mem_mask);
return m_mmu.desc[(offset - 0x4020) / 4].length; return m_mmu.desc[(offset - 0x4020) / 4].length;
case 0x8044/2: case 0x8044/2:
case 0x804c/2: case 0x804c/2:
@ -1017,7 +827,7 @@ READ16_MEMBER( scc68070_device::periphs_r )
case 0x807c/2: // Segment Number (SD0-7, A0=1 only) case 0x807c/2: // Segment Number (SD0-7, A0=1 only)
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_r: MMU descriptor %d segment: %02x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].segment, mem_mask); LOGMASKED(LOG_MMU, "%s: MMU descriptor %d segment Read: %02x & %04x\n", machine().describe_context(), (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].segment, mem_mask);
return m_mmu.desc[(offset - 0x4020) / 4].segment; return m_mmu.desc[(offset - 0x4020) / 4].segment;
} }
break; break;
@ -1029,10 +839,10 @@ READ16_MEMBER( scc68070_device::periphs_r )
case 0x806e/2: case 0x806e/2:
case 0x8076/2: case 0x8076/2:
case 0x807e/2: // Base Address (SD0-7) case 0x807e/2: // Base Address (SD0-7)
verboselog(*this, 2, "periphs_r: MMU descriptor %d base: %04x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].base, mem_mask); LOGMASKED(LOG_MMU, "%s: MMU descriptor %d base Read: %04x & %04x\n", machine().describe_context(), (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].base, mem_mask);
return m_mmu.desc[(offset - 0x4020) / 4].base; return m_mmu.desc[(offset - 0x4020) / 4].base;
default: default:
verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Read: %04x & %04x\n", machine().describe_context(), offset * 2, mem_mask);
break; break;
} }
@ -1045,7 +855,7 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
{ {
// Interrupts: 80001001 // Interrupts: 80001001
case 0x1000/2: // LIR priority level case 0x1000/2: // LIR priority level
verboselog(*this, 2, "periphs_w: LIR: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_IRQS, "%s: LIR Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
COMBINE_DATA(&m_lir); COMBINE_DATA(&m_lir);
break; break;
@ -1053,35 +863,35 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
case 0x2000/2: case 0x2000/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: I2C Data Register: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_I2C, "%s: I2C Data Register Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_i2c.data_register = data & 0x00ff; m_i2c.data_register = data & 0x00ff;
} }
break; break;
case 0x2002/2: case 0x2002/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: I2C Address Register: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_I2C, "%s: I2C Address Register Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_i2c.address_register = data & 0x00ff; m_i2c.address_register = data & 0x00ff;
} }
break; break;
case 0x2004/2: case 0x2004/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: I2C Status Register: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_I2C, "%s: I2C Status Register Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_i2c.status_register = data & 0x00ff; m_i2c.status_register = data & 0x00ff;
} }
break; break;
case 0x2006/2: case 0x2006/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: I2C Control Register: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_I2C, "%s: I2C Control Register Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_i2c.control_register = data & 0x00ff; m_i2c.control_register = data & 0x00ff;
} }
break; break;
case 0x2008/2: case 0x2008/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: I2C Clock Control Register: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_I2C, "%s: I2C Clock Control Register Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_i2c.clock_control_register = data & 0x00ff; m_i2c.clock_control_register = data & 0x00ff;
} }
break; break;
@ -1090,70 +900,70 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
case 0x2010/2: case 0x2010/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: UART Mode Register: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_UART, "%s: UART Mode Register Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_uart.mode_register = data & 0x00ff; m_uart.mode_register = data & 0x00ff;
} }
else else
{ {
verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Write: %04x = %04x & %04x\n", machine().describe_context(), offset * 2, data, mem_mask);
} }
break; break;
case 0x2012/2: case 0x2012/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: UART Status Register: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_UART, "%s: UART Status Register Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_uart.status_register = data & 0x00ff; m_uart.status_register = data & 0x00ff;
} }
else else
{ {
verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Write: %04x = %04x & %04x\n", machine().describe_context(), offset * 2, data, mem_mask);
} }
break; break;
case 0x2014/2: case 0x2014/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: UART Clock Select: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_UART, "%s: UART Clock Select Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_uart.clock_select = data & 0x00ff; m_uart.clock_select = data & 0x00ff;
} }
else else
{ {
verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Write: %04x = %04x & %04x\n", machine().describe_context(), offset * 2, data, mem_mask);
} }
break; break;
case 0x2016/2: case 0x2016/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: UART Command Register: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_UART, "%s: UART Command Register Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_uart.command_register = data & 0x00ff; m_uart.command_register = data & 0x00ff;
uart_rx_check(); uart_rx_check();
uart_tx_check(); uart_tx_check();
} }
else else
{ {
verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Write: %04x = %04x & %04x\n", machine().describe_context(), offset * 2, data, mem_mask);
} }
break; break;
case 0x2018/2: case 0x2018/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: UART Transmit Holding Register: %04x & %04x: %c\n", data, mem_mask, (data >= 0x20 && data < 0x7f) ? (data & 0x00ff) : ' '); LOGMASKED(LOG_UART, "%s: UART Transmit Holding Register Write: %04x & %04x: %c\n", machine().describe_context(), data, mem_mask, (data >= 0x20 && data < 0x7f) ? (data & 0x00ff) : ' ');
uart_tx(data & 0x00ff); uart_tx(data & 0x00ff);
m_uart.transmit_holding_register = data & 0x00ff; m_uart.transmit_holding_register = data & 0x00ff;
} }
else else
{ {
verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Write: %04x = %04x & %04x\n", machine().describe_context(), offset * 2, data, mem_mask);
} }
break; break;
case 0x201a/2: case 0x201a/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: UART Receive Holding Register: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_UART, "%s: UART Receive Holding Register Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_uart.receive_holding_register = data & 0x00ff; m_uart.receive_holding_register = data & 0x00ff;
} }
else else
{ {
verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Write: %04x = %04x & %04x\n", machine().describe_context(), offset * 2, data, mem_mask);
} }
break; break;
@ -1161,30 +971,30 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
case 0x2020/2: case 0x2020/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: Timer Control Register: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_TIMERS, "%s: Timer Control Register Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_timers.timer_control_register = data & 0x00ff; m_timers.timer_control_register = data & 0x00ff;
} }
if (ACCESSING_BITS_8_15) if (ACCESSING_BITS_8_15)
{ {
verboselog(*this, 12, "periphs_w: Timer Status Register: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_TIMERS_HF, "%s: Timer Status Register Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_timers.timer_status_register &= ~(data >> 8); m_timers.timer_status_register &= ~(data >> 8);
} }
break; break;
case 0x2022/2: case 0x2022/2:
verboselog(*this, 2, "periphs_w: Timer Reload Register: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_TIMERS, "%s: Timer Reload Register Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
COMBINE_DATA(&m_timers.reload_register); COMBINE_DATA(&m_timers.reload_register);
break; break;
case 0x2024/2: case 0x2024/2:
verboselog(*this, 2, "periphs_w: Timer 0: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_TIMERS, "%s: Timer 0 Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
COMBINE_DATA(&m_timers.timer0); COMBINE_DATA(&m_timers.timer0);
set_timer_callback(0); set_timer_callback(0);
break; break;
case 0x2026/2: case 0x2026/2:
verboselog(*this, 2, "periphs_w: Timer 1: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_TIMERS, "%s: Timer 1 Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
COMBINE_DATA(&m_timers.timer1); COMBINE_DATA(&m_timers.timer1);
break; break;
case 0x2028/2: case 0x2028/2:
verboselog(*this, 2, "periphs_w: Timer 2: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_TIMERS, "%s: Timer 2 Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
COMBINE_DATA(&m_timers.timer2); COMBINE_DATA(&m_timers.timer2);
break; break;
@ -1192,7 +1002,7 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
case 0x2044/2: case 0x2044/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: Peripheral Interrupt Control Register 1: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_IRQS, "%s: Peripheral Interrupt Control Register 1 Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_picr1 = data & 0x0077; m_picr1 = data & 0x0077;
switch (data & 0x0088) switch (data & 0x0088)
{ {
@ -1228,7 +1038,7 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
case 0x2046/2: case 0x2046/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: Peripheral Interrupt Control Register 2: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_IRQS, "%s: Peripheral Interrupt Control Register 2 Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_picr2 = data & 0x0077; m_picr2 = data & 0x0077;
switch (data & 0x0088) switch (data & 0x0088)
{ {
@ -1265,11 +1075,11 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
case 0x4040/2: case 0x4040/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: DMA(%d) Error (invalid): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Error (invalid) Write: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, data, mem_mask);
} }
if (ACCESSING_BITS_8_15) if (ACCESSING_BITS_8_15)
{ {
verboselog(*this, 2, "periphs_w: DMA(%d) Status: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Status Write: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, data, mem_mask);
m_dma.channel[(offset - 0x2000) / 32].channel_status &= ~((data >> 8) & 0xb0); m_dma.channel[(offset - 0x2000) / 32].channel_status &= ~((data >> 8) & 0xb0);
update_ipl(); update_ipl();
} }
@ -1278,12 +1088,12 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
case 0x4044/2: case 0x4044/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: DMA(%d) Operation Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Operation Control Register Write: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, data, mem_mask);
m_dma.channel[(offset - 0x2000) / 32].operation_control = data & 0x00ff; m_dma.channel[(offset - 0x2000) / 32].operation_control = data & 0x00ff;
} }
if (ACCESSING_BITS_8_15) if (ACCESSING_BITS_8_15)
{ {
verboselog(*this, 2, "periphs_w: DMA(%d) Device Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Device Control Register Write: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, data, mem_mask);
m_dma.channel[(offset - 0x2000) / 32].device_control = data >> 8; m_dma.channel[(offset - 0x2000) / 32].device_control = data >> 8;
} }
break; break;
@ -1291,7 +1101,7 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
case 0x4046/2: case 0x4046/2:
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: DMA(%d) Channel Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Channel Control Register Write: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, data, mem_mask);
m_dma.channel[(offset - 0x2000) / 32].channel_control = data & 0x007f; m_dma.channel[(offset - 0x2000) / 32].channel_control = data & 0x007f;
if (data & CCR_SO) if (data & CCR_SO)
{ {
@ -1301,35 +1111,35 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
} }
if (ACCESSING_BITS_8_15) if (ACCESSING_BITS_8_15)
{ {
verboselog(*this, 2, "periphs_w: DMA(%d) Sequence Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Sequence Control Register Write: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, data, mem_mask);
m_dma.channel[(offset - 0x2000) / 32].sequence_control = data >> 8; m_dma.channel[(offset - 0x2000) / 32].sequence_control = data >> 8;
} }
break; break;
case 0x400a/2: case 0x400a/2:
verboselog(*this, 2, "periphs_w: DMA(%d) Memory Transfer Counter: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Memory Transfer Counter Write: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, data, mem_mask);
COMBINE_DATA(&m_dma.channel[(offset - 0x2000) / 32].transfer_counter); COMBINE_DATA(&m_dma.channel[(offset - 0x2000) / 32].transfer_counter);
break; break;
case 0x400c/2: case 0x400c/2:
case 0x404c/2: case 0x404c/2:
verboselog(*this, 2, "periphs_w: DMA(%d) Memory Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Memory Address Counter (High Word) Write: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, data, mem_mask);
m_dma.channel[(offset - 0x2000) / 32].memory_address_counter &= ~(mem_mask << 16); m_dma.channel[(offset - 0x2000) / 32].memory_address_counter &= ~(mem_mask << 16);
m_dma.channel[(offset - 0x2000) / 32].memory_address_counter |= data << 16; m_dma.channel[(offset - 0x2000) / 32].memory_address_counter |= data << 16;
break; break;
case 0x400e/2: case 0x400e/2:
case 0x404e/2: case 0x404e/2:
verboselog(*this, 2, "periphs_w: DMA(%d) Memory Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Memory Address Counter (Low Word) Write: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, data, mem_mask);
m_dma.channel[(offset - 0x2000) / 32].memory_address_counter &= ~mem_mask; m_dma.channel[(offset - 0x2000) / 32].memory_address_counter &= ~mem_mask;
m_dma.channel[(offset - 0x2000) / 32].memory_address_counter |= data; m_dma.channel[(offset - 0x2000) / 32].memory_address_counter |= data;
break; break;
case 0x4014/2: case 0x4014/2:
case 0x4054/2: case 0x4054/2:
verboselog(*this, 2, "periphs_w: DMA(%d) Device Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Device Address Counter (High Word) Write: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, data, mem_mask);
m_dma.channel[(offset - 0x2000) / 32].device_address_counter &= ~(mem_mask << 16); m_dma.channel[(offset - 0x2000) / 32].device_address_counter &= ~(mem_mask << 16);
m_dma.channel[(offset - 0x2000) / 32].device_address_counter |= data << 16; m_dma.channel[(offset - 0x2000) / 32].device_address_counter |= data << 16;
break; break;
case 0x4016/2: case 0x4016/2:
case 0x4056/2: case 0x4056/2:
verboselog(*this, 2, "periphs_w: DMA(%d) Device Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); LOGMASKED(LOG_DMA, "%s: DMA(%d) Device Address Counter (Low Word) Write: %04x & %04x\n", machine().describe_context(), (offset - 0x2000) / 32, data, mem_mask);
m_dma.channel[(offset - 0x2000) / 32].device_address_counter &= ~mem_mask; m_dma.channel[(offset - 0x2000) / 32].device_address_counter &= ~mem_mask;
m_dma.channel[(offset - 0x2000) / 32].device_address_counter |= data; m_dma.channel[(offset - 0x2000) / 32].device_address_counter |= data;
break; break;
@ -1338,12 +1148,12 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
case 0x8000/2: // Status / Control register case 0x8000/2: // Status / Control register
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ // Control { // Control
verboselog(*this, 2, "periphs_w: MMU Control: %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_MMU, "%s: MMU Control Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
m_mmu.control = data & 0x00ff; m_mmu.control = data & 0x00ff;
} // Status } // Status
else else
{ {
verboselog(*this, 0, "periphs_w: MMU Status (invalid): %04x & %04x\n", data, mem_mask); LOGMASKED(LOG_MMU, "%s: MMU Status (invalid) Write: %04x & %04x\n", machine().describe_context(), data, mem_mask);
} }
break; break;
case 0x8040/2: case 0x8040/2:
@ -1354,7 +1164,7 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
case 0x8068/2: case 0x8068/2:
case 0x8070/2: case 0x8070/2:
case 0x8078/2: // Attributes (SD0-7) case 0x8078/2: // Attributes (SD0-7)
verboselog(*this, 2, "periphs_w: MMU descriptor %d attributes: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask); LOGMASKED(LOG_MMU, "%s: MMU descriptor %d attributes Write: %04x & %04x\n", machine().describe_context(), (offset - 0x4020) / 4, data, mem_mask);
COMBINE_DATA(&m_mmu.desc[(offset - 0x4020) / 4].attr); COMBINE_DATA(&m_mmu.desc[(offset - 0x4020) / 4].attr);
break; break;
case 0x8042/2: case 0x8042/2:
@ -1365,7 +1175,7 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
case 0x806a/2: case 0x806a/2:
case 0x8072/2: case 0x8072/2:
case 0x807a/2: // Segment Length (SD0-7) case 0x807a/2: // Segment Length (SD0-7)
verboselog(*this, 2, "periphs_w: MMU descriptor %d length: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask); LOGMASKED(LOG_MMU, "%s: MMU descriptor %d length Write: %04x & %04x\n", machine().describe_context(), (offset - 0x4020) / 4, data, mem_mask);
COMBINE_DATA(&m_mmu.desc[(offset - 0x4020) / 4].length); COMBINE_DATA(&m_mmu.desc[(offset - 0x4020) / 4].length);
break; break;
case 0x8044/2: case 0x8044/2:
@ -1378,7 +1188,7 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
case 0x807c/2: // Segment Number (SD0-7, A0=1 only) case 0x807c/2: // Segment Number (SD0-7, A0=1 only)
if (ACCESSING_BITS_0_7) if (ACCESSING_BITS_0_7)
{ {
verboselog(*this, 2, "periphs_w: MMU descriptor %d segment: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask); LOGMASKED(LOG_MMU, "%s: MMU descriptor %d segment Write: %04x & %04x\n", machine().describe_context(), (offset - 0x4020) / 4, data, mem_mask);
m_mmu.desc[(offset - 0x4020) / 4].segment = data & 0x00ff; m_mmu.desc[(offset - 0x4020) / 4].segment = data & 0x00ff;
} }
break; break;
@ -1390,11 +1200,11 @@ WRITE16_MEMBER( scc68070_device::periphs_w )
case 0x806e/2: case 0x806e/2:
case 0x8076/2: case 0x8076/2:
case 0x807e/2: // Base Address (SD0-7) case 0x807e/2: // Base Address (SD0-7)
verboselog(*this, 2, "periphs_w: MMU descriptor %d base: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask); LOGMASKED(LOG_MMU, "%s: MMU descriptor %d base Write: %04x & %04x\n", machine().describe_context(), (offset - 0x4020) / 4, data, mem_mask);
COMBINE_DATA(&m_mmu.desc[(offset - 0x4020) / 4].base); COMBINE_DATA(&m_mmu.desc[(offset - 0x4020) / 4].base);
break; break;
default: default:
verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); LOGMASKED(LOG_UNKNOWN, "%s: Unknown Register Write: %04x = %04x & %04x\n", machine().describe_context(), offset * 2, data, mem_mask);
break; break;
} }
} }

22
src/devices/machine/scc68070.h
View File

@ -139,6 +139,7 @@ public:
auto iack4_callback() { return m_iack4_callback.bind(); } auto iack4_callback() { return m_iack4_callback.bind(); }
auto iack5_callback() { return m_iack5_callback.bind(); } auto iack5_callback() { return m_iack5_callback.bind(); }
auto iack7_callback() { return m_iack7_callback.bind(); } auto iack7_callback() { return m_iack7_callback.bind(); }
auto uart_tx_callback() { return m_uart_tx_callback.bind(); }
DECLARE_WRITE_LINE_MEMBER(in2_w); DECLARE_WRITE_LINE_MEMBER(in2_w);
DECLARE_WRITE_LINE_MEMBER(in4_w); DECLARE_WRITE_LINE_MEMBER(in4_w);
@ -149,14 +150,6 @@ public:
// external callbacks // external callbacks
void uart_rx(uint8_t data); void uart_rx(uint8_t data);
void uart_tx(uint8_t data);
// UART Access for Quizard
void set_quizard_mcu_value(uint16_t value);
void set_quizard_mcu_ack(uint8_t ack);
void quizard_rx(uint8_t data);
void mcu_frame();
TIMER_CALLBACK_MEMBER( timer0_callback ); TIMER_CALLBACK_MEMBER( timer0_callback );
TIMER_CALLBACK_MEMBER( rx_callback ); TIMER_CALLBACK_MEMBER( rx_callback );
@ -285,6 +278,7 @@ private:
void uart_rx_check(); void uart_rx_check();
void uart_tx_check(); void uart_tx_check();
void uart_tx(uint8_t data);
void set_timer_callback(int channel); void set_timer_callback(int channel);
// callbacks // callbacks
@ -292,14 +286,9 @@ private:
devcb_read8 m_iack4_callback; devcb_read8 m_iack4_callback;
devcb_read8 m_iack5_callback; devcb_read8 m_iack5_callback;
devcb_read8 m_iack7_callback; devcb_read8 m_iack7_callback;
devcb_write8 m_uart_tx_callback;
// internal state // internal state
uint16_t m_seeds[10];
uint8_t m_state[8];
uint16_t m_mcu_value;
uint8_t m_mcu_ack;
uint8_t m_ipl; uint8_t m_ipl;
int m_in2_line; int m_in2_line;
int m_in4_line; int m_in4_line;
@ -321,11 +310,6 @@ private:
timer_regs_t m_timers; timer_regs_t m_timers;
dma_regs_t m_dma; dma_regs_t m_dma;
mmu_regs_t m_mmu; mmu_regs_t m_mmu;
// non-static internal members
void quizard_calculate_state();
void quizard_set_seeds(uint8_t *rx);
void quizard_handle_byte_tx();
}; };
// device type definition // device type definition

206
src/mame/drivers/cdi.cpp
View File

@ -178,7 +178,7 @@ INPUT_CHANGED_MEMBER(cdi_state::mcu_input)
if(send) if(send)
{ {
uint8_t data = (uint8_t)((uintptr_t)param & 0x000000ff); uint8_t data = (uint8_t)((uintptr_t)param & 0x000000ff);
m_maincpu->quizard_rx(data); quizard_rx(data);
} }
} }
@ -264,10 +264,9 @@ static INPUT_PORTS_START( quizard )
INPUT_PORTS_END INPUT_PORTS_END
INTERRUPT_GEN_MEMBER( cdi_state::mcu_frame ) /***************************
{ * Machine Initialization *
m_maincpu->mcu_frame(); ***************************/
}
MACHINE_RESET_MEMBER( cdi_state, cdimono1 ) MACHINE_RESET_MEMBER( cdi_state, cdimono1 )
{ {
@ -276,6 +275,12 @@ MACHINE_RESET_MEMBER( cdi_state, cdimono1 )
memcpy(dst, src, 0x8); memcpy(dst, src, 0x8);
memset(m_servo_io_regs, 0, 0x20); memset(m_servo_io_regs, 0, 0x20);
memset(m_slave_io_regs, 0, 0x20); memset(m_slave_io_regs, 0, 0x20);
// Quizard Protection HLE data
memset(m_seeds, 0, 10 * sizeof(uint16_t));
memset(m_state, 0, 8 * sizeof(uint8_t));
m_mcu_value = 0;
m_mcu_ack = 0;
} }
MACHINE_RESET_MEMBER( cdi_state, cdimono2 ) MACHINE_RESET_MEMBER( cdi_state, cdimono2 )
@ -291,8 +296,8 @@ MACHINE_RESET_MEMBER( cdi_state, quizard1 )
{ {
MACHINE_RESET_CALL_MEMBER( cdimono1 ); MACHINE_RESET_CALL_MEMBER( cdimono1 );
m_maincpu->set_quizard_mcu_value(0x021f); set_quizard_mcu_value(0x021f);
m_maincpu->set_quizard_mcu_ack(0x5a); set_quizard_mcu_ack(0x5a);
} }
MACHINE_RESET_MEMBER( cdi_state, quizard2 ) MACHINE_RESET_MEMBER( cdi_state, quizard2 )
@ -303,30 +308,194 @@ MACHINE_RESET_MEMBER( cdi_state, quizard2 )
// 0x001: French // 0x001: French
// 0x188: German // 0x188: German
m_maincpu->set_quizard_mcu_value(0x188); set_quizard_mcu_value(0x188);
m_maincpu->set_quizard_mcu_ack(0x59); set_quizard_mcu_ack(0x59);
} }
MACHINE_RESET_MEMBER( cdi_state, quizard3 ) MACHINE_RESET_MEMBER( cdi_state, quizard3 )
{ {
MACHINE_RESET_CALL_MEMBER( cdimono1 ); MACHINE_RESET_CALL_MEMBER( cdimono1 );
m_maincpu->set_quizard_mcu_value(0x00ae); set_quizard_mcu_value(0x00ae);
m_maincpu->set_quizard_mcu_ack(0x58); set_quizard_mcu_ack(0x58);
} }
MACHINE_RESET_MEMBER( cdi_state, quizard4 ) MACHINE_RESET_MEMBER( cdi_state, quizard4 )
{ {
MACHINE_RESET_CALL_MEMBER( cdimono1 ); MACHINE_RESET_CALL_MEMBER( cdimono1 );
//m_maincpu->set_quizard_mcu_value(0x0139); set_quizard_mcu_value(0x011f);
m_maincpu->set_quizard_mcu_value(0x011f); set_quizard_mcu_ack(0x57);
m_maincpu->set_quizard_mcu_ack(0x57);
} }
/***************************
* Quizard Protection HLE *
***************************/
void cdi_state::set_quizard_mcu_ack(uint8_t ack)
{
m_mcu_ack = ack;
}
void cdi_state::set_quizard_mcu_value(uint16_t value)
{
m_mcu_value = value;
}
void cdi_state::quizard_rx(uint8_t data)
{
m_maincpu->uart_rx(0x5a);
m_maincpu->uart_rx(data);
}
void cdi_state::quizard_set_seeds(uint8_t *rx)
{
m_seeds[0] = (rx[1] << 8) | rx[0];
m_seeds[1] = (rx[3] << 8) | rx[2];
m_seeds[2] = (rx[5] << 8) | rx[4];
m_seeds[3] = (rx[7] << 8) | rx[6];
m_seeds[4] = (rx[9] << 8) | rx[8];
m_seeds[5] = (rx[11] << 8) | rx[10];
m_seeds[6] = (rx[13] << 8) | rx[12];
m_seeds[7] = (rx[15] << 8) | rx[14];
m_seeds[8] = (rx[17] << 8) | rx[16];
m_seeds[9] = (rx[19] << 8) | rx[18];
}
void cdi_state::quizard_calculate_state()
{
//const uint16_t desired_bitfield = mcu_value;
const uint16_t field0 = 0x00ff;
const uint16_t field1 = m_mcu_value ^ 0x00ff;
uint16_t total0 = 0;
uint16_t total1 = 0;
for(int index = 0; index < 10; index++)
{
if (field0 & (1 << index))
{
total0 += m_seeds[index];
}
if (field1 & (1 << index))
{
total1 += m_seeds[index];
}
}
uint16_t hi0 = (total0 >> 8) + 0x40;
m_state[2] = hi0 / 2;
m_state[3] = hi0 - m_state[2];
uint16_t lo0 = (total0 & 0x00ff) + 0x40;
m_state[0] = lo0 / 2;
m_state[1] = lo0 - m_state[0];
uint16_t hi1 = (total1 >> 8) + 0x40;
m_state[6] = hi1 / 2;
m_state[7] = hi1 - m_state[6];
uint16_t lo1 = (total1 & 0x00ff) + 0x40;
m_state[4] = lo1 / 2;
m_state[5] = lo1 - m_state[4];
}
void cdi_state::quizard_handle_byte_tx(uint8_t data)
{
static int state = 0;
static uint8_t rx[0x100];
static uint8_t rx_ptr = 0xff;
switch (state)
{
case 0: // Waiting for a leadoff byte
if (data == m_mcu_ack) // Sequence end
{
//scc68070_uart_rx(machine, scc68070, 0x5a);
//scc68070_uart_rx(machine, scc68070, 0x42);
}
else
{
switch (data)
{
case 0x44: // DATABASEPATH = **_DATABASE/
rx[0] = 0x44;
rx_ptr = 1;
state = 3;
break;
case 0x2e: // Unknown; ignored
break;
case 0x56: // Seed start
rx_ptr = 0;
state = 1;
break;
default:
//printf("Unknown leadoff byte: %02x\n", data);
break;
}
}
break;
case 1: // Receiving the seed
rx[rx_ptr] = data;
rx_ptr++;
if (rx_ptr == 20)
{
//printf("Calculating seeds\n");
quizard_set_seeds(rx);
quizard_calculate_state();
state = 2;
}
break;
case 2: // Receiving the seed acknowledge
case 4:
if (data == m_mcu_ack)
{
if (state == 2)
{
state = 4;
}
else
{
state = 0;
}
//printf("Sending seed ack\n");
m_maincpu->uart_rx(0x5a);
m_maincpu->uart_rx(m_state[0]);
m_maincpu->uart_rx(m_state[1]);
m_maincpu->uart_rx(m_state[2]);
m_maincpu->uart_rx(m_state[3]);
m_maincpu->uart_rx(m_state[4]);
m_maincpu->uart_rx(m_state[5]);
m_maincpu->uart_rx(m_state[6]);
m_maincpu->uart_rx(m_state[7]);
}
break;
case 3: // Receiving the database path
rx[rx_ptr] = data;
rx_ptr++;
if (data == 0x0a)
{
/*rx[rx_ptr] = 0;
//printf("Database path: %s\n", rx);
scc68070_uart_rx(machine, scc68070, 0x5a);
scc68070_uart_rx(machine, scc68070, g_state[0]);
scc68070_uart_rx(machine, scc68070, g_state[1]);
scc68070_uart_rx(machine, scc68070, g_state[2]);
scc68070_uart_rx(machine, scc68070, g_state[3]);
scc68070_uart_rx(machine, scc68070, g_state[4]);
scc68070_uart_rx(machine, scc68070, g_state[5]);
scc68070_uart_rx(machine, scc68070, g_state[6]);
scc68070_uart_rx(machine, scc68070, g_state[7]);*/
state = 0;
}
break;
}
}
/************************** /**************************
* 68HC05 Handlers * * 68HC05 Handlers *
@ -981,13 +1150,14 @@ void cdi_state::quizard(machine_config &config)
{ {
cdimono1_base(config); cdimono1_base(config);
m_maincpu->set_addrmap(AS_PROGRAM, &cdi_state::cdimono1_mem); m_maincpu->set_addrmap(AS_PROGRAM, &cdi_state::cdimono1_mem);
m_maincpu->set_vblank_int("screen", FUNC(cdi_state::mcu_frame)); m_maincpu->uart_tx_callback().set(FUNC(cdi_state::quizard_handle_byte_tx));
} }
READ8_MEMBER( cdi_state::quizard_mcu_p1_r ) READ8_MEMBER( cdi_state::quizard_mcu_p1_r )
{ {
return machine().rand(); LOG("%s: MCU Port 1 Read\n", machine().describe_context());
return 0;
} }
void cdi_state::quizard1(machine_config &config) void cdi_state::quizard1(machine_config &config)

16
src/mame/includes/cdi.h
View File

@ -113,6 +113,7 @@ public:
void draw_lcd(int y); void draw_lcd(int y);
uint32_t screen_update_cdimono1_lcd(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); uint32_t screen_update_cdimono1_lcd(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
void cdimono1(machine_config &config); void cdimono1(machine_config &config);
void cdimono2(machine_config &config); void cdimono2(machine_config &config);
void quizard4(machine_config &config); void quizard4(machine_config &config);
@ -122,12 +123,27 @@ public:
void quizard3(machine_config &config); void quizard3(machine_config &config);
void quizard1(machine_config &config); void quizard1(machine_config &config);
void quizard(machine_config &config); void quizard(machine_config &config);
void cdi910_mem(address_map &map); void cdi910_mem(address_map &map);
void cdimono1_mem(address_map &map); void cdimono1_mem(address_map &map);
void cdimono2_mem(address_map &map); void cdimono2_mem(address_map &map);
void cdimono2_servo_mem(address_map &map); void cdimono2_servo_mem(address_map &map);
void cdimono2_slave_mem(address_map &map); void cdimono2_slave_mem(address_map &map);
void cdi070_cpuspace(address_map &map); void cdi070_cpuspace(address_map &map);
// Quizard Protection HLE
void set_quizard_mcu_value(uint16_t value);
void set_quizard_mcu_ack(uint8_t ack);
void quizard_rx(uint8_t data);
void quizard_calculate_state();
void quizard_set_seeds(uint8_t *rx);
void quizard_handle_byte_tx(uint8_t data);
uint16_t m_seeds[10];
uint8_t m_state[8];
uint16_t m_mcu_value;
uint8_t m_mcu_ack;
}; };
#endif // MAME_INCLUDES_CDI_H #endif // MAME_INCLUDES_CDI_H

151
src/osd/osdcore.h
View File

@ -864,6 +864,157 @@ enum osd_output_channel
OSD_OUTPUT_CHANNEL_COUNT OSD_OUTPUT_CHANNEL_COUNT
}; };
class osd_gpu
{
public:
osd_gpu() { }
virtual ~osd_gpu() { }
typedef uint64_t handle_t;
class vertex_decl
{
public:
enum attr_type : uint32_t
{
FLOAT32,
FLOAT16,
UINT32,
UINT16,
UINT8,
MAX_TYPES
};
static constexpr size_t TYPE_SIZES[MAX_TYPES] = { 4, 2, 4, 2, 1 };
static constexpr uint32_t MAX_COLORS = 2;
static constexpr uint32_t MAX_TEXCOORDS = 8;
enum attr_usage : uint32_t
{
POSITION,
COLOR,
TEXCOORD = COLOR + MAX_COLORS,
NORMAL = TEXCOORD + MAX_TEXCOORDS,
BINORMAL,
TANGENT,
MAX_ATTRS
};
class attr_entry
{
public:
attr_entry() : m_usage(POSITION), m_type(FLOAT32), m_count(3), m_size(12) { }
attr_entry(attr_usage usage, attr_type type, size_t count) : m_usage(usage), m_type(type), m_count(count), m_size(TYPE_SIZES[type] * count) { }
attr_usage usage() const { return m_usage; }
attr_type type() const { return m_type; }
size_t count() const { return m_count; }
size_t size() const { return m_size; }
private:
attr_usage m_usage;
attr_type m_type;
size_t m_count;
size_t m_size;
};
vertex_decl()
: m_entry_count(0)
, m_size(0)
{
}
vertex_decl & add_attr(attr_usage usage, attr_type type, size_t count)
{
m_entries[m_entry_count] = attr_entry(usage, type, count);
m_size += m_entries[m_entry_count].size();
m_entry_count++;
return *this;
}
size_t entry_count() const { return m_entry_count; }
size_t size() const { return m_size; }
const attr_entry &entry(const uint32_t index) const { return m_entries[index]; }
protected:
attr_entry m_entries[MAX_ATTRS];
size_t m_entry_count;
size_t m_size;
};
class vertex_buffer_interface
{
public:
vertex_buffer_interface(vertex_decl &decl, uint32_t flags)
: m_decl(decl)
, m_flags(flags)
{
}
virtual ~vertex_buffer_interface() {}
const vertex_decl &decl() const { return m_decl; }
uint32_t flags() const { return m_flags; }
handle_t handle() { return m_handle; }
virtual size_t count() const = 0;
virtual size_t size() const = 0;
virtual void upload() = 0;
protected:
const vertex_decl &m_decl;
const uint32_t m_flags;
handle_t m_handle;
};
class static_vertex_buffer_interface : public vertex_buffer_interface
{
public:
enum vertex_buffer_flags : uint32_t
{
RETAIN_ON_CPU = 0x00000001
};
static_vertex_buffer_interface(vertex_decl &decl, size_t count, uint32_t flags)
: vertex_buffer_interface(decl, flags)
, m_count(count)
, m_size(decl.size() * count)
{
}
virtual ~static_vertex_buffer_interface()
{
if (m_data)
delete [] m_data;
}
size_t count() const override { return m_count; }
size_t size() const override { return m_size; }
void set_data(void *data)
{
allocate_if_needed();
memcpy(m_data, data, m_size);
}
protected:
void allocate_if_needed()
{
if ((m_flags & RETAIN_ON_CPU) != 0 && m_data == nullptr)
m_data = new uint8_t[m_size];
}
const size_t m_count;
const size_t m_size;
uint8_t *m_data;
};
virtual void bind_buffer(vertex_buffer_interface *vb) = 0;
virtual void unbind_buffer(vertex_buffer_interface *vb) = 0;
};
class osd_output class osd_output
{ {
public: public: