diff --git a/src/emu/cpu/mcs48/mcs48.c b/src/emu/cpu/mcs48/mcs48.c index 9df18d0afd5..ce3783120f4 100644 --- a/src/emu/cpu/mcs48/mcs48.c +++ b/src/emu/cpu/mcs48/mcs48.c @@ -113,143 +113,239 @@ T0 output clock -/*************************************************************************** - TYPE DEFINITIONS -***************************************************************************/ - -/* live processor state */ -struct mcs48_state -{ - UINT16 prevpc; /* 16-bit previous program counter */ - UINT16 pc; /* 16-bit program counter */ - - UINT8 a; /* 8-bit accumulator */ - UINT8 * regptr; /* pointer to r0-r7 */ - UINT8 psw; /* 8-bit cpustate->psw */ - UINT8 p1; /* 8-bit latched port 1 */ - UINT8 p2; /* 8-bit latched port 2 */ - UINT8 ea; /* 1-bit latched ea input */ - UINT8 timer; /* 8-bit timer */ - UINT8 prescaler; /* 5-bit timer prescaler */ - UINT8 t1_history; /* 8-bit history of the T1 input */ - UINT8 sts; /* 8-bit status register (UPI-41 only, except for F1) */ - UINT8 dbbi; /* 8-bit input data buffer (UPI-41 only) */ - UINT8 dbbo; /* 8-bit output data buffer (UPI-41 only) */ - - UINT8 irq_state; /* TRUE if an IRQ is pending */ - UINT8 irq_in_progress; /* TRUE if an IRQ is in progress */ - UINT8 timer_overflow; /* TRUE on a timer overflow; cleared by taking interrupt */ - UINT8 timer_flag; /* TRUE on a timer overflow; cleared on JTF */ - UINT8 tirq_enabled; /* TRUE if the timer IRQ is enabled */ - UINT8 xirq_enabled; /* TRUE if the external IRQ is enabled */ - UINT8 timecount_enabled; /* bitmask of timer/counter enabled */ - UINT8 flags_enabled; /* TRUE if I/O flags have been enabled (UPI-41 only) */ - UINT8 dma_enabled; /* TRUE if DMA has been enabled (UPI-41 only) */ - - UINT16 a11; /* A11 value, either 0x000 or 0x800 */ - - device_irq_acknowledge_callback irq_callback; - legacy_cpu_device *device; - int icount; - - /* Memory spaces */ - address_space *program; - direct_read_data *direct; - address_space *data; - address_space *io; - - UINT8 feature_mask; /* processor feature flags */ - UINT16 int_rom_size; /* internal rom size */ - - UINT8 rtemp; /* temporary for import/export */ -}; - - -/* opcode table entry */ -typedef int (*mcs48_ophandler)(mcs48_state *state); - - - /*************************************************************************** MACROS ***************************************************************************/ /* ROM is mapped to AS_PROGRAM */ -#define program_r(a) cpustate->program->read_byte(a) +#define program_r(a) m_program->read_byte(a) /* RAM is mapped to AS_DATA */ -#define ram_r(a) cpustate->data->read_byte(a) -#define ram_w(a,V) cpustate->data->write_byte(a, V) +#define ram_r(a) m_data->read_byte(a) +#define ram_w(a,V) m_data->write_byte(a, V) /* ports are mapped to AS_IO */ -#define ext_r(a) cpustate->io->read_byte(a) -#define ext_w(a,V) cpustate->io->write_byte(a, V) -#define port_r(a) cpustate->io->read_byte(MCS48_PORT_P0 + a) -#define port_w(a,V) cpustate->io->write_byte(MCS48_PORT_P0 + a, V) -#define test_r(a) cpustate->io->read_byte(MCS48_PORT_T0 + a) -#define test_w(a,V) cpustate->io->write_byte(MCS48_PORT_T0 + a, V) -#define bus_r() cpustate->io->read_byte(MCS48_PORT_BUS) -#define bus_w(V) cpustate->io->write_byte(MCS48_PORT_BUS, V) -#define ea_r() cpustate->io->read_byte(MCS48_PORT_EA) -#define prog_w(V) cpustate->io->write_byte(MCS48_PORT_PROG, V) +#define ext_r(a) m_io->read_byte(a) +#define ext_w(a,V) m_io->write_byte(a, V) +#define port_r(a) m_io->read_byte(MCS48_PORT_P0 + a) +#define port_w(a,V) m_io->write_byte(MCS48_PORT_P0 + a, V) +#define test_r(a) m_io->read_byte(MCS48_PORT_T0 + a) +#define test_w(a,V) m_io->write_byte(MCS48_PORT_T0 + a, V) +#define bus_r() m_io->read_byte(MCS48_PORT_BUS) +#define bus_w(V) m_io->write_byte(MCS48_PORT_BUS, V) +#define ea_r() m_io->read_byte(MCS48_PORT_EA) +#define prog_w(V) m_io->write_byte(MCS48_PORT_PROG, V) /* r0-r7 map to memory via the regptr */ -#define R0 regptr[0] -#define R1 regptr[1] -#define R2 regptr[2] -#define R3 regptr[3] -#define R4 regptr[4] -#define R5 regptr[5] -#define R6 regptr[6] -#define R7 regptr[7] +#define R0 m_regptr[0] +#define R1 m_regptr[1] +#define R2 m_regptr[2] +#define R3 m_regptr[3] +#define R4 m_regptr[4] +#define R5 m_regptr[5] +#define R6 m_regptr[6] +#define R7 m_regptr[7] +const device_type I8021 = &device_creator; +const device_type I8022 = &device_creator; +const device_type I8035 = &device_creator; +const device_type I8048 = &device_creator; +const device_type I8648 = &device_creator; +const device_type I8748 = &device_creator; +const device_type I8039 = &device_creator; +const device_type I8049 = &device_creator; +const device_type I8749 = &device_creator; +const device_type I8040 = &device_creator; +const device_type I8050 = &device_creator; +const device_type I8041 = &device_creator; +const device_type I8741 = &device_creator; +const device_type I8042 = &device_creator; +const device_type I8242 = &device_creator; +const device_type I8742 = &device_creator; +const device_type MB8884 = &device_creator; +const device_type N7751 = &device_creator; +const device_type M58715 = &device_creator; + + /*************************************************************************** - FUNCTION PROTOTYPES + ADDRESS MAPS ***************************************************************************/ -static int check_irqs(mcs48_state *cpustate); +/* FIXME: the memory maps should probably support rom banking for EA */ +static ADDRESS_MAP_START(program_10bit, AS_PROGRAM, 8, mcs48_cpu_device) + AM_RANGE(0x000, 0x3ff) AM_ROM +ADDRESS_MAP_END + +static ADDRESS_MAP_START(program_11bit, AS_PROGRAM, 8, mcs48_cpu_device) + AM_RANGE(0x000, 0x7ff) AM_ROM +ADDRESS_MAP_END + +static ADDRESS_MAP_START(program_12bit, AS_PROGRAM, 8, mcs48_cpu_device) + AM_RANGE(0x000, 0xfff) AM_ROM +ADDRESS_MAP_END + +static ADDRESS_MAP_START(data_6bit, AS_DATA, 8, mcs48_cpu_device) + AM_RANGE(0x00, 0x3f) AM_RAM +ADDRESS_MAP_END + +static ADDRESS_MAP_START(data_7bit, AS_DATA, 8, mcs48_cpu_device) + AM_RANGE(0x00, 0x7f) AM_RAM +ADDRESS_MAP_END + +static ADDRESS_MAP_START(data_8bit, AS_DATA, 8, mcs48_cpu_device) + AM_RANGE(0x00, 0xff) AM_RAM +ADDRESS_MAP_END +mcs48_cpu_device::mcs48_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int rom_size, int ram_size, UINT8 feature_mask) + : cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__) + , m_program_config("program", ENDIANNESS_LITTLE, 8, 12, 0 + , ( ( rom_size == 1024 ) ? ADDRESS_MAP_NAME(program_10bit) : ( ( rom_size == 2048 ) ? ADDRESS_MAP_NAME(program_11bit) : ( ( rom_size == 4096 ) ? ADDRESS_MAP_NAME(program_12bit) : NULL ) ) )) + , m_data_config("data", ENDIANNESS_LITTLE, 8, ( ( ram_size == 64 ) ? 6 : ( ( ram_size == 128 ) ? 7 : 8 ) ), 0 + , ( ( ram_size == 64 ) ? ADDRESS_MAP_NAME(data_6bit) : ( ( ram_size == 128 ) ? ADDRESS_MAP_NAME(data_7bit) : ADDRESS_MAP_NAME(data_8bit) ) )) + , m_io_config("io", ENDIANNESS_LITTLE, 8, 9, 0) + , m_feature_mask(feature_mask) + , m_int_rom_size(rom_size) +{ + // Sanity checks + if ( ram_size != 64 && ram_size != 128 && ram_size != 256 ) + { + fatalerror("mcs48: Invalid RAM size\n"); + } + + if ( rom_size != 0 && rom_size != 1024 && rom_size != 2048 && rom_size != 4096 ) + { + fatalerror("mcs48: Invalid ROM size\n"); + } +} + +i8021_device::i8021_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, I8021, "I8021", tag, owner, clock, "i8021", 1024, 64) +{ +} + +i8022_device::i8022_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, I8022, "I8022", tag, owner, clock, "i8022", 2048, 128) +{ +} + +i8035_device::i8035_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, I8035, "I8035", tag, owner, clock, "i8035", 0, 64) +{ +} + +i8048_device::i8048_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, I8048, "I8048", tag, owner, clock, "i8048", 1024, 64) +{ +} + +i8648_device::i8648_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, I8648, "I8648", tag, owner, clock, "i8648", 1024, 64) +{ +} + +i8748_device::i8748_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, I8748, "I8748", tag, owner, clock, "i8748", 1024, 64) +{ +} + +i8039_device::i8039_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, I8039, "I8039", tag, owner, clock, "i8039", 0, 128) +{ +} + +i8049_device::i8049_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, I8049, "I8049", tag, owner, clock, "i8049", 2048, 128) +{ +} + +i8749_device::i8749_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, I8749, "I8749", tag, owner, clock, "i8749", 2048, 128) +{ +} + +i8040_device::i8040_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, I8040, "I8040", tag, owner, clock, "i8040", 0, 256) +{ +} + +i8050_device::i8050_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, I8050, "I8050", tag, owner, clock, "i8050", 4096, 256) +{ +} + +mb8884_device::mb8884_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, MB8884, "MB8884", tag, owner, clock, "mb8884", 0, 64) +{ +} + +n7751_device::n7751_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, N7751, "N7751", tag, owner, clock, "n7751", 1024, 64) +{ +} + +m58715_device::m58715_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mcs48_cpu_device(mconfig, M58715, "M58715", tag, owner, clock, "m58715", 2048, 128) +{ +} + +upi41_cpu_device::upi41_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int rom_size, int ram_size) + : mcs48_cpu_device(mconfig, type, name, tag, owner, clock, shortname, rom_size, ram_size, UPI41_FEATURE) +{ +} + +i8041_device::i8041_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : upi41_cpu_device(mconfig, I8041, "I8041", tag, owner, clock, "i8041", 1024, 128) +{ +} + +i8741_device::i8741_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : upi41_cpu_device(mconfig, I8741, "I8741", tag, owner, clock, "i8741", 1024, 128) +{ +} + +i8042_device::i8042_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : upi41_cpu_device(mconfig, I8042, "I8042", tag, owner, clock, "i8042", 2048, 256) +{ +} + +i8242_device::i8242_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : upi41_cpu_device(mconfig, I8242, "I8242", tag, owner, clock, "i8242", 2048, 256) +{ +} + +i8742_device::i8742_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : upi41_cpu_device(mconfig, I8742, "I8742", tag, owner, clock, "i8742", 2048, 256) +{ +} + + +offs_t mcs48_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + extern CPU_DISASSEMBLE( mcs48 ); + return CPU_DISASSEMBLE_NAME(mcs48)(this, buffer, pc, oprom, opram, options); +} + + +offs_t upi41_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + extern CPU_DISASSEMBLE( upi41 ); + return CPU_DISASSEMBLE_NAME(upi41)(this, buffer, pc, oprom, opram, options); +} /*************************************************************************** INLINE FUNCTIONS ***************************************************************************/ -INLINE mcs48_state *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == I8021 || - device->type() == I8022 || - device->type() == I8035 || - device->type() == I8048 || - device->type() == I8648 || - device->type() == I8748 || - device->type() == I8039 || - device->type() == I8049 || - device->type() == I8749 || - device->type() == I8040 || - device->type() == I8050 || - device->type() == I8041 || - device->type() == I8741 || - device->type() == I8042 || - device->type() == I8242 || - device->type() == I8742 || - device->type() == MB8884 || - device->type() == N7751 || - device->type() == M58715); - return (mcs48_state *)downcast(device)->token(); -} - - /*------------------------------------------------- opcode_fetch - fetch an opcode byte -------------------------------------------------*/ -INLINE UINT8 opcode_fetch(mcs48_state *cpustate) +UINT8 mcs48_cpu_device::opcode_fetch() { - return cpustate->direct->read_decrypted_byte(cpustate->pc++); + return m_direct->read_decrypted_byte(m_pc++); } @@ -258,9 +354,9 @@ INLINE UINT8 opcode_fetch(mcs48_state *cpustate) byte -------------------------------------------------*/ -INLINE UINT8 argument_fetch(mcs48_state *cpustate) +UINT8 mcs48_cpu_device::argument_fetch() { - return cpustate->direct->read_raw_byte(cpustate->pc++); + return m_direct->read_raw_byte(m_pc++); } @@ -269,23 +365,23 @@ INLINE UINT8 argument_fetch(mcs48_state *cpustate) point to the appropriate register bank -------------------------------------------------*/ -INLINE void update_regptr(mcs48_state *cpustate) +void mcs48_cpu_device::update_regptr() { - cpustate->regptr = (UINT8 *)cpustate->data->get_write_ptr((cpustate->psw & B_FLAG) ? 24 : 0); + m_regptr = (UINT8 *)m_data->get_write_ptr((m_psw & B_FLAG) ? 24 : 0); } /*------------------------------------------------- - push_pc_psw - push the cpustate->pc and cpustate->psw values onto + push_pc_psw - push the m_pc and m_psw values onto the stack -------------------------------------------------*/ -INLINE void push_pc_psw(mcs48_state *cpustate) +void mcs48_cpu_device::push_pc_psw() { - UINT8 sp = cpustate->psw & 0x07; - ram_w(8 + 2*sp, cpustate->pc); - ram_w(9 + 2*sp, ((cpustate->pc >> 8) & 0x0f) | (cpustate->psw & 0xf0)); - cpustate->psw = (cpustate->psw & 0xf8) | ((sp + 1) & 0x07); + UINT8 sp = m_psw & 0x07; + ram_w(8 + 2*sp, m_pc); + ram_w(9 + 2*sp, ((m_pc >> 8) & 0x0f) | (m_psw & 0xf0)); + m_psw = (m_psw & 0xf8) | ((sp + 1) & 0x07); } @@ -294,14 +390,14 @@ INLINE void push_pc_psw(mcs48_state *cpustate) the stack -------------------------------------------------*/ -INLINE void pull_pc_psw(mcs48_state *cpustate) +void mcs48_cpu_device::pull_pc_psw() { - UINT8 sp = (cpustate->psw - 1) & 0x07; - cpustate->pc = ram_r(8 + 2*sp); - cpustate->pc |= ram_r(9 + 2*sp) << 8; - cpustate->psw = ((cpustate->pc >> 8) & 0xf0) | 0x08 | sp; - cpustate->pc &= 0xfff; - update_regptr(cpustate); + UINT8 sp = (m_psw - 1) & 0x07; + m_pc = ram_r(8 + 2*sp); + m_pc |= ram_r(9 + 2*sp) << 8; + m_psw = ((m_pc >> 8) & 0xf0) | 0x08 | sp; + m_pc &= 0xfff; + update_regptr(); } @@ -310,13 +406,13 @@ INLINE void pull_pc_psw(mcs48_state *cpustate) leaving the upper part of PSW intact -------------------------------------------------*/ -INLINE void pull_pc(mcs48_state *cpustate) +void mcs48_cpu_device::pull_pc() { - UINT8 sp = (cpustate->psw - 1) & 0x07; - cpustate->pc = ram_r(8 + 2*sp); - cpustate->pc |= ram_r(9 + 2*sp) << 8; - cpustate->pc &= 0xfff; - cpustate->psw = (cpustate->psw & 0xf0) | 0x08 | sp; + UINT8 sp = (m_psw - 1) & 0x07; + m_pc = ram_r(8 + 2*sp); + m_pc |= ram_r(9 + 2*sp) << 8; + m_pc &= 0xfff; + m_psw = (m_psw & 0xf0) | 0x08 | sp; } @@ -325,15 +421,15 @@ INLINE void pull_pc(mcs48_state *cpustate) instruction -------------------------------------------------*/ -INLINE void execute_add(mcs48_state *cpustate, UINT8 dat) +void mcs48_cpu_device::execute_add(UINT8 dat) { - UINT16 temp = cpustate->a + dat; - UINT16 temp4 = (cpustate->a & 0x0f) + (dat & 0x0f); + UINT16 temp = m_a + dat; + UINT16 temp4 = (m_a & 0x0f) + (dat & 0x0f); - cpustate->psw &= ~(C_FLAG | A_FLAG); - cpustate->psw |= (temp4 << 2) & A_FLAG; - cpustate->psw |= (temp >> 1) & C_FLAG; - cpustate->a = temp; + m_psw &= ~(C_FLAG | A_FLAG); + m_psw |= (temp4 << 2) & A_FLAG; + m_psw |= (temp >> 1) & C_FLAG; + m_a = temp; } @@ -342,16 +438,16 @@ INLINE void execute_add(mcs48_state *cpustate, UINT8 dat) instruction -------------------------------------------------*/ -INLINE void execute_addc(mcs48_state *cpustate, UINT8 dat) +void mcs48_cpu_device::execute_addc(UINT8 dat) { - UINT8 carryin = (cpustate->psw & C_FLAG) >> 7; - UINT16 temp = cpustate->a + dat + carryin; - UINT16 temp4 = (cpustate->a & 0x0f) + (dat & 0x0f) + carryin; + UINT8 carryin = (m_psw & C_FLAG) >> 7; + UINT16 temp = m_a + dat + carryin; + UINT16 temp4 = (m_a & 0x0f) + (dat & 0x0f) + carryin; - cpustate->psw &= ~(C_FLAG | A_FLAG); - cpustate->psw |= (temp4 << 2) & A_FLAG; - cpustate->psw |= (temp >> 1) & C_FLAG; - cpustate->a = temp; + m_psw &= ~(C_FLAG | A_FLAG); + m_psw |= (temp4 << 2) & A_FLAG; + m_psw |= (temp >> 1) & C_FLAG; + m_a = temp; } @@ -360,10 +456,10 @@ INLINE void execute_addc(mcs48_state *cpustate, UINT8 dat) instruction -------------------------------------------------*/ -INLINE void execute_jmp(mcs48_state *cpustate, UINT16 address) +void mcs48_cpu_device::execute_jmp(UINT16 address) { - UINT16 a11 = (cpustate->irq_in_progress) ? 0 : cpustate->a11; - cpustate->pc = address | a11; + UINT16 a11 = (m_irq_in_progress) ? 0 : m_a11; + m_pc = address | a11; } @@ -372,10 +468,10 @@ INLINE void execute_jmp(mcs48_state *cpustate, UINT16 address) instruction -------------------------------------------------*/ -INLINE void execute_call(mcs48_state *cpustate, UINT16 address) +void mcs48_cpu_device::execute_call(UINT16 address) { - push_pc_psw(cpustate); - execute_jmp(cpustate, address); + push_pc_psw(); + execute_jmp(address); } @@ -384,11 +480,11 @@ INLINE void execute_call(mcs48_state *cpustate, UINT16 address) conditional jump instruction -------------------------------------------------*/ -INLINE void execute_jcc(mcs48_state *cpustate, UINT8 result) +void mcs48_cpu_device::execute_jcc(UINT8 result) { - UINT8 offset = argument_fetch(cpustate); + UINT8 offset = argument_fetch(); if (result != 0) - cpustate->pc = ((cpustate->pc - 1) & 0xf00) | offset; + m_pc = ((m_pc - 1) & 0xf00) | offset; } @@ -397,14 +493,14 @@ INLINE void execute_jcc(mcs48_state *cpustate, UINT8 result) code can directly affect -------------------------------------------------*/ -INLINE UINT8 p2_mask(mcs48_state *cpustate) +UINT8 mcs48_cpu_device::p2_mask() { UINT8 result = 0xff; - if ((cpustate->feature_mask & UPI41_FEATURE) == 0) + if ((m_feature_mask & UPI41_FEATURE) == 0) return result; - if (cpustate->flags_enabled) + if (m_flags_enabled) result &= ~(P2_OBF | P2_NIBF); - if (cpustate->dma_enabled) + if (m_dma_enabled) result &= ~(P2_DRQ | P2_NDACK); return result; } @@ -415,19 +511,19 @@ INLINE UINT8 p2_mask(mcs48_state *cpustate) the 8243 expander chip -------------------------------------------------*/ -INLINE void expander_operation(mcs48_state *cpustate, UINT8 operation, UINT8 port) +void mcs48_cpu_device::expander_operation(UINT8 operation, UINT8 port) { /* put opcode/data on low 4 bits of P2 */ - port_w(2, cpustate->p2 = (cpustate->p2 & 0xf0) | (operation << 2) | (port & 3)); + port_w(2, m_p2 = (m_p2 & 0xf0) | (operation << 2) | (port & 3)); /* generate high-to-low transition on PROG line */ prog_w(0); /* put data on low 4 bits of P2 */ if (operation != 0) - port_w(2, cpustate->p2 = (cpustate->p2 & 0xf0) | (cpustate->a & 0x0f)); + port_w(2, m_p2 = (m_p2 & 0xf0) | (m_a & 0x0f)); else - cpustate->a = port_r(2) | 0x0f; + m_a = port_r(2) | 0x0f; /* generate low-to-high transition on PROG line */ prog_w(1); @@ -439,340 +535,340 @@ INLINE void expander_operation(mcs48_state *cpustate, UINT8 operation, UINT8 por OPCODE HANDLERS ***************************************************************************/ -#define OPHANDLER(_name) static int _name(mcs48_state *cpustate) +#define OPHANDLER(_name) int mcs48_cpu_device::_name() #define SPLIT_OPHANDLER(_name, _mcs48name, _upi41name) \ -OPHANDLER(_name) { return (!(cpustate->feature_mask & UPI41_FEATURE)) ? _mcs48name(cpustate) : _upi41name(cpustate); } +OPHANDLER(_name) { return (!(m_feature_mask & UPI41_FEATURE)) ? _mcs48name() : _upi41name(); } OPHANDLER( illegal ) { - logerror("MCS-48 PC:%04X - Illegal opcode = %02x\n", cpustate->pc - 1, program_r(cpustate->pc - 1)); + logerror("MCS-48 PC:%04X - Illegal opcode = %02x\n", m_pc - 1, program_r(m_pc - 1)); return 1; } -OPHANDLER( add_a_r0 ) { execute_add(cpustate, cpustate->R0); return 1; } -OPHANDLER( add_a_r1 ) { execute_add(cpustate, cpustate->R1); return 1; } -OPHANDLER( add_a_r2 ) { execute_add(cpustate, cpustate->R2); return 1; } -OPHANDLER( add_a_r3 ) { execute_add(cpustate, cpustate->R3); return 1; } -OPHANDLER( add_a_r4 ) { execute_add(cpustate, cpustate->R4); return 1; } -OPHANDLER( add_a_r5 ) { execute_add(cpustate, cpustate->R5); return 1; } -OPHANDLER( add_a_r6 ) { execute_add(cpustate, cpustate->R6); return 1; } -OPHANDLER( add_a_r7 ) { execute_add(cpustate, cpustate->R7); return 1; } -OPHANDLER( add_a_xr0 ) { execute_add(cpustate, ram_r(cpustate->R0)); return 1; } -OPHANDLER( add_a_xr1 ) { execute_add(cpustate, ram_r(cpustate->R1)); return 1; } -OPHANDLER( add_a_n ) { execute_add(cpustate, argument_fetch(cpustate)); return 2; } +OPHANDLER( add_a_r0 ) { execute_add(R0); return 1; } +OPHANDLER( add_a_r1 ) { execute_add(R1); return 1; } +OPHANDLER( add_a_r2 ) { execute_add(R2); return 1; } +OPHANDLER( add_a_r3 ) { execute_add(R3); return 1; } +OPHANDLER( add_a_r4 ) { execute_add(R4); return 1; } +OPHANDLER( add_a_r5 ) { execute_add(R5); return 1; } +OPHANDLER( add_a_r6 ) { execute_add(R6); return 1; } +OPHANDLER( add_a_r7 ) { execute_add(R7); return 1; } +OPHANDLER( add_a_xr0 ) { execute_add(ram_r(R0)); return 1; } +OPHANDLER( add_a_xr1 ) { execute_add(ram_r(R1)); return 1; } +OPHANDLER( add_a_n ) { execute_add(argument_fetch()); return 2; } -OPHANDLER( adc_a_r0 ) { execute_addc(cpustate, cpustate->R0); return 1; } -OPHANDLER( adc_a_r1 ) { execute_addc(cpustate, cpustate->R1); return 1; } -OPHANDLER( adc_a_r2 ) { execute_addc(cpustate, cpustate->R2); return 1; } -OPHANDLER( adc_a_r3 ) { execute_addc(cpustate, cpustate->R3); return 1; } -OPHANDLER( adc_a_r4 ) { execute_addc(cpustate, cpustate->R4); return 1; } -OPHANDLER( adc_a_r5 ) { execute_addc(cpustate, cpustate->R5); return 1; } -OPHANDLER( adc_a_r6 ) { execute_addc(cpustate, cpustate->R6); return 1; } -OPHANDLER( adc_a_r7 ) { execute_addc(cpustate, cpustate->R7); return 1; } -OPHANDLER( adc_a_xr0 ) { execute_addc(cpustate, ram_r(cpustate->R0)); return 1; } -OPHANDLER( adc_a_xr1 ) { execute_addc(cpustate, ram_r(cpustate->R1)); return 1; } -OPHANDLER( adc_a_n ) { execute_addc(cpustate, argument_fetch(cpustate)); return 2; } +OPHANDLER( adc_a_r0 ) { execute_addc(R0); return 1; } +OPHANDLER( adc_a_r1 ) { execute_addc(R1); return 1; } +OPHANDLER( adc_a_r2 ) { execute_addc(R2); return 1; } +OPHANDLER( adc_a_r3 ) { execute_addc(R3); return 1; } +OPHANDLER( adc_a_r4 ) { execute_addc(R4); return 1; } +OPHANDLER( adc_a_r5 ) { execute_addc(R5); return 1; } +OPHANDLER( adc_a_r6 ) { execute_addc(R6); return 1; } +OPHANDLER( adc_a_r7 ) { execute_addc(R7); return 1; } +OPHANDLER( adc_a_xr0 ) { execute_addc(ram_r(R0)); return 1; } +OPHANDLER( adc_a_xr1 ) { execute_addc(ram_r(R1)); return 1; } +OPHANDLER( adc_a_n ) { execute_addc(argument_fetch()); return 2; } -OPHANDLER( anl_a_r0 ) { cpustate->a &= cpustate->R0; return 1; } -OPHANDLER( anl_a_r1 ) { cpustate->a &= cpustate->R1; return 1; } -OPHANDLER( anl_a_r2 ) { cpustate->a &= cpustate->R2; return 1; } -OPHANDLER( anl_a_r3 ) { cpustate->a &= cpustate->R3; return 1; } -OPHANDLER( anl_a_r4 ) { cpustate->a &= cpustate->R4; return 1; } -OPHANDLER( anl_a_r5 ) { cpustate->a &= cpustate->R5; return 1; } -OPHANDLER( anl_a_r6 ) { cpustate->a &= cpustate->R6; return 1; } -OPHANDLER( anl_a_r7 ) { cpustate->a &= cpustate->R7; return 1; } -OPHANDLER( anl_a_xr0 ) { cpustate->a &= ram_r(cpustate->R0); return 1; } -OPHANDLER( anl_a_xr1 ) { cpustate->a &= ram_r(cpustate->R1); return 1; } -OPHANDLER( anl_a_n ) { cpustate->a &= argument_fetch(cpustate); return 2; } +OPHANDLER( anl_a_r0 ) { m_a &= R0; return 1; } +OPHANDLER( anl_a_r1 ) { m_a &= R1; return 1; } +OPHANDLER( anl_a_r2 ) { m_a &= R2; return 1; } +OPHANDLER( anl_a_r3 ) { m_a &= R3; return 1; } +OPHANDLER( anl_a_r4 ) { m_a &= R4; return 1; } +OPHANDLER( anl_a_r5 ) { m_a &= R5; return 1; } +OPHANDLER( anl_a_r6 ) { m_a &= R6; return 1; } +OPHANDLER( anl_a_r7 ) { m_a &= R7; return 1; } +OPHANDLER( anl_a_xr0 ) { m_a &= ram_r(R0); return 1; } +OPHANDLER( anl_a_xr1 ) { m_a &= ram_r(R1); return 1; } +OPHANDLER( anl_a_n ) { m_a &= argument_fetch(); return 2; } -OPHANDLER( anl_bus_n ) { bus_w(bus_r() & argument_fetch(cpustate)); return 2; } -OPHANDLER( anl_p1_n ) { port_w(1, cpustate->p1 &= argument_fetch(cpustate)); return 2; } -OPHANDLER( anl_p2_n ) { port_w(2, cpustate->p2 &= argument_fetch(cpustate) | ~p2_mask(cpustate)); return 2; } -OPHANDLER( anld_p4_a ) { expander_operation(cpustate, MCS48_EXPANDER_OP_AND, 4); return 2; } -OPHANDLER( anld_p5_a ) { expander_operation(cpustate, MCS48_EXPANDER_OP_AND, 5); return 2; } -OPHANDLER( anld_p6_a ) { expander_operation(cpustate, MCS48_EXPANDER_OP_AND, 6); return 2; } -OPHANDLER( anld_p7_a ) { expander_operation(cpustate, MCS48_EXPANDER_OP_AND, 7); return 2; } +OPHANDLER( anl_bus_n ) { bus_w(bus_r() & argument_fetch()); return 2; } +OPHANDLER( anl_p1_n ) { port_w(1, m_p1 &= argument_fetch()); return 2; } +OPHANDLER( anl_p2_n ) { port_w(2, m_p2 &= argument_fetch() | ~p2_mask()); return 2; } +OPHANDLER( anld_p4_a ) { expander_operation(MCS48_EXPANDER_OP_AND, 4); return 2; } +OPHANDLER( anld_p5_a ) { expander_operation(MCS48_EXPANDER_OP_AND, 5); return 2; } +OPHANDLER( anld_p6_a ) { expander_operation(MCS48_EXPANDER_OP_AND, 6); return 2; } +OPHANDLER( anld_p7_a ) { expander_operation(MCS48_EXPANDER_OP_AND, 7); return 2; } -OPHANDLER( call_0 ) { execute_call(cpustate, argument_fetch(cpustate) | 0x000); return 2; } -OPHANDLER( call_1 ) { execute_call(cpustate, argument_fetch(cpustate) | 0x100); return 2; } -OPHANDLER( call_2 ) { execute_call(cpustate, argument_fetch(cpustate) | 0x200); return 2; } -OPHANDLER( call_3 ) { execute_call(cpustate, argument_fetch(cpustate) | 0x300); return 2; } -OPHANDLER( call_4 ) { execute_call(cpustate, argument_fetch(cpustate) | 0x400); return 2; } -OPHANDLER( call_5 ) { execute_call(cpustate, argument_fetch(cpustate) | 0x500); return 2; } -OPHANDLER( call_6 ) { execute_call(cpustate, argument_fetch(cpustate) | 0x600); return 2; } -OPHANDLER( call_7 ) { execute_call(cpustate, argument_fetch(cpustate) | 0x700); return 2; } +OPHANDLER( call_0 ) { execute_call(argument_fetch() | 0x000); return 2; } +OPHANDLER( call_1 ) { execute_call(argument_fetch() | 0x100); return 2; } +OPHANDLER( call_2 ) { execute_call(argument_fetch() | 0x200); return 2; } +OPHANDLER( call_3 ) { execute_call(argument_fetch() | 0x300); return 2; } +OPHANDLER( call_4 ) { execute_call(argument_fetch() | 0x400); return 2; } +OPHANDLER( call_5 ) { execute_call(argument_fetch() | 0x500); return 2; } +OPHANDLER( call_6 ) { execute_call(argument_fetch() | 0x600); return 2; } +OPHANDLER( call_7 ) { execute_call(argument_fetch() | 0x700); return 2; } -OPHANDLER( clr_a ) { cpustate->a = 0; return 1; } -OPHANDLER( clr_c ) { cpustate->psw &= ~C_FLAG; return 1; } -OPHANDLER( clr_f0 ) { cpustate->psw &= ~F_FLAG; cpustate->sts &= ~STS_F0; return 1; } -OPHANDLER( clr_f1 ) { cpustate->sts &= ~STS_F1; return 1; } +OPHANDLER( clr_a ) { m_a = 0; return 1; } +OPHANDLER( clr_c ) { m_psw &= ~C_FLAG; return 1; } +OPHANDLER( clr_f0 ) { m_psw &= ~F_FLAG; m_sts &= ~STS_F0; return 1; } +OPHANDLER( clr_f1 ) { m_sts &= ~STS_F1; return 1; } -OPHANDLER( cpl_a ) { cpustate->a ^= 0xff; return 1; } -OPHANDLER( cpl_c ) { cpustate->psw ^= C_FLAG; return 1; } -OPHANDLER( cpl_f0 ) { cpustate->psw ^= F_FLAG; cpustate->sts ^= STS_F0; return 1; } -OPHANDLER( cpl_f1 ) { cpustate->sts ^= STS_F1; return 1; } +OPHANDLER( cpl_a ) { m_a ^= 0xff; return 1; } +OPHANDLER( cpl_c ) { m_psw ^= C_FLAG; return 1; } +OPHANDLER( cpl_f0 ) { m_psw ^= F_FLAG; m_sts ^= STS_F0; return 1; } +OPHANDLER( cpl_f1 ) { m_sts ^= STS_F1; return 1; } OPHANDLER( da_a ) { - if ((cpustate->a & 0x0f) > 0x09 || (cpustate->psw & A_FLAG)) + if ((m_a & 0x0f) > 0x09 || (m_psw & A_FLAG)) { - cpustate->a += 0x06; - if ((cpustate->a & 0xf0) == 0x00) - cpustate->psw |= C_FLAG; + m_a += 0x06; + if ((m_a & 0xf0) == 0x00) + m_psw |= C_FLAG; } - if ((cpustate->a & 0xf0) > 0x90 || (cpustate->psw & C_FLAG)) + if ((m_a & 0xf0) > 0x90 || (m_psw & C_FLAG)) { - cpustate->a += 0x60; - cpustate->psw |= C_FLAG; + m_a += 0x60; + m_psw |= C_FLAG; } else - cpustate->psw &= ~C_FLAG; + m_psw &= ~C_FLAG; return 1; } -OPHANDLER( dec_a ) { cpustate->a--; return 1; } -OPHANDLER( dec_r0 ) { cpustate->R0--; return 1; } -OPHANDLER( dec_r1 ) { cpustate->R1--; return 1; } -OPHANDLER( dec_r2 ) { cpustate->R2--; return 1; } -OPHANDLER( dec_r3 ) { cpustate->R3--; return 1; } -OPHANDLER( dec_r4 ) { cpustate->R4--; return 1; } -OPHANDLER( dec_r5 ) { cpustate->R5--; return 1; } -OPHANDLER( dec_r6 ) { cpustate->R6--; return 1; } -OPHANDLER( dec_r7 ) { cpustate->R7--; return 1; } +OPHANDLER( dec_a ) { m_a--; return 1; } +OPHANDLER( dec_r0 ) { R0--; return 1; } +OPHANDLER( dec_r1 ) { R1--; return 1; } +OPHANDLER( dec_r2 ) { R2--; return 1; } +OPHANDLER( dec_r3 ) { R3--; return 1; } +OPHANDLER( dec_r4 ) { R4--; return 1; } +OPHANDLER( dec_r5 ) { R5--; return 1; } +OPHANDLER( dec_r6 ) { R6--; return 1; } +OPHANDLER( dec_r7 ) { R7--; return 1; } -OPHANDLER( dis_i ) { cpustate->xirq_enabled = FALSE; return 1; } -OPHANDLER( dis_tcnti ) { cpustate->tirq_enabled = FALSE; cpustate->timer_overflow = FALSE; return 1; } +OPHANDLER( dis_i ) { m_xirq_enabled = FALSE; return 1; } +OPHANDLER( dis_tcnti ) { m_tirq_enabled = FALSE; m_timer_overflow = FALSE; return 1; } -OPHANDLER( djnz_r0 ) { execute_jcc(cpustate, --cpustate->R0 != 0); return 2; } -OPHANDLER( djnz_r1 ) { execute_jcc(cpustate, --cpustate->R1 != 0); return 2; } -OPHANDLER( djnz_r2 ) { execute_jcc(cpustate, --cpustate->R2 != 0); return 2; } -OPHANDLER( djnz_r3 ) { execute_jcc(cpustate, --cpustate->R3 != 0); return 2; } -OPHANDLER( djnz_r4 ) { execute_jcc(cpustate, --cpustate->R4 != 0); return 2; } -OPHANDLER( djnz_r5 ) { execute_jcc(cpustate, --cpustate->R5 != 0); return 2; } -OPHANDLER( djnz_r6 ) { execute_jcc(cpustate, --cpustate->R6 != 0); return 2; } -OPHANDLER( djnz_r7 ) { execute_jcc(cpustate, --cpustate->R7 != 0); return 2; } +OPHANDLER( djnz_r0 ) { execute_jcc(--R0 != 0); return 2; } +OPHANDLER( djnz_r1 ) { execute_jcc(--R1 != 0); return 2; } +OPHANDLER( djnz_r2 ) { execute_jcc(--R2 != 0); return 2; } +OPHANDLER( djnz_r3 ) { execute_jcc(--R3 != 0); return 2; } +OPHANDLER( djnz_r4 ) { execute_jcc(--R4 != 0); return 2; } +OPHANDLER( djnz_r5 ) { execute_jcc(--R5 != 0); return 2; } +OPHANDLER( djnz_r6 ) { execute_jcc(--R6 != 0); return 2; } +OPHANDLER( djnz_r7 ) { execute_jcc(--R7 != 0); return 2; } -OPHANDLER( en_i ) { cpustate->xirq_enabled = TRUE; return 1 + check_irqs(cpustate); } -OPHANDLER( en_tcnti ) { cpustate->tirq_enabled = TRUE; return 1 + check_irqs(cpustate); } -OPHANDLER( en_dma ) { cpustate->dma_enabled = TRUE; port_w(2, cpustate->p2); return 1; } -OPHANDLER( en_flags ) { cpustate->flags_enabled = TRUE; port_w(2, cpustate->p2); return 1; } +OPHANDLER( en_i ) { m_xirq_enabled = TRUE; return 1 + check_irqs(); } +OPHANDLER( en_tcnti ) { m_tirq_enabled = TRUE; return 1 + check_irqs(); } +OPHANDLER( en_dma ) { m_dma_enabled = TRUE; port_w(2, m_p2); return 1; } +OPHANDLER( en_flags ) { m_flags_enabled = TRUE; port_w(2, m_p2); return 1; } OPHANDLER( ent0_clk ) { - logerror("MCS-48 PC:%04X - Unimplemented opcode = %02x\n", cpustate->pc - 1, program_r(cpustate->pc - 1)); + logerror("MCS-48 PC:%04X - Unimplemented opcode = %02x\n", m_pc - 1, program_r(m_pc - 1)); return 1; } -OPHANDLER( in_a_p1 ) { cpustate->a = port_r(1) & cpustate->p1; return 2; } -OPHANDLER( in_a_p2 ) { cpustate->a = port_r(2) & cpustate->p2; return 2; } -OPHANDLER( ins_a_bus ) { cpustate->a = bus_r(); return 2; } +OPHANDLER( in_a_p1 ) { m_a = port_r(1) & m_p1; return 2; } +OPHANDLER( in_a_p2 ) { m_a = port_r(2) & m_p2; return 2; } +OPHANDLER( ins_a_bus ) { m_a = bus_r(); return 2; } OPHANDLER( in_a_dbb ) { /* acknowledge the IBF IRQ and clear the bit in STS */ - if ((cpustate->sts & STS_IBF) != 0 && cpustate->irq_callback != NULL) - (*cpustate->irq_callback)(cpustate->device, UPI41_INPUT_IBF); - cpustate->sts &= ~STS_IBF; + if ((m_sts & STS_IBF) != 0) + standard_irq_callback(UPI41_INPUT_IBF); + m_sts &= ~STS_IBF; /* if P2 flags are enabled, update the state of P2 */ - if (cpustate->flags_enabled && (cpustate->p2 & P2_NIBF) == 0) - port_w(2, cpustate->p2 |= P2_NIBF); - cpustate->a = cpustate->dbbi; + if (m_flags_enabled && (m_p2 & P2_NIBF) == 0) + port_w(2, m_p2 |= P2_NIBF); + m_a = m_dbbi; return 2; } -OPHANDLER( inc_a ) { cpustate->a++; return 1; } -OPHANDLER( inc_r0 ) { cpustate->R0++; return 1; } -OPHANDLER( inc_r1 ) { cpustate->R1++; return 1; } -OPHANDLER( inc_r2 ) { cpustate->R2++; return 1; } -OPHANDLER( inc_r3 ) { cpustate->R3++; return 1; } -OPHANDLER( inc_r4 ) { cpustate->R4++; return 1; } -OPHANDLER( inc_r5 ) { cpustate->R5++; return 1; } -OPHANDLER( inc_r6 ) { cpustate->R6++; return 1; } -OPHANDLER( inc_r7 ) { cpustate->R7++; return 1; } -OPHANDLER( inc_xr0 ) { ram_w(cpustate->R0, ram_r(cpustate->R0) + 1); return 1; } -OPHANDLER( inc_xr1 ) { ram_w(cpustate->R1, ram_r(cpustate->R1) + 1); return 1; } +OPHANDLER( inc_a ) { m_a++; return 1; } +OPHANDLER( inc_r0 ) { R0++; return 1; } +OPHANDLER( inc_r1 ) { R1++; return 1; } +OPHANDLER( inc_r2 ) { R2++; return 1; } +OPHANDLER( inc_r3 ) { R3++; return 1; } +OPHANDLER( inc_r4 ) { R4++; return 1; } +OPHANDLER( inc_r5 ) { R5++; return 1; } +OPHANDLER( inc_r6 ) { R6++; return 1; } +OPHANDLER( inc_r7 ) { R7++; return 1; } +OPHANDLER( inc_xr0 ) { ram_w(R0, ram_r(R0) + 1); return 1; } +OPHANDLER( inc_xr1 ) { ram_w(R1, ram_r(R1) + 1); return 1; } -OPHANDLER( jb_0 ) { execute_jcc(cpustate, (cpustate->a & 0x01) != 0); return 2; } -OPHANDLER( jb_1 ) { execute_jcc(cpustate, (cpustate->a & 0x02) != 0); return 2; } -OPHANDLER( jb_2 ) { execute_jcc(cpustate, (cpustate->a & 0x04) != 0); return 2; } -OPHANDLER( jb_3 ) { execute_jcc(cpustate, (cpustate->a & 0x08) != 0); return 2; } -OPHANDLER( jb_4 ) { execute_jcc(cpustate, (cpustate->a & 0x10) != 0); return 2; } -OPHANDLER( jb_5 ) { execute_jcc(cpustate, (cpustate->a & 0x20) != 0); return 2; } -OPHANDLER( jb_6 ) { execute_jcc(cpustate, (cpustate->a & 0x40) != 0); return 2; } -OPHANDLER( jb_7 ) { execute_jcc(cpustate, (cpustate->a & 0x80) != 0); return 2; } -OPHANDLER( jc ) { execute_jcc(cpustate, (cpustate->psw & C_FLAG) != 0); return 2; } -OPHANDLER( jf0 ) { execute_jcc(cpustate, (cpustate->psw & F_FLAG) != 0); return 2; } -OPHANDLER( jf1 ) { execute_jcc(cpustate, (cpustate->sts & STS_F1) != 0); return 2; } -OPHANDLER( jnc ) { execute_jcc(cpustate, (cpustate->psw & C_FLAG) == 0); return 2; } -OPHANDLER( jni ) { execute_jcc(cpustate, cpustate->irq_state != 0); return 2; } -OPHANDLER( jnibf ) { execute_jcc(cpustate, (cpustate->sts & STS_IBF) == 0); return 2; } -OPHANDLER( jnt_0 ) { execute_jcc(cpustate, test_r(0) == 0); return 2; } -OPHANDLER( jnt_1 ) { execute_jcc(cpustate, test_r(1) == 0); return 2; } -OPHANDLER( jnz ) { execute_jcc(cpustate, cpustate->a != 0); return 2; } -OPHANDLER( jobf ) { execute_jcc(cpustate, (cpustate->sts & STS_OBF) != 0); return 2; } -OPHANDLER( jtf ) { execute_jcc(cpustate, cpustate->timer_flag); cpustate->timer_flag = FALSE; return 2; } -OPHANDLER( jt_0 ) { execute_jcc(cpustate, test_r(0) != 0); return 2; } -OPHANDLER( jt_1 ) { execute_jcc(cpustate, test_r(1) != 0); return 2; } -OPHANDLER( jz ) { execute_jcc(cpustate, cpustate->a == 0); return 2; } +OPHANDLER( jb_0 ) { execute_jcc((m_a & 0x01) != 0); return 2; } +OPHANDLER( jb_1 ) { execute_jcc((m_a & 0x02) != 0); return 2; } +OPHANDLER( jb_2 ) { execute_jcc((m_a & 0x04) != 0); return 2; } +OPHANDLER( jb_3 ) { execute_jcc((m_a & 0x08) != 0); return 2; } +OPHANDLER( jb_4 ) { execute_jcc((m_a & 0x10) != 0); return 2; } +OPHANDLER( jb_5 ) { execute_jcc((m_a & 0x20) != 0); return 2; } +OPHANDLER( jb_6 ) { execute_jcc((m_a & 0x40) != 0); return 2; } +OPHANDLER( jb_7 ) { execute_jcc((m_a & 0x80) != 0); return 2; } +OPHANDLER( jc ) { execute_jcc((m_psw & C_FLAG) != 0); return 2; } +OPHANDLER( jf0 ) { execute_jcc((m_psw & F_FLAG) != 0); return 2; } +OPHANDLER( jf1 ) { execute_jcc((m_sts & STS_F1) != 0); return 2; } +OPHANDLER( jnc ) { execute_jcc((m_psw & C_FLAG) == 0); return 2; } +OPHANDLER( jni ) { execute_jcc(m_irq_state != 0); return 2; } +OPHANDLER( jnibf ) { execute_jcc((m_sts & STS_IBF) == 0); return 2; } +OPHANDLER( jnt_0 ) { execute_jcc(test_r(0) == 0); return 2; } +OPHANDLER( jnt_1 ) { execute_jcc(test_r(1) == 0); return 2; } +OPHANDLER( jnz ) { execute_jcc(m_a != 0); return 2; } +OPHANDLER( jobf ) { execute_jcc((m_sts & STS_OBF) != 0); return 2; } +OPHANDLER( jtf ) { execute_jcc(m_timer_flag); m_timer_flag = FALSE; return 2; } +OPHANDLER( jt_0 ) { execute_jcc(test_r(0) != 0); return 2; } +OPHANDLER( jt_1 ) { execute_jcc(test_r(1) != 0); return 2; } +OPHANDLER( jz ) { execute_jcc(m_a == 0); return 2; } -OPHANDLER( jmp_0 ) { execute_jmp(cpustate, argument_fetch(cpustate) | 0x000); return 2; } -OPHANDLER( jmp_1 ) { execute_jmp(cpustate, argument_fetch(cpustate) | 0x100); return 2; } -OPHANDLER( jmp_2 ) { execute_jmp(cpustate, argument_fetch(cpustate) | 0x200); return 2; } -OPHANDLER( jmp_3 ) { execute_jmp(cpustate, argument_fetch(cpustate) | 0x300); return 2; } -OPHANDLER( jmp_4 ) { execute_jmp(cpustate, argument_fetch(cpustate) | 0x400); return 2; } -OPHANDLER( jmp_5 ) { execute_jmp(cpustate, argument_fetch(cpustate) | 0x500); return 2; } -OPHANDLER( jmp_6 ) { execute_jmp(cpustate, argument_fetch(cpustate) | 0x600); return 2; } -OPHANDLER( jmp_7 ) { execute_jmp(cpustate, argument_fetch(cpustate) | 0x700); return 2; } -OPHANDLER( jmpp_xa ) { cpustate->pc &= 0xf00; cpustate->pc |= program_r(cpustate->pc | cpustate->a); return 2; } +OPHANDLER( jmp_0 ) { execute_jmp(argument_fetch() | 0x000); return 2; } +OPHANDLER( jmp_1 ) { execute_jmp(argument_fetch() | 0x100); return 2; } +OPHANDLER( jmp_2 ) { execute_jmp(argument_fetch() | 0x200); return 2; } +OPHANDLER( jmp_3 ) { execute_jmp(argument_fetch() | 0x300); return 2; } +OPHANDLER( jmp_4 ) { execute_jmp(argument_fetch() | 0x400); return 2; } +OPHANDLER( jmp_5 ) { execute_jmp(argument_fetch() | 0x500); return 2; } +OPHANDLER( jmp_6 ) { execute_jmp(argument_fetch() | 0x600); return 2; } +OPHANDLER( jmp_7 ) { execute_jmp(argument_fetch() | 0x700); return 2; } +OPHANDLER( jmpp_xa ) { m_pc &= 0xf00; m_pc |= program_r(m_pc | m_a); return 2; } -OPHANDLER( mov_a_n ) { cpustate->a = argument_fetch(cpustate); return 2; } -OPHANDLER( mov_a_psw ) { cpustate->a = cpustate->psw; return 1; } -OPHANDLER( mov_a_r0 ) { cpustate->a = cpustate->R0; return 1; } -OPHANDLER( mov_a_r1 ) { cpustate->a = cpustate->R1; return 1; } -OPHANDLER( mov_a_r2 ) { cpustate->a = cpustate->R2; return 1; } -OPHANDLER( mov_a_r3 ) { cpustate->a = cpustate->R3; return 1; } -OPHANDLER( mov_a_r4 ) { cpustate->a = cpustate->R4; return 1; } -OPHANDLER( mov_a_r5 ) { cpustate->a = cpustate->R5; return 1; } -OPHANDLER( mov_a_r6 ) { cpustate->a = cpustate->R6; return 1; } -OPHANDLER( mov_a_r7 ) { cpustate->a = cpustate->R7; return 1; } -OPHANDLER( mov_a_xr0 ) { cpustate->a = ram_r(cpustate->R0); return 1; } -OPHANDLER( mov_a_xr1 ) { cpustate->a = ram_r(cpustate->R1); return 1; } -OPHANDLER( mov_a_t ) { cpustate->a = cpustate->timer; return 1; } +OPHANDLER( mov_a_n ) { m_a = argument_fetch(); return 2; } +OPHANDLER( mov_a_psw ) { m_a = m_psw; return 1; } +OPHANDLER( mov_a_r0 ) { m_a = R0; return 1; } +OPHANDLER( mov_a_r1 ) { m_a = R1; return 1; } +OPHANDLER( mov_a_r2 ) { m_a = R2; return 1; } +OPHANDLER( mov_a_r3 ) { m_a = R3; return 1; } +OPHANDLER( mov_a_r4 ) { m_a = R4; return 1; } +OPHANDLER( mov_a_r5 ) { m_a = R5; return 1; } +OPHANDLER( mov_a_r6 ) { m_a = R6; return 1; } +OPHANDLER( mov_a_r7 ) { m_a = R7; return 1; } +OPHANDLER( mov_a_xr0 ) { m_a = ram_r(R0); return 1; } +OPHANDLER( mov_a_xr1 ) { m_a = ram_r(R1); return 1; } +OPHANDLER( mov_a_t ) { m_a = m_timer; return 1; } -OPHANDLER( mov_psw_a ) { cpustate->psw = cpustate->a; update_regptr(cpustate); return 1; } -OPHANDLER( mov_sts_a ) { cpustate->sts = (cpustate->sts & 0x0f) | (cpustate->a & 0xf0); return 1; } -OPHANDLER( mov_r0_a ) { cpustate->R0 = cpustate->a; return 1; } -OPHANDLER( mov_r1_a ) { cpustate->R1 = cpustate->a; return 1; } -OPHANDLER( mov_r2_a ) { cpustate->R2 = cpustate->a; return 1; } -OPHANDLER( mov_r3_a ) { cpustate->R3 = cpustate->a; return 1; } -OPHANDLER( mov_r4_a ) { cpustate->R4 = cpustate->a; return 1; } -OPHANDLER( mov_r5_a ) { cpustate->R5 = cpustate->a; return 1; } -OPHANDLER( mov_r6_a ) { cpustate->R6 = cpustate->a; return 1; } -OPHANDLER( mov_r7_a ) { cpustate->R7 = cpustate->a; return 1; } -OPHANDLER( mov_r0_n ) { cpustate->R0 = argument_fetch(cpustate); return 2; } -OPHANDLER( mov_r1_n ) { cpustate->R1 = argument_fetch(cpustate); return 2; } -OPHANDLER( mov_r2_n ) { cpustate->R2 = argument_fetch(cpustate); return 2; } -OPHANDLER( mov_r3_n ) { cpustate->R3 = argument_fetch(cpustate); return 2; } -OPHANDLER( mov_r4_n ) { cpustate->R4 = argument_fetch(cpustate); return 2; } -OPHANDLER( mov_r5_n ) { cpustate->R5 = argument_fetch(cpustate); return 2; } -OPHANDLER( mov_r6_n ) { cpustate->R6 = argument_fetch(cpustate); return 2; } -OPHANDLER( mov_r7_n ) { cpustate->R7 = argument_fetch(cpustate); return 2; } -OPHANDLER( mov_t_a ) { cpustate->timer = cpustate->a; return 1; } -OPHANDLER( mov_xr0_a ) { ram_w(cpustate->R0, cpustate->a); return 1; } -OPHANDLER( mov_xr1_a ) { ram_w(cpustate->R1, cpustate->a); return 1; } -OPHANDLER( mov_xr0_n ) { ram_w(cpustate->R0, argument_fetch(cpustate)); return 2; } -OPHANDLER( mov_xr1_n ) { ram_w(cpustate->R1, argument_fetch(cpustate)); return 2; } +OPHANDLER( mov_psw_a ) { m_psw = m_a; update_regptr(); return 1; } +OPHANDLER( mov_sts_a ) { m_sts = (m_sts & 0x0f) | (m_a & 0xf0); return 1; } +OPHANDLER( mov_r0_a ) { R0 = m_a; return 1; } +OPHANDLER( mov_r1_a ) { R1 = m_a; return 1; } +OPHANDLER( mov_r2_a ) { R2 = m_a; return 1; } +OPHANDLER( mov_r3_a ) { R3 = m_a; return 1; } +OPHANDLER( mov_r4_a ) { R4 = m_a; return 1; } +OPHANDLER( mov_r5_a ) { R5 = m_a; return 1; } +OPHANDLER( mov_r6_a ) { R6 = m_a; return 1; } +OPHANDLER( mov_r7_a ) { R7 = m_a; return 1; } +OPHANDLER( mov_r0_n ) { R0 = argument_fetch(); return 2; } +OPHANDLER( mov_r1_n ) { R1 = argument_fetch(); return 2; } +OPHANDLER( mov_r2_n ) { R2 = argument_fetch(); return 2; } +OPHANDLER( mov_r3_n ) { R3 = argument_fetch(); return 2; } +OPHANDLER( mov_r4_n ) { R4 = argument_fetch(); return 2; } +OPHANDLER( mov_r5_n ) { R5 = argument_fetch(); return 2; } +OPHANDLER( mov_r6_n ) { R6 = argument_fetch(); return 2; } +OPHANDLER( mov_r7_n ) { R7 = argument_fetch(); return 2; } +OPHANDLER( mov_t_a ) { m_timer = m_a; return 1; } +OPHANDLER( mov_xr0_a ) { ram_w(R0, m_a); return 1; } +OPHANDLER( mov_xr1_a ) { ram_w(R1, m_a); return 1; } +OPHANDLER( mov_xr0_n ) { ram_w(R0, argument_fetch()); return 2; } +OPHANDLER( mov_xr1_n ) { ram_w(R1, argument_fetch()); return 2; } -OPHANDLER( movd_a_p4 ) { expander_operation(cpustate, MCS48_EXPANDER_OP_READ, 4); return 2; } -OPHANDLER( movd_a_p5 ) { expander_operation(cpustate, MCS48_EXPANDER_OP_READ, 5); return 2; } -OPHANDLER( movd_a_p6 ) { expander_operation(cpustate, MCS48_EXPANDER_OP_READ, 6); return 2; } -OPHANDLER( movd_a_p7 ) { expander_operation(cpustate, MCS48_EXPANDER_OP_READ, 7); return 2; } -OPHANDLER( movd_p4_a ) { expander_operation(cpustate, MCS48_EXPANDER_OP_WRITE, 4); return 2; } -OPHANDLER( movd_p5_a ) { expander_operation(cpustate, MCS48_EXPANDER_OP_WRITE, 5); return 2; } -OPHANDLER( movd_p6_a ) { expander_operation(cpustate, MCS48_EXPANDER_OP_WRITE, 6); return 2; } -OPHANDLER( movd_p7_a ) { expander_operation(cpustate, MCS48_EXPANDER_OP_WRITE, 7); return 2; } +OPHANDLER( movd_a_p4 ) { expander_operation(MCS48_EXPANDER_OP_READ, 4); return 2; } +OPHANDLER( movd_a_p5 ) { expander_operation(MCS48_EXPANDER_OP_READ, 5); return 2; } +OPHANDLER( movd_a_p6 ) { expander_operation(MCS48_EXPANDER_OP_READ, 6); return 2; } +OPHANDLER( movd_a_p7 ) { expander_operation(MCS48_EXPANDER_OP_READ, 7); return 2; } +OPHANDLER( movd_p4_a ) { expander_operation(MCS48_EXPANDER_OP_WRITE, 4); return 2; } +OPHANDLER( movd_p5_a ) { expander_operation(MCS48_EXPANDER_OP_WRITE, 5); return 2; } +OPHANDLER( movd_p6_a ) { expander_operation(MCS48_EXPANDER_OP_WRITE, 6); return 2; } +OPHANDLER( movd_p7_a ) { expander_operation(MCS48_EXPANDER_OP_WRITE, 7); return 2; } -OPHANDLER( movp_a_xa ) { cpustate->a = program_r((cpustate->pc & 0xf00) | cpustate->a); return 2; } -OPHANDLER( movp3_a_xa ) { cpustate->a = program_r(0x300 | cpustate->a); return 2; } +OPHANDLER( movp_a_xa ) { m_a = program_r((m_pc & 0xf00) | m_a); return 2; } +OPHANDLER( movp3_a_xa ) { m_a = program_r(0x300 | m_a); return 2; } -OPHANDLER( movx_a_xr0 ) { cpustate->a = ext_r(cpustate->R0); return 2; } -OPHANDLER( movx_a_xr1 ) { cpustate->a = ext_r(cpustate->R1); return 2; } -OPHANDLER( movx_xr0_a ) { ext_w(cpustate->R0, cpustate->a); return 2; } -OPHANDLER( movx_xr1_a ) { ext_w(cpustate->R1, cpustate->a); return 2; } +OPHANDLER( movx_a_xr0 ) { m_a = ext_r(R0); return 2; } +OPHANDLER( movx_a_xr1 ) { m_a = ext_r(R1); return 2; } +OPHANDLER( movx_xr0_a ) { ext_w(R0, m_a); return 2; } +OPHANDLER( movx_xr1_a ) { ext_w(R1, m_a); return 2; } OPHANDLER( nop ) { return 1; } -OPHANDLER( orl_a_r0 ) { cpustate->a |= cpustate->R0; return 1; } -OPHANDLER( orl_a_r1 ) { cpustate->a |= cpustate->R1; return 1; } -OPHANDLER( orl_a_r2 ) { cpustate->a |= cpustate->R2; return 1; } -OPHANDLER( orl_a_r3 ) { cpustate->a |= cpustate->R3; return 1; } -OPHANDLER( orl_a_r4 ) { cpustate->a |= cpustate->R4; return 1; } -OPHANDLER( orl_a_r5 ) { cpustate->a |= cpustate->R5; return 1; } -OPHANDLER( orl_a_r6 ) { cpustate->a |= cpustate->R6; return 1; } -OPHANDLER( orl_a_r7 ) { cpustate->a |= cpustate->R7; return 1; } -OPHANDLER( orl_a_xr0 ) { cpustate->a |= ram_r(cpustate->R0); return 1; } -OPHANDLER( orl_a_xr1 ) { cpustate->a |= ram_r(cpustate->R1); return 1; } -OPHANDLER( orl_a_n ) { cpustate->a |= argument_fetch(cpustate); return 2; } +OPHANDLER( orl_a_r0 ) { m_a |= R0; return 1; } +OPHANDLER( orl_a_r1 ) { m_a |= R1; return 1; } +OPHANDLER( orl_a_r2 ) { m_a |= R2; return 1; } +OPHANDLER( orl_a_r3 ) { m_a |= R3; return 1; } +OPHANDLER( orl_a_r4 ) { m_a |= R4; return 1; } +OPHANDLER( orl_a_r5 ) { m_a |= R5; return 1; } +OPHANDLER( orl_a_r6 ) { m_a |= R6; return 1; } +OPHANDLER( orl_a_r7 ) { m_a |= R7; return 1; } +OPHANDLER( orl_a_xr0 ) { m_a |= ram_r(R0); return 1; } +OPHANDLER( orl_a_xr1 ) { m_a |= ram_r(R1); return 1; } +OPHANDLER( orl_a_n ) { m_a |= argument_fetch(); return 2; } -OPHANDLER( orl_bus_n ) { bus_w(bus_r() | argument_fetch(cpustate)); return 2; } -OPHANDLER( orl_p1_n ) { port_w(1, cpustate->p1 |= argument_fetch(cpustate)); return 2; } -OPHANDLER( orl_p2_n ) { port_w(2, cpustate->p2 |= argument_fetch(cpustate) & p2_mask(cpustate)); return 2; } -OPHANDLER( orld_p4_a ) { expander_operation(cpustate, MCS48_EXPANDER_OP_OR, 4); return 2; } -OPHANDLER( orld_p5_a ) { expander_operation(cpustate, MCS48_EXPANDER_OP_OR, 5); return 2; } -OPHANDLER( orld_p6_a ) { expander_operation(cpustate, MCS48_EXPANDER_OP_OR, 6); return 2; } -OPHANDLER( orld_p7_a ) { expander_operation(cpustate, MCS48_EXPANDER_OP_OR, 7); return 2; } +OPHANDLER( orl_bus_n ) { bus_w(bus_r() | argument_fetch()); return 2; } +OPHANDLER( orl_p1_n ) { port_w(1, m_p1 |= argument_fetch()); return 2; } +OPHANDLER( orl_p2_n ) { port_w(2, m_p2 |= argument_fetch() & p2_mask()); return 2; } +OPHANDLER( orld_p4_a ) { expander_operation(MCS48_EXPANDER_OP_OR, 4); return 2; } +OPHANDLER( orld_p5_a ) { expander_operation(MCS48_EXPANDER_OP_OR, 5); return 2; } +OPHANDLER( orld_p6_a ) { expander_operation(MCS48_EXPANDER_OP_OR, 6); return 2; } +OPHANDLER( orld_p7_a ) { expander_operation(MCS48_EXPANDER_OP_OR, 7); return 2; } -OPHANDLER( outl_bus_a ) { bus_w(cpustate->a); return 2; } -OPHANDLER( outl_p1_a ) { port_w(1, cpustate->p1 = cpustate->a); return 2; } -OPHANDLER( outl_p2_a ) { UINT8 mask = p2_mask(cpustate); port_w(2, cpustate->p2 = (cpustate->p2 & ~mask) | (cpustate->a & mask)); return 2; } +OPHANDLER( outl_bus_a ) { bus_w(m_a); return 2; } +OPHANDLER( outl_p1_a ) { port_w(1, m_p1 = m_a); return 2; } +OPHANDLER( outl_p2_a ) { UINT8 mask = p2_mask(); port_w(2, m_p2 = (m_p2 & ~mask) | (m_a & mask)); return 2; } OPHANDLER( out_dbb_a ) { /* copy to the DBBO and update the bit in STS */ - cpustate->dbbo = cpustate->a; - cpustate->sts |= STS_OBF; + m_dbbo = m_a; + m_sts |= STS_OBF; /* if P2 flags are enabled, update the state of P2 */ - if (cpustate->flags_enabled && (cpustate->p2 & P2_OBF) == 0) - port_w(2, cpustate->p2 |= P2_OBF); + if (m_flags_enabled && (m_p2 & P2_OBF) == 0) + port_w(2, m_p2 |= P2_OBF); return 2; } -OPHANDLER( ret ) { pull_pc(cpustate); return 2; } +OPHANDLER( ret ) { pull_pc(); return 2; } OPHANDLER( retr ) { - pull_pc_psw(cpustate); + pull_pc_psw(); /* implicitly clear the IRQ in progress flip flop and re-check interrupts */ - cpustate->irq_in_progress = FALSE; - return 2 + check_irqs(cpustate); + m_irq_in_progress = FALSE; + return 2 + check_irqs(); } -OPHANDLER( rl_a ) { cpustate->a = (cpustate->a << 1) | (cpustate->a >> 7); return 1; } -OPHANDLER( rlc_a ) { UINT8 newc = cpustate->a & C_FLAG; cpustate->a = (cpustate->a << 1) | (cpustate->psw >> 7); cpustate->psw = (cpustate->psw & ~C_FLAG) | newc; return 1; } +OPHANDLER( rl_a ) { m_a = (m_a << 1) | (m_a >> 7); return 1; } +OPHANDLER( rlc_a ) { UINT8 newc = m_a & C_FLAG; m_a = (m_a << 1) | (m_psw >> 7); m_psw = (m_psw & ~C_FLAG) | newc; return 1; } -OPHANDLER( rr_a ) { cpustate->a = (cpustate->a >> 1) | (cpustate->a << 7); return 1; } -OPHANDLER( rrc_a ) { UINT8 newc = (cpustate->a << 7) & C_FLAG; cpustate->a = (cpustate->a >> 1) | (cpustate->psw & C_FLAG); cpustate->psw = (cpustate->psw & ~C_FLAG) | newc; return 1; } +OPHANDLER( rr_a ) { m_a = (m_a >> 1) | (m_a << 7); return 1; } +OPHANDLER( rrc_a ) { UINT8 newc = (m_a << 7) & C_FLAG; m_a = (m_a >> 1) | (m_psw & C_FLAG); m_psw = (m_psw & ~C_FLAG) | newc; return 1; } -OPHANDLER( sel_mb0 ) { cpustate->a11 = 0x000; return 1; } -OPHANDLER( sel_mb1 ) { cpustate->a11 = 0x800; return 1; } +OPHANDLER( sel_mb0 ) { m_a11 = 0x000; return 1; } +OPHANDLER( sel_mb1 ) { m_a11 = 0x800; return 1; } -OPHANDLER( sel_rb0 ) { cpustate->psw &= ~B_FLAG; update_regptr(cpustate); return 1; } -OPHANDLER( sel_rb1 ) { cpustate->psw |= B_FLAG; update_regptr(cpustate); return 1; } +OPHANDLER( sel_rb0 ) { m_psw &= ~B_FLAG; update_regptr(); return 1; } +OPHANDLER( sel_rb1 ) { m_psw |= B_FLAG; update_regptr(); return 1; } -OPHANDLER( stop_tcnt ) { cpustate->timecount_enabled = 0; return 1; } +OPHANDLER( stop_tcnt ) { m_timecount_enabled = 0; return 1; } -OPHANDLER( strt_cnt ) { cpustate->timecount_enabled = COUNTER_ENABLED; cpustate->t1_history = test_r(1); return 1; } -OPHANDLER( strt_t ) { cpustate->timecount_enabled = TIMER_ENABLED; cpustate->prescaler = 0; return 1; } +OPHANDLER( strt_cnt ) { m_timecount_enabled = COUNTER_ENABLED; m_t1_history = test_r(1); return 1; } +OPHANDLER( strt_t ) { m_timecount_enabled = TIMER_ENABLED; m_prescaler = 0; return 1; } -OPHANDLER( swap_a ) { cpustate->a = (cpustate->a << 4) | (cpustate->a >> 4); return 1; } +OPHANDLER( swap_a ) { m_a = (m_a << 4) | (m_a >> 4); return 1; } -OPHANDLER( xch_a_r0 ) { UINT8 tmp = cpustate->a; cpustate->a = cpustate->R0; cpustate->R0 = tmp; return 1; } -OPHANDLER( xch_a_r1 ) { UINT8 tmp = cpustate->a; cpustate->a = cpustate->R1; cpustate->R1 = tmp; return 1; } -OPHANDLER( xch_a_r2 ) { UINT8 tmp = cpustate->a; cpustate->a = cpustate->R2; cpustate->R2 = tmp; return 1; } -OPHANDLER( xch_a_r3 ) { UINT8 tmp = cpustate->a; cpustate->a = cpustate->R3; cpustate->R3 = tmp; return 1; } -OPHANDLER( xch_a_r4 ) { UINT8 tmp = cpustate->a; cpustate->a = cpustate->R4; cpustate->R4 = tmp; return 1; } -OPHANDLER( xch_a_r5 ) { UINT8 tmp = cpustate->a; cpustate->a = cpustate->R5; cpustate->R5 = tmp; return 1; } -OPHANDLER( xch_a_r6 ) { UINT8 tmp = cpustate->a; cpustate->a = cpustate->R6; cpustate->R6 = tmp; return 1; } -OPHANDLER( xch_a_r7 ) { UINT8 tmp = cpustate->a; cpustate->a = cpustate->R7; cpustate->R7 = tmp; return 1; } -OPHANDLER( xch_a_xr0 ) { UINT8 tmp = cpustate->a; cpustate->a = ram_r(cpustate->R0); ram_w(cpustate->R0, tmp); return 1; } -OPHANDLER( xch_a_xr1 ) { UINT8 tmp = cpustate->a; cpustate->a = ram_r(cpustate->R1); ram_w(cpustate->R1, tmp); return 1; } +OPHANDLER( xch_a_r0 ) { UINT8 tmp = m_a; m_a = R0; R0 = tmp; return 1; } +OPHANDLER( xch_a_r1 ) { UINT8 tmp = m_a; m_a = R1; R1 = tmp; return 1; } +OPHANDLER( xch_a_r2 ) { UINT8 tmp = m_a; m_a = R2; R2 = tmp; return 1; } +OPHANDLER( xch_a_r3 ) { UINT8 tmp = m_a; m_a = R3; R3 = tmp; return 1; } +OPHANDLER( xch_a_r4 ) { UINT8 tmp = m_a; m_a = R4; R4 = tmp; return 1; } +OPHANDLER( xch_a_r5 ) { UINT8 tmp = m_a; m_a = R5; R5 = tmp; return 1; } +OPHANDLER( xch_a_r6 ) { UINT8 tmp = m_a; m_a = R6; R6 = tmp; return 1; } +OPHANDLER( xch_a_r7 ) { UINT8 tmp = m_a; m_a = R7; R7 = tmp; return 1; } +OPHANDLER( xch_a_xr0 ) { UINT8 tmp = m_a; m_a = ram_r(R0); ram_w(R0, tmp); return 1; } +OPHANDLER( xch_a_xr1 ) { UINT8 tmp = m_a; m_a = ram_r(R1); ram_w(R1, tmp); return 1; } -OPHANDLER( xchd_a_xr0 ) { UINT8 oldram = ram_r(cpustate->R0); ram_w(cpustate->R0, (oldram & 0xf0) | (cpustate->a & 0x0f)); cpustate->a = (cpustate->a & 0xf0) | (oldram & 0x0f); return 1; } -OPHANDLER( xchd_a_xr1 ) { UINT8 oldram = ram_r(cpustate->R1); ram_w(cpustate->R1, (oldram & 0xf0) | (cpustate->a & 0x0f)); cpustate->a = (cpustate->a & 0xf0) | (oldram & 0x0f); return 1; } +OPHANDLER( xchd_a_xr0 ) { UINT8 oldram = ram_r(R0); ram_w(R0, (oldram & 0xf0) | (m_a & 0x0f)); m_a = (m_a & 0xf0) | (oldram & 0x0f); return 1; } +OPHANDLER( xchd_a_xr1 ) { UINT8 oldram = ram_r(R1); ram_w(R1, (oldram & 0xf0) | (m_a & 0x0f)); m_a = (m_a & 0xf0) | (oldram & 0x0f); return 1; } -OPHANDLER( xrl_a_r0 ) { cpustate->a ^= cpustate->R0; return 1; } -OPHANDLER( xrl_a_r1 ) { cpustate->a ^= cpustate->R1; return 1; } -OPHANDLER( xrl_a_r2 ) { cpustate->a ^= cpustate->R2; return 1; } -OPHANDLER( xrl_a_r3 ) { cpustate->a ^= cpustate->R3; return 1; } -OPHANDLER( xrl_a_r4 ) { cpustate->a ^= cpustate->R4; return 1; } -OPHANDLER( xrl_a_r5 ) { cpustate->a ^= cpustate->R5; return 1; } -OPHANDLER( xrl_a_r6 ) { cpustate->a ^= cpustate->R6; return 1; } -OPHANDLER( xrl_a_r7 ) { cpustate->a ^= cpustate->R7; return 1; } -OPHANDLER( xrl_a_xr0 ) { cpustate->a ^= ram_r(cpustate->R0); return 1; } -OPHANDLER( xrl_a_xr1 ) { cpustate->a ^= ram_r(cpustate->R1); return 1; } -OPHANDLER( xrl_a_n ) { cpustate->a ^= argument_fetch(cpustate); return 2; } +OPHANDLER( xrl_a_r0 ) { m_a ^= R0; return 1; } +OPHANDLER( xrl_a_r1 ) { m_a ^= R1; return 1; } +OPHANDLER( xrl_a_r2 ) { m_a ^= R2; return 1; } +OPHANDLER( xrl_a_r3 ) { m_a ^= R3; return 1; } +OPHANDLER( xrl_a_r4 ) { m_a ^= R4; return 1; } +OPHANDLER( xrl_a_r5 ) { m_a ^= R5; return 1; } +OPHANDLER( xrl_a_r6 ) { m_a ^= R6; return 1; } +OPHANDLER( xrl_a_r7 ) { m_a ^= R7; return 1; } +OPHANDLER( xrl_a_xr0 ) { m_a ^= ram_r(R0); return 1; } +OPHANDLER( xrl_a_xr1 ) { m_a ^= ram_r(R1); return 1; } +OPHANDLER( xrl_a_n ) { m_a ^= argument_fetch(); return 2; } SPLIT_OPHANDLER( split_02, outl_bus_a, out_dbb_a ) SPLIT_OPHANDLER( split_08, ins_a_bus, illegal ) @@ -795,40 +891,42 @@ SPLIT_OPHANDLER( split_f5, sel_mb1, en_flags ) OPCODE TABLES ***************************************************************************/ -static const mcs48_ophandler opcode_table[256]= +#define OP(_a) &mcs48_cpu_device::_a + +const mcs48_cpu_device::mcs48_ophandler mcs48_cpu_device::s_opcode_table[256]= { - nop, illegal, split_02, add_a_n, jmp_0, en_i, illegal, dec_a, /* 00 */ - split_08, in_a_p1, in_a_p2, illegal, movd_a_p4, movd_a_p5, movd_a_p6, movd_a_p7, - inc_xr0, inc_xr1, jb_0, adc_a_n, call_0, dis_i, jtf, inc_a, /* 10 */ - inc_r0, inc_r1, inc_r2, inc_r3, inc_r4, inc_r5, inc_r6, inc_r7, - xch_a_xr0, xch_a_xr1, split_22, mov_a_n, jmp_1, en_tcnti, jnt_0, clr_a, /* 20 */ - xch_a_r0, xch_a_r1, xch_a_r2, xch_a_r3, xch_a_r4, xch_a_r5, xch_a_r6, xch_a_r7, - xchd_a_xr0, xchd_a_xr1, jb_1, illegal, call_1, dis_tcnti, jt_0, cpl_a, /* 30 */ - illegal, outl_p1_a, outl_p2_a, illegal, movd_p4_a, movd_p5_a, movd_p6_a, movd_p7_a, - orl_a_xr0, orl_a_xr1, mov_a_t, orl_a_n, jmp_2, strt_cnt, jnt_1, swap_a, /* 40 */ - orl_a_r0, orl_a_r1, orl_a_r2, orl_a_r3, orl_a_r4, orl_a_r5, orl_a_r6, orl_a_r7, - anl_a_xr0, anl_a_xr1, jb_2, anl_a_n, call_2, strt_t, jt_1, da_a, /* 50 */ - anl_a_r0, anl_a_r1, anl_a_r2, anl_a_r3, anl_a_r4, anl_a_r5, anl_a_r6, anl_a_r7, - add_a_xr0, add_a_xr1, mov_t_a, illegal, jmp_3, stop_tcnt, illegal, rrc_a, /* 60 */ - add_a_r0, add_a_r1, add_a_r2, add_a_r3, add_a_r4, add_a_r5, add_a_r6, add_a_r7, - adc_a_xr0, adc_a_xr1, jb_3, illegal, call_3, split_75, jf1, rr_a, /* 70 */ - adc_a_r0, adc_a_r1, adc_a_r2, adc_a_r3, adc_a_r4, adc_a_r5, adc_a_r6, adc_a_r7, - split_80, split_81, illegal, ret, jmp_4, clr_f0, split_86, illegal, /* 80 */ - split_88, orl_p1_n, orl_p2_n, illegal, orld_p4_a, orld_p5_a, orld_p6_a, orld_p7_a, - split_90, split_91, jb_4, retr, call_4, cpl_f0, jnz, clr_c, /* 90 */ - split_98, anl_p1_n, anl_p2_n, illegal, anld_p4_a, anld_p5_a, anld_p6_a, anld_p7_a, - mov_xr0_a, mov_xr1_a, illegal, movp_a_xa, jmp_5, clr_f1, illegal, cpl_c, /* A0 */ - mov_r0_a, mov_r1_a, mov_r2_a, mov_r3_a, mov_r4_a, mov_r5_a, mov_r6_a, mov_r7_a, - mov_xr0_n, mov_xr1_n, jb_5, jmpp_xa, call_5, cpl_f1, jf0, illegal, /* B0 */ - mov_r0_n, mov_r1_n, mov_r2_n, mov_r3_n, mov_r4_n, mov_r5_n, mov_r6_n, mov_r7_n, - illegal, illegal, illegal, illegal, jmp_6, sel_rb0, jz, mov_a_psw, /* C0 */ - dec_r0, dec_r1, dec_r2, dec_r3, dec_r4, dec_r5, dec_r6, dec_r7, - xrl_a_xr0, xrl_a_xr1, jb_6, xrl_a_n, call_6, sel_rb1, split_d6, mov_psw_a, /* D0 */ - xrl_a_r0, xrl_a_r1, xrl_a_r2, xrl_a_r3, xrl_a_r4, xrl_a_r5, xrl_a_r6, xrl_a_r7, - illegal, illegal, illegal, movp3_a_xa,jmp_7, split_e5, jnc, rl_a, /* E0 */ - djnz_r0, djnz_r1, djnz_r2, djnz_r3, djnz_r4, djnz_r5, djnz_r6, djnz_r7, - mov_a_xr0, mov_a_xr1, jb_7, illegal, call_7, split_f5, jc, rlc_a, /* F0 */ - mov_a_r0, mov_a_r1, mov_a_r2, mov_a_r3, mov_a_r4, mov_a_r5, mov_a_r6, mov_a_r7 + OP(nop), OP(illegal), OP(split_02), OP(add_a_n), OP(jmp_0), OP(en_i), OP(illegal), OP(dec_a), /* 00 */ + OP(split_08), OP(in_a_p1), OP(in_a_p2), OP(illegal), OP(movd_a_p4), OP(movd_a_p5), OP(movd_a_p6), OP(movd_a_p7), + OP(inc_xr0), OP(inc_xr1), OP(jb_0), OP(adc_a_n), OP(call_0), OP(dis_i), OP(jtf), OP(inc_a), /* 10 */ + OP(inc_r0), OP(inc_r1), OP(inc_r2), OP(inc_r3), OP(inc_r4), OP(inc_r5), OP(inc_r6), OP(inc_r7), + OP(xch_a_xr0), OP(xch_a_xr1), OP(split_22), OP(mov_a_n), OP(jmp_1), OP(en_tcnti), OP(jnt_0), OP(clr_a), /* 20 */ + OP(xch_a_r0), OP(xch_a_r1), OP(xch_a_r2), OP(xch_a_r3), OP(xch_a_r4), OP(xch_a_r5), OP(xch_a_r6), OP(xch_a_r7), + OP(xchd_a_xr0), OP(xchd_a_xr1), OP(jb_1), OP(illegal), OP(call_1), OP(dis_tcnti), OP(jt_0), OP(cpl_a), /* 30 */ + OP(illegal), OP(outl_p1_a), OP(outl_p2_a), OP(illegal), OP(movd_p4_a), OP(movd_p5_a), OP(movd_p6_a), OP(movd_p7_a), + OP(orl_a_xr0), OP(orl_a_xr1), OP(mov_a_t), OP(orl_a_n), OP(jmp_2), OP(strt_cnt), OP(jnt_1), OP(swap_a), /* 40 */ + OP(orl_a_r0), OP(orl_a_r1), OP(orl_a_r2), OP(orl_a_r3), OP(orl_a_r4), OP(orl_a_r5), OP(orl_a_r6), OP(orl_a_r7), + OP(anl_a_xr0), OP(anl_a_xr1), OP(jb_2), OP(anl_a_n), OP(call_2), OP(strt_t), OP(jt_1), OP(da_a), /* 50 */ + OP(anl_a_r0), OP(anl_a_r1), OP(anl_a_r2), OP(anl_a_r3), OP(anl_a_r4), OP(anl_a_r5), OP(anl_a_r6), OP(anl_a_r7), + OP(add_a_xr0), OP(add_a_xr1), OP(mov_t_a), OP(illegal), OP(jmp_3), OP(stop_tcnt), OP(illegal), OP(rrc_a), /* 60 */ + OP(add_a_r0), OP(add_a_r1), OP(add_a_r2), OP(add_a_r3), OP(add_a_r4), OP(add_a_r5), OP(add_a_r6), OP(add_a_r7), + OP(adc_a_xr0), OP(adc_a_xr1), OP(jb_3), OP(illegal), OP(call_3), OP(split_75), OP(jf1), OP(rr_a), /* 70 */ + OP(adc_a_r0), OP(adc_a_r1), OP(adc_a_r2), OP(adc_a_r3), OP(adc_a_r4), OP(adc_a_r5), OP(adc_a_r6), OP(adc_a_r7), + OP(split_80), OP(split_81), OP(illegal), OP(ret), OP(jmp_4), OP(clr_f0), OP(split_86), OP(illegal), /* 80 */ + OP(split_88), OP(orl_p1_n), OP(orl_p2_n), OP(illegal), OP(orld_p4_a), OP(orld_p5_a), OP(orld_p6_a), OP(orld_p7_a), + OP(split_90), OP(split_91), OP(jb_4), OP(retr), OP(call_4), OP(cpl_f0), OP(jnz), OP(clr_c), /* 90 */ + OP(split_98), OP(anl_p1_n), OP(anl_p2_n), OP(illegal), OP(anld_p4_a), OP(anld_p5_a), OP(anld_p6_a), OP(anld_p7_a), + OP(mov_xr0_a), OP(mov_xr1_a), OP(illegal), OP(movp_a_xa), OP(jmp_5), OP(clr_f1), OP(illegal), OP(cpl_c), /* A0 */ + OP(mov_r0_a), OP(mov_r1_a), OP(mov_r2_a), OP(mov_r3_a), OP(mov_r4_a), OP(mov_r5_a), OP(mov_r6_a), OP(mov_r7_a), + OP(mov_xr0_n), OP(mov_xr1_n), OP(jb_5), OP(jmpp_xa), OP(call_5), OP(cpl_f1), OP(jf0), OP(illegal), /* B0 */ + OP(mov_r0_n), OP(mov_r1_n), OP(mov_r2_n), OP(mov_r3_n), OP(mov_r4_n), OP(mov_r5_n), OP(mov_r6_n), OP(mov_r7_n), + OP(illegal), OP(illegal), OP(illegal), OP(illegal), OP(jmp_6), OP(sel_rb0), OP(jz), OP(mov_a_psw), /* C0 */ + OP(dec_r0), OP(dec_r1), OP(dec_r2), OP(dec_r3), OP(dec_r4), OP(dec_r5), OP(dec_r6), OP(dec_r7), + OP(xrl_a_xr0), OP(xrl_a_xr1), OP(jb_6), OP(xrl_a_n), OP(call_6), OP(sel_rb1), OP(split_d6), OP(mov_psw_a), /* D0 */ + OP(xrl_a_r0), OP(xrl_a_r1), OP(xrl_a_r2), OP(xrl_a_r3), OP(xrl_a_r4), OP(xrl_a_r5), OP(xrl_a_r6), OP(xrl_a_r7), + OP(illegal), OP(illegal), OP(illegal), OP(movp3_a_xa),OP(jmp_7), OP(split_e5), OP(jnc), OP(rl_a), /* E0 */ + OP(djnz_r0), OP(djnz_r1), OP(djnz_r2), OP(djnz_r3), OP(djnz_r4), OP(djnz_r5), OP(djnz_r6), OP(djnz_r7), + OP(mov_a_xr0), OP(mov_a_xr1), OP(jb_7), OP(illegal), OP(call_7), OP(split_f5), OP(jc), OP(rlc_a), /* F0 */ + OP(mov_a_r0), OP(mov_a_r1), OP(mov_a_r2), OP(mov_a_r3), OP(mov_a_r4), OP(mov_a_r5), OP(mov_a_r6), OP(mov_a_r7) }; @@ -841,184 +939,113 @@ static const mcs48_ophandler opcode_table[256]= mcs48_init - generic MCS-48 initialization -------------------------------------------------*/ -static void mcs48_init(legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback, UINT8 feature_mask, UINT16 romsize) +void mcs48_cpu_device::device_start() { - mcs48_state *cpustate = get_safe_token(device); - /* External access line * EA=1 : read from external rom * EA=0 : read from internal rom */ + m_a = 0; + m_timer = 0; + m_prescaler = 0; + m_t1_history = 0; + m_dbbi = 0; + m_dbbo = 0; + m_irq_state = 0; + /* FIXME: Current implementation suboptimal */ - cpustate->ea = (romsize ? 0 : 1); + m_ea = (m_int_rom_size ? 0 : 1); - cpustate->irq_callback = irqcallback; - cpustate->device = device; - cpustate->int_rom_size = romsize; - cpustate->feature_mask = feature_mask; - - cpustate->program = &device->space(AS_PROGRAM); - cpustate->direct = &cpustate->program->direct(); - cpustate->data = &device->space(AS_DATA); - cpustate->io = &device->space(AS_IO); + m_program = &space(AS_PROGRAM); + m_direct = &m_program->direct(); + m_data = &space(AS_DATA); + m_io = &space(AS_IO); /* set up the state table */ { - device_state_interface *state; - device->interface(state); - state->state_add(MCS48_PC, "PC", cpustate->pc).mask(0xfff); - state->state_add(STATE_GENPC, "GENPC", cpustate->pc).mask(0xfff).noshow(); - state->state_add(STATE_GENPCBASE, "GENPCBASE", cpustate->prevpc).mask(0xfff).noshow(); - state->state_add(STATE_GENSP, "GENSP", cpustate->psw).mask(0x7).noshow(); - state->state_add(STATE_GENFLAGS, "GENFLAGS", cpustate->psw).noshow().formatstr("%10s"); - state->state_add(MCS48_A, "A", cpustate->a); - state->state_add(MCS48_TC, "TC", cpustate->timer); - state->state_add(MCS48_TPRE, "TPRE", cpustate->prescaler).mask(0x1f); - state->state_add(MCS48_P1, "P1", cpustate->p1); - state->state_add(MCS48_P2, "P2", cpustate->p2); + state_add(MCS48_PC, "PC", m_pc).mask(0xfff); + state_add(STATE_GENPC, "GENPC", m_pc).mask(0xfff).noshow(); + state_add(STATE_GENPCBASE, "GENPCBASE", m_prevpc).mask(0xfff).noshow(); + state_add(STATE_GENSP, "GENSP", m_psw).mask(0x7).noshow(); + state_add(STATE_GENFLAGS, "GENFLAGS", m_psw).noshow().formatstr("%10s"); + state_add(MCS48_A, "A", m_a); + state_add(MCS48_TC, "TC", m_timer); + state_add(MCS48_TPRE, "TPRE", m_prescaler).mask(0x1f); + state_add(MCS48_P1, "P1", m_p1); + state_add(MCS48_P2, "P2", m_p2); astring tempstr; for (int regnum = 0; regnum < 8; regnum++) - state->state_add(MCS48_R0 + regnum, tempstr.format("R%d", regnum), cpustate->rtemp).callimport().callexport(); + state_add(MCS48_R0 + regnum, tempstr.format("R%d", regnum), m_rtemp).callimport().callexport(); - state->state_add(MCS48_EA, "EA", cpustate->ea).mask(0x1); + state_add(MCS48_EA, "EA", m_ea).mask(0x1); - if (feature_mask & UPI41_FEATURE) + if (m_feature_mask & UPI41_FEATURE) { - state->state_add(MCS48_STS, "STS", cpustate->sts); - state->state_add(MCS48_DBBI, "DBBI", cpustate->dbbi); - state->state_add(MCS48_DBBO, "DBBO", cpustate->dbbo); + state_add(MCS48_STS, "STS", m_sts); + state_add(MCS48_DBBI, "DBBI", m_dbbi); + state_add(MCS48_DBBO, "DBBO", m_dbbo); } } /* ensure that regptr is valid before get_info gets called */ - update_regptr(cpustate); + update_regptr(); - device->save_item(NAME(cpustate->prevpc)); - device->save_item(NAME(cpustate->pc)); + save_item(NAME(m_prevpc)); + save_item(NAME(m_pc)); - device->save_item(NAME(cpustate->a)); - device->save_item(NAME(cpustate->psw)); - device->save_item(NAME(cpustate->p1)); - device->save_item(NAME(cpustate->p2)); - device->save_item(NAME(cpustate->ea)); - device->save_item(NAME(cpustate->timer)); - device->save_item(NAME(cpustate->prescaler)); - device->save_item(NAME(cpustate->t1_history)); - device->save_item(NAME(cpustate->sts)); - device->save_item(NAME(cpustate->dbbi)); - device->save_item(NAME(cpustate->dbbo)); + save_item(NAME(m_a)); + save_item(NAME(m_psw)); + save_item(NAME(m_p1)); + save_item(NAME(m_p2)); + save_item(NAME(m_ea)); + save_item(NAME(m_timer)); + save_item(NAME(m_prescaler)); + save_item(NAME(m_t1_history)); + save_item(NAME(m_sts)); + save_item(NAME(m_dbbi)); + save_item(NAME(m_dbbo)); - device->save_item(NAME(cpustate->irq_state)); - device->save_item(NAME(cpustate->irq_in_progress)); - device->save_item(NAME(cpustate->timer_overflow)); - device->save_item(NAME(cpustate->timer_flag)); - device->save_item(NAME(cpustate->tirq_enabled)); - device->save_item(NAME(cpustate->xirq_enabled)); - device->save_item(NAME(cpustate->timecount_enabled)); - device->save_item(NAME(cpustate->flags_enabled)); - device->save_item(NAME(cpustate->dma_enabled)); + save_item(NAME(m_irq_state)); + save_item(NAME(m_irq_in_progress)); + save_item(NAME(m_timer_overflow)); + save_item(NAME(m_timer_flag)); + save_item(NAME(m_tirq_enabled)); + save_item(NAME(m_xirq_enabled)); + save_item(NAME(m_timecount_enabled)); + save_item(NAME(m_flags_enabled)); + save_item(NAME(m_dma_enabled)); - device->save_item(NAME(cpustate->a11)); + save_item(NAME(m_a11)); + + m_icountptr = &m_icount; } -/*------------------------------------------------- - mcs48_norom_init - initialization for systems - with no internal ROM --------------------------------------------------*/ - -static CPU_INIT( mcs48_norom ) +void mcs48_cpu_device::device_reset() { - mcs48_init(device, irqcallback, MCS48_FEATURE, 0x0); -} - - -/*------------------------------------------------- - mcs48_1k_rom_init - initialization for systems - with 1k of internal ROM --------------------------------------------------*/ - -static CPU_INIT( mcs48_1k_rom ) -{ - mcs48_init(device, irqcallback, MCS48_FEATURE, 0x400); -} - - -/*------------------------------------------------- - mcs48_2k_rom - initialization for systems - with 2k of internal ROM --------------------------------------------------*/ - -static CPU_INIT( mcs48_2k_rom ) -{ - mcs48_init(device, irqcallback, MCS48_FEATURE, 0x800); -} - - -/*------------------------------------------------- - mcs48_4k_rom - initialization for systems - with 2k of internal ROM --------------------------------------------------*/ - -static CPU_INIT( mcs48_4k_rom ) -{ - mcs48_init(device, irqcallback, MCS48_FEATURE, 0x1000); -} - - -/*------------------------------------------------- - upi41_1k_rom_init - initialization for systems - with 1k of internal ROM --------------------------------------------------*/ - -static CPU_INIT( upi41_1k_rom ) -{ - mcs48_init(device, irqcallback, UPI41_FEATURE, 0x400); -} - - -/*------------------------------------------------- - upi41_2k_rom_init - initialization for systems - with 2k of internal ROM --------------------------------------------------*/ - -static CPU_INIT( upi41_2k_rom ) -{ - mcs48_init(device, irqcallback, UPI41_FEATURE, 0x800); -} - - -/*------------------------------------------------- - mcs48_reset - general reset routine --------------------------------------------------*/ - -static CPU_RESET( mcs48 ) -{ - mcs48_state *cpustate = get_safe_token(device); - /* confirmed from reset description */ - cpustate->pc = 0; - cpustate->psw = (cpustate->psw & (C_FLAG | A_FLAG)) | 0x08; - cpustate->a11 = 0x000; + m_pc = 0; + m_psw = (m_psw & (C_FLAG | A_FLAG)) | 0x08; + m_a11 = 0x000; bus_w(0xff); - cpustate->p1 = 0xff; - cpustate->p2 = 0xff; - port_w(1, cpustate->p1); - port_w(2, cpustate->p2); - cpustate->tirq_enabled = FALSE; - cpustate->xirq_enabled = FALSE; - cpustate->timecount_enabled = 0; - cpustate->timer_flag = FALSE; - cpustate->sts = 0; - cpustate->flags_enabled = FALSE; - cpustate->dma_enabled = FALSE; + m_p1 = 0xff; + m_p2 = 0xff; + port_w(1, m_p1); + port_w(2, m_p2); + m_tirq_enabled = FALSE; + m_xirq_enabled = FALSE; + m_timecount_enabled = 0; + m_timer_flag = FALSE; + m_sts = 0; + m_flags_enabled = FALSE; + m_dma_enabled = FALSE; /* confirmed from interrupt logic description */ - cpustate->irq_in_progress = FALSE; - cpustate->timer_overflow = FALSE; + m_irq_in_progress = FALSE; + m_timer_overflow = FALSE; } @@ -1031,38 +1058,37 @@ static CPU_RESET( mcs48 ) check_irqs - check for and process IRQs -------------------------------------------------*/ -static int check_irqs(mcs48_state *cpustate) +int mcs48_cpu_device::check_irqs() { /* if something is in progress, we do nothing */ - if (cpustate->irq_in_progress) + if (m_irq_in_progress) return 0; /* external interrupts take priority */ - if ((cpustate->irq_state || (cpustate->sts & STS_IBF) != 0) && cpustate->xirq_enabled) + if ((m_irq_state || (m_sts & STS_IBF) != 0) && m_xirq_enabled) { - cpustate->irq_in_progress = TRUE; + m_irq_in_progress = TRUE; /* transfer to location 0x03 */ - push_pc_psw(cpustate); - cpustate->pc = 0x03; + push_pc_psw(); + m_pc = 0x03; /* indicate we took the external IRQ */ - if (cpustate->irq_callback != NULL) - (*cpustate->irq_callback)(cpustate->device, 0); + standard_irq_callback(0); return 2; } /* timer overflow interrupts follow */ - if (cpustate->timer_overflow && cpustate->tirq_enabled) + if (m_timer_overflow && m_tirq_enabled) { - cpustate->irq_in_progress = TRUE; + m_irq_in_progress = TRUE; /* transfer to location 0x07 */ - push_pc_psw(cpustate); - cpustate->pc = 0x07; + push_pc_psw(); + m_pc = 0x07; /* timer overflow flip-flop is reset once taken */ - cpustate->timer_overflow = FALSE; + m_timer_overflow = FALSE; return 2; } return 0; @@ -1074,39 +1100,39 @@ static int check_irqs(mcs48_state *cpustate) and counters -------------------------------------------------*/ -static void burn_cycles(mcs48_state *cpustate, int count) +void mcs48_cpu_device::burn_cycles(int count) { int timerover = FALSE; /* if the timer is enabled, accumulate prescaler cycles */ - if (cpustate->timecount_enabled & TIMER_ENABLED) + if (m_timecount_enabled & TIMER_ENABLED) { - UINT8 oldtimer = cpustate->timer; - cpustate->prescaler += count; - cpustate->timer += cpustate->prescaler >> 5; - cpustate->prescaler &= 0x1f; - timerover = (oldtimer != 0 && cpustate->timer == 0); + UINT8 oldtimer = m_timer; + m_prescaler += count; + m_timer += m_prescaler >> 5; + m_prescaler &= 0x1f; + timerover = (oldtimer != 0 && m_timer == 0); } /* if the counter is enabled, poll the T1 test input once for each cycle */ - else if (cpustate->timecount_enabled & COUNTER_ENABLED) + else if (m_timecount_enabled & COUNTER_ENABLED) for ( ; count > 0; count--) { - cpustate->t1_history = (cpustate->t1_history << 1) | (test_r(1) & 1); - if ((cpustate->t1_history & 3) == 2) - timerover = (++cpustate->timer == 0); + m_t1_history = (m_t1_history << 1) | (test_r(1) & 1); + if ((m_t1_history & 3) == 2) + timerover = (++m_timer == 0); } /* if either source caused a timer overflow, set the flags and check IRQs */ if (timerover) { - cpustate->timer_flag = TRUE; + m_timer_flag = TRUE; /* according to the docs, if an overflow occurs with interrupts disabled, the overflow is not stored */ - if (cpustate->tirq_enabled) + if (m_tirq_enabled) { - cpustate->timer_overflow = TRUE; - check_irqs(cpustate); + m_timer_overflow = TRUE; + check_irqs(); } } } @@ -1117,18 +1143,17 @@ static void burn_cycles(mcs48_state *cpustate, int count) of cycles -------------------------------------------------*/ -static CPU_EXECUTE( mcs48 ) +void mcs48_cpu_device::execute_run() { - mcs48_state *cpustate = get_safe_token(device); int curcycles; - update_regptr(cpustate); + update_regptr(); /* external interrupts may have been set since we last checked */ - curcycles = check_irqs(cpustate); - cpustate->icount -= curcycles; - if (cpustate->timecount_enabled != 0) - burn_cycles(cpustate, curcycles); + curcycles = check_irqs(); + m_icount -= curcycles; + if (m_timecount_enabled != 0) + burn_cycles(curcycles); /* iterate over remaining cycles, guaranteeing at least one instruction */ do @@ -1136,19 +1161,19 @@ static CPU_EXECUTE( mcs48 ) unsigned opcode; /* fetch next opcode */ - cpustate->prevpc = cpustate->pc; - debugger_instruction_hook(device, cpustate->pc); - opcode = opcode_fetch(cpustate); + m_prevpc = m_pc; + debugger_instruction_hook(this, m_pc); + opcode = opcode_fetch(); /* process opcode and count cycles */ - curcycles = (*opcode_table[opcode])(cpustate); + curcycles = (this->*s_opcode_table[opcode])(); /* burn the cycles */ - cpustate->icount -= curcycles; - if (cpustate->timecount_enabled != 0) - burn_cycles(cpustate, curcycles); + m_icount -= curcycles; + if (m_timecount_enabled != 0) + burn_cycles(curcycles); - } while (cpustate->icount > 0); + } while (m_icount > 0); } @@ -1162,22 +1187,20 @@ static CPU_EXECUTE( mcs48 ) read -------------------------------------------------*/ -UINT8 upi41_master_r(device_t *device, UINT8 a0) +READ8_MEMBER( upi41_cpu_device::upi41_master_r ) { - mcs48_state *cpustate = get_safe_token(device); - /* if just reading the status, return it */ - if ((a0 & 1) != 0) - return cpustate->sts; + if ((offset & 1) != 0) + return m_sts; /* if the output buffer was full, it gets cleared now */ - if (cpustate->sts & STS_OBF) + if (m_sts & STS_OBF) { - cpustate->sts &= ~STS_OBF; - if (cpustate->flags_enabled) - port_w(2, cpustate->p2 &= ~P2_OBF); + m_sts &= ~STS_OBF; + if (m_flags_enabled) + port_w(2, m_p2 &= ~P2_OBF); } - return cpustate->dbbo; + return m_dbbo; } @@ -1186,70 +1209,36 @@ UINT8 upi41_master_r(device_t *device, UINT8 a0) write -------------------------------------------------*/ -static TIMER_CALLBACK( master_callback ) +TIMER_CALLBACK_MEMBER( upi41_cpu_device::master_callback ) { - legacy_cpu_device *device = (legacy_cpu_device *)ptr; - mcs48_state *cpustate = get_safe_token(device); UINT8 a0 = (param >> 8) & 1; UINT8 data = param; /* data always goes to the input buffer */ - cpustate->dbbi = data; + m_dbbi = data; /* set the appropriate flags */ - if ((cpustate->sts & STS_IBF) == 0) + if ((m_sts & STS_IBF) == 0) { - cpustate->sts |= STS_IBF; - if (cpustate->flags_enabled) - port_w(2, cpustate->p2 &= ~P2_NIBF); + m_sts |= STS_IBF; + if (m_flags_enabled) + port_w(2, m_p2 &= ~P2_NIBF); } /* set F1 accordingly */ if (a0 == 0) - cpustate->sts &= ~STS_F1; + m_sts &= ~STS_F1; else - cpustate->sts |= STS_F1; + m_sts |= STS_F1; } -void upi41_master_w(device_t *_device, UINT8 a0, UINT8 data) +WRITE8_MEMBER( upi41_cpu_device::upi41_master_w ) { - legacy_cpu_device *device = downcast(_device); - device->machine().scheduler().synchronize(FUNC(master_callback), (a0 << 8) | data, (void *)device); + machine().scheduler().synchronize(timer_expired_delegate(FUNC(upi41_cpu_device::master_callback), this), (offset << 8) | data); } -/*************************************************************************** - ADDRESS MAPS -***************************************************************************/ - -/* FIXME: the memory maps should probably support rom banking for EA */ -static ADDRESS_MAP_START(program_10bit, AS_PROGRAM, 8, legacy_cpu_device) - AM_RANGE(0x000, 0x3ff) AM_ROM -ADDRESS_MAP_END - -static ADDRESS_MAP_START(program_11bit, AS_PROGRAM, 8, legacy_cpu_device) - AM_RANGE(0x000, 0x7ff) AM_ROM -ADDRESS_MAP_END - -static ADDRESS_MAP_START(program_12bit, AS_PROGRAM, 8, legacy_cpu_device) - AM_RANGE(0x000, 0xfff) AM_ROM -ADDRESS_MAP_END - -static ADDRESS_MAP_START(data_6bit, AS_DATA, 8, legacy_cpu_device) - AM_RANGE(0x00, 0x3f) AM_RAM -ADDRESS_MAP_END - -static ADDRESS_MAP_START(data_7bit, AS_DATA, 8, legacy_cpu_device) - AM_RANGE(0x00, 0x7f) AM_RAM -ADDRESS_MAP_END - -static ADDRESS_MAP_START(data_8bit, AS_DATA, 8, legacy_cpu_device) - AM_RANGE(0x00, 0xff) AM_RAM -ADDRESS_MAP_END - - - /*************************************************************************** GENERAL CONTEXT ACCESS ***************************************************************************/ @@ -1259,10 +1248,8 @@ ADDRESS_MAP_END debugger into our internal format -------------------------------------------------*/ -static CPU_IMPORT_STATE( mcs48 ) +void mcs48_cpu_device::state_import(const device_state_entry &entry) { - mcs48_state *cpustate = get_safe_token(device); - switch (entry.index()) { case MCS48_R0: @@ -1273,7 +1260,7 @@ static CPU_IMPORT_STATE( mcs48 ) case MCS48_R5: case MCS48_R6: case MCS48_R7: - cpustate->regptr[entry.index() - MCS48_R0] = cpustate->rtemp; + m_regptr[entry.index() - MCS48_R0] = m_rtemp; break; default: @@ -1288,10 +1275,8 @@ static CPU_IMPORT_STATE( mcs48 ) exporting to the debugger -------------------------------------------------*/ -static CPU_EXPORT_STATE( mcs48 ) +void mcs48_cpu_device::state_export(const device_state_entry &entry) { - mcs48_state *cpustate = get_safe_token(device); - switch (entry.index()) { case MCS48_R0: @@ -1302,7 +1287,7 @@ static CPU_EXPORT_STATE( mcs48 ) case MCS48_R5: case MCS48_R6: case MCS48_R7: - cpustate->rtemp = cpustate->regptr[entry.index() - MCS48_R0]; + m_rtemp = m_regptr[entry.index() - MCS48_R0]; break; default: @@ -1311,242 +1296,38 @@ static CPU_EXPORT_STATE( mcs48 ) } } -static CPU_EXPORT_STRING( mcs48 ) +void mcs48_cpu_device::state_string_export(const device_state_entry &entry, astring &string) { - mcs48_state *cpustate = get_safe_token(device); - switch (entry.index()) { case CPUINFO_STR_FLAGS: string.printf("%c%c %c%c%c%c%c%c%c%c", - cpustate->irq_state ? 'I':'.', - cpustate->a11 ? 'M':'.', - cpustate->psw & 0x80 ? 'C':'.', - cpustate->psw & 0x40 ? 'A':'.', - cpustate->psw & 0x20 ? 'F':'.', - cpustate->psw & 0x10 ? 'B':'.', - cpustate->psw & 0x08 ? '?':'.', - cpustate->psw & 0x04 ? '4':'.', - cpustate->psw & 0x02 ? '2':'.', - cpustate->psw & 0x01 ? '1':'.'); + m_irq_state ? 'I':'.', + m_a11 ? 'M':'.', + m_psw & 0x80 ? 'C':'.', + m_psw & 0x40 ? 'A':'.', + m_psw & 0x20 ? 'F':'.', + m_psw & 0x10 ? 'B':'.', + m_psw & 0x08 ? '?':'.', + m_psw & 0x04 ? '4':'.', + m_psw & 0x02 ? '2':'.', + m_psw & 0x01 ? '1':'.'); break; } } -/*------------------------------------------------- - mcs48_set_info - set a piece of information - on the CPU core --------------------------------------------------*/ -static CPU_SET_INFO( mcs48 ) +void mcs48_cpu_device::execute_set_input(int inputnum, int state) { - mcs48_state *cpustate = get_safe_token(device); - - switch (state) + switch( inputnum ) { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + MCS48_INPUT_IRQ: cpustate->irq_state = (info->i != CLEAR_LINE); break; - case CPUINFO_INT_INPUT_STATE + MCS48_INPUT_EA: cpustate->ea = (info->i != CLEAR_LINE); break; - } -} - - -/*------------------------------------------------- - mcs48_get_info - retrieve a piece of - information from the CPU core --------------------------------------------------*/ - -static CPU_GET_INFO( mcs48 ) -{ - mcs48_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(mcs48_state); break; - case CPUINFO_INT_INPUT_LINES: info->i = 2; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = MCS48_INPUT_IRQ; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 2; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 3; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 12; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: /*info->i = 6 or 7 or 8;*/ break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 9; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + MCS48_INPUT_IRQ: info->i = cpustate->irq_state ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + MCS48_INPUT_EA: info->i = cpustate->ea; break; - - /* --- the following bits of info are returned as pointers to functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mcs48); break; - case CPUINFO_FCT_INIT: /* set per-core */ break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(mcs48); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(mcs48); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(mcs48); break; - case CPUINFO_FCT_IMPORT_STATE: info->import_state = CPU_IMPORT_STATE_NAME(mcs48); break; - case CPUINFO_FCT_EXPORT_STATE: info->export_state = CPU_EXPORT_STATE_NAME(mcs48); break; - case CPUINFO_FCT_EXPORT_STRING: info->export_string = CPU_EXPORT_STRING_NAME(mcs48); break; - - /* --- the following bits of info are returned as pointers --- */ - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: /* set per-core */ break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: /* set per-core */ break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: /* set per-core */ break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Intel 8039"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.2"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Mirko Buffoni\nBased on the original work Copyright Dan Boris"); break; - } -} - - - -/*************************************************************************** - CPU-SPECIFIC CONTEXT ACCESS -***************************************************************************/ - -static void mcs48_generic_get_info(legacy_cpu_device *device, UINT32 state, cpuinfo *info, UINT8 features, int romsize, int ramsize, int cycle_states, const char *name, const char *shortname) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CLOCK_DIVIDER: - info->i = 3 * cycle_states; + case MCS48_INPUT_IRQ: + m_irq_state = (state != CLEAR_LINE); break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: - if (ramsize == 64) - info->i = 6; - else if (ramsize == 128) - info->i = 7; - else if (ramsize == 256) - info->i = 8; - else - fatalerror("mcs48_generic_get_info: Invalid RAM size\n"); - break; - - /* --- the following bits of info are returned as pointers to functions --- */ - case CPUINFO_FCT_INIT: - if (romsize == 0) - info->init = CPU_INIT_NAME(mcs48_norom); - else if (romsize == 1024) - info->init = (features == UPI41_FEATURE) ? CPU_INIT_NAME(upi41_1k_rom) : CPU_INIT_NAME(mcs48_1k_rom); - else if (romsize == 2048) - info->init = (features == UPI41_FEATURE) ? CPU_INIT_NAME(upi41_2k_rom) : CPU_INIT_NAME(mcs48_2k_rom); - else if (romsize == 4096) - info->init = CPU_INIT_NAME(mcs48_4k_rom); - else - fatalerror("mcs48_generic_get_info: Invalid ROM size\n"); - break; - - case CPUINFO_FCT_DISASSEMBLE: - if (features == UPI41_FEATURE) - info->disassemble = CPU_DISASSEMBLE_NAME(upi41); - else - info->disassemble = CPU_DISASSEMBLE_NAME(mcs48); - break; - - /* --- the following bits of info are returned as pointers --- */ - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: - if (romsize == 0) - info->internal_map8 = NULL; - else if (romsize == 1024) - info->internal_map8 = ADDRESS_MAP_NAME(program_10bit); - else if (romsize == 2048) - info->internal_map8 = ADDRESS_MAP_NAME(program_11bit); - else if (romsize == 4096) - info->internal_map8 = ADDRESS_MAP_NAME(program_12bit); - else - fatalerror("mcs48_generic_get_info: Invalid RAM size\n"); - break; - - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: - if (ramsize == 64) - info->internal_map8 = ADDRESS_MAP_NAME(data_6bit); - else if (ramsize == 128) - info->internal_map8 = ADDRESS_MAP_NAME(data_7bit); - else if (ramsize == 256) - info->internal_map8 = ADDRESS_MAP_NAME(data_8bit); - else - fatalerror("mcs48_generic_get_info: Invalid RAM size\n"); - break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: - strcpy(info->s, name); - break; - - case CPUINFO_STR_SHORTNAME: - strcpy(info->s, shortname); - break; - - /* default case */ - default: - CPU_GET_INFO_CALL(mcs48); + case MCS48_INPUT_EA: + m_ea = (state != CLEAR_LINE); break; } } - -/* Official Intel MCS-48 parts */ -CPU_GET_INFO( i8021 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 1024, 64, 10, "I8021", "i8021"); } -CPU_GET_INFO( i8022 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 2048, 128, 10, "I8022", "i8022"); } -CPU_GET_INFO( i8035 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 0, 64, 5, "I8035", "i8035"); } -CPU_GET_INFO( i8048 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 1024, 64, 5, "I8048", "i8048"); } -CPU_GET_INFO( i8648 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 1024, 64, 5, "I8648", "i8648"); } -CPU_GET_INFO( i8748 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 1024, 64, 5, "I8748", "i8748"); } -CPU_GET_INFO( i8039 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 0, 128, 5, "I8039", "i8039"); } -CPU_GET_INFO( i8049 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 2048, 128, 5, "I8049", "i8049"); } -CPU_GET_INFO( i8749 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 2048, 128, 5, "I8749", "i8749"); } -CPU_GET_INFO( i8040 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 0, 256, 5, "I8040", "i8040"); } -CPU_GET_INFO( i8050 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 4096, 256, 5, "I8050", "i8050"); } - - -/* Official Intel UPI-41 parts */ -CPU_GET_INFO( i8041 ) { mcs48_generic_get_info(device, state, info, UPI41_FEATURE, 1024, 128, 5, "I8041", "i8041"); } -CPU_GET_INFO( i8741 ) { mcs48_generic_get_info(device, state, info, UPI41_FEATURE, 1024, 128, 5, "I8741", "i8741"); } -CPU_GET_INFO( i8042 ) { mcs48_generic_get_info(device, state, info, UPI41_FEATURE, 2048, 256, 5, "I8042", "i8042"); } -CPU_GET_INFO( i8242 ) { mcs48_generic_get_info(device, state, info, UPI41_FEATURE, 2048, 256, 5, "I8242", "i8242"); } -CPU_GET_INFO( i8742 ) { mcs48_generic_get_info(device, state, info, UPI41_FEATURE, 2048, 256, 5, "I8742", "i8742"); } - - -/* Clones */ -CPU_GET_INFO( mb8884 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 0, 64, 5, "MB8884", "mb8884"); } -CPU_GET_INFO( n7751 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 1024, 64, 5, "N7751", "n7751"); } -CPU_GET_INFO( m58715 ) { mcs48_generic_get_info(device, state, info, MCS48_FEATURE, 2048, 128, 5, "M58715", "m58715"); } - -/* Official Intel MCS-48 parts */ -DEFINE_LEGACY_CPU_DEVICE(I8021, i8021); /* 1k internal ROM, 64 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8022, i8022); /* 2k internal ROM, 128 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8035, i8035); /* external ROM, 64 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8048, i8048); /* 1k internal ROM, 64 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8648, i8648); /* 1k internal OTP ROM, 64 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8748, i8748); /* 1k internal EEPROM, 64 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8039, i8039); /* external ROM, 128 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8049, i8049); /* 2k internal ROM, 128 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8749, i8749); /* 2k internal EEPROM, 128 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8040, i8040); /* external ROM, 256 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8050, i8050); /* 4k internal ROM, 256 bytes internal RAM */ - -/* Official Intel UPI-41 parts */ -DEFINE_LEGACY_CPU_DEVICE(I8041, i8041); /* 1k internal ROM, 128 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8741, i8741); /* 1k internal EEPROM, 128 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8042, i8042); /* 2k internal ROM, 256 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8242, i8242); /* 2k internal ROM, 256 bytes internal RAM */ -DEFINE_LEGACY_CPU_DEVICE(I8742, i8742); /* 2k internal EEPROM, 256 bytes internal RAM */ - -/* Clones */ -DEFINE_LEGACY_CPU_DEVICE(MB8884, mb8884); /* 8035 clone */ -DEFINE_LEGACY_CPU_DEVICE(N7751, n7751); /* 8048 clone */ -DEFINE_LEGACY_CPU_DEVICE(M58715, m58715); /* 8049 clone */ diff --git a/src/emu/cpu/mcs48/mcs48.h b/src/emu/cpu/mcs48/mcs48.h index 590eb7f9152..b95ea95b405 100644 --- a/src/emu/cpu/mcs48/mcs48.h +++ b/src/emu/cpu/mcs48/mcs48.h @@ -94,44 +94,548 @@ enum attotime::from_hz(_clock/(3*5)) /* Official Intel MCS-48 parts */ -DECLARE_LEGACY_CPU_DEVICE(I8021, i8021); /* 1k internal ROM, 64 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8022, i8022); /* 2k internal ROM, 128 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8035, i8035); /* external ROM, 64 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8048, i8048); /* 1k internal ROM, 64 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8648, i8648); /* 1k internal OTP ROM, 64 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8748, i8748); /* 1k internal EEPROM, 64 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8039, i8039); /* external ROM, 128 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8049, i8049); /* 2k internal ROM, 128 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8749, i8749); /* 2k internal EEPROM, 128 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8040, i8040); /* external ROM, 256 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8050, i8050); /* 4k internal ROM, 256 bytes internal RAM */ +extern const device_type I8021; /* 1k internal ROM, 64 bytes internal RAM */ +extern const device_type I8022; /* 2k internal ROM, 128 bytes internal RAM */ +extern const device_type I8035; /* external ROM, 64 bytes internal RAM */ +extern const device_type I8048; /* 1k internal ROM, 64 bytes internal RAM */ +extern const device_type I8648; /* 1k internal OTP ROM, 64 bytes internal RAM */ +extern const device_type I8748; /* 1k internal EEPROM, 64 bytes internal RAM */ +extern const device_type I8039; /* external ROM, 128 bytes internal RAM */ +extern const device_type I8049; /* 2k internal ROM, 128 bytes internal RAM */ +extern const device_type I8749; /* 2k internal EEPROM, 128 bytes internal RAM */ +extern const device_type I8040; /* external ROM, 256 bytes internal RAM */ +extern const device_type I8050; /* 4k internal ROM, 256 bytes internal RAM */ /* Official Intel UPI-41 parts */ -DECLARE_LEGACY_CPU_DEVICE(I8041, i8041); /* 1k internal ROM, 128 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8741, i8741); /* 1k internal EEPROM, 128 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8042, i8042); /* 2k internal ROM, 256 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8242, i8242); /* 2k internal ROM, 256 bytes internal RAM */ -DECLARE_LEGACY_CPU_DEVICE(I8742, i8742); /* 2k internal EEPROM, 256 bytes internal RAM */ +extern const device_type I8041; /* 1k internal ROM, 128 bytes internal RAM */ +extern const device_type I8741; /* 1k internal EEPROM, 128 bytes internal RAM */ +extern const device_type I8042; /* 2k internal ROM, 256 bytes internal RAM */ +extern const device_type I8242; /* 2k internal ROM, 256 bytes internal RAM */ +extern const device_type I8742; /* 2k internal EEPROM, 256 bytes internal RAM */ /* Clones */ -DECLARE_LEGACY_CPU_DEVICE(MB8884, mb8884); /* 8035 clone */ -DECLARE_LEGACY_CPU_DEVICE(N7751, n7751); /* 8048 clone */ -DECLARE_LEGACY_CPU_DEVICE(M58715, m58715); /* 8049 clone */ +extern const device_type MB8884; /* 8035 clone */ +extern const device_type N7751; /* 8048 clone */ +extern const device_type M58715; /* 8049 clone */ -/*************************************************************************** - FUNCTION PROTOTYPES -***************************************************************************/ +class mcs48_cpu_device : public cpu_device +{ +public: + // construction/destruction + mcs48_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int rom_size, int ram_size, UINT8 feature_mask = 0); -/* functions for talking to the input/output buffers on the UPI41-class chips */ -UINT8 upi41_master_r(device_t *device, UINT8 a0); -void upi41_master_w(device_t *device, UINT8 a0, UINT8 data); +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 15 - 1) / 15; } + virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 15); } + virtual UINT32 execute_min_cycles() const { return 1; } + virtual UINT32 execute_max_cycles() const { return 3; } + virtual UINT32 execute_input_lines() const { return 2; } + virtual UINT32 execute_default_irq_vector() const { return MCS48_INPUT_IRQ; } + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const + { + return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) ); + } + + // device_state_interface overrides + virtual void state_import(const device_state_entry &entry); + virtual void state_export(const device_state_entry &entry); + void state_string_export(const device_state_entry &entry, astring &string); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 1; } + virtual UINT32 disasm_max_opcode_bytes() const { return 2; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + +protected: + address_space_config m_program_config; + address_space_config m_data_config; + address_space_config m_io_config; + + UINT16 m_prevpc; /* 16-bit previous program counter */ + UINT16 m_pc; /* 16-bit program counter */ + + UINT8 m_a; /* 8-bit accumulator */ + UINT8 * m_regptr; /* pointer to r0-r7 */ + UINT8 m_psw; /* 8-bit psw */ + UINT8 m_p1; /* 8-bit latched port 1 */ + UINT8 m_p2; /* 8-bit latched port 2 */ + UINT8 m_ea; /* 1-bit latched ea input */ + UINT8 m_timer; /* 8-bit timer */ + UINT8 m_prescaler; /* 5-bit timer prescaler */ + UINT8 m_t1_history; /* 8-bit history of the T1 input */ + UINT8 m_sts; /* 8-bit status register (UPI-41 only, except for F1) */ + UINT8 m_dbbi; /* 8-bit input data buffer (UPI-41 only) */ + UINT8 m_dbbo; /* 8-bit output data buffer (UPI-41 only) */ + + UINT8 m_irq_state; /* TRUE if an IRQ is pending */ + UINT8 m_irq_in_progress; /* TRUE if an IRQ is in progress */ + UINT8 m_timer_overflow; /* TRUE on a timer overflow; cleared by taking interrupt */ + UINT8 m_timer_flag; /* TRUE on a timer overflow; cleared on JTF */ + UINT8 m_tirq_enabled; /* TRUE if the timer IRQ is enabled */ + UINT8 m_xirq_enabled; /* TRUE if the external IRQ is enabled */ + UINT8 m_timecount_enabled; /* bitmask of timer/counter enabled */ + UINT8 m_flags_enabled; /* TRUE if I/O flags have been enabled (UPI-41 only) */ + UINT8 m_dma_enabled; /* TRUE if DMA has been enabled (UPI-41 only) */ + + UINT16 m_a11; /* A11 value, either 0x000 or 0x800 */ + + int m_icount; + + /* Memory spaces */ + address_space *m_program; + direct_read_data *m_direct; + address_space *m_data; + address_space *m_io; + + UINT8 m_feature_mask; /* processor feature flags */ + UINT16 m_int_rom_size; /* internal rom size */ + + UINT8 m_rtemp; /* temporary for import/export */ + + typedef int (mcs48_cpu_device::*mcs48_ophandler)(); + static const mcs48_ophandler s_opcode_table[256]; + + UINT8 opcode_fetch(); + UINT8 argument_fetch(); + void update_regptr(); + void push_pc_psw(); + void pull_pc_psw(); + void pull_pc(); + void execute_add(UINT8 dat); + void execute_addc(UINT8 dat); + void execute_jmp(UINT16 address); + void execute_call(UINT16 address); + void execute_jcc(UINT8 result); + UINT8 p2_mask(); + void expander_operation(UINT8 operation, UINT8 port); + int check_irqs(); + void burn_cycles(int count); + + int illegal(); + int add_a_r0(); + int add_a_r1(); + int add_a_r2(); + int add_a_r3(); + int add_a_r4(); + int add_a_r5(); + int add_a_r6(); + int add_a_r7(); + int add_a_xr0(); + int add_a_xr1(); + int add_a_n(); + int adc_a_r0(); + int adc_a_r1(); + int adc_a_r2(); + int adc_a_r3(); + int adc_a_r4(); + int adc_a_r5(); + int adc_a_r6(); + int adc_a_r7(); + int adc_a_xr0(); + int adc_a_xr1(); + int adc_a_n(); + int anl_a_r0(); + int anl_a_r1(); + int anl_a_r2(); + int anl_a_r3(); + int anl_a_r4(); + int anl_a_r5(); + int anl_a_r6(); + int anl_a_r7(); + int anl_a_xr0(); + int anl_a_xr1(); + int anl_a_n(); + int anl_bus_n(); + int anl_p1_n(); + int anl_p2_n(); + int anld_p4_a(); + int anld_p5_a(); + int anld_p6_a(); + int anld_p7_a(); + int call_0(); + int call_1(); + int call_2(); + int call_3(); + int call_4(); + int call_5(); + int call_6(); + int call_7(); + int clr_a(); + int clr_c(); + int clr_f0(); + int clr_f1(); + int cpl_a(); + int cpl_c(); + int cpl_f0(); + int cpl_f1(); + int da_a(); + int dec_a(); + int dec_r0(); + int dec_r1(); + int dec_r2(); + int dec_r3(); + int dec_r4(); + int dec_r5(); + int dec_r6(); + int dec_r7(); + int dis_i(); + int dis_tcnti(); + int djnz_r0(); + int djnz_r1(); + int djnz_r2(); + int djnz_r3(); + int djnz_r4(); + int djnz_r5(); + int djnz_r6(); + int djnz_r7(); + int en_i(); + int en_tcnti(); + int en_dma(); + int en_flags(); + int ent0_clk(); + int in_a_p1(); + int in_a_p2(); + int ins_a_bus(); + int in_a_dbb(); + int inc_a(); + int inc_r0(); + int inc_r1(); + int inc_r2(); + int inc_r3(); + int inc_r4(); + int inc_r5(); + int inc_r6(); + int inc_r7(); + int inc_xr0(); + int inc_xr1(); + int jb_0(); + int jb_1(); + int jb_2(); + int jb_3(); + int jb_4(); + int jb_5(); + int jb_6(); + int jb_7(); + int jc(); + int jf0(); + int jf1(); + int jnc(); + int jni(); + int jnibf(); + int jnt_0(); + int jnt_1(); + int jnz(); + int jobf(); + int jtf(); + int jt_0(); + int jt_1(); + int jz(); + int jmp_0(); + int jmp_1(); + int jmp_2(); + int jmp_3(); + int jmp_4(); + int jmp_5(); + int jmp_6(); + int jmp_7(); + int jmpp_xa(); + int mov_a_n(); + int mov_a_psw(); + int mov_a_r0(); + int mov_a_r1(); + int mov_a_r2(); + int mov_a_r3(); + int mov_a_r4(); + int mov_a_r5(); + int mov_a_r6(); + int mov_a_r7(); + int mov_a_xr0(); + int mov_a_xr1(); + int mov_a_t(); + int mov_psw_a(); + int mov_sts_a(); + int mov_r0_a(); + int mov_r1_a(); + int mov_r2_a(); + int mov_r3_a(); + int mov_r4_a(); + int mov_r5_a(); + int mov_r6_a(); + int mov_r7_a(); + int mov_r0_n(); + int mov_r1_n(); + int mov_r2_n(); + int mov_r3_n(); + int mov_r4_n(); + int mov_r5_n(); + int mov_r6_n(); + int mov_r7_n(); + int mov_t_a(); + int mov_xr0_a(); + int mov_xr1_a(); + int mov_xr0_n(); + int mov_xr1_n(); + int movd_a_p4(); + int movd_a_p5(); + int movd_a_p6(); + int movd_a_p7(); + int movd_p4_a(); + int movd_p5_a(); + int movd_p6_a(); + int movd_p7_a(); + int movp_a_xa(); + int movp3_a_xa(); + int movx_a_xr0(); + int movx_a_xr1(); + int movx_xr0_a(); + int movx_xr1_a(); + int nop(); + int orl_a_r0(); + int orl_a_r1(); + int orl_a_r2(); + int orl_a_r3(); + int orl_a_r4(); + int orl_a_r5(); + int orl_a_r6(); + int orl_a_r7(); + int orl_a_xr0(); + int orl_a_xr1(); + int orl_a_n(); + int orl_bus_n(); + int orl_p1_n(); + int orl_p2_n(); + int orld_p4_a(); + int orld_p5_a(); + int orld_p6_a(); + int orld_p7_a(); + int outl_bus_a(); + int outl_p1_a(); + int outl_p2_a(); + int out_dbb_a(); + int ret(); + int retr(); + int rl_a(); + int rlc_a(); + int rr_a(); + int rrc_a(); + int sel_mb0(); + int sel_mb1(); + int sel_rb0(); + int sel_rb1(); + int stop_tcnt(); + int strt_cnt(); + int strt_t(); + int swap_a(); + int xch_a_r0(); + int xch_a_r1(); + int xch_a_r2(); + int xch_a_r3(); + int xch_a_r4(); + int xch_a_r5(); + int xch_a_r6(); + int xch_a_r7(); + int xch_a_xr0(); + int xch_a_xr1(); + int xchd_a_xr0(); + int xchd_a_xr1(); + int xrl_a_r0(); + int xrl_a_r1(); + int xrl_a_r2(); + int xrl_a_r3(); + int xrl_a_r4(); + int xrl_a_r5(); + int xrl_a_r6(); + int xrl_a_r7(); + int xrl_a_xr0(); + int xrl_a_xr1(); + int xrl_a_n(); + int split_02(); + int split_08(); + int split_22(); + int split_75(); + int split_80(); + int split_81(); + int split_86(); + int split_88(); + int split_90(); + int split_91(); + int split_98(); + int split_d6(); + int split_e5(); + int split_f5(); + +}; + +class i8021_device : public mcs48_cpu_device +{ +public: + // construction/destruction + i8021_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + +protected: + // device_execute_interface overrides + virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 30 - 1) / 30; } + virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 30); } +}; + +class i8022_device : public mcs48_cpu_device +{ +public: + // construction/destruction + i8022_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + +protected: + // device_execute_interface overrides + virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 30 - 1) / 30; } + virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 30); } +}; + +class i8035_device : public mcs48_cpu_device +{ +public: + // construction/destruction + i8035_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class i8048_device : public mcs48_cpu_device +{ +public: + // construction/destruction + i8048_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class i8648_device : public mcs48_cpu_device +{ +public: + // construction/destruction + i8648_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class i8748_device : public mcs48_cpu_device +{ +public: + // construction/destruction + i8748_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class i8039_device : public mcs48_cpu_device +{ +public: + // construction/destruction + i8039_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class i8049_device : public mcs48_cpu_device +{ +public: + // construction/destruction + i8049_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class i8749_device : public mcs48_cpu_device +{ +public: + // construction/destruction + i8749_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class i8040_device : public mcs48_cpu_device +{ +public: + // construction/destruction + i8040_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class i8050_device : public mcs48_cpu_device +{ +public: + // construction/destruction + i8050_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class mb8884_device : public mcs48_cpu_device +{ +public: + // construction/destruction + mb8884_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class n7751_device : public mcs48_cpu_device +{ +public: + // construction/destruction + n7751_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class m58715_device : public mcs48_cpu_device +{ +public: + // construction/destruction + m58715_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; -/* disassemblers */ -CPU_DISASSEMBLE( mcs48 ); -CPU_DISASSEMBLE( upi41 ); +class upi41_cpu_device : public mcs48_cpu_device +{ +public: + // construction/destruction + upi41_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int rom_size, int ram_size); + + /* functions for talking to the input/output buffers on the UPI41-class chips */ + DECLARE_READ8_MEMBER(upi41_master_r); + DECLARE_WRITE8_MEMBER(upi41_master_w); + +protected: + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + + TIMER_CALLBACK_MEMBER( master_callback ); +}; + +class i8041_device : public upi41_cpu_device +{ +public: + // construction/destruction + i8041_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class i8741_device : public upi41_cpu_device +{ +public: + // construction/destruction + i8741_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class i8042_device : public upi41_cpu_device +{ +public: + // construction/destruction + i8042_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class i8242_device : public upi41_cpu_device +{ +public: + // construction/destruction + i8242_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + +class i8742_device : public upi41_cpu_device +{ +public: + // construction/destruction + i8742_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; #endif /* __MCS48_H__ */ diff --git a/src/mame/includes/decocass.h b/src/mame/includes/decocass.h index c0b230facc9..a4f9066e507 100644 --- a/src/mame/includes/decocass.h +++ b/src/mame/includes/decocass.h @@ -6,6 +6,7 @@ #define LOG(n,x) do { if (LOGLEVEL >= n) logerror x; } while (0) #include "machine/decocass_tape.h" +#include "cpu/mcs48/mcs48.h" #define T1PROM 1 #define T1DIRECT 2 @@ -35,7 +36,7 @@ public: /* devices */ required_device m_maincpu; required_device m_audiocpu; - required_device m_mcu; + required_device m_mcu; required_device m_cassette; /* memory pointers */ diff --git a/src/mame/includes/tnzs.h b/src/mame/includes/tnzs.h index a4339a906de..884148392ca 100644 --- a/src/mame/includes/tnzs.h +++ b/src/mame/includes/tnzs.h @@ -1,6 +1,7 @@ #include "sound/dac.h" #include "sound/samples.h" #include "video/seta001.h" +#include "cpu/mcs48/mcs48.h" #define MAX_SAMPLES 0x2f /* max samples */ @@ -64,7 +65,7 @@ public: /* devices */ optional_device m_audiocpu; optional_device m_subcpu; - optional_device m_mcu; + optional_device m_mcu; DECLARE_WRITE8_MEMBER(tnzsb_sound_command_w); DECLARE_WRITE8_MEMBER(jpopnics_palette_w); DECLARE_WRITE8_MEMBER(jpopnics_subbankswitch_w); diff --git a/src/mame/machine/decocass.c b/src/mame/machine/decocass.c index 5d764c0d42e..f0910db1434 100644 --- a/src/mame/machine/decocass.c +++ b/src/mame/machine/decocass.c @@ -249,7 +249,7 @@ READ8_MEMBER(decocass_state::decocass_type1_r) if (1 == (offset & 1)) { if (0 == (offset & E5XX_MASK)) - data = upi41_master_r(m_mcu, 1); + data = m_mcu->upi41_master_r(space,1); else data = 0xff; @@ -279,7 +279,7 @@ READ8_MEMBER(decocass_state::decocass_type1_r) } if (0 == (offset & E5XX_MASK)) - data = upi41_master_r(m_mcu, 0); + data = m_mcu->upi41_master_r(space,0); else data = 0xff; @@ -426,7 +426,7 @@ READ8_MEMBER(decocass_state::decocass_type2_r) else { if (0 == (offset & E5XX_MASK)) - data = upi41_master_r(m_mcu, offset); + data = m_mcu->upi41_master_r(space,offset); else data = offset & 0xff; @@ -463,7 +463,7 @@ WRITE8_MEMBER(decocass_state::decocass_type2_w) LOG(3,("PROM:%s D2:%d", m_type2_xx_latch ? "on" : "off", m_type2_d2_latch)); } } - upi41_master_w(m_mcu, offset & 1, data); + m_mcu->upi41_master_w(space,offset & 1, data); #ifdef MAME_DEBUG decocass_fno(offset, data); @@ -506,7 +506,7 @@ READ8_MEMBER(decocass_state::decocass_type3_r) { if (0 == (offset & E5XX_MASK)) { - data = upi41_master_r(m_mcu, 1); + data = m_mcu->upi41_master_r(space,1); LOG(4,("%10s 6502-PC: %04x decocass_type3_r(%02x): $%02x <- 8041 STATUS\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data)); } else @@ -527,7 +527,7 @@ READ8_MEMBER(decocass_state::decocass_type3_r) { if (0 == (offset & E5XX_MASK)) { - save = upi41_master_r(m_mcu, 0); + save = m_mcu->upi41_master_r(space,0); switch (m_type3_swap) { case TYPE3_SWAP_01: @@ -710,7 +710,7 @@ WRITE8_MEMBER(decocass_state::decocass_type3_w) } } LOG(3,("%10s 6502-PC: %04x decocass_e5xx_w(%02x): $%02x -> %s\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, offset & 1 ? "8041-CMND" : "8041-DATA")); - upi41_master_w(m_mcu, offset, data); + m_mcu->upi41_master_w(space,offset, data); } /*************************************************************************** @@ -734,7 +734,7 @@ READ8_MEMBER(decocass_state::decocass_type4_r) { if (0 == (offset & E5XX_MASK)) { - data = upi41_master_r(m_mcu, 1); + data = m_mcu->upi41_master_r(space,1); LOG(4,("%10s 6502-PC: %04x decocass_type4_r(%02x): $%02x <- 8041 STATUS\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data)); } else @@ -757,7 +757,7 @@ READ8_MEMBER(decocass_state::decocass_type4_r) { if (0 == (offset & E5XX_MASK)) { - data = upi41_master_r(m_mcu, 0); + data = m_mcu->upi41_master_r(space,0); LOG(3,("%10s 6502-PC: %04x decocass_type4_r(%02x): $%02x '%c' <- open bus (D0 replaced with latch)\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, (data >= 32) ? data : '.')); } else @@ -797,7 +797,7 @@ WRITE8_MEMBER(decocass_state::decocass_type4_w) } } LOG(3,("%10s 6502-PC: %04x decocass_e5xx_w(%02x): $%02x -> %s\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, offset & 1 ? "8041-CMND" : "8041-DATA")); - upi41_master_w(m_mcu, offset, data); + m_mcu->upi41_master_w(space,offset, data); } /*************************************************************************** @@ -817,7 +817,7 @@ READ8_MEMBER(decocass_state::decocass_type5_r) { if (0 == (offset & E5XX_MASK)) { - data = upi41_master_r(m_mcu, 1); + data = m_mcu->upi41_master_r(space,1); LOG(4,("%10s 6502-PC: %04x decocass_type5_r(%02x): $%02x <- 8041 STATUS\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data)); } else @@ -837,7 +837,7 @@ READ8_MEMBER(decocass_state::decocass_type5_r) { if (0 == (offset & E5XX_MASK)) { - data = upi41_master_r(m_mcu, 0); + data = m_mcu->upi41_master_r(space,0); LOG(3,("%10s 6502-PC: %04x decocass_type5_r(%02x): $%02x '%c' <- open bus (D0 replaced with latch)\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, (data >= 32) ? data : '.')); } else @@ -874,7 +874,7 @@ WRITE8_MEMBER(decocass_state::decocass_type5_w) } } LOG(3,("%10s 6502-PC: %04x decocass_e5xx_w(%02x): $%02x -> %s\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, offset & 1 ? "8041-CMND" : "8041-DATA")); - upi41_master_w(m_mcu, offset, data); + m_mcu->upi41_master_w(space,offset, data); } /*************************************************************************** @@ -893,7 +893,7 @@ READ8_MEMBER(decocass_state::decocass_nodong_r) { if (0 == (offset & E5XX_MASK)) { - data = upi41_master_r(m_mcu, 1); + data = m_mcu->upi41_master_r(space,1); LOG(4,("%10s 6502-PC: %04x decocass_nodong_r(%02x): $%02x <- 8041 STATUS\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data)); } else @@ -906,7 +906,7 @@ READ8_MEMBER(decocass_state::decocass_nodong_r) { if (0 == (offset & E5XX_MASK)) { - data = upi41_master_r(m_mcu, 0); + data = m_mcu->upi41_master_r(space,0); LOG(3,("%10s 6502-PC: %04x decocass_nodong_r(%02x): $%02x '%c' <- open bus (D0 replaced with latch)\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, (data >= 32) ? data : '.')); } else @@ -978,7 +978,7 @@ WRITE8_MEMBER(decocass_state::decocass_e5xx_w) if (0 == (offset & E5XX_MASK)) { LOG(3,("%10s 6502-PC: %04x decocass_e5xx_w(%02x): $%02x -> %s\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, offset & 1 ? "8041-CMND" : "8041-DATA")); - upi41_master_w(m_mcu, offset & 1, data); + m_mcu->upi41_master_w(space,offset & 1, data); #ifdef MAME_DEBUG decocass_fno(offset, data); #endif diff --git a/src/mame/machine/tnzs.c b/src/mame/machine/tnzs.c index 03d50612643..8d1b638e304 100644 --- a/src/mame/machine/tnzs.c +++ b/src/mame/machine/tnzs.c @@ -47,7 +47,7 @@ READ8_MEMBER(tnzs_state::mcu_tnzs_r) { UINT8 data; - data = upi41_master_r(m_mcu, offset & 1); + data = m_mcu->upi41_master_r(space, offset & 1); space.device().execute().yield(); // logerror("PC %04x: read %02x from mcu $c00%01x\n", space.device().safe_pcbase(), data, offset); @@ -59,7 +59,7 @@ WRITE8_MEMBER(tnzs_state::mcu_tnzs_w) { // logerror("PC %04x: write %02x to mcu $c00%01x\n", space.device().safe_pcbase(), data, offset); - upi41_master_w(m_mcu, offset & 1, data); + m_mcu->upi41_master_w(space, offset & 1, data); } diff --git a/src/mess/drivers/dmv.c b/src/mess/drivers/dmv.c index ce91aebd07f..242c8a0f058 100644 --- a/src/mess/drivers/dmv.c +++ b/src/mess/drivers/dmv.c @@ -133,12 +133,12 @@ READ8_MEMBER(dmv_state::sys_status_r) READ8_MEMBER(dmv_state::kb_ctrl_mcu_r) { - return upi41_master_r(machine().device("kb_ctrl_mcu"), offset); + return machine().device("kb_ctrl_mcu")->upi41_master_r(space, offset); } WRITE8_MEMBER(dmv_state::kb_ctrl_mcu_w) { - upi41_master_w(machine().device("kb_ctrl_mcu"), offset, data); + machine().device("kb_ctrl_mcu")->upi41_master_w(space, offset, data); } static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels ) diff --git a/src/mess/drivers/fidelz80.c b/src/mess/drivers/fidelz80.c index fb04203a08d..359b6b77655 100644 --- a/src/mess/drivers/fidelz80.c +++ b/src/mess/drivers/fidelz80.c @@ -976,22 +976,22 @@ WRITE8_MEMBER(fidelz80_state::digit_w) WRITE8_MEMBER(fidelz80_state::mcu_data_w) { - upi41_master_w(m_i8041, 0, data); + m_i8041->upi41_master_w(space, 0, data); } WRITE8_MEMBER(fidelz80_state::mcu_command_w) { - upi41_master_w(m_i8041, 1, data); + m_i8041->upi41_master_w(space, 1, data); } READ8_MEMBER(fidelz80_state::mcu_data_r) { - return upi41_master_r(m_i8041, 0); + return m_i8041->upi41_master_r(space, 0); } READ8_MEMBER(fidelz80_state::mcu_status_r) { - return upi41_master_r(m_i8041, 1); + return m_i8041->upi41_master_r(space, 1); } WRITE8_MEMBER( fidelz80_state::bridgec_speech_w ) diff --git a/src/mess/drivers/pcw.c b/src/mess/drivers/pcw.c index 4bc20952ee3..79439db7460 100644 --- a/src/mess/drivers/pcw.c +++ b/src/mess/drivers/pcw.c @@ -641,14 +641,14 @@ void pcw_state::pcw_printer_fire_pins(UINT16 pins) WRITE8_MEMBER(pcw_state::pcw_printer_data_w) { m_printer_data = data; - upi41_master_w(machine().device("printer_mcu"),0,data); + machine().device("printer_mcu")->upi41_master_w(space,0,data); logerror("PRN [0xFC]: Sent command %02x\n",data); } WRITE8_MEMBER(pcw_state::pcw_printer_command_w) { m_printer_command = data; - upi41_master_w(machine().device("printer_mcu"),1,data); + machine().device("printer_mcu")->upi41_master_w(space,1,data); logerror("PRN [0xFD]: Sent command %02x\n",data); } @@ -661,7 +661,7 @@ WRITE8_MEMBER(pcw_state::pcw_printer_command_w) // anything else = no printer READ8_MEMBER(pcw_state::pcw_printer_data_r) { - return upi41_master_r(machine().device("printer_mcu"),0); + return machine().device("printer_mcu")->upi41_master_r(space,0); } // printer status @@ -675,7 +675,7 @@ READ8_MEMBER(pcw_state::pcw_printer_data_r) // bit 0 - controller fault READ8_MEMBER(pcw_state::pcw_printer_status_r) { - return upi41_master_r(machine().device("printer_mcu"),1); + return machine().device("printer_mcu")->upi41_master_r(space,1); } /* MCU handlers */ diff --git a/src/mess/includes/fidelz80.h b/src/mess/includes/fidelz80.h index a871752eead..2287caf1129 100644 --- a/src/mess/includes/fidelz80.h +++ b/src/mess/includes/fidelz80.h @@ -27,7 +27,7 @@ public: required_device m_maincpu; optional_device m_speech; optional_device m_beep; - optional_device m_i8041; + optional_device m_i8041; optional_device m_i8243; UINT16 m_kp_matrix; // keypad/leds matrix diff --git a/src/mess/machine/at_keybc.c b/src/mess/machine/at_keybc.c index 1c1845f4438..fa918b079b4 100644 --- a/src/mess/machine/at_keybc.c +++ b/src/mess/machine/at_keybc.c @@ -108,7 +108,7 @@ void at_keyboard_controller_device::device_config_complete() void at_keyboard_controller_device::device_start() { // find our cpu - m_cpu = downcast(subdevice("at_keybc")); + m_cpu = downcast(subdevice("at_keybc")); // resolve callbacks m_system_reset_func.resolve(m_system_reset_cb, *this); @@ -199,22 +199,22 @@ WRITE8_MEMBER( at_keyboard_controller_device::p2_w ) READ8_MEMBER( at_keyboard_controller_device::data_r ) { - return upi41_master_r(m_cpu, 0); + return m_cpu->upi41_master_r(space, 0); } WRITE8_MEMBER( at_keyboard_controller_device::data_w ) { - upi41_master_w(m_cpu, 0, data); + m_cpu->upi41_master_w(space, 0, data); } READ8_MEMBER( at_keyboard_controller_device::status_r ) { - return upi41_master_r(m_cpu, 1); + return m_cpu->upi41_master_r(space, 1); } WRITE8_MEMBER( at_keyboard_controller_device::command_w ) { - upi41_master_w(m_cpu, 1, data); + m_cpu->upi41_master_w(space, 1, data); } WRITE_LINE_MEMBER( at_keyboard_controller_device::keyboard_clock_w ) diff --git a/src/mess/machine/at_keybc.h b/src/mess/machine/at_keybc.h index 01a5bb0f6ec..f773cb632d2 100644 --- a/src/mess/machine/at_keybc.h +++ b/src/mess/machine/at_keybc.h @@ -10,6 +10,7 @@ #define __AT_KEYBC_H__ #include "emu.h" +#include "cpu/mcs48/mcs48.h" //************************************************************************** @@ -76,7 +77,7 @@ protected: virtual machine_config_constructor device_mconfig_additions() const; private: // internal state - device_t *m_cpu; + upi41_cpu_device *m_cpu; devcb_resolved_write_line m_system_reset_func; devcb_resolved_write_line m_gate_a20_func;