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https://github.com/holub/mame
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mc68000: IO cleanup
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cc64f0ccc8
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@ -162,29 +162,27 @@ uint16_t mc68000_state::memory_r(offs_t offset, uint16_t mem_mask)
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LOGMASKED(LOG_IO_READ, "Read from IO: %06x = %04x & %04x\n", offset << 1, data, mem_mask);
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LOGMASKED(LOG_IO_READ, "Read from IO: %06x = %04x & %04x\n", offset << 1, data, mem_mask);
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offset = (offset << 1) & 0x3fff;
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// ic45, 74ls139
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// ic45, 74ls139
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switch (offset >> 12)
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switch ((offset >> 11) & 0x03)
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{
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{
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case 0:
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case 0:
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if (ACCESSING_BITS_8_15 && (BIT(offset, 1) == 1))
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if (ACCESSING_BITS_8_15 && (BIT(offset, 0) == 1))
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data = m_crtc->register_r() << 8;
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data = m_crtc->register_r() << 8;
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break;
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break;
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case 1:
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case 1:
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if (ACCESSING_BITS_0_7)
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if (ACCESSING_BITS_0_7)
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data |= m_via[0]->read(offset >> 1) << 0;
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data |= m_via[0]->read(offset) << 0;
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if (ACCESSING_BITS_8_15)
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if (ACCESSING_BITS_8_15)
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data |= m_via[1]->read(offset >> 1) << 8;
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data |= m_via[1]->read(offset) << 8;
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break;
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break;
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case 2:
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case 2:
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data = m_sysbus->floppy_r(offset >> 1, mem_mask);
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data = m_sysbus->floppy_r(offset, mem_mask);
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break;
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break;
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case 3:
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case 3:
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if (ACCESSING_BITS_8_15 && (BIT(offset, 1) == 0))
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if (ACCESSING_BITS_8_15 && (BIT(offset, 0) == 0))
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{
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{
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data = m_key << 8;
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data = m_key << 8;
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@ -192,7 +190,7 @@ uint16_t mc68000_state::memory_r(offs_t offset, uint16_t mem_mask)
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m_via[1]->write_cb1(1);
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m_via[1]->write_cb1(1);
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m_via[1]->write_cb1(BIT(m_switches->read(), 1));
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m_via[1]->write_cb1(BIT(m_switches->read(), 1));
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}
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}
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if (ACCESSING_BITS_8_15 && (BIT(offset, 1) == 1))
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if (ACCESSING_BITS_8_15 && (BIT(offset, 0) == 1))
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m_apm_view.select(0);
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m_apm_view.select(0);
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break;
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break;
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}
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}
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@ -251,31 +249,29 @@ void mc68000_state::memory_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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case 0x1:
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case 0x1:
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LOGMASKED(LOG_IO_WRITE, "Write to IO: %06x = %04x & %04x\n", offset << 1, data, mem_mask);
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LOGMASKED(LOG_IO_WRITE, "Write to IO: %06x = %04x & %04x\n", offset << 1, data, mem_mask);
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offset = (offset << 1) & 0x3fff;
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// ic45, 74ls139
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// ic45, 74ls139
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switch (offset >> 12)
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switch ((offset >> 11) & 0x03)
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{
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{
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case 0:
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case 0:
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if (ACCESSING_BITS_8_15 && (BIT(offset, 1) == 0))
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if (ACCESSING_BITS_8_15 && (BIT(offset, 0) == 0))
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m_crtc->address_w(data >> 8);
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m_crtc->address_w(data >> 8);
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if (ACCESSING_BITS_8_15 && (BIT(offset, 1) == 1))
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if (ACCESSING_BITS_8_15 && (BIT(offset, 0) == 1))
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m_crtc->register_w(data >> 8);
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m_crtc->register_w(data >> 8);
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break;
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break;
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case 1:
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case 1:
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if (ACCESSING_BITS_0_7)
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if (ACCESSING_BITS_0_7)
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m_via[0]->write(offset >> 1, data >> 0);
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m_via[0]->write(offset, data >> 0);
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if (ACCESSING_BITS_8_15)
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if (ACCESSING_BITS_8_15)
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m_via[1]->write(offset >> 1, data >> 8);
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m_via[1]->write(offset, data >> 8);
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break;
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break;
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case 2:
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case 2:
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m_sysbus->floppy_w(offset >> 1, data, mem_mask);
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m_sysbus->floppy_w(offset, data, mem_mask);
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break;
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break;
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case 3:
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case 3:
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if (ACCESSING_BITS_8_15 && (BIT(offset, 1) == 0))
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if (ACCESSING_BITS_8_15 && (BIT(offset, 0) == 0))
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{
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{
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m_centronics_latch->write(data >> 8);
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m_centronics_latch->write(data >> 8);
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@ -283,7 +279,7 @@ void mc68000_state::memory_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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m_via[1]->write_cb1(1);
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m_via[1]->write_cb1(1);
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m_via[1]->write_cb1(BIT(m_switches->read(), 0));
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m_via[1]->write_cb1(BIT(m_switches->read(), 0));
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}
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}
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if (ACCESSING_BITS_8_15 && (BIT(offset, 1) == 1))
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if (ACCESSING_BITS_8_15 && (BIT(offset, 0) == 1))
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LOGMASKED(LOG_IO_WRITE, "Unhandled volume latch write\n");
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LOGMASKED(LOG_IO_WRITE, "Unhandled volume latch write\n");
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break;
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break;
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}
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}
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