From ec6a340d1ddd5dafb9765d48e47aa99743959a55 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 8 Oct 2011 18:03:57 +0000 Subject: [PATCH] More interrupt work by Haze (no whatsnew) --- src/emu/cpu/sh4/sh3comn.c | 59 +++++++++++++++++++++++++++++++++++++- src/emu/cpu/sh4/sh3comn.h | 1 + src/emu/cpu/sh4/sh4.c | 3 +- src/emu/cpu/sh4/sh4comn.c | 9 +++--- src/emu/cpu/sh4/sh4comn.h | 2 ++ src/mame/drivers/cavesh3.c | 52 +++++++++++++++++++++++---------- 6 files changed, 105 insertions(+), 21 deletions(-) diff --git a/src/emu/cpu/sh4/sh3comn.c b/src/emu/cpu/sh4/sh3comn.c index c9b9d9a90e3..0b2dc4bf443 100644 --- a/src/emu/cpu/sh4/sh3comn.c +++ b/src/emu/cpu/sh4/sh3comn.c @@ -153,6 +153,30 @@ READ32_HANDLER( sh3_internal_r ) break; + case IRR0_IRR1: + { + { + if (mem_mask & 0xff000000) + { + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + return sh4->m_sh3internal_lower[offset]; + } + + if (mem_mask & 0x0000ff00) + { + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR1)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + return sh4->m_sh3internal_lower[offset]; + } + + if (mem_mask & 0x00ff00ff); + { + fatalerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0/1 unused bits)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + } + + } + } + break; + case PEDR_PFDR: { if (mem_mask & 0xffff0000) @@ -224,8 +248,34 @@ WRITE32_HANDLER( sh3_internal_w ) switch (offset) { + case IRR0_IRR1: + { + { + if (mem_mask & 0xff000000) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + // not sure if this is how we should clear lines in this core... + if (!(data & 0x01000000)) sh4_set_irq_line(sh4, 0, CLEAR_LINE); + if (!(data & 0x02000000)) sh4_set_irq_line(sh4, 1, CLEAR_LINE); + if (!(data & 0x04000000)) sh4_set_irq_line(sh4, 2, CLEAR_LINE); + if (!(data & 0x08000000)) sh4_set_irq_line(sh4, 3, CLEAR_LINE); + + } + if (mem_mask & 0x0000ff00) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR1)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + if (mem_mask & 0x00ff00ff) + { + fatalerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0/1 unused bits)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + } + break; + case PINTER_IPRC: { + if (mem_mask & 0xffff0000) { logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PINTER)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); @@ -233,7 +283,14 @@ WRITE32_HANDLER( sh3_internal_w ) if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IPRC)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + data &= 0xffff; mem_mask &= 0xffff; + COMBINE_DATA(&sh4->SH4_IPRC); + logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (IPRC)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + sh4->exception_priority[SH4_INTC_IRL0] = INTPRI((sh4->SH4_IPRC & 0x000f)>>0, SH4_INTC_IRL0); + sh4->exception_priority[SH4_INTC_IRL1] = INTPRI((sh4->SH4_IPRC & 0x00f0)>>4, SH4_INTC_IRL1); + sh4->exception_priority[SH4_INTC_IRL2] = INTPRI((sh4->SH4_IPRC & 0x0f00)>>8, SH4_INTC_IRL2); + sh4->exception_priority[SH4_INTC_IRL3] = INTPRI((sh4->SH4_IPRC & 0xf000)>>12,SH4_INTC_IRL3); + sh4_exception_recompute(sh4); } } break; diff --git a/src/emu/cpu/sh4/sh3comn.h b/src/emu/cpu/sh4/sh3comn.h index 3c97fde5637..6c1271b68c2 100644 --- a/src/emu/cpu/sh4/sh3comn.h +++ b/src/emu/cpu/sh4/sh3comn.h @@ -9,6 +9,7 @@ #define SH3_LOWER_REGEND (0x07ffffff) #define INTEVT2 ((0x4000000 - SH3_LOWER_REGBASE)/4) +#define IRR0_IRR1 ((0x4000004 - SH3_LOWER_REGBASE)/4) #define PINTER_IPRC ((0x4000014 - SH3_LOWER_REGBASE)/4) #define PCCR_PDCR ((0x4000104 - SH3_LOWER_REGBASE)/4) #define PECR_PFCR ((0x4000108 - SH3_LOWER_REGBASE)/4) diff --git a/src/emu/cpu/sh4/sh4.c b/src/emu/cpu/sh4/sh4.c index 4dc2ac67646..93735b5f9c2 100644 --- a/src/emu/cpu/sh4/sh4.c +++ b/src/emu/cpu/sh4/sh4.c @@ -1718,7 +1718,7 @@ INLINE void TRAPA(sh4_state *sh4, UINT32 i) else /* SH3 */ { sh4->m_sh3internal_upper[SH3_TRA_ADDR] = imm << 2; - } + } sh4->ssr = sh4->sr; @@ -3548,6 +3548,7 @@ static CPU_INIT( sh4 ) device->save_item(NAME(sh4->SH4_IPRA)); + device->save_item(NAME(sh4->SH4_IPRC)); diff --git a/src/emu/cpu/sh4/sh4comn.c b/src/emu/cpu/sh4/sh4comn.c index 45c767eaecf..340e318555f 100644 --- a/src/emu/cpu/sh4/sh4comn.c +++ b/src/emu/cpu/sh4/sh4comn.c @@ -188,10 +188,11 @@ static const int sh3_intevt2_exception_codes[] = -1, /* D */ -1, /* E */ - -1, /* SH4_INTC_IRL0 */ - -1, /* SH4_INTC_IRL1 */ - -1, /* SH4_INTC_IRL2 */ - -1, /* SH4_INTC_IRL3 */ + 0x600, /* SH4_INTC_IRL0 */ + 0x620, /* SH4_INTC_IRL1 */ + 0x640, /* SH4_INTC_IRL2 */ + 0x660, /* SH4_INTC_IRL3 */ + /* todo: SH3 should have lines 4+5 too? */ -1, /* HUDI */ -1, /* SH4_INTC_GPOI */ diff --git a/src/emu/cpu/sh4/sh4comn.h b/src/emu/cpu/sh4/sh4comn.h index 37bfdbaac20..76476a7202f 100644 --- a/src/emu/cpu/sh4/sh4comn.h +++ b/src/emu/cpu/sh4/sh4comn.h @@ -99,6 +99,8 @@ typedef struct // INTC regs UINT32 SH4_IPRA; + UINT32 SH4_IPRC; + // sh3 internal UINT32 m_sh3internal_upper[0x3000/4]; diff --git a/src/mame/drivers/cavesh3.c b/src/mame/drivers/cavesh3.c index a529e9135db..4a6c812621e 100644 --- a/src/mame/drivers/cavesh3.c +++ b/src/mame/drivers/cavesh3.c @@ -48,15 +48,34 @@ static READ64_HANDLER( cavesh3_blitter_r ) { UINT64 ret = space->machine().rand(); - return ret ^ (ret<<32); + logerror("cavesh3_blitter_r access at %08x (%08x) - mem_mask %08x%08x\n",offset, offset*8, (UINT32)(mem_mask>>32),(UINT32)(mem_mask&0xffffffff)); + + switch (offset) + { + + case 0x2: + return ret ^ (ret<<32); + + case 0x4: + return 0; + + default: + logerror("no case for blit read\n"); + return 0; + } + + + return 0; + + + } static WRITE64_HANDLER( cavesh3_blitter_w ) { - + logerror("cavesh3_blitter_w access at %08x (%08x) - %08x%08x %08x%08x\n",offset, offset*8, (UINT32)(data>>32),(UINT32)(data&0xffffffff),(UINT32)(mem_mask>>32),(UINT32)(mem_mask&0xffffffff)); } - static READ64_HANDLER( ymz2770c_z_r ) { UINT64 ret = space->machine().rand(); @@ -75,15 +94,23 @@ static READ64_HANDLER( cavesh3_nand_r ) { logerror("unknown cavesh3_nand_r access %08x%08x\n",(UINT32)(mem_mask>>32),(UINT32)(mem_mask&0xffffffff)); } + else + { + logerror("cavesh3_nand_r access %08x%08x\n",(UINT32)(mem_mask>>32),(UINT32)(mem_mask&0xffffffff)); + } - return (UINT64)(space->machine().rand()&0xff)<<(32+16+8); + return 0;// (UINT64)(space->machine().rand()&0xff)<<(32+16+8); } static WRITE64_HANDLER( cavesh3_nand_w ) { if (mem_mask & U64(0xff0000ffffffffff)) { - logerror("unknown cavesh3_nand_w access %08x%08x\n",(UINT32)(mem_mask>>32),(UINT32)(mem_mask&0xffffffff)); + logerror("unknown cavesh3_nand_w access %08x%08x %08x%08x\n",(UINT32)(data>>32),(UINT32)(data&0xffffffff),(UINT32)(mem_mask>>32),(UINT32)(mem_mask&0xffffffff)); + } + else + { + logerror("cavesh3_nand_w access %08x%08x %08x%08x\n",(UINT32)(data>>32),(UINT32)(data&0xffffffff),(UINT32)(mem_mask>>32),(UINT32)(mem_mask&0xffffffff)); } } @@ -116,15 +143,11 @@ static INPUT_PORTS_START( cavesh3 ) INPUT_PORTS_END -#define CAVE_CPU_CLOCK 133333333/4 +#define CAVE_CPU_CLOCK 133333333 static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, CAVE_CPU_CLOCK }; -/*static TIMER_CALLBACK( cavesh3_interrupt_off ) -{ - cputag_set_input_line(machine, "maincpu", 3, CLEAR_LINE); -} -*/ + static IRQ_CALLBACK(cavesh3_int_callback) { @@ -135,16 +158,15 @@ static IRQ_CALLBACK(cavesh3_int_callback) else { logerror("irqline %02x\n",irqline); - cputag_set_input_line(device->machine(), "maincpu", 2, CLEAR_LINE); - return 0;// 0x640; // hack vector until SH3 core works better + + return 0; } } static INTERRUPT_GEN(cavesh3_interrupt) { -// device_set_input_line(device, 2, ASSERT_LINE); -// device->machine().scheduler().timer_set(downcast(device)->cycles_to_attotime(10000), FUNC(cavesh3_interrupt_off)); + device_set_input_line(device, 2, HOLD_LINE); } static MACHINE_RESET( cavesh3 )