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i960: Fix disassembly of REG instructions
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@ -163,7 +163,7 @@ offs_t i960_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat
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u32 iCode = opcodes.r32(IP);
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u32 iCode = opcodes.r32(IP);
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u8 op = (unsigned char) (iCode >> 24);
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u8 op = (unsigned char) (iCode >> 24);
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u8 op2 = (unsigned char) (iCode >> 7)&0xf;
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u8 op2 = (unsigned char) (iCode >> 7)&0xf;
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u8 opc = 0;
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u16 opc = 0;
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u32 i = 0;
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u32 i = 0;
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u8 model = (unsigned char) (iCode >> 10) &0x3;
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u8 model = (unsigned char) (iCode >> 10) &0x3;
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@ -262,7 +262,7 @@ offs_t i960_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat
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}
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}
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if (mnem_reg[i].type == opc) util::stream_format(stream, "%-8s%s", mnem_reg[i].mnem,dis_decode_reg(iCode,0));
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if (mnem_reg[i].type == opc) util::stream_format(stream, "%-8s%s", mnem_reg[i].mnem,dis_decode_reg(iCode,0));
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else util::stream_format(stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
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else util::stream_format(stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,opc,iCode, modeh, model);
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break;
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break;
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case 6: // bitpos and branch type
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case 6: // bitpos and branch type
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