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https://github.com/holub/mame
synced 2025-04-19 23:12:11 +03:00
nothing precious about r3000 irq numbers (nw)
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53b63cef9d
commit
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@ -100,5 +100,5 @@ void iop_intc_device::update_interrupts()
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{
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bool active = (m_enabled && (m_status & m_mask));
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//printf("iop_intc: %d && (%08x & %08x) = %d\n", m_enabled, m_status, m_mask, active);
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m_iop->set_input_line(R3000_IRQ0, active ? ASSERT_LINE : CLEAR_LINE);
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m_iop->set_input_line(INPUT_LINE_IRQ0, active ? ASSERT_LINE : CLEAR_LINE);
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}
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@ -305,7 +305,7 @@ WRITE32_MEMBER(decstation_state::cfb_w)
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WRITE_LINE_MEMBER(decstation_state::ioga_irq_w)
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{
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// not sure this is correct
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m_maincpu->set_input_line(R3000_IRQ3, state);
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m_maincpu->set_input_line(INPUT_LINE_IRQ3, state);
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}
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void decstation_state::machine_start()
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@ -102,7 +102,7 @@ PC5380-9651 5380-JY3306A 5380-N1045503A
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WRITE_LINE_MEMBER(policetr_state::vblank)
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{
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m_maincpu->set_input_line(state ? R3000_IRQ4 : R3000_IRQ5, ASSERT_LINE);
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m_maincpu->set_input_line(state ? INPUT_LINE_IRQ4 : INPUT_LINE_IRQ5, ASSERT_LINE);
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}
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/*************************************
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@ -264,7 +264,7 @@ READ32_MEMBER(speglsht_state::cop_r)
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READ32_MEMBER(speglsht_state::irq_ack_clear)
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{
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m_subcpu->set_input_line(R3000_IRQ4, CLEAR_LINE);
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m_subcpu->set_input_line(INPUT_LINE_IRQ4, CLEAR_LINE);
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return 0;
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}
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@ -362,7 +362,7 @@ WRITE32_MEMBER(srmp5_state::srmp5_vidregs_w)
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READ32_MEMBER(srmp5_state::irq_ack_clear)
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{
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m_maincpu->set_input_line(R3000_IRQ4, CLEAR_LINE);
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m_maincpu->set_input_line(INPUT_LINE_IRQ4, CLEAR_LINE);
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return 0;
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}
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@ -253,7 +253,7 @@ uint32_t turrett_state::update_inputs(void)
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}
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// Update IRQ state
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m_maincpu->set_input_line(R3000_IRQ1, m_inputs_active ? ASSERT_LINE : CLEAR_LINE);
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m_maincpu->set_input_line(INPUT_LINE_IRQ1, m_inputs_active ? ASSERT_LINE : CLEAR_LINE);
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return val;
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}
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@ -270,13 +270,13 @@ INPUT_CHANGED_MEMBER( turrett_state::ipt_change )
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if (newval == 0)
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{
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m_inputs_active |= p;
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m_maincpu->set_input_line(R3000_IRQ1, ASSERT_LINE);
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m_maincpu->set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
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}
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}
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else
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{
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m_inputs_active |= p;
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m_maincpu->set_input_line(R3000_IRQ1, ASSERT_LINE);
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m_maincpu->set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
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}
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}
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}
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@ -297,7 +297,7 @@ INTERRUPT_GEN_MEMBER( turrett_state::vblank )
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m_inputs_active |= 0x02000000;
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m_frame ^= 1;
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m_maincpu->set_input_line(R3000_IRQ1, ASSERT_LINE);
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m_maincpu->set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
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}
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@ -309,7 +309,7 @@ INTERRUPT_GEN_MEMBER( turrett_state::adc )
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m_inputs_active |= 0x00000002;
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m_adc ^= 1;
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m_maincpu->set_input_line(R3000_IRQ1, ASSERT_LINE);
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m_maincpu->set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
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}
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/*************************************
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@ -270,9 +270,9 @@ inline bool jaguar_state::adjust_object_timer(int vc)
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void jaguar_state::update_cpu_irq()
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{
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if ((m_cpu_irq_state & m_gpu_regs[INT1] & 0x1f) != 0)
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m_maincpu->set_input_line(m_is_r3000 ? R3000_IRQ4 : M68K_IRQ_6, ASSERT_LINE);
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m_maincpu->set_input_line(m_is_r3000 ? INPUT_LINE_IRQ4 : M68K_IRQ_6, ASSERT_LINE);
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else
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m_maincpu->set_input_line(m_is_r3000 ? R3000_IRQ4 : M68K_IRQ_6, CLEAR_LINE);
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m_maincpu->set_input_line(m_is_r3000 ? INPUT_LINE_IRQ4 : M68K_IRQ_6, CLEAR_LINE);
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}
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@ -226,12 +226,12 @@ WRITE32_MEMBER(policetr_state::video_w)
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/* latch 0x50 clears IRQ4 */
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case 0x50:
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m_maincpu->set_input_line(R3000_IRQ4, CLEAR_LINE);
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m_maincpu->set_input_line(INPUT_LINE_IRQ4, CLEAR_LINE);
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break;
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/* latch 0x60 clears IRQ5 */
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case 0x60:
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m_maincpu->set_input_line(R3000_IRQ5, CLEAR_LINE);
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m_maincpu->set_input_line(INPUT_LINE_IRQ5, CLEAR_LINE);
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break;
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/* log anything else */
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