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https://github.com/holub/mame
synced 2025-10-07 01:16:22 +03:00
isa/pgc: accelerated VRAM writes + cleanups (#3385)
* isa/pgc: use logmacro.h (nw) * isa/pgc: implement accelerated VRAM writes * isa/pgc: code style cleanup (nw)
This commit is contained in:
Sergey Svishchev
Vas Crabb
parent
a8d254d416
commit
ecb3c47796
@ -3,7 +3,7 @@
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/***************************************************************************
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IBM Professional Graphics Controller (PGC), skeleton driver.
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IBM Professional Graphics Controller (PGC).
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Designed for IBM by Vermont Microsystems. References:
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@ -16,13 +16,13 @@
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http://www.seasip.info/VintagePC/pgc.html
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To do:
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- decode memory map
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- various VRAM write modes
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- pass IBM diagnostics (currently fail with code 3905)
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- CGA emulator
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- what's up with irq 3 (= vblank irq)? (causes soft reset)
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- "test pin of the microprocessor samples the hsync pulse"
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- CGA emulator
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- bus state handling?
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- VRAM address translator ROM?
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- clones/compatibles? CompuShow apparently was tested with a clone and sends opcode E6, writes 2 to C630C
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***************************************************************************/
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@ -32,17 +32,18 @@
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#include "screen.h"
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#define VERBOSE_PGC 1
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//#define LOG_GENERAL (1U << 0) //defined in logmacro.h already
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#define LOG_VRAM (1U << 1)
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#define LOG_CMD (1U << 2)
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//#define VERBOSE (LOG_GENERAL | LOG_VRAM)
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//#define LOG_OUTPUT_STREAM std::cout
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#include "logmacro.h"
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#define LOGV(...) LOGMASKED(LOG_VRAM, __VA_ARGS__)
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#define LOGCMD(...) LOGMASKED(LOG_CMD, __VA_ARGS__)
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#define DBG_LOG(N,M,A) \
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do { \
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if(VERBOSE_PGC>=N) \
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{ \
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if( M ) \
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logerror("%11.6f at %s: %-24s",machine().time().as_double(),machine().describe_context(),(char*)M ); \
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logerror A; \
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} \
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} while (0)
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#define PGC_SCREEN_NAME "pgc_screen"
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@ -111,18 +112,16 @@ void isa8_pgc_device::pgc_map(address_map &map)
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map(0x00000, 0x07fff).rom();
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map(0x08000, 0x0ffff).rom().region("maincpu", 0x8000);
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map(0x10000, 0x1001f).rw(this, FUNC(isa8_pgc_device::stateparam_r), FUNC(isa8_pgc_device::stateparam_w));
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// AM_RANGE(0x18000, 0x18fff) AM_RAM // ??
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// map(0x18000, 0x18fff).ram(); // ??
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map(0x28000, 0x287ff).ram().region("commarea", 0).mirror(0x800);
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map(0x32001, 0x32001).nopw();
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map(0x32020, 0x3203f).w(this, FUNC(isa8_pgc_device::accel_w));
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map(0x3c000, 0x3c001).r(this, FUNC(isa8_pgc_device::init_r));
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// AM_RANGE(0x3e000, 0x3efff) AM_RAM // ??
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// map(0x3e000, 0x3efff).ram(); // ??
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map(0x80000, 0xf7fff).rw(this, FUNC(isa8_pgc_device::vram_r), FUNC(isa8_pgc_device::vram_w));
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map(0xf8000, 0xfffff).rom().region("maincpu", 0x8000);
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}
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void isa8_pgc_device::pgc_io(address_map &map)
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{
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map.unmap_value_high();
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}
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static const gfx_layout pgc_charlayout =
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{
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8, 16, /* 8x16 pixels */
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@ -155,7 +154,6 @@ DEFINE_DEVICE_TYPE(ISA8_PGC, isa8_pgc_device, "isa_ibm_pgc", "IBM Professional G
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MACHINE_CONFIG_START(isa8_pgc_device::device_add_mconfig)
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MCFG_CPU_ADD("maincpu", I8088, XTAL(24'000'000)/3)
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MCFG_CPU_PROGRAM_MAP(pgc_map)
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MCFG_CPU_IO_MAP(pgc_io)
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#if 0
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MCFG_CPU_VBLANK_INT_DRIVER(PGC_SCREEN_NAME, isa8_pgc_device, vblank_irq)
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MCFG_CPU_IRQ_ACKNOWLEDGE_DRIVER(isa8_pgc_device, irq_callback)
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@ -182,7 +180,7 @@ MACHINE_CONFIG_END
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const tiny_rom_entry *isa8_pgc_device::device_rom_region() const
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{
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return ROM_NAME( pgc );
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return ROM_NAME(pgc);
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}
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//-------------------------------------------------
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@ -191,7 +189,7 @@ const tiny_rom_entry *isa8_pgc_device::device_rom_region() const
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ioport_constructor isa8_pgc_device::device_input_ports() const
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{
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return INPUT_PORTS_NAME( pgc );
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return INPUT_PORTS_NAME(pgc);
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}
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//**************************************************************************
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@ -219,7 +217,6 @@ isa8_pgc_device::isa8_pgc_device(const machine_config &mconfig, device_type type
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void isa8_pgc_device::device_start()
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{
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address_space &space = m_cpu->space( AS_PROGRAM );
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int width = PGC_DISP_HORZ;
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int height = PGC_DISP_VERT;
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@ -228,18 +225,15 @@ void isa8_pgc_device::device_start()
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set_isa_device();
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for (int i = 0; i < 256; i++ )
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for (int i = 0; i < 256; i++)
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{
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m_palette->set_pen_color( i, 0, 0, 0 );
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m_palette->set_pen_color(i, 0, 0, 0);
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}
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m_bitmap = std::make_unique<bitmap_ind16>(width, height);
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m_bitmap->fill(0);
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m_vram = std::make_unique<uint8_t[]>(0x78000);
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space.install_readwrite_bank(0x80000, 0xf7fff, "vram");
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membank("vram")->set_base(m_vram.get());
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m_eram = std::make_unique<uint8_t[]>(0x8000);
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machine().add_notifier(MACHINE_NOTIFY_RESET, machine_notify_delegate(&isa8_pgc_device::reset_common, this));
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@ -247,7 +241,7 @@ void isa8_pgc_device::device_start()
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void isa8_pgc_device::reset_common()
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{
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address_space &space = m_cpu->space( AS_PROGRAM );
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address_space &space = m_cpu->space(AS_PROGRAM);
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space.unmap_readwrite(0xf8000, 0xfffff);
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space.install_rom(0xf8000, 0xfffff, memregion("maincpu")->base() + 0x8000);
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@ -257,6 +251,7 @@ void isa8_pgc_device::device_reset()
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{
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memset(m_stateparam, 0, sizeof(m_stateparam));
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memset(m_lut, 0, sizeof(m_lut));
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m_accel = 0;
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m_commarea = memregion("commarea")->base();
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if (BIT(ioport("DSW")->read(), 1))
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@ -269,61 +264,135 @@ void isa8_pgc_device::device_reset()
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INTERRUPT_GEN_MEMBER(isa8_pgc_device::vblank_irq)
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{
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DBG_LOG(2,"irq",("vblank_irq\n"));
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LOGCMD("vblank_irq\n");
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m_cpu->set_input_line(0, ASSERT_LINE);
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}
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IRQ_CALLBACK_MEMBER(isa8_pgc_device::irq_callback)
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{
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DBG_LOG(2,"irq",("irq_callback\n"));
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LOGCMD("irq_callback\n");
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m_cpu->set_input_line(0, CLEAR_LINE);
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return 3;
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}
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// memory handlers
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READ8_MEMBER( isa8_pgc_device::stateparam_r ) {
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READ8_MEMBER(isa8_pgc_device::vram_r)
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{
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uint8_t ret;
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ret = m_vram[offset];
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LOGV("vram R @ %02x == %02x\n", offset, ret);
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return ret;
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}
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/*
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* accel modes (decimal)
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*
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* 0 - none
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* 1 - write 4 pixels, starting at offset
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* 2 - write up to 4 pixels, ending at offset
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* 3 - write up to 4 pixels, starting at offset
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* 5 - write 20 pixels, starting at offset
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* 9 - write up to 5 pixel groups, ending at offset. offset may be in the middle of pixel group.
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* 13 - write up to 5 pixel groups, starting at offset.
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*/
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WRITE8_MEMBER(isa8_pgc_device::vram_w)
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{
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bool handled = true;
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switch (m_accel)
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{
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case 0:
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m_vram[offset] = data;
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break;
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case 1:
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std::fill(&m_vram[offset], &m_vram[offset + 4], data);
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break;
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case 2:
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std::fill(&m_vram[offset & ~3], &m_vram[offset + 1], data);
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break;
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case 3:
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std::fill(&m_vram[offset], &m_vram[(offset + 4) & ~3], data);
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break;
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case 5:
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std::fill(&m_vram[offset], &m_vram[offset + 20], data);
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break;
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case 9:
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std::fill(&m_vram[offset - ((offset % 1024) % 20)], &m_vram[(offset + 4) & ~3], data);
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break;
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case 13:
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std::fill(&m_vram[offset], &m_vram[(offset + 20) - ((offset % 1024) + 20) % 20], data);
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break;
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default:
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m_vram[offset] = data;
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handled = false;
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break;
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}
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LOGV("vram W @ %02x <- %02x (accel %d)%s\n", offset, data, m_accel,
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handled ? "" : " (unsupported)");
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}
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WRITE8_MEMBER(isa8_pgc_device::accel_w)
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{
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m_accel = offset >> 1;
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LOGV("accel @ %05x <- %02x (%d)\n", 0x32020 + offset, data, m_accel);
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}
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READ8_MEMBER(isa8_pgc_device::stateparam_r)
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{
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uint8_t ret;
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ret = m_stateparam[offset >> 1];
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if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
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{
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DBG_LOG(1,"stateparam",("R @ %02x == %02x\n", offset, ret));
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LOG("stateparam R @ %02x == %02x\n", offset, ret);
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}
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return ret;
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}
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WRITE8_MEMBER( isa8_pgc_device::stateparam_w ) {
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WRITE8_MEMBER(isa8_pgc_device::stateparam_w)
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{
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if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
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{
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DBG_LOG(1,"stateparam",("W @ %02x <- %02x\n", offset, data));
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LOG("stateparam W @ %02x <- %02x\n", offset, data);
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}
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m_stateparam[offset >> 1] = data;
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}
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WRITE8_MEMBER( isa8_pgc_device::lut_w ) {
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WRITE8_MEMBER(isa8_pgc_device::lut_w)
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{
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uint8_t o = (offset >> 1) * 3;
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if (offset & 1) {
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if (offset & 1)
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{
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m_lut[o + 2] = (data & 15) << 4;
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m_palette->set_pen_color( offset >> 1, m_lut[o], m_lut[o + 1], m_lut[o + 2] );
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DBG_LOG(1,"lut",("W @ %02X <- %d %d %d\n",
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offset >> 1, m_lut[o], m_lut[o + 1], m_lut[o + 2] ));
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LOG("lut W @ %02X <- %d %d %d\n",
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offset >> 1, m_lut[o], m_lut[o + 1], m_lut[o + 2] );
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} else {
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m_lut[o ] = data & 0xf0;
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m_lut[o + 1] = (data & 15) << 4;
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}
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}
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READ8_MEMBER( isa8_pgc_device::init_r ) {
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DBG_LOG(1,"INIT",("unmapping ROM\n"));
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READ8_MEMBER(isa8_pgc_device::init_r)
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{
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LOG("INIT: unmapping ROM\n");
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space.unmap_read(0xf8000, 0xfffff);
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DBG_LOG(1,"INIT",("mapping emulator RAM\n"));
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LOG("INIT: mapping emulator RAM\n");
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space.install_readwrite_bank(0xf8000, 0xfffff, "eram");
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membank("eram")->set_base(m_eram.get());
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DBG_LOG(1,"INIT",("mapping LUT\n"));
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LOG("INIT: mapping LUT\n");
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space.install_write_handler(0xf8400, 0xf85ff,
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write8_delegate(FUNC(isa8_pgc_device::lut_w), this));
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@ -337,9 +406,8 @@ TIMER_DEVICE_CALLBACK_MEMBER(isa8_pgc_device::scanline_callback)
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uint8_t *v;
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// XXX hpos shifts every frame -- fix
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if (y == 0) DBG_LOG(2,"scanline_cb",
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("frame %d x %.4d y %.3d\n",
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(int) m_screen->frame_number(), m_screen->hpos(), y));
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if (y == 0) LOGCMD("scanline_cb frame %d x %.4d y %.3d\n",
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(int) m_screen->frame_number(), m_screen->hpos(), y);
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if (y < PGC_VERT_START) return;
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y -= PGC_VERT_START;
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@ -349,7 +417,8 @@ TIMER_DEVICE_CALLBACK_MEMBER(isa8_pgc_device::scanline_callback)
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v = &m_vram[y * 1024];
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p = &m_bitmap->pix16(y, 0);
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for (x = 0; x < PGC_DISP_HORZ; x++) {
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for (x = 0; x < PGC_DISP_HORZ; x++)
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{
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*p++ = *v++;
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}
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}
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@ -40,15 +40,18 @@ protected:
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private:
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uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
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TIMER_DEVICE_CALLBACK_MEMBER( scanline_callback );
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TIMER_DEVICE_CALLBACK_MEMBER(scanline_callback);
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INTERRUPT_GEN_MEMBER(vblank_irq);
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IRQ_CALLBACK_MEMBER(irq_callback);
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DECLARE_WRITE8_MEMBER( stateparam_w );
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DECLARE_READ8_MEMBER( stateparam_r );
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DECLARE_WRITE8_MEMBER( lut_w );
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DECLARE_READ8_MEMBER( init_r );
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DECLARE_WRITE8_MEMBER(vram_w);
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DECLARE_READ8_MEMBER(vram_r);
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DECLARE_WRITE8_MEMBER(stateparam_w);
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DECLARE_READ8_MEMBER(stateparam_r);
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DECLARE_WRITE8_MEMBER(lut_w);
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DECLARE_READ8_MEMBER(init_r);
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DECLARE_WRITE8_MEMBER(accel_w);
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void reset_common();
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@ -63,8 +66,9 @@ private:
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std::unique_ptr<uint8_t[]> m_vram;
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std::unique_ptr<uint8_t[]> m_eram;
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uint8_t m_stateparam[16];
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uint8_t m_lut[256*3];
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uint8_t m_lut[256 * 3];
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std::unique_ptr<bitmap_ind16> m_bitmap;
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int m_accel;
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};
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