diff --git a/src/emu/cpu/mc68hc11/hc11ops.c b/src/emu/cpu/mc68hc11/hc11ops.c index ffdd452f43a..21e96a1fe8f 100644 --- a/src/emu/cpu/mc68hc11/hc11ops.c +++ b/src/emu/cpu/mc68hc11/hc11ops.c @@ -1,60 +1,60 @@ -#define SET_Z8(r) (cpustate->ccr |= ((UINT8)r == 0) ? CC_Z : 0) -#define SET_Z16(r) (cpustate->ccr |= ((UINT16)r == 0) ? CC_Z : 0) -#define SET_N8(r) (cpustate->ccr |= (r & 0x80) ? CC_N : 0) -#define SET_N16(r) (cpustate->ccr |= (r & 0x8000) ? CC_N : 0) -#define SET_V_ADD8(r,s,d) (cpustate->ccr |= (((r) ^ (s)) & ((r) ^ (d)) & 0x80) ? CC_V : 0) -#define SET_V_SUB8(r,s,d) (cpustate->ccr |= (((d) ^ (s)) & ((d) ^ (r)) & 0x80) ? CC_V : 0) -#define SET_V_ADD16(r,s,d) (cpustate->ccr |= (((r) ^ (s)) & ((r) ^ (d)) & 0x8000) ? CC_V : 0) -#define SET_V_SUB16(r,s,d) (cpustate->ccr |= (((d) ^ (s)) & ((d) ^ (r)) & 0x8000) ? CC_V : 0) -#define SET_H(r,s,d) (cpustate->ccr |= (((r) ^ (s) ^ (d)) & 0x10) ? CC_H : 0) -#define SET_C8(x) (cpustate->ccr |= ((x) & 0x100) ? CC_C : 0) -#define SET_C16(x) (cpustate->ccr |= ((x) & 0x10000) ? CC_C : 0) -#define CLEAR_Z(cpustate) (cpustate->ccr &= ~(CC_Z)) -#define CLEAR_C(cpustate) (cpustate->ccr &= ~(CC_C)) -#define CLEAR_NZV(cpustate) (cpustate->ccr &= ~(CC_N | CC_Z | CC_V)) -#define CLEAR_ZVC(cpustate) (cpustate->ccr &= ~(CC_Z | CC_V | CC_C)) -#define CLEAR_NZVC(cpustate) (cpustate->ccr &= ~(CC_N | CC_Z | CC_V | CC_C)) -#define CLEAR_HNZVC(cpustate) (cpustate->ccr &= ~(CC_H | CC_N | CC_Z | CC_V | CC_C)) +#define SET_Z8(r) (m_ccr |= ((UINT8)r == 0) ? CC_Z : 0) +#define SET_Z16(r) (m_ccr |= ((UINT16)r == 0) ? CC_Z : 0) +#define SET_N8(r) (m_ccr |= (r & 0x80) ? CC_N : 0) +#define SET_N16(r) (m_ccr |= (r & 0x8000) ? CC_N : 0) +#define SET_V_ADD8(r,s,d) (m_ccr |= (((r) ^ (s)) & ((r) ^ (d)) & 0x80) ? CC_V : 0) +#define SET_V_SUB8(r,s,d) (m_ccr |= (((d) ^ (s)) & ((d) ^ (r)) & 0x80) ? CC_V : 0) +#define SET_V_ADD16(r,s,d) (m_ccr |= (((r) ^ (s)) & ((r) ^ (d)) & 0x8000) ? CC_V : 0) +#define SET_V_SUB16(r,s,d) (m_ccr |= (((d) ^ (s)) & ((d) ^ (r)) & 0x8000) ? CC_V : 0) +#define SET_H(r,s,d) (m_ccr |= (((r) ^ (s) ^ (d)) & 0x10) ? CC_H : 0) +#define SET_C8(x) (m_ccr |= ((x) & 0x100) ? CC_C : 0) +#define SET_C16(x) (m_ccr |= ((x) & 0x10000) ? CC_C : 0) +#define CLEAR_Z() (m_ccr &= ~(CC_Z)) +#define CLEAR_C() (m_ccr &= ~(CC_C)) +#define CLEAR_NZV() (m_ccr &= ~(CC_N | CC_Z | CC_V)) +#define CLEAR_ZVC() (m_ccr &= ~(CC_Z | CC_V | CC_C)) +#define CLEAR_NZVC() (m_ccr &= ~(CC_N | CC_Z | CC_V | CC_C)) +#define CLEAR_HNZVC() (m_ccr &= ~(CC_H | CC_N | CC_Z | CC_V | CC_C)) -#define SET_ZFLAG(cpustate) (cpustate->ccr |= CC_Z) -#define SET_NFLAG(cpustate) (cpustate->ccr |= CC_N) -#define SET_VFLAG(cpustate) (cpustate->ccr |= CC_V) +#define SET_ZFLAG() (m_ccr |= CC_Z) +#define SET_NFLAG() (m_ccr |= CC_N) +#define SET_VFLAG() (m_ccr |= CC_V) -#define REG_A cpustate->d.d8.a -#define REG_B cpustate->d.d8.b -#define REG_D cpustate->d.d16 +#define REG_A m_d.d8.a +#define REG_B m_d.d8.b +#define REG_D m_d.d16 -INLINE void CYCLES(hc11_state *cpustate, int cycles) +void mc68hc11_cpu_device::CYCLES(int cycles) { - cpustate->icount -= cycles; + m_icount -= cycles; } -INLINE void SET_PC(hc11_state *cpustate, int pc) +void mc68hc11_cpu_device::SET_PC(int pc) { - cpustate->pc = pc; + m_pc = pc; } -INLINE void PUSH8(hc11_state *cpustate, UINT8 value) +void mc68hc11_cpu_device::PUSH8(UINT8 value) { - WRITE8(cpustate, cpustate->sp--, value); + WRITE8(m_sp--, value); } -INLINE void PUSH16(hc11_state *cpustate, UINT16 value) +void mc68hc11_cpu_device::PUSH16(UINT16 value) { - WRITE8(cpustate, cpustate->sp--, (value >> 0) & 0xff); - WRITE8(cpustate, cpustate->sp--, (value >> 8) & 0xff); + WRITE8(m_sp--, (value >> 0) & 0xff); + WRITE8(m_sp--, (value >> 8) & 0xff); } -INLINE UINT8 POP8(hc11_state *cpustate) +UINT8 mc68hc11_cpu_device::POP8() { - return READ8(cpustate, ++cpustate->sp); + return READ8(++m_sp); } -INLINE UINT16 POP16(hc11_state *cpustate) +UINT16 mc68hc11_cpu_device::POP16() { UINT16 r = 0; - r |= (READ8(cpustate, ++cpustate->sp) << 8); - r |= (READ8(cpustate, ++cpustate->sp) << 0); + r |= (READ8(++m_sp) << 8); + r |= (READ8(++m_sp) << 0); return r; } @@ -63,3527 +63,3527 @@ INLINE UINT16 POP16(hc11_state *cpustate) /*****************************************************************************/ /* ABA 0x1B */ -static void HC11OP(aba)(hc11_state *cpustate) +void HC11OP(aba)() { UINT16 r = REG_A + REG_B; - CLEAR_HNZVC(cpustate); + CLEAR_HNZVC(); SET_H(r, REG_B, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, REG_B, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 2); + CYCLES(2); } /* ABX 0x3A */ -static void HC11OP(abx)(hc11_state *cpustate) +void HC11OP(abx)() { - cpustate->ix += REG_B; - CYCLES(cpustate, 3); + m_ix += REG_B; + CYCLES(3); } /* ABY 0x18, 0x3A */ -static void HC11OP(aby)(hc11_state *cpustate) +void HC11OP(aby)() { - cpustate->iy += REG_B; - CYCLES(cpustate, 4); + m_iy += REG_B; + CYCLES(4); } /* ADCA IMM 0x89 */ -static void HC11OP(adca_imm)(hc11_state *cpustate) +void HC11OP(adca_imm)() { - UINT8 i = FETCH(cpustate); - UINT16 r = REG_A + i + ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_HNZVC(cpustate); + UINT8 i = FETCH(); + UINT16 r = REG_A + i + ((m_ccr & CC_C) ? 1 : 0); + CLEAR_HNZVC(); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 2); + CYCLES(2); } /* ADCA DIR 0x99 */ -static void HC11OP(adca_dir)(hc11_state *cpustate) +void HC11OP(adca_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); - UINT16 r = REG_A + i + ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_HNZVC(cpustate); + UINT8 d = FETCH(); + UINT8 i = READ8(d); + UINT16 r = REG_A + i + ((m_ccr & CC_C) ? 1 : 0); + CLEAR_HNZVC(); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 3); + CYCLES(3); } /* ADCA EXT 0xB9 */ -static void HC11OP(adca_ext)(hc11_state *cpustate) +void HC11OP(adca_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); - UINT16 r = REG_A + i + ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_HNZVC(cpustate); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); + UINT16 r = REG_A + i + ((m_ccr & CC_C) ? 1 : 0); + CLEAR_HNZVC(); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* ADCA IND, X 0xA9 */ -static void HC11OP(adca_indx)(hc11_state *cpustate) +void HC11OP(adca_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); - UINT16 r = REG_A + i + ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_HNZVC(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); + UINT16 r = REG_A + i + ((m_ccr & CC_C) ? 1 : 0); + CLEAR_HNZVC(); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* ADCA IND, Y 0x18, 0xA9 */ -static void HC11OP(adca_indy)(hc11_state *cpustate) +void HC11OP(adca_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); - UINT16 r = REG_A + i + ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_HNZVC(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); + UINT16 r = REG_A + i + ((m_ccr & CC_C) ? 1 : 0); + CLEAR_HNZVC(); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 5); + CYCLES(5); } /* ADCB IMM 0xC9 */ -static void HC11OP(adcb_imm)(hc11_state *cpustate) +void HC11OP(adcb_imm)() { - UINT8 i = FETCH(cpustate); - UINT16 r = REG_B + i + ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_HNZVC(cpustate); + UINT8 i = FETCH(); + UINT16 r = REG_B + i + ((m_ccr & CC_C) ? 1 : 0); + CLEAR_HNZVC(); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 2); + CYCLES(2); } /* ADCB DIR 0xD9 */ -static void HC11OP(adcb_dir)(hc11_state *cpustate) +void HC11OP(adcb_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); - UINT16 r = REG_B + i + ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_HNZVC(cpustate); + UINT8 d = FETCH(); + UINT8 i = READ8(d); + UINT16 r = REG_B + i + ((m_ccr & CC_C) ? 1 : 0); + CLEAR_HNZVC(); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 3); + CYCLES(3); } /* ADCB EXT 0xF9 */ -static void HC11OP(adcb_ext)(hc11_state *cpustate) +void HC11OP(adcb_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); - UINT16 r = REG_B + i + ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_HNZVC(cpustate); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); + UINT16 r = REG_B + i + ((m_ccr & CC_C) ? 1 : 0); + CLEAR_HNZVC(); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* ADCB IND, X 0xE9 */ -static void HC11OP(adcb_indx)(hc11_state *cpustate) +void HC11OP(adcb_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); - UINT16 r = REG_B + i + ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_HNZVC(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); + UINT16 r = REG_B + i + ((m_ccr & CC_C) ? 1 : 0); + CLEAR_HNZVC(); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* ADCB IND, Y 0x18, 0xE9 */ -static void HC11OP(adcb_indy)(hc11_state *cpustate) +void HC11OP(adcb_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); - UINT16 r = REG_B + i + ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_HNZVC(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); + UINT16 r = REG_B + i + ((m_ccr & CC_C) ? 1 : 0); + CLEAR_HNZVC(); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 5); + CYCLES(5); } /* ADDA IMM 0x8B */ -static void HC11OP(adda_imm)(hc11_state *cpustate) +void HC11OP(adda_imm)() { - UINT8 i = FETCH(cpustate); + UINT8 i = FETCH(); UINT16 r = REG_A + i; - CLEAR_HNZVC(cpustate); + CLEAR_HNZVC(); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 2); + CYCLES(2); } /* ADDA DIR 0x9B */ -static void HC11OP(adda_dir)(hc11_state *cpustate) +void HC11OP(adda_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); + UINT8 d = FETCH(); + UINT8 i = READ8(d); UINT16 r = REG_A + i; - CLEAR_HNZVC(cpustate); + CLEAR_HNZVC(); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 3); + CYCLES(3); } /* ADDA EXT 0xBB */ -static void HC11OP(adda_ext)(hc11_state *cpustate) +void HC11OP(adda_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); UINT16 r = REG_A + i; - CLEAR_HNZVC(cpustate); + CLEAR_HNZVC(); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* ADDA IND, X 0xAB */ -static void HC11OP(adda_indx)(hc11_state *cpustate) +void HC11OP(adda_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); UINT16 r = REG_A + i; - CLEAR_HNZVC(cpustate); + CLEAR_HNZVC(); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* ADDA IND, Y 0x18, 0xAB */ -static void HC11OP(adda_indy)(hc11_state *cpustate) +void HC11OP(adda_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); UINT16 r = REG_A + i; - CLEAR_HNZVC(cpustate); + CLEAR_HNZVC(); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 5); + CYCLES(5); } /* ADDB IMM 0xCB */ -static void HC11OP(addb_imm)(hc11_state *cpustate) +void HC11OP(addb_imm)() { - UINT8 i = FETCH(cpustate); + UINT8 i = FETCH(); UINT16 r = REG_B + i; - CLEAR_HNZVC(cpustate); + CLEAR_HNZVC(); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 2); + CYCLES(2); } /* ADDB DIR 0xDB */ -static void HC11OP(addb_dir)(hc11_state *cpustate) +void HC11OP(addb_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); + UINT8 d = FETCH(); + UINT8 i = READ8(d); UINT16 r = REG_B + i; - CLEAR_HNZVC(cpustate); + CLEAR_HNZVC(); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 3); + CYCLES(3); } /* ADDB EXT 0xFB */ -static void HC11OP(addb_ext)(hc11_state *cpustate) +void HC11OP(addb_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); UINT16 r = REG_B + i; - CLEAR_HNZVC(cpustate); + CLEAR_HNZVC(); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* ADDB IND, X 0xEB */ -static void HC11OP(addb_indx)(hc11_state *cpustate) +void HC11OP(addb_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); UINT16 r = REG_B + i; - CLEAR_HNZVC(cpustate); + CLEAR_HNZVC(); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* ADDB IND, Y 0x18, 0xEB */ -static void HC11OP(addb_indy)(hc11_state *cpustate) +void HC11OP(addb_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); UINT16 r = REG_B + i; - CLEAR_HNZVC(cpustate); + CLEAR_HNZVC(); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 5); + CYCLES(5); } /* ADDD IMM 0xC3 */ -static void HC11OP(addd_imm)(hc11_state *cpustate) +void HC11OP(addd_imm)() { - UINT16 i = FETCH16(cpustate); + UINT16 i = FETCH16(); UINT32 r = REG_D + i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_ADD16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* ADDD DIR 0xD3 */ -static void HC11OP(addd_dir)(hc11_state *cpustate) +void HC11OP(addd_dir)() { - UINT8 d = FETCH(cpustate); - UINT16 i = READ16(cpustate, d); + UINT8 d = FETCH(); + UINT16 i = READ16(d); UINT32 r = REG_D + i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_ADD16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(cpustate, 5); + CYCLES(5); } /* ADDD EXT 0xF3 */ -static void HC11OP(addd_ext)(hc11_state *cpustate) +void HC11OP(addd_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT16 i = READ16(cpustate, adr); + UINT16 adr = FETCH16(); + UINT16 i = READ16(adr); UINT32 r = REG_D + i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_ADD16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(cpustate, 6); + CYCLES(6); } /* ADDD IND, X 0xE3 */ -static void HC11OP(addd_indx)(hc11_state *cpustate) +void HC11OP(addd_indx)() { - UINT8 offset = FETCH(cpustate); - UINT16 i = READ16(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT16 i = READ16(m_ix + offset); UINT32 r = REG_D + i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_ADD16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(cpustate, 6); + CYCLES(6); } /* ADDD IND, Y 0x18, 0xE3 */ -static void HC11OP(addd_indy)(hc11_state *cpustate) +void HC11OP(addd_indy)() { - UINT8 offset = FETCH(cpustate); - UINT16 i = READ16(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + UINT16 i = READ16(m_iy + offset); UINT32 r = REG_D + i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_ADD16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(cpustate, 7); + CYCLES(7); } /* ANDA IMM 0x84 */ -static void HC11OP(anda_imm)(hc11_state *cpustate) +void HC11OP(anda_imm)() { - UINT8 i = FETCH(cpustate); - CLEAR_NZV(cpustate); + UINT8 i = FETCH(); + CLEAR_NZV(); REG_A &= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 2); + CYCLES(2); } /* ANDA DIR 0x94 */ -static void HC11OP(anda_dir)(hc11_state *cpustate) +void HC11OP(anda_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); - CLEAR_NZV(cpustate); + UINT8 d = FETCH(); + UINT8 i = READ8(d); + CLEAR_NZV(); REG_A &= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 3); + CYCLES(3); } /* ANDA EXT 0xB4 */ -static void HC11OP(anda_ext)(hc11_state *cpustate) +void HC11OP(anda_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); - CLEAR_NZV(cpustate); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); + CLEAR_NZV(); REG_A &= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 4); + CYCLES(4); } /* ANDA IND, X 0xA4 */ -static void HC11OP(anda_indx)(hc11_state *cpustate) +void HC11OP(anda_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); + CLEAR_NZV(); REG_A &= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 4); + CYCLES(4); } /* ANDA IND, Y 0x18, 0xA4 */ -static void HC11OP(anda_indy)(hc11_state *cpustate) +void HC11OP(anda_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); + CLEAR_NZV(); REG_A &= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 5); + CYCLES(5); } /* ANDB IMM 0xC4 */ -static void HC11OP(andb_imm)(hc11_state *cpustate) +void HC11OP(andb_imm)() { - UINT8 i = FETCH(cpustate); - CLEAR_NZV(cpustate); + UINT8 i = FETCH(); + CLEAR_NZV(); REG_B &= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 2); + CYCLES(2); } /* ANDB DIR 0xD4 */ -static void HC11OP(andb_dir)(hc11_state *cpustate) +void HC11OP(andb_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); - CLEAR_NZV(cpustate); + UINT8 d = FETCH(); + UINT8 i = READ8(d); + CLEAR_NZV(); REG_B &= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 3); + CYCLES(3); } /* ANDB EXT 0xF4 */ -static void HC11OP(andb_ext)(hc11_state *cpustate) +void HC11OP(andb_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); - CLEAR_NZV(cpustate); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); + CLEAR_NZV(); REG_B &= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 4); + CYCLES(4); } /* ANDB IND, X 0xE4 */ -static void HC11OP(andb_indx)(hc11_state *cpustate) +void HC11OP(andb_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); + CLEAR_NZV(); REG_B &= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 4); + CYCLES(4); } /* ANDB IND, Y 0x18, 0xE4 */ -static void HC11OP(andb_indy)(hc11_state *cpustate) +void HC11OP(andb_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); + CLEAR_NZV(); REG_B &= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 5); + CYCLES(5); } /* ASLA 0x48 */ -static void HC11OP(asla)(hc11_state *cpustate) +void HC11OP(asla)() { UINT16 r = REG_A << 1; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_C8(r); REG_A = (UINT16)(r); SET_N8(REG_A); SET_Z8(REG_A); - if (((cpustate->ccr & CC_N) && (cpustate->ccr & CC_C) == 0) || - ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C))) + if (((m_ccr & CC_N) && (m_ccr & CC_C) == 0) || + ((m_ccr & CC_N) == 0 && (m_ccr & CC_C))) { - cpustate->ccr |= CC_V; + m_ccr |= CC_V; } - CYCLES(cpustate, 2); + CYCLES(2); } /* ASLB 0x58 */ -static void HC11OP(aslb)(hc11_state *cpustate) +void HC11OP(aslb)() { UINT16 r = REG_B << 1; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_C8(r); REG_B = (UINT16)(r); SET_N8(REG_B); SET_Z8(REG_B); - if (((cpustate->ccr & CC_N) && (cpustate->ccr & CC_C) == 0) || - ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C))) + if (((m_ccr & CC_N) && (m_ccr & CC_C) == 0) || + ((m_ccr & CC_N) == 0 && (m_ccr & CC_C))) { - cpustate->ccr |= CC_V; + m_ccr |= CC_V; } - CYCLES(cpustate, 2); + CYCLES(2); } /* ASL EXT 0x78 */ -static void HC11OP(asl_ext)(hc11_state *cpustate) +void HC11OP(asl_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); UINT16 r = i << 1; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_C8(r); - WRITE8(cpustate, adr, r); + WRITE8(adr, r); SET_N8(r); SET_Z8(r); - if (((cpustate->ccr & CC_N) && (cpustate->ccr & CC_C) == 0) || - ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C))) + if (((m_ccr & CC_N) && (m_ccr & CC_C) == 0) || + ((m_ccr & CC_N) == 0 && (m_ccr & CC_C))) { - cpustate->ccr |= CC_V; + m_ccr |= CC_V; } - CYCLES(cpustate, 6); + CYCLES(6); } /* BITA IMM 0x85 */ -static void HC11OP(bita_imm)(hc11_state *cpustate) +void HC11OP(bita_imm)() { - UINT8 i = FETCH(cpustate); + UINT8 i = FETCH(); UINT8 r = REG_A & i; - CLEAR_NZV(cpustate); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 2); + CYCLES(2); } /* BITA DIR 0x95 */ -static void HC11OP(bita_dir)(hc11_state *cpustate) +void HC11OP(bita_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); + UINT8 d = FETCH(); + UINT8 i = READ8(d); UINT8 r = REG_A & i; - CLEAR_NZV(cpustate); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 3); + CYCLES(3); } /* BITA EXT 0xB5 */ -static void HC11OP(bita_ext)(hc11_state *cpustate) +void HC11OP(bita_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); UINT8 r = REG_A & i; - CLEAR_NZV(cpustate); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 4); + CYCLES(4); } /* BITA IND, X 0xA5 */ -static void HC11OP(bita_indx)(hc11_state *cpustate) +void HC11OP(bita_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); UINT8 r = REG_A & i; - CLEAR_NZV(cpustate); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 4); + CYCLES(4); } /* BITA IND, Y 0x18, 0xA5 */ -static void HC11OP(bita_indy)(hc11_state *cpustate) +void HC11OP(bita_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); UINT8 r = REG_A & i; - CLEAR_NZV(cpustate); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 5); + CYCLES(5); } /* BITB IMM 0xC5 */ -static void HC11OP(bitb_imm)(hc11_state *cpustate) +void HC11OP(bitb_imm)() { - UINT8 i = FETCH(cpustate); + UINT8 i = FETCH(); UINT8 r = REG_B & i; - CLEAR_NZV(cpustate); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 2); + CYCLES(2); } /* BITB DIR 0xD5 */ -static void HC11OP(bitb_dir)(hc11_state *cpustate) +void HC11OP(bitb_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); + UINT8 d = FETCH(); + UINT8 i = READ8(d); UINT8 r = REG_B & i; - CLEAR_NZV(cpustate); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 3); + CYCLES(3); } /* BITB EXT 0xF5 */ -static void HC11OP(bitb_ext)(hc11_state *cpustate) +void HC11OP(bitb_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); UINT8 r = REG_B & i; - CLEAR_NZV(cpustate); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 4); + CYCLES(4); } /* BITB IND, X 0xE5 */ -static void HC11OP(bitb_indx)(hc11_state *cpustate) +void HC11OP(bitb_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); UINT8 r = REG_B & i; - CLEAR_NZV(cpustate); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 4); + CYCLES(4); } /* BITB IND, Y 0x18, 0xE5 */ -static void HC11OP(bitb_indy)(hc11_state *cpustate) +void HC11OP(bitb_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); UINT8 r = REG_B & i; - CLEAR_NZV(cpustate); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 5); + CYCLES(5); } /* BCC 0x24 */ -static void HC11OP(bcc)(hc11_state *cpustate) +void HC11OP(bcc)() { - INT8 rel = FETCH(cpustate); - if ((cpustate->ccr & CC_C) == 0) /* Branch if C flag clear */ + INT8 rel = FETCH(); + if ((m_ccr & CC_C) == 0) /* Branch if C flag clear */ { - SET_PC(cpustate, cpustate->ppc + rel + 2); + SET_PC(m_ppc + rel + 2); } - CYCLES(cpustate, 3); + CYCLES(3); } /* BCLR DIR 0x15 */ -static void HC11OP(bclr_dir)(hc11_state *cpustate) +void HC11OP(bclr_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 mask = FETCH(cpustate); - UINT8 r = READ8(cpustate, d) & ~mask; - WRITE8(cpustate, d, r); - CLEAR_NZV(cpustate); + UINT8 d = FETCH(); + UINT8 mask = FETCH(); + UINT8 r = READ8(d) & ~mask; + WRITE8(d, r); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 6); + CYCLES(6); } /* BCLR INDX 0x1d */ -static void HC11OP(bclr_indx)(hc11_state *cpustate) +void HC11OP(bclr_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 mask = FETCH(cpustate); - UINT8 r = READ8(cpustate, cpustate->ix + offset) & ~mask; - WRITE8(cpustate, cpustate->ix + offset, r); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 mask = FETCH(); + UINT8 r = READ8(m_ix + offset) & ~mask; + WRITE8(m_ix + offset, r); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 7); + CYCLES(7); } /* BCS 0x25 */ -static void HC11OP(bcs)(hc11_state *cpustate) +void HC11OP(bcs)() { - INT8 rel = FETCH(cpustate); - if (cpustate->ccr & CC_C) /* Branch if C flag set */ + INT8 rel = FETCH(); + if (m_ccr & CC_C) /* Branch if C flag set */ { - SET_PC(cpustate, cpustate->ppc + rel + 2); + SET_PC(m_ppc + rel + 2); } - CYCLES(cpustate, 3); + CYCLES(3); } /* BEQ 0x27 */ -static void HC11OP(beq)(hc11_state *cpustate) +void HC11OP(beq)() { - INT8 rel = FETCH(cpustate); - if (cpustate->ccr & CC_Z) /* Branch if Z flag set */ + INT8 rel = FETCH(); + if (m_ccr & CC_Z) /* Branch if Z flag set */ { - SET_PC(cpustate, cpustate->ppc + rel + 2); + SET_PC(m_ppc + rel + 2); } - CYCLES(cpustate, 3); + CYCLES(3); } /* BHI 0x22 */ -static void HC11OP(bhi)(hc11_state *cpustate) +void HC11OP(bhi)() { - INT8 rel = FETCH(cpustate); - if (((cpustate->ccr & CC_C) == 0) && ((cpustate->ccr & CC_Z) == 0)) /* Branch if C and Z flag clear */ + INT8 rel = FETCH(); + if (((m_ccr & CC_C) == 0) && ((m_ccr & CC_Z) == 0)) /* Branch if C and Z flag clear */ { - SET_PC(cpustate, cpustate->ppc + rel + 2); + SET_PC(m_ppc + rel + 2); } - CYCLES(cpustate, 3); + CYCLES(3); } /* BNE 0x26 */ -static void HC11OP(bne)(hc11_state *cpustate) +void HC11OP(bne)() { - INT8 rel = FETCH(cpustate); - if ((cpustate->ccr & CC_Z) == 0) /* Branch if Z flag clear */ + INT8 rel = FETCH(); + if ((m_ccr & CC_Z) == 0) /* Branch if Z flag clear */ { - SET_PC(cpustate, cpustate->ppc + rel + 2); + SET_PC(m_ppc + rel + 2); } - CYCLES(cpustate, 3); + CYCLES(3); } /* BLE 0x2F */ -static void HC11OP(ble)(hc11_state *cpustate) +void HC11OP(ble)() { - UINT8 n = (cpustate->ccr & CC_N) ? 1 : 0; - UINT8 v = (cpustate->ccr & CC_V) ? 1 : 0; - INT8 rel = FETCH(cpustate); - if ((cpustate->ccr & CC_Z) || (n ^ v)) /* Branch if Z flag set or (N ^ V) */ + UINT8 n = (m_ccr & CC_N) ? 1 : 0; + UINT8 v = (m_ccr & CC_V) ? 1 : 0; + INT8 rel = FETCH(); + if ((m_ccr & CC_Z) || (n ^ v)) /* Branch if Z flag set or (N ^ V) */ { - SET_PC(cpustate, cpustate->ppc + rel + 2); + SET_PC(m_ppc + rel + 2); } - CYCLES(cpustate, 3); + CYCLES(3); } /* BLS 0x23 */ -static void HC11OP(bls)(hc11_state *cpustate) +void HC11OP(bls)() { - INT8 rel = FETCH(cpustate); - if (cpustate->ccr & CC_C || cpustate->ccr & CC_Z) /* Branch if C or Z flag set */ + INT8 rel = FETCH(); + if (m_ccr & CC_C || m_ccr & CC_Z) /* Branch if C or Z flag set */ { - SET_PC(cpustate, cpustate->ppc + rel + 2); + SET_PC(m_ppc + rel + 2); } - CYCLES(cpustate, 3); + CYCLES(3); } /* BMI 0x2B */ -static void HC11OP(bmi)(hc11_state *cpustate) +void HC11OP(bmi)() { - INT8 rel = FETCH(cpustate); - if (cpustate->ccr & CC_N) /* Branch if N flag set */ + INT8 rel = FETCH(); + if (m_ccr & CC_N) /* Branch if N flag set */ { - SET_PC(cpustate, cpustate->ppc + rel + 2); + SET_PC(m_ppc + rel + 2); } - CYCLES(cpustate, 3); + CYCLES(3); } /* BPL 0x2A */ -static void HC11OP(bpl)(hc11_state *cpustate) +void HC11OP(bpl)() { - INT8 rel = FETCH(cpustate); - if ((cpustate->ccr & CC_N) == 0) /* Branch if N flag clear */ + INT8 rel = FETCH(); + if ((m_ccr & CC_N) == 0) /* Branch if N flag clear */ { - SET_PC(cpustate, cpustate->ppc + rel + 2); + SET_PC(m_ppc + rel + 2); } - CYCLES(cpustate, 3); + CYCLES(3); } /* BRA 0x20 */ -static void HC11OP(bra)(hc11_state *cpustate) +void HC11OP(bra)() { - INT8 rel = FETCH(cpustate); - SET_PC(cpustate, cpustate->ppc + rel + 2); - CYCLES(cpustate, 3); + INT8 rel = FETCH(); + SET_PC(m_ppc + rel + 2); + CYCLES(3); } /* BRCLR DIR 0x13 */ -static void HC11OP(brclr_dir)(hc11_state *cpustate) +void HC11OP(brclr_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 mask = FETCH(cpustate); - INT8 rel = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); + UINT8 d = FETCH(); + UINT8 mask = FETCH(); + INT8 rel = FETCH(); + UINT8 i = READ8(d); if ((i & mask) == 0) { - SET_PC(cpustate, cpustate->ppc + rel + 4); + SET_PC(m_ppc + rel + 4); } - CYCLES(cpustate, 6); + CYCLES(6); } /* BRCLR INDX 0x1F */ -static void HC11OP(brclr_indx)(hc11_state *cpustate) +void HC11OP(brclr_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 mask = FETCH(cpustate); - INT8 rel = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT8 mask = FETCH(); + INT8 rel = FETCH(); + UINT8 i = READ8(m_ix + offset); if ((i & mask) == 0) { - SET_PC(cpustate, cpustate->ppc + rel + 4); + SET_PC(m_ppc + rel + 4); } - CYCLES(cpustate, 7); + CYCLES(7); } /* BRSET DIR 0x12 */ -static void HC11OP(brset_dir)(hc11_state *cpustate) +void HC11OP(brset_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 mask = FETCH(cpustate); - INT8 rel = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); + UINT8 d = FETCH(); + UINT8 mask = FETCH(); + INT8 rel = FETCH(); + UINT8 i = READ8(d); if(i & mask) { - SET_PC(cpustate, cpustate->ppc + rel + 4); + SET_PC(m_ppc + rel + 4); } - CYCLES(cpustate, 6); + CYCLES(6); } /* BRSET INDX 0x1E */ -static void HC11OP(brset_indx)(hc11_state *cpustate) +void HC11OP(brset_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 mask = FETCH(cpustate); - INT8 rel = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT8 mask = FETCH(); + INT8 rel = FETCH(); + UINT8 i = READ8(m_ix + offset); if ((~i & mask) == 0) { - SET_PC(cpustate, cpustate->ppc + rel + 4); + SET_PC(m_ppc + rel + 4); } - CYCLES(cpustate, 7); + CYCLES(7); } /* BRN 0x21 */ -static void HC11OP(brn)(hc11_state *cpustate) +void HC11OP(brn)() { /* with this opcode the branch condition is always false. */ - SET_PC(cpustate, cpustate->ppc + 2); - CYCLES(cpustate, 3); + SET_PC(m_ppc + 2); + CYCLES(3); } /* BSET DIR 0x14 */ -static void HC11OP(bset_dir)(hc11_state *cpustate) +void HC11OP(bset_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 mask = FETCH(cpustate); - UINT8 r = READ8(cpustate, d) | mask; - WRITE8(cpustate, d, r); - CLEAR_NZV(cpustate); + UINT8 d = FETCH(); + UINT8 mask = FETCH(); + UINT8 r = READ8(d) | mask; + WRITE8(d, r); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 6); + CYCLES(6); } /* BSET INDX 0x1c */ -static void HC11OP(bset_indx)(hc11_state *cpustate) +void HC11OP(bset_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 mask = FETCH(cpustate); - UINT8 r = READ8(cpustate, cpustate->ix + offset) | mask; - WRITE8(cpustate, cpustate->ix + offset, r); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 mask = FETCH(); + UINT8 r = READ8(m_ix + offset) | mask; + WRITE8(m_ix + offset, r); + CLEAR_NZV(); SET_N8(r); SET_Z8(r); - CYCLES(cpustate, 7); + CYCLES(7); } /* BSR 0x8D */ -static void HC11OP(bsr)(hc11_state *cpustate) +void HC11OP(bsr)() { - INT8 rel = FETCH(cpustate); - UINT16 rt_adr = cpustate->pc; - PUSH16(cpustate, rt_adr); - SET_PC(cpustate, cpustate->ppc + rel + 2); - CYCLES(cpustate, 6); + INT8 rel = FETCH(); + UINT16 rt_adr = m_pc; + PUSH16(rt_adr); + SET_PC(m_ppc + rel + 2); + CYCLES(6); } /* BVC 0x28 */ -static void HC11OP(bvc)(hc11_state *cpustate) +void HC11OP(bvc)() { - INT8 rel = FETCH(cpustate); - if ((cpustate->ccr & CC_V) == 0) /* Branch if V flag clear */ + INT8 rel = FETCH(); + if ((m_ccr & CC_V) == 0) /* Branch if V flag clear */ { - SET_PC(cpustate, cpustate->ppc + rel + 2); + SET_PC(m_ppc + rel + 2); } - CYCLES(cpustate, 3); + CYCLES(3); } /* BVS 0x29 */ -static void HC11OP(bvs)(hc11_state *cpustate) +void HC11OP(bvs)() { - INT8 rel = FETCH(cpustate); - if (cpustate->ccr & CC_V) /* Branch if V flag set */ + INT8 rel = FETCH(); + if (m_ccr & CC_V) /* Branch if V flag set */ { - SET_PC(cpustate, cpustate->ppc + rel + 2); + SET_PC(m_ppc + rel + 2); } - CYCLES(cpustate, 3); + CYCLES(3); } /* CBA 0x11 */ -static void HC11OP(cba)(hc11_state *cpustate) +void HC11OP(cba)() { UINT16 r = REG_A - REG_B; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, REG_B, REG_A); SET_C8(r); - CYCLES(cpustate, 2); + CYCLES(2); } /* CLC 0x0C */ -static void HC11OP(clc)(hc11_state *cpustate) +void HC11OP(clc)() { - cpustate->ccr &= ~CC_C; - CYCLES(cpustate, 2); + m_ccr &= ~CC_C; + CYCLES(2); } /* CLI 0x0E */ -static void HC11OP(cli)(hc11_state *cpustate) +void HC11OP(cli)() { - cpustate->ccr &= ~CC_I; - CYCLES(cpustate, 2); + m_ccr &= ~CC_I; + CYCLES(2); } /* CLRA 0x4F */ -static void HC11OP(clra)(hc11_state *cpustate) +void HC11OP(clra)() { REG_A = 0; - CLEAR_NZVC(cpustate); - SET_ZFLAG(cpustate); - CYCLES(cpustate, 2); + CLEAR_NZVC(); + SET_ZFLAG(); + CYCLES(2); } /* CLRB 0x5F */ -static void HC11OP(clrb)(hc11_state *cpustate) +void HC11OP(clrb)() { REG_B = 0; - CLEAR_NZVC(cpustate); - SET_ZFLAG(cpustate); - CYCLES(cpustate, 2); + CLEAR_NZVC(); + SET_ZFLAG(); + CYCLES(2); } /* CLR EXT 0x7F */ -static void HC11OP(clr_ext)(hc11_state *cpustate) +void HC11OP(clr_ext)() { - UINT16 adr = FETCH16(cpustate); - WRITE8(cpustate, adr, 0); - CLEAR_NZVC(cpustate); - SET_ZFLAG(cpustate); - CYCLES(cpustate, 6); + UINT16 adr = FETCH16(); + WRITE8(adr, 0); + CLEAR_NZVC(); + SET_ZFLAG(); + CYCLES(6); } /* CLR IND, X 0x6F */ -static void HC11OP(clr_indx)(hc11_state *cpustate) +void HC11OP(clr_indx)() { - UINT8 offset = FETCH(cpustate); - WRITE8(cpustate, cpustate->ix + offset, 0); - CLEAR_NZVC(cpustate); - SET_ZFLAG(cpustate); - CYCLES(cpustate, 6); + UINT8 offset = FETCH(); + WRITE8(m_ix + offset, 0); + CLEAR_NZVC(); + SET_ZFLAG(); + CYCLES(6); } /* CLR IND, Y 0x18, 0x6F */ -static void HC11OP(clr_indy)(hc11_state *cpustate) +void HC11OP(clr_indy)() { - UINT8 offset = FETCH(cpustate); - WRITE8(cpustate, cpustate->iy + offset, 0); - CLEAR_NZVC(cpustate); - SET_ZFLAG(cpustate); - CYCLES(cpustate, 7); + UINT8 offset = FETCH(); + WRITE8(m_iy + offset, 0); + CLEAR_NZVC(); + SET_ZFLAG(); + CYCLES(7); } /* CLV 0x0A */ -static void HC11OP(clv)(hc11_state *cpustate) +void HC11OP(clv)() { - cpustate->ccr &= ~CC_V; - CYCLES(cpustate, 2); + m_ccr &= ~CC_V; + CYCLES(2); } /* CMPA IMM 0x81 */ -static void HC11OP(cmpa_imm)(hc11_state *cpustate) +void HC11OP(cmpa_imm)() { - UINT8 i = FETCH(cpustate); + UINT8 i = FETCH(); UINT16 r = REG_A - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); - CYCLES(cpustate, 2); + CYCLES(2); } /* CMPA DIR 0x91 */ -static void HC11OP(cmpa_dir)(hc11_state *cpustate) +void HC11OP(cmpa_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); + UINT8 d = FETCH(); + UINT8 i = READ8(d); UINT16 r = REG_A - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); - CYCLES(cpustate, 3); + CYCLES(3); } /* CMPA EXT 0xB1 */ -static void HC11OP(cmpa_ext)(hc11_state *cpustate) +void HC11OP(cmpa_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); UINT16 r = REG_A - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); - CYCLES(cpustate, 4); + CYCLES(4); } /* CMPA IND, X 0xA1 */ -static void HC11OP(cmpa_indx)(hc11_state *cpustate) +void HC11OP(cmpa_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); UINT16 r = REG_A - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); - CYCLES(cpustate, 4); + CYCLES(4); } /* CMPA IND, Y 0x18, 0xA1 */ -static void HC11OP(cmpa_indy)(hc11_state *cpustate) +void HC11OP(cmpa_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); UINT16 r = REG_A - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); - CYCLES(cpustate, 5); + CYCLES(5); } /* CMPB IMM 0xC1 */ -static void HC11OP(cmpb_imm)(hc11_state *cpustate) +void HC11OP(cmpb_imm)() { - UINT8 i = FETCH(cpustate); + UINT8 i = FETCH(); UINT16 r = REG_B - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); - CYCLES(cpustate, 2); + CYCLES(2); } /* CMPB DIR 0xD1 */ -static void HC11OP(cmpb_dir)(hc11_state *cpustate) +void HC11OP(cmpb_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); + UINT8 d = FETCH(); + UINT8 i = READ8(d); UINT16 r = REG_B - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); - CYCLES(cpustate, 3); + CYCLES(3); } /* CMPB EXT 0xF1 */ -static void HC11OP(cmpb_ext)(hc11_state *cpustate) +void HC11OP(cmpb_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); UINT16 r = REG_B - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); - CYCLES(cpustate, 4); + CYCLES(4); } /* CMPB IND, X 0xE1 */ -static void HC11OP(cmpb_indx)(hc11_state *cpustate) +void HC11OP(cmpb_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); UINT16 r = REG_B - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); - CYCLES(cpustate, 4); + CYCLES(4); } /* CMPB IND, Y 0x18, 0xE1 */ -static void HC11OP(cmpb_indy)(hc11_state *cpustate) +void HC11OP(cmpb_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); UINT16 r = REG_B - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); - CYCLES(cpustate, 5); + CYCLES(5); } /* COMA , 0x43 */ -static void HC11OP(coma)(hc11_state *cpustate) +void HC11OP(coma)() { UINT16 r = 0xff - REG_A; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); - cpustate->ccr |= CC_C; //always set for M6800 compatibility + m_ccr |= CC_C; //always set for M6800 compatibility REG_A = r; - CYCLES(cpustate, 2); + CYCLES(2); } /* COMB , 0x53 */ -static void HC11OP(comb)(hc11_state *cpustate) +void HC11OP(comb)() { UINT16 r = 0xff - REG_B; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); - cpustate->ccr |= CC_C; //always set for M6800 compatibility + m_ccr |= CC_C; //always set for M6800 compatibility REG_B = r; - CYCLES(cpustate, 2); + CYCLES(2); } /* CPD IMM 0x1A, 0x83 */ -static void HC11OP(cpd_imm)(hc11_state *cpustate) +void HC11OP(cpd_imm)() { - UINT16 i = FETCH16(cpustate); + UINT16 i = FETCH16(); UINT32 r = REG_D - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); - CYCLES(cpustate, 5); + CYCLES(5); } /* CPD DIR 0x1A, 0x93 */ -static void HC11OP(cpd_dir)(hc11_state *cpustate) +void HC11OP(cpd_dir)() { - UINT8 d = FETCH(cpustate); - UINT16 i = READ16(cpustate, d); + UINT8 d = FETCH(); + UINT16 i = READ16(d); UINT32 r = REG_D - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); - CYCLES(cpustate, 6); + CYCLES(6); } /* CPD EXT 0x1A, 0xB3 */ -static void HC11OP(cpd_ext)(hc11_state *cpustate) +void HC11OP(cpd_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT16 i = READ16(cpustate, adr); + UINT16 adr = FETCH16(); + UINT16 i = READ16(adr); UINT32 r = REG_D - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); - CYCLES(cpustate, 7); + CYCLES(7); } /* CPD IND, X 0x1A, 0xA3 */ -static void HC11OP(cpd_indx)(hc11_state *cpustate) +void HC11OP(cpd_indx)() { - UINT8 offset = FETCH(cpustate); - UINT16 i = READ16(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT16 i = READ16(m_ix + offset); UINT32 r = REG_D - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); - CYCLES(cpustate, 7); + CYCLES(7); } /* CPD IND, Y 0xCD, 0xA3 */ -static void HC11OP(cpd_indy)(hc11_state *cpustate) +void HC11OP(cpd_indy)() { - UINT8 offset = FETCH(cpustate); - UINT16 i = READ16(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + UINT16 i = READ16(m_iy + offset); UINT32 r = REG_D - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); - CYCLES(cpustate, 7); + CYCLES(7); } /* CPX IMM 0x8C */ -static void HC11OP(cpx_imm)(hc11_state *cpustate) +void HC11OP(cpx_imm)() { - UINT16 i = FETCH16(cpustate); - UINT32 r = cpustate->ix - i; - CLEAR_NZVC(cpustate); + UINT16 i = FETCH16(); + UINT32 r = m_ix - i; + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, cpustate->ix); + SET_V_SUB16(r, i, m_ix); SET_C16(r); - CYCLES(cpustate, 4); + CYCLES(4); } /* CPX DIR 0x9C */ -static void HC11OP(cpx_dir)(hc11_state *cpustate) +void HC11OP(cpx_dir)() { - UINT8 d = FETCH(cpustate); - UINT16 i = READ16(cpustate, d); - UINT32 r = cpustate->ix - i; - CLEAR_NZVC(cpustate); + UINT8 d = FETCH(); + UINT16 i = READ16(d); + UINT32 r = m_ix - i; + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, cpustate->ix); + SET_V_SUB16(r, i, m_ix); SET_C16(r); - CYCLES(cpustate, 5); + CYCLES(5); } /* CPX EXT 0xBC */ -static void HC11OP(cpx_ext)(hc11_state *cpustate) +void HC11OP(cpx_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT16 i = READ16(cpustate, adr); - UINT32 r = cpustate->ix - i; - CLEAR_NZVC(cpustate); + UINT16 adr = FETCH16(); + UINT16 i = READ16(adr); + UINT32 r = m_ix - i; + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, cpustate->ix); + SET_V_SUB16(r, i, m_ix); SET_C16(r); - CYCLES(cpustate, 6); + CYCLES(6); } /* CPX IND, X 0xAC */ -static void HC11OP(cpx_indx)(hc11_state *cpustate) +void HC11OP(cpx_indx)() { - UINT8 offset = FETCH(cpustate); - UINT16 i = READ16(cpustate, cpustate->ix + offset); - UINT32 r = cpustate->ix - i; - CLEAR_NZVC(cpustate); + UINT8 offset = FETCH(); + UINT16 i = READ16(m_ix + offset); + UINT32 r = m_ix - i; + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, cpustate->ix); + SET_V_SUB16(r, i, m_ix); SET_C16(r); - CYCLES(cpustate, 6); + CYCLES(6); } /* CPX IND, Y 0xCD, 0xAC */ -static void HC11OP(cpx_indy)(hc11_state *cpustate) +void HC11OP(cpx_indy)() { - UINT8 offset = FETCH(cpustate); - UINT16 i = READ16(cpustate, cpustate->iy + offset); - UINT32 r = cpustate->ix - i; - CLEAR_NZVC(cpustate); + UINT8 offset = FETCH(); + UINT16 i = READ16(m_iy + offset); + UINT32 r = m_ix - i; + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, cpustate->ix); + SET_V_SUB16(r, i, m_ix); SET_C16(r); - CYCLES(cpustate, 7); + CYCLES(7); } /* CPY IMM 0x18, 0x8C */ -static void HC11OP(cpy_imm)(hc11_state *cpustate) +void HC11OP(cpy_imm)() { - UINT16 i = FETCH16(cpustate); - UINT32 r = cpustate->iy - i; - CLEAR_NZVC(cpustate); + UINT16 i = FETCH16(); + UINT32 r = m_iy - i; + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, cpustate->iy); + SET_V_SUB16(r, i, m_iy); SET_C16(r); - CYCLES(cpustate, 5); + CYCLES(5); } /* CPY DIR 0x18 0x9C */ -static void HC11OP(cpy_dir)(hc11_state *cpustate) +void HC11OP(cpy_dir)() { - UINT8 d = FETCH(cpustate); - UINT16 i = READ16(cpustate, d); - UINT32 r = cpustate->iy - i; - CLEAR_NZVC(cpustate); + UINT8 d = FETCH(); + UINT16 i = READ16(d); + UINT32 r = m_iy - i; + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, cpustate->iy); + SET_V_SUB16(r, i, m_iy); SET_C16(r); - CYCLES(cpustate, 6); + CYCLES(6); } /* CPY EXT 0x18 0xBC */ -static void HC11OP(cpy_ext)(hc11_state *cpustate) +void HC11OP(cpy_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT16 i = READ16(cpustate, adr); - UINT32 r = cpustate->iy - i; - CLEAR_NZVC(cpustate); + UINT16 adr = FETCH16(); + UINT16 i = READ16(adr); + UINT32 r = m_iy - i; + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, cpustate->iy); + SET_V_SUB16(r, i, m_iy); SET_C16(r); - CYCLES(cpustate, 7); + CYCLES(7); } /* CPY IND, X 0x1A 0xAC */ -static void HC11OP(cpy_indx)(hc11_state *cpustate) +void HC11OP(cpy_indx)() { - UINT8 offset = FETCH(cpustate); - UINT16 i = READ16(cpustate, cpustate->ix + offset); - UINT32 r = cpustate->iy - i; - CLEAR_NZVC(cpustate); + UINT8 offset = FETCH(); + UINT16 i = READ16(m_ix + offset); + UINT32 r = m_iy - i; + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, cpustate->iy); + SET_V_SUB16(r, i, m_iy); SET_C16(r); - CYCLES(cpustate, 7); + CYCLES(7); } /* CPY IND, Y 0x18 0xAC */ -static void HC11OP(cpy_indy)(hc11_state *cpustate) +void HC11OP(cpy_indy)() { - UINT8 offset = FETCH(cpustate); - UINT16 i = READ16(cpustate, cpustate->iy + offset); - UINT32 r = cpustate->iy - i; - CLEAR_NZVC(cpustate); + UINT8 offset = FETCH(); + UINT16 i = READ16(m_iy + offset); + UINT32 r = m_iy - i; + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, cpustate->iy); + SET_V_SUB16(r, i, m_iy); SET_C16(r); - CYCLES(cpustate, 7); + CYCLES(7); } /* DECA 0x4A */ -static void HC11OP(deca)(hc11_state *cpustate) +void HC11OP(deca)() { - CLEAR_NZV(cpustate); + CLEAR_NZV(); if (REG_A == 0x80) - SET_VFLAG(cpustate); + SET_VFLAG(); REG_A--; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 2); + CYCLES(2); } /* DECB 0x5A */ -static void HC11OP(decb)(hc11_state *cpustate) +void HC11OP(decb)() { - CLEAR_NZV(cpustate); + CLEAR_NZV(); if (REG_B == 0x80) - SET_VFLAG(cpustate); + SET_VFLAG(); REG_B--; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 2); + CYCLES(2); } /* DEC EXT 0x7A */ -static void HC11OP(dec_ext)(hc11_state *cpustate) +void HC11OP(dec_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); - CLEAR_NZV(cpustate); + CLEAR_NZV(); if (i == 0x80) - SET_VFLAG(cpustate); + SET_VFLAG(); i--; SET_N8(i); SET_Z8(i); - WRITE8(cpustate, adr, i); - CYCLES(cpustate, 6); + WRITE8(adr, i); + CYCLES(6); } /* DEC INDX 0x6A */ -static void HC11OP(dec_indx)(hc11_state *cpustate) +void HC11OP(dec_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); - CLEAR_NZV(cpustate); + CLEAR_NZV(); if (i == 0x80) - SET_VFLAG(cpustate); + SET_VFLAG(); i--; SET_N8(i); SET_Z8(i); - WRITE8(cpustate, cpustate->ix + offset, i); - CYCLES(cpustate, 6); + WRITE8(m_ix + offset, i); + CYCLES(6); } /* DEC INDY 0x18 0x6A */ -static void HC11OP(dec_indy)(hc11_state *cpustate) +void HC11OP(dec_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); - CLEAR_NZV(cpustate); + CLEAR_NZV(); if (i == 0x80) - SET_VFLAG(cpustate); + SET_VFLAG(); i--; SET_N8(i); SET_Z8(i); - WRITE8(cpustate, cpustate->iy + offset, i); - CYCLES(cpustate, 7); + WRITE8(m_iy + offset, i); + CYCLES(7); } /* DEX 0x09 */ -static void HC11OP(dex)(hc11_state *cpustate) +void HC11OP(dex)() { - CLEAR_Z(cpustate); - cpustate->ix--; - SET_Z16(cpustate->ix); - CYCLES(cpustate, 3); + CLEAR_Z(); + m_ix--; + SET_Z16(m_ix); + CYCLES(3); } /* DEY 0x18, 0x09 */ -static void HC11OP(dey)(hc11_state *cpustate) +void HC11OP(dey)() { - CLEAR_Z(cpustate); - cpustate->iy--; - SET_Z16(cpustate->iy); - CYCLES(cpustate, 4); + CLEAR_Z(); + m_iy--; + SET_Z16(m_iy); + CYCLES(4); } /* EORA IMM 0x88 */ -static void HC11OP(eora_imm)(hc11_state *cpustate) +void HC11OP(eora_imm)() { - UINT8 i = FETCH(cpustate); - CLEAR_NZV(cpustate); + UINT8 i = FETCH(); + CLEAR_NZV(); REG_A ^= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 2); + CYCLES(2); } /* EORA DIR 0x98 */ -static void HC11OP(eora_dir)(hc11_state *cpustate) +void HC11OP(eora_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); - CLEAR_NZV(cpustate); + UINT8 d = FETCH(); + UINT8 i = READ8(d); + CLEAR_NZV(); REG_A ^= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 3); + CYCLES(3); } /* EORA EXT 0xB8 */ -static void HC11OP(eora_ext)(hc11_state *cpustate) +void HC11OP(eora_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); - CLEAR_NZV(cpustate); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); + CLEAR_NZV(); REG_A ^= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 4); + CYCLES(4); } /* EORA IND, X 0xA8 */ -static void HC11OP(eora_indx)(hc11_state *cpustate) +void HC11OP(eora_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); + CLEAR_NZV(); REG_A ^= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 4); + CYCLES(4); } /* EORA IND, Y 0x18, 0xA8 */ -static void HC11OP(eora_indy)(hc11_state *cpustate) +void HC11OP(eora_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); + CLEAR_NZV(); REG_A ^= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 5); + CYCLES(5); } /* EORB IMM 0xC8 */ -static void HC11OP(eorb_imm)(hc11_state *cpustate) +void HC11OP(eorb_imm)() { - UINT8 i = FETCH(cpustate); - CLEAR_NZV(cpustate); + UINT8 i = FETCH(); + CLEAR_NZV(); REG_B ^= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 2); + CYCLES(2); } /* EORB DIR 0xD8 */ -static void HC11OP(eorb_dir)(hc11_state *cpustate) +void HC11OP(eorb_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); - CLEAR_NZV(cpustate); + UINT8 d = FETCH(); + UINT8 i = READ8(d); + CLEAR_NZV(); REG_B ^= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 3); + CYCLES(3); } /* EORB EXT 0xF8 */ -static void HC11OP(eorb_ext)(hc11_state *cpustate) +void HC11OP(eorb_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); - CLEAR_NZV(cpustate); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); + CLEAR_NZV(); REG_B ^= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 4); + CYCLES(4); } /* EORB IND, X 0xE8 */ -static void HC11OP(eorb_indx)(hc11_state *cpustate) +void HC11OP(eorb_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); + CLEAR_NZV(); REG_B ^= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 4); + CYCLES(4); } /* EORB IND, Y 0x18, 0xE8 */ -static void HC11OP(eorb_indy)(hc11_state *cpustate) +void HC11OP(eorb_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); + CLEAR_NZV(); REG_B ^= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 5); + CYCLES(5); } /* IDIV 0x02 */ -static void HC11OP(idiv)(hc11_state *cpustate) +void HC11OP(idiv)() { UINT16 numerator = REG_D; - UINT16 denominator = cpustate->ix; + UINT16 denominator = m_ix; UINT16 remainder; UINT16 result; - CLEAR_ZVC(cpustate); + CLEAR_ZVC(); if(denominator == 0) // divide by zero behaviour { remainder = 0xffff; // TODO: undefined behaviour according to the docs result = 0xffff; - logerror("HC11: divide by zero at PC=%04x\n",cpustate->pc-1); - cpustate->ccr |= CC_C; + logerror("HC11: divide by zero at PC=%04x\n",m_pc-1); + m_ccr |= CC_C; } else { remainder = numerator % denominator; result = numerator / denominator; } - cpustate->ix = result; + m_ix = result; REG_D = remainder; SET_Z16(result); - CYCLES(cpustate, 41); + CYCLES(41); } /* INCA 0x4C */ -static void HC11OP(inca)(hc11_state *cpustate) +void HC11OP(inca)() { - CLEAR_NZV(cpustate); + CLEAR_NZV(); if (REG_A == 0x7f) - SET_VFLAG(cpustate); + SET_VFLAG(); REG_A++; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 2); + CYCLES(2); } /* INCB 0x5C */ -static void HC11OP(incb)(hc11_state *cpustate) +void HC11OP(incb)() { - CLEAR_NZV(cpustate); + CLEAR_NZV(); if (REG_B == 0x7f) - SET_VFLAG(cpustate); + SET_VFLAG(); REG_B++; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 2); + CYCLES(2); } /* INC EXT 0x7C */ -static void HC11OP(inc_ext)(hc11_state *cpustate) +void HC11OP(inc_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); - CLEAR_NZV(cpustate); + CLEAR_NZV(); if (i == 0x7f) - SET_VFLAG(cpustate); + SET_VFLAG(); i++; SET_N8(i); SET_Z8(i); - WRITE8(cpustate, adr, i); - CYCLES(cpustate, 6); + WRITE8(adr, i); + CYCLES(6); } /* INC INDX 0x6C */ -static void HC11OP(inc_indx)(hc11_state *cpustate) +void HC11OP(inc_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); - CLEAR_NZV(cpustate); + CLEAR_NZV(); if (i == 0x7f) - SET_VFLAG(cpustate); + SET_VFLAG(); i++; SET_N8(i); SET_Z8(i); - WRITE8(cpustate, cpustate->ix + offset, i); - CYCLES(cpustate, 6); + WRITE8(m_ix + offset, i); + CYCLES(6); } /* INC INDY 0x18 0x6C */ -static void HC11OP(inc_indy)(hc11_state *cpustate) +void HC11OP(inc_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); - CLEAR_NZV(cpustate); + CLEAR_NZV(); if (i == 0x7f) - SET_VFLAG(cpustate); + SET_VFLAG(); i++; SET_N8(i); SET_Z8(i); - WRITE8(cpustate, cpustate->iy + offset, i); - CYCLES(cpustate, 7); + WRITE8(m_iy + offset, i); + CYCLES(7); } /* INX 0x08 */ -static void HC11OP(inx)(hc11_state *cpustate) +void HC11OP(inx)() { - CLEAR_Z(cpustate); - cpustate->ix++; - SET_Z16(cpustate->ix); - CYCLES(cpustate, 3); + CLEAR_Z(); + m_ix++; + SET_Z16(m_ix); + CYCLES(3); } /* INY 0x18, 0x08 */ -static void HC11OP(iny)(hc11_state *cpustate) +void HC11OP(iny)() { - CLEAR_Z(cpustate); - cpustate->iy++; - SET_Z16(cpustate->iy); - CYCLES(cpustate, 4); + CLEAR_Z(); + m_iy++; + SET_Z16(m_iy); + CYCLES(4); } /* JMP IND X 0x6E */ -static void HC11OP(jmp_indx)(hc11_state *cpustate) +void HC11OP(jmp_indx)() { - UINT16 adr = FETCH(cpustate); - SET_PC(cpustate, cpustate->ix + adr); - CYCLES(cpustate, 3); + UINT16 adr = FETCH(); + SET_PC(m_ix + adr); + CYCLES(3); } /* JMP IND Y 0x18 0x6E */ -static void HC11OP(jmp_indy)(hc11_state *cpustate) +void HC11OP(jmp_indy)() { - UINT16 adr = FETCH(cpustate); - SET_PC(cpustate, cpustate->iy + adr); - CYCLES(cpustate, 4); + UINT16 adr = FETCH(); + SET_PC(m_iy + adr); + CYCLES(4); } /* JMP EXT 0x7E */ -static void HC11OP(jmp_ext)(hc11_state *cpustate) +void HC11OP(jmp_ext)() { - UINT16 adr = FETCH16(cpustate); - SET_PC(cpustate, adr); - CYCLES(cpustate, 3); + UINT16 adr = FETCH16(); + SET_PC(adr); + CYCLES(3); } /* JSR DIR 0x9D */ -static void HC11OP(jsr_dir)(hc11_state *cpustate) +void HC11OP(jsr_dir)() { - UINT8 i = FETCH(cpustate); - UINT16 rt_adr = cpustate->pc; - PUSH16(cpustate, rt_adr); - SET_PC(cpustate, i); - CYCLES(cpustate, 5); + UINT8 i = FETCH(); + UINT16 rt_adr = m_pc; + PUSH16(rt_adr); + SET_PC(i); + CYCLES(5); } /* JSR EXT 0xBD */ -static void HC11OP(jsr_ext)(hc11_state *cpustate) +void HC11OP(jsr_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT16 rt_adr = cpustate->pc; - PUSH16(cpustate, rt_adr); - SET_PC(cpustate, adr); - CYCLES(cpustate, 6); + UINT16 adr = FETCH16(); + UINT16 rt_adr = m_pc; + PUSH16(rt_adr); + SET_PC(adr); + CYCLES(6); } /* JSR IND, X 0xAD */ -static void HC11OP(jsr_indx)(hc11_state *cpustate) +void HC11OP(jsr_indx)() { - UINT8 offset = FETCH(cpustate); - UINT16 rt_adr = cpustate->pc; - PUSH16(cpustate, rt_adr); - SET_PC(cpustate, cpustate->ix + offset); - CYCLES(cpustate, 6); + UINT8 offset = FETCH(); + UINT16 rt_adr = m_pc; + PUSH16(rt_adr); + SET_PC(m_ix + offset); + CYCLES(6); } /* JSR IND, Y 0x18, 0xAD */ -static void HC11OP(jsr_indy)(hc11_state *cpustate) +void HC11OP(jsr_indy)() { - UINT8 offset = FETCH(cpustate); - UINT16 rt_adr = cpustate->pc; - PUSH16(cpustate, rt_adr); - SET_PC(cpustate, cpustate->iy + offset); - CYCLES(cpustate, 6); + UINT8 offset = FETCH(); + UINT16 rt_adr = m_pc; + PUSH16(rt_adr); + SET_PC(m_iy + offset); + CYCLES(6); } /* LDAA IMM 0x86 */ -static void HC11OP(ldaa_imm)(hc11_state *cpustate) +void HC11OP(ldaa_imm)() { - CLEAR_NZV(cpustate); - REG_A = FETCH(cpustate); + CLEAR_NZV(); + REG_A = FETCH(); SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 2); + CYCLES(2); } /* LDAA DIR 0x96 */ -static void HC11OP(ldaa_dir)(hc11_state *cpustate) +void HC11OP(ldaa_dir)() { - UINT8 d = FETCH(cpustate); - CLEAR_NZV(cpustate); - REG_A = READ8(cpustate, d); + UINT8 d = FETCH(); + CLEAR_NZV(); + REG_A = READ8(d); SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 3); + CYCLES(3); } /* LDAA EXT 0xB6 */ -static void HC11OP(ldaa_ext)(hc11_state *cpustate) +void HC11OP(ldaa_ext)() { - UINT16 adr = FETCH16(cpustate); - CLEAR_NZV(cpustate); - REG_A = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + CLEAR_NZV(); + REG_A = READ8(adr); SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 4); + CYCLES(4); } /* LDAA IND, X 0xA6 */ -static void HC11OP(ldaa_indx)(hc11_state *cpustate) +void HC11OP(ldaa_indx)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - REG_A = READ8(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + CLEAR_NZV(); + REG_A = READ8(m_ix + offset); SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 4); + CYCLES(4); } /* LDAA IND, Y 0x18, 0xA6 */ -static void HC11OP(ldaa_indy)(hc11_state *cpustate) +void HC11OP(ldaa_indy)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - REG_A = READ8(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + CLEAR_NZV(); + REG_A = READ8(m_iy + offset); SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 5); + CYCLES(5); } /* LDAB IMM 0xC6 */ -static void HC11OP(ldab_imm)(hc11_state *cpustate) +void HC11OP(ldab_imm)() { - CLEAR_NZV(cpustate); - REG_B = FETCH(cpustate); + CLEAR_NZV(); + REG_B = FETCH(); SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 2); + CYCLES(2); } /* LDAB DIR 0xD6 */ -static void HC11OP(ldab_dir)(hc11_state *cpustate) +void HC11OP(ldab_dir)() { - UINT8 d = FETCH(cpustate); - CLEAR_NZV(cpustate); - REG_B = READ8(cpustate, d); + UINT8 d = FETCH(); + CLEAR_NZV(); + REG_B = READ8(d); SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 3); + CYCLES(3); } /* LDAB EXT 0xF6 */ -static void HC11OP(ldab_ext)(hc11_state *cpustate) +void HC11OP(ldab_ext)() { - UINT16 adr = FETCH16(cpustate); - CLEAR_NZV(cpustate); - REG_B = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + CLEAR_NZV(); + REG_B = READ8(adr); SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 4); + CYCLES(4); } /* LDAB IND, X 0xE6 */ -static void HC11OP(ldab_indx)(hc11_state *cpustate) +void HC11OP(ldab_indx)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - REG_B = READ8(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + CLEAR_NZV(); + REG_B = READ8(m_ix + offset); SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 4); + CYCLES(4); } /* LDAB IND, Y 0x18, 0xE6 */ -static void HC11OP(ldab_indy)(hc11_state *cpustate) +void HC11OP(ldab_indy)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - REG_B = READ8(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + CLEAR_NZV(); + REG_B = READ8(m_iy + offset); SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 5); + CYCLES(5); } /* LDD IMM 0xCC */ -static void HC11OP(ldd_imm)(hc11_state *cpustate) +void HC11OP(ldd_imm)() { - CLEAR_NZV(cpustate); - REG_D = FETCH16(cpustate); + CLEAR_NZV(); + REG_D = FETCH16(); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(cpustate, 3); + CYCLES(3); } /* LDD DIR 0xDC */ -static void HC11OP(ldd_dir)(hc11_state *cpustate) +void HC11OP(ldd_dir)() { - UINT8 d = FETCH(cpustate); - CLEAR_NZV(cpustate); - REG_D = READ16(cpustate, d); + UINT8 d = FETCH(); + CLEAR_NZV(); + REG_D = READ16(d); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(cpustate, 4); + CYCLES(4); } /* LDD EXT 0xFC */ -static void HC11OP(ldd_ext)(hc11_state *cpustate) +void HC11OP(ldd_ext)() { - UINT16 adr = FETCH16(cpustate); - CLEAR_NZV(cpustate); - REG_D = READ16(cpustate, adr); + UINT16 adr = FETCH16(); + CLEAR_NZV(); + REG_D = READ16(adr); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(cpustate, 5); + CYCLES(5); } /* LDD IND, X 0xEC */ -static void HC11OP(ldd_indx)(hc11_state *cpustate) +void HC11OP(ldd_indx)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - REG_D = READ16(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + CLEAR_NZV(); + REG_D = READ16(m_ix + offset); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(cpustate, 5); + CYCLES(5); } /* LDD IND, Y 0x18, 0xEC */ -static void HC11OP(ldd_indy)(hc11_state *cpustate) +void HC11OP(ldd_indy)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - REG_D = READ16(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + CLEAR_NZV(); + REG_D = READ16(m_iy + offset); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(cpustate, 6); + CYCLES(6); } /* LDS IMM 0x8E */ -static void HC11OP(lds_imm)(hc11_state *cpustate) +void HC11OP(lds_imm)() { - CLEAR_NZV(cpustate); - cpustate->sp = FETCH16(cpustate); - SET_N16(cpustate->sp); - SET_Z16(cpustate->sp); - CYCLES(cpustate, 3); + CLEAR_NZV(); + m_sp = FETCH16(); + SET_N16(m_sp); + SET_Z16(m_sp); + CYCLES(3); } /* LDS DIR 0x9E */ -static void HC11OP(lds_dir)(hc11_state *cpustate) +void HC11OP(lds_dir)() { - UINT8 i = FETCH(cpustate); - CLEAR_NZV(cpustate); - cpustate->sp = READ16(cpustate, i); - SET_N16(cpustate->sp); - SET_Z16(cpustate->sp); - CYCLES(cpustate, 4); + UINT8 i = FETCH(); + CLEAR_NZV(); + m_sp = READ16(i); + SET_N16(m_sp); + SET_Z16(m_sp); + CYCLES(4); } /* LDS EXT 0xBE */ -static void HC11OP(lds_ext)(hc11_state *cpustate) +void HC11OP(lds_ext)() { - UINT16 adr = FETCH16(cpustate); - CLEAR_NZV(cpustate); - cpustate->sp = READ16(cpustate, adr); - SET_N16(cpustate->sp); - SET_Z16(cpustate->sp); - CYCLES(cpustate, 5); + UINT16 adr = FETCH16(); + CLEAR_NZV(); + m_sp = READ16(adr); + SET_N16(m_sp); + SET_Z16(m_sp); + CYCLES(5); } /* LDS IND, X 0xAE */ -static void HC11OP(lds_indx)(hc11_state *cpustate) +void HC11OP(lds_indx)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - cpustate->sp = READ16(cpustate, cpustate->ix + offset); - SET_N16(cpustate->sp); - SET_Z16(cpustate->sp); - CYCLES(cpustate, 5); + UINT8 offset = FETCH(); + CLEAR_NZV(); + m_sp = READ16(m_ix + offset); + SET_N16(m_sp); + SET_Z16(m_sp); + CYCLES(5); } /* LDS IND, Y 0x18, 0xAE */ -static void HC11OP(lds_indy)(hc11_state *cpustate) +void HC11OP(lds_indy)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - cpustate->sp = READ16(cpustate, cpustate->iy + offset); - SET_N16(cpustate->sp); - SET_Z16(cpustate->sp); - CYCLES(cpustate, 6); + UINT8 offset = FETCH(); + CLEAR_NZV(); + m_sp = READ16(m_iy + offset); + SET_N16(m_sp); + SET_Z16(m_sp); + CYCLES(6); } /* LDX IMM 0xCE */ -static void HC11OP(ldx_imm)(hc11_state *cpustate) +void HC11OP(ldx_imm)() { - CLEAR_NZV(cpustate); - cpustate->ix = FETCH16(cpustate); - SET_N16(cpustate->ix); - SET_Z16(cpustate->ix); - CYCLES(cpustate, 3); + CLEAR_NZV(); + m_ix = FETCH16(); + SET_N16(m_ix); + SET_Z16(m_ix); + CYCLES(3); } /* LDX DIR 0xDE */ -static void HC11OP(ldx_dir)(hc11_state *cpustate) +void HC11OP(ldx_dir)() { - UINT8 d = FETCH(cpustate); - CLEAR_NZV(cpustate); - cpustate->ix = READ16(cpustate, d); - SET_N16(cpustate->ix); - SET_Z16(cpustate->ix); - CYCLES(cpustate, 4); + UINT8 d = FETCH(); + CLEAR_NZV(); + m_ix = READ16(d); + SET_N16(m_ix); + SET_Z16(m_ix); + CYCLES(4); } /* LDX EXT 0xFE */ -static void HC11OP(ldx_ext)(hc11_state *cpustate) +void HC11OP(ldx_ext)() { - UINT16 adr = FETCH16(cpustate); - CLEAR_NZV(cpustate); - cpustate->ix = READ16(cpustate, adr); - SET_N16(cpustate->ix); - SET_Z16(cpustate->ix); - CYCLES(cpustate, 5); + UINT16 adr = FETCH16(); + CLEAR_NZV(); + m_ix = READ16(adr); + SET_N16(m_ix); + SET_Z16(m_ix); + CYCLES(5); } /* LDX IND, X 0xEE */ -static void HC11OP(ldx_indx)(hc11_state *cpustate) +void HC11OP(ldx_indx)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - cpustate->ix = READ16(cpustate, cpustate->ix + offset); - SET_N16(cpustate->ix); - SET_Z16(cpustate->ix); - CYCLES(cpustate, 5); + UINT8 offset = FETCH(); + CLEAR_NZV(); + m_ix = READ16(m_ix + offset); + SET_N16(m_ix); + SET_Z16(m_ix); + CYCLES(5); } /* LDX IND, Y 0xCD, 0xEE */ -static void HC11OP(ldx_indy)(hc11_state *cpustate) +void HC11OP(ldx_indy)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - cpustate->ix = READ16(cpustate, cpustate->iy + offset); - SET_N16(cpustate->ix); - SET_Z16(cpustate->ix); - CYCLES(cpustate, 6); + UINT8 offset = FETCH(); + CLEAR_NZV(); + m_ix = READ16(m_iy + offset); + SET_N16(m_ix); + SET_Z16(m_ix); + CYCLES(6); } /* LDY IMM 0x18, 0xCE */ -static void HC11OP(ldy_imm)(hc11_state *cpustate) +void HC11OP(ldy_imm)() { - CLEAR_NZV(cpustate); - cpustate->iy = FETCH16(cpustate); - SET_N16(cpustate->iy); - SET_Z16(cpustate->iy); - CYCLES(cpustate, 4); + CLEAR_NZV(); + m_iy = FETCH16(); + SET_N16(m_iy); + SET_Z16(m_iy); + CYCLES(4); } /* LDY DIR 0x18, 0xDE */ -static void HC11OP(ldy_dir)(hc11_state *cpustate) +void HC11OP(ldy_dir)() { - UINT8 d = FETCH(cpustate); - CLEAR_NZV(cpustate); - cpustate->iy = READ16(cpustate, d); - SET_N16(cpustate->iy); - SET_Z16(cpustate->iy); - CYCLES(cpustate, 5); + UINT8 d = FETCH(); + CLEAR_NZV(); + m_iy = READ16(d); + SET_N16(m_iy); + SET_Z16(m_iy); + CYCLES(5); } /* LDY EXT 0x18, 0xFE */ -static void HC11OP(ldy_ext)(hc11_state *cpustate) +void HC11OP(ldy_ext)() { - UINT16 adr = FETCH16(cpustate); - CLEAR_NZV(cpustate); - cpustate->iy = READ16(cpustate, adr); - SET_N16(cpustate->iy); - SET_Z16(cpustate->iy); - CYCLES(cpustate, 6); + UINT16 adr = FETCH16(); + CLEAR_NZV(); + m_iy = READ16(adr); + SET_N16(m_iy); + SET_Z16(m_iy); + CYCLES(6); } /* LDY IND, X 0x1A, 0xEE */ -static void HC11OP(ldy_indx)(hc11_state *cpustate) +void HC11OP(ldy_indx)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - cpustate->iy = READ16(cpustate, cpustate->ix + offset); - SET_N16(cpustate->iy); - SET_Z16(cpustate->iy); - CYCLES(cpustate, 6); + UINT8 offset = FETCH(); + CLEAR_NZV(); + m_iy = READ16(m_ix + offset); + SET_N16(m_iy); + SET_Z16(m_iy); + CYCLES(6); } /* LDY IND, Y 0x18, 0xEE */ -static void HC11OP(ldy_indy)(hc11_state *cpustate) +void HC11OP(ldy_indy)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - cpustate->iy = READ16(cpustate, cpustate->iy + offset); - SET_N16(cpustate->iy); - SET_Z16(cpustate->iy); - CYCLES(cpustate, 6); + UINT8 offset = FETCH(); + CLEAR_NZV(); + m_iy = READ16(m_iy + offset); + SET_N16(m_iy); + SET_Z16(m_iy); + CYCLES(6); } /* LSLD 0x05 */ -static void HC11OP(lsld)(hc11_state *cpustate) +void HC11OP(lsld)() { UINT32 r = REG_D << 1; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_C16(r); REG_D = (UINT16)(r); SET_N16(REG_D); SET_Z16(REG_D); - if (((cpustate->ccr & CC_N) && (cpustate->ccr & CC_C) == 0) || - ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C))) + if (((m_ccr & CC_N) && (m_ccr & CC_C) == 0) || + ((m_ccr & CC_N) == 0 && (m_ccr & CC_C))) { - cpustate->ccr |= CC_V; + m_ccr |= CC_V; } - CYCLES(cpustate, 3); + CYCLES(3); } /* LSRA 0x44 */ -static void HC11OP(lsra)(hc11_state *cpustate) +void HC11OP(lsra)() { UINT16 r = REG_A >> 1; - CLEAR_NZVC(cpustate); - cpustate->ccr |= (REG_A & 1) ? CC_C : 0; + CLEAR_NZVC(); + m_ccr |= (REG_A & 1) ? CC_C : 0; REG_A = (UINT8)(r); - cpustate->ccr |= ((cpustate->ccr & CC_C)) ? CC_V : 0; + m_ccr |= ((m_ccr & CC_C)) ? CC_V : 0; SET_Z8(REG_A); - CYCLES(cpustate, 2); + CYCLES(2); } /* LSRB 0x54 */ -static void HC11OP(lsrb)(hc11_state *cpustate) +void HC11OP(lsrb)() { UINT16 r = REG_B >> 1; - CLEAR_NZVC(cpustate); - cpustate->ccr |= (REG_B & 1) ? CC_C : 0; + CLEAR_NZVC(); + m_ccr |= (REG_B & 1) ? CC_C : 0; REG_B = (UINT8)(r); - cpustate->ccr |= ((cpustate->ccr & CC_C)) ? CC_V : 0; + m_ccr |= ((m_ccr & CC_C)) ? CC_V : 0; SET_Z8(REG_B); - CYCLES(cpustate, 2); + CYCLES(2); } /* LSRD 0x04 */ -static void HC11OP(lsrd)(hc11_state *cpustate) +void HC11OP(lsrd)() { UINT32 r = REG_D >> 1; - CLEAR_NZVC(cpustate); - cpustate->ccr |= (REG_D & 1) ? CC_C : 0; + CLEAR_NZVC(); + m_ccr |= (REG_D & 1) ? CC_C : 0; REG_D = (UINT16)(r); - cpustate->ccr |= ((cpustate->ccr & CC_C)) ? CC_V : 0; + m_ccr |= ((m_ccr & CC_C)) ? CC_V : 0; SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(cpustate, 3); + CYCLES(3); } /* MUL 0x3d */ -static void HC11OP(mul)(hc11_state *cpustate) +void HC11OP(mul)() { REG_D = REG_A * REG_B; - CLEAR_C(cpustate); - cpustate->ccr |= (REG_B & 0x80) ? CC_C : 0; - CYCLES(cpustate, 10); + CLEAR_C(); + m_ccr |= (REG_B & 0x80) ? CC_C : 0; + CYCLES(10); } /* NEGA 0x40 */ -static void HC11OP(nega)(hc11_state *cpustate) +void HC11OP(nega)() { REG_A = 0x00 - REG_A; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(REG_A); SET_Z8(REG_A); - cpustate->ccr |= (REG_A == 0x80) ? CC_V : 0; - cpustate->ccr |= (REG_A != 0x00) ? CC_C : 0; - CYCLES(cpustate, 2); + m_ccr |= (REG_A == 0x80) ? CC_V : 0; + m_ccr |= (REG_A != 0x00) ? CC_C : 0; + CYCLES(2); } /* NEGB 0x50 */ -static void HC11OP(negb)(hc11_state *cpustate) +void HC11OP(negb)() { REG_B = 0x00 - REG_B; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(REG_B); SET_Z8(REG_B); - cpustate->ccr |= (REG_B == 0x80) ? CC_V : 0; - cpustate->ccr |= (REG_B != 0x00) ? CC_C : 0; - CYCLES(cpustate, 2); + m_ccr |= (REG_B == 0x80) ? CC_V : 0; + m_ccr |= (REG_B != 0x00) ? CC_C : 0; + CYCLES(2); } /* NEG EXT 0x70 */ -static void HC11OP(neg_ext)(hc11_state *cpustate) +void HC11OP(neg_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = 0x00 - READ8(cpustate, adr); - CLEAR_NZVC(cpustate); + UINT16 adr = FETCH16(); + UINT8 i = 0x00 - READ8(adr); + CLEAR_NZVC(); SET_N8(i); SET_Z8(i); - cpustate->ccr |= (i == 0x80) ? CC_V : 0; - cpustate->ccr |= (i != 0x00) ? CC_C : 0; - WRITE8(cpustate, adr, i); - CYCLES(cpustate, 6); + m_ccr |= (i == 0x80) ? CC_V : 0; + m_ccr |= (i != 0x00) ? CC_C : 0; + WRITE8(adr, i); + CYCLES(6); } /* NEG INDX 0x60 */ -static void HC11OP(neg_indx)(hc11_state *cpustate) +void HC11OP(neg_indx)() { - UINT16 offset = FETCH(cpustate); - UINT8 i = 0x00 - READ8(cpustate, cpustate->ix + offset); - CLEAR_NZVC(cpustate); + UINT16 offset = FETCH(); + UINT8 i = 0x00 - READ8(m_ix + offset); + CLEAR_NZVC(); SET_N8(i); SET_Z8(i); - cpustate->ccr |= (i == 0x80) ? CC_V : 0; - cpustate->ccr |= (i != 0x00) ? CC_C : 0; - WRITE8(cpustate, cpustate->ix + offset, i); - CYCLES(cpustate, 6); + m_ccr |= (i == 0x80) ? CC_V : 0; + m_ccr |= (i != 0x00) ? CC_C : 0; + WRITE8(m_ix + offset, i); + CYCLES(6); } /* NEG INDY 0x18 0x60 */ -static void HC11OP(neg_indy)(hc11_state *cpustate) +void HC11OP(neg_indy)() { - UINT16 offset = FETCH(cpustate); - UINT8 i = 0x00 - READ8(cpustate, cpustate->iy + offset); - CLEAR_NZVC(cpustate); + UINT16 offset = FETCH(); + UINT8 i = 0x00 - READ8(m_iy + offset); + CLEAR_NZVC(); SET_N8(i); SET_Z8(i); - cpustate->ccr |= (i == 0x80) ? CC_V : 0; - cpustate->ccr |= (i != 0x00) ? CC_C : 0; - WRITE8(cpustate, cpustate->iy + offset, i); - CYCLES(cpustate, 7); + m_ccr |= (i == 0x80) ? CC_V : 0; + m_ccr |= (i != 0x00) ? CC_C : 0; + WRITE8(m_iy + offset, i); + CYCLES(7); } /* NOP 0x01 */ -static void HC11OP(nop)(hc11_state *cpustate) +void HC11OP(nop)() { - CYCLES(cpustate, 2); + CYCLES(2); } /* PSHA 0x36 */ -static void HC11OP(psha)(hc11_state *cpustate) +void HC11OP(psha)() { - PUSH8(cpustate, REG_A); - CYCLES(cpustate, 3); + PUSH8(REG_A); + CYCLES(3); } /* ORAA IMM 0x8A */ -static void HC11OP(oraa_imm)(hc11_state *cpustate) +void HC11OP(oraa_imm)() { - UINT8 i = FETCH(cpustate); - CLEAR_NZV(cpustate); + UINT8 i = FETCH(); + CLEAR_NZV(); REG_A |= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 2); + CYCLES(2); } /* ORAA DIR 0x9A */ -static void HC11OP(oraa_dir)(hc11_state *cpustate) +void HC11OP(oraa_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); - CLEAR_NZV(cpustate); + UINT8 d = FETCH(); + UINT8 i = READ8(d); + CLEAR_NZV(); REG_A |= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 3); + CYCLES(3); } /* ORAA EXT 0xBA */ -static void HC11OP(oraa_ext)(hc11_state *cpustate) +void HC11OP(oraa_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); - CLEAR_NZV(cpustate); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); + CLEAR_NZV(); REG_A |= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 4); + CYCLES(4); } /* ORAA IND, X 0xAA */ -static void HC11OP(oraa_indx)(hc11_state *cpustate) +void HC11OP(oraa_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); + CLEAR_NZV(); REG_A |= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 4); + CYCLES(4); } /* ORAA IND, Y 0x18, 0xAA */ -static void HC11OP(oraa_indy)(hc11_state *cpustate) +void HC11OP(oraa_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); + CLEAR_NZV(); REG_A |= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 5); + CYCLES(5); } /* ORAB IMM 0xCA */ -static void HC11OP(orab_imm)(hc11_state *cpustate) +void HC11OP(orab_imm)() { - UINT8 i = FETCH(cpustate); - CLEAR_NZV(cpustate); + UINT8 i = FETCH(); + CLEAR_NZV(); REG_B |= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 2); + CYCLES(2); } /* ORAB DIR 0xDA */ -static void HC11OP(orab_dir)(hc11_state *cpustate) +void HC11OP(orab_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); - CLEAR_NZV(cpustate); + UINT8 d = FETCH(); + UINT8 i = READ8(d); + CLEAR_NZV(); REG_B |= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 3); + CYCLES(3); } /* ORAB EXT 0xFA */ -static void HC11OP(orab_ext)(hc11_state *cpustate) +void HC11OP(orab_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); - CLEAR_NZV(cpustate); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); + CLEAR_NZV(); REG_B |= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 4); + CYCLES(4); } /* ORAB IND, X 0xEA */ -static void HC11OP(orab_indx)(hc11_state *cpustate) +void HC11OP(orab_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); + CLEAR_NZV(); REG_B |= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 4); + CYCLES(4); } /* ORAB IND, Y 0x18, 0xEA */ -static void HC11OP(orab_indy)(hc11_state *cpustate) +void HC11OP(orab_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); + CLEAR_NZV(); REG_B |= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 5); + CYCLES(5); } /* PSHB 0x37 */ -static void HC11OP(pshb)(hc11_state *cpustate) +void HC11OP(pshb)() { - PUSH8(cpustate, REG_B); - CYCLES(cpustate, 3); + PUSH8(REG_B); + CYCLES(3); } /* PSHX 0x3C */ -static void HC11OP(pshx)(hc11_state *cpustate) +void HC11OP(pshx)() { - PUSH16(cpustate, cpustate->ix); - CYCLES(cpustate, 4); + PUSH16(m_ix); + CYCLES(4); } /* PSHY 0x18, 0x3C */ -static void HC11OP(pshy)(hc11_state *cpustate) +void HC11OP(pshy)() { - PUSH16(cpustate, cpustate->iy); - CYCLES(cpustate, 5); + PUSH16(m_iy); + CYCLES(5); } /* PULA 0x32 */ -static void HC11OP(pula)(hc11_state *cpustate) +void HC11OP(pula)() { - REG_A = POP8(cpustate); - CYCLES(cpustate, 4); + REG_A = POP8(); + CYCLES(4); } /* PULB 0x33 */ -static void HC11OP(pulb)(hc11_state *cpustate) +void HC11OP(pulb)() { - REG_B = POP8(cpustate); - CYCLES(cpustate, 4); + REG_B = POP8(); + CYCLES(4); } /* PULX 0x38 */ -static void HC11OP(pulx)(hc11_state *cpustate) +void HC11OP(pulx)() { - cpustate->ix = POP16(cpustate); - CYCLES(cpustate, 5); + m_ix = POP16(); + CYCLES(5); } /* PULY 0x18, 0x38 */ -static void HC11OP(puly)(hc11_state *cpustate) +void HC11OP(puly)() { - cpustate->iy = POP16(cpustate); - CYCLES(cpustate, 6); + m_iy = POP16(); + CYCLES(6); } /* ROLA 0x49 */ -static void HC11OP(rola)(hc11_state *cpustate) +void HC11OP(rola)() { - UINT16 r = ((REG_A & 0x7f) << 1) | ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_NZVC(cpustate); - cpustate->ccr |= (REG_A & 0x80) ? CC_C : 0; + UINT16 r = ((REG_A & 0x7f) << 1) | ((m_ccr & CC_C) ? 1 : 0); + CLEAR_NZVC(); + m_ccr |= (REG_A & 0x80) ? CC_C : 0; REG_A = (UINT8)(r); SET_N8(REG_A); SET_Z8(REG_A); - if (((cpustate->ccr & CC_N) && (cpustate->ccr & CC_C) == 0) || - ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C))) + if (((m_ccr & CC_N) && (m_ccr & CC_C) == 0) || + ((m_ccr & CC_N) == 0 && (m_ccr & CC_C))) { - cpustate->ccr |= CC_V; + m_ccr |= CC_V; } - CYCLES(cpustate, 2); + CYCLES(2); } /* ROLB 0x59 */ -static void HC11OP(rolb)(hc11_state *cpustate) +void HC11OP(rolb)() { - UINT16 r = ((REG_B & 0x7f) << 1) | ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_NZVC(cpustate); - cpustate->ccr |= (REG_B & 0x80) ? CC_C : 0; + UINT16 r = ((REG_B & 0x7f) << 1) | ((m_ccr & CC_C) ? 1 : 0); + CLEAR_NZVC(); + m_ccr |= (REG_B & 0x80) ? CC_C : 0; REG_B = (UINT8)(r); SET_N8(REG_B); SET_Z8(REG_B); - if (((cpustate->ccr & CC_N) && (cpustate->ccr & CC_C) == 0) || - ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C))) + if (((m_ccr & CC_N) && (m_ccr & CC_C) == 0) || + ((m_ccr & CC_N) == 0 && (m_ccr & CC_C))) { - cpustate->ccr |= CC_V; + m_ccr |= CC_V; } - CYCLES(cpustate, 2); + CYCLES(2); } /* ROL EXT 0x79 */ -static void HC11OP(rol_ext)(hc11_state *cpustate) +void HC11OP(rol_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 r = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + UINT8 r = READ8(adr); UINT8 c = (r & 0x80); - r = ((r & 0x7f) << 1) | ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_NZVC(cpustate); - cpustate->ccr |= (c & 0x80) ? CC_C : 0; + r = ((r & 0x7f) << 1) | ((m_ccr & CC_C) ? 1 : 0); + CLEAR_NZVC(); + m_ccr |= (c & 0x80) ? CC_C : 0; SET_N8(r); SET_Z8(r); - WRITE8(cpustate, adr, r); + WRITE8(adr, r); - if (((cpustate->ccr & CC_N) && (cpustate->ccr & CC_C) == 0) || - ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C))) + if (((m_ccr & CC_N) && (m_ccr & CC_C) == 0) || + ((m_ccr & CC_N) == 0 && (m_ccr & CC_C))) { - cpustate->ccr |= CC_V; + m_ccr |= CC_V; } - CYCLES(cpustate, 6); + CYCLES(6); } /* ROL INDX 0x69 */ -static void HC11OP(rol_indx)(hc11_state *cpustate) +void HC11OP(rol_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); UINT8 c = (i & 0x80); - i = ((i & 0x7f) << 1) | ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_NZVC(cpustate); - cpustate->ccr |= (c & 0x80) ? CC_C : 0; + i = ((i & 0x7f) << 1) | ((m_ccr & CC_C) ? 1 : 0); + CLEAR_NZVC(); + m_ccr |= (c & 0x80) ? CC_C : 0; SET_N8(i); SET_Z8(i); - WRITE8(cpustate, cpustate->ix + offset, i); + WRITE8(m_ix + offset, i); - if (((cpustate->ccr & CC_N) && (cpustate->ccr & CC_C) == 0) || - ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C))) + if (((m_ccr & CC_N) && (m_ccr & CC_C) == 0) || + ((m_ccr & CC_N) == 0 && (m_ccr & CC_C))) { - cpustate->ccr |= CC_V; + m_ccr |= CC_V; } - CYCLES(cpustate, 6); + CYCLES(6); } /* ROL INDY 0x18 0x69 */ -static void HC11OP(rol_indy)(hc11_state *cpustate) +void HC11OP(rol_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); UINT8 c = (i & 0x80); - i = ((i & 0x7f) << 1) | ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_NZVC(cpustate); - cpustate->ccr |= (c & 0x80) ? CC_C : 0; + i = ((i & 0x7f) << 1) | ((m_ccr & CC_C) ? 1 : 0); + CLEAR_NZVC(); + m_ccr |= (c & 0x80) ? CC_C : 0; SET_N8(i); SET_Z8(i); - WRITE8(cpustate, cpustate->iy + offset, i); + WRITE8(m_iy + offset, i); - if (((cpustate->ccr & CC_N) && (cpustate->ccr & CC_C) == 0) || - ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C))) + if (((m_ccr & CC_N) && (m_ccr & CC_C) == 0) || + ((m_ccr & CC_N) == 0 && (m_ccr & CC_C))) { - cpustate->ccr |= CC_V; + m_ccr |= CC_V; } - CYCLES(cpustate, 6); + CYCLES(6); } /* RORA 0x46 */ -static void HC11OP(rora)(hc11_state *cpustate) +void HC11OP(rora)() { - UINT16 r = ((REG_A & 0xfe) >> 1) | ((cpustate->ccr & CC_C) ? 0x80 : 0); - CLEAR_NZVC(cpustate); - cpustate->ccr |= (REG_A & 1) ? CC_C : 0; + UINT16 r = ((REG_A & 0xfe) >> 1) | ((m_ccr & CC_C) ? 0x80 : 0); + CLEAR_NZVC(); + m_ccr |= (REG_A & 1) ? CC_C : 0; REG_A = (UINT8)(r); SET_N8(REG_A); SET_Z8(REG_A); - if (((cpustate->ccr & CC_N) && (cpustate->ccr & CC_C) == 0) || - ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C))) + if (((m_ccr & CC_N) && (m_ccr & CC_C) == 0) || + ((m_ccr & CC_N) == 0 && (m_ccr & CC_C))) { - cpustate->ccr |= CC_V; + m_ccr |= CC_V; } - CYCLES(cpustate, 2); + CYCLES(2); } /* RORB 0x56 */ -static void HC11OP(rorb)(hc11_state *cpustate) +void HC11OP(rorb)() { - UINT16 r = ((REG_B & 0xfe) >> 1) | ((cpustate->ccr & CC_C) ? 0x80 : 0); - CLEAR_NZVC(cpustate); - cpustate->ccr |= (REG_B & 1) ? CC_C : 0; + UINT16 r = ((REG_B & 0xfe) >> 1) | ((m_ccr & CC_C) ? 0x80 : 0); + CLEAR_NZVC(); + m_ccr |= (REG_B & 1) ? CC_C : 0; REG_B = (UINT8)(r); SET_N8(REG_B); SET_Z8(REG_B); - if (((cpustate->ccr & CC_N) && (cpustate->ccr & CC_C) == 0) || - ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C))) + if (((m_ccr & CC_N) && (m_ccr & CC_C) == 0) || + ((m_ccr & CC_N) == 0 && (m_ccr & CC_C))) { - cpustate->ccr |= CC_V; + m_ccr |= CC_V; } - CYCLES(cpustate, 2); + CYCLES(2); } /* RTI 0x3B */ -static void HC11OP(rti)(hc11_state *cpustate) +void HC11OP(rti)() { UINT16 rt_adr; - UINT8 x_flag = cpustate->ccr & CC_X; - cpustate->ccr = POP8(cpustate); - if(x_flag == 0 && cpustate->ccr & CC_X) //X flag cannot do a 0->1 transition with this instruction. - cpustate->ccr &= ~CC_X; - REG_B = POP8(cpustate); - REG_A = POP8(cpustate); - cpustate->ix = POP16(cpustate); - cpustate->iy = POP16(cpustate); - rt_adr = POP16(cpustate); - SET_PC(cpustate, rt_adr); - CYCLES(cpustate, 12); + UINT8 x_flag = m_ccr & CC_X; + m_ccr = POP8(); + if(x_flag == 0 && m_ccr & CC_X) //X flag cannot do a 0->1 transition with this instruction. + m_ccr &= ~CC_X; + REG_B = POP8(); + REG_A = POP8(); + m_ix = POP16(); + m_iy = POP16(); + rt_adr = POP16(); + SET_PC(rt_adr); + CYCLES(12); } /* RTS 0x39 */ -static void HC11OP(rts)(hc11_state *cpustate) +void HC11OP(rts)() { - UINT16 rt_adr = POP16(cpustate); - SET_PC(cpustate, rt_adr); - CYCLES(cpustate, 5); + UINT16 rt_adr = POP16(); + SET_PC(rt_adr); + CYCLES(5); } /* SBA 0x10 */ -static void HC11OP(sba)(hc11_state *cpustate) +void HC11OP(sba)() { UINT16 r = REG_A - REG_B; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, REG_B, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 2); + CYCLES(2); } /* SBCA IMM 0x82 */ -static void HC11OP(sbca_imm)(hc11_state *cpustate) +void HC11OP(sbca_imm)() { - UINT8 i = FETCH(cpustate); - UINT16 r = (REG_A - i) - ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_NZVC(cpustate); + UINT8 i = FETCH(); + UINT16 r = (REG_A - i) - ((m_ccr & CC_C) ? 1 : 0); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 2); + CYCLES(2); } /* SBCA IND, X 0xA2 */ -static void HC11OP(sbca_indx)(hc11_state *cpustate) +void HC11OP(sbca_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); - UINT16 r = (REG_A - i) - ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_NZVC(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); + UINT16 r = (REG_A - i) - ((m_ccr & CC_C) ? 1 : 0); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* SBCA IND, Y 0x18, 0xA2 */ -static void HC11OP(sbca_indy)(hc11_state *cpustate) +void HC11OP(sbca_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); - UINT16 r = (REG_A - i) - ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_NZVC(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); + UINT16 r = (REG_A - i) - ((m_ccr & CC_C) ? 1 : 0); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 5); + CYCLES(5); } /* SBCB IMM 0xC2 */ -static void HC11OP(sbcb_imm)(hc11_state *cpustate) +void HC11OP(sbcb_imm)() { - UINT8 i = FETCH(cpustate); - UINT16 r = (REG_B - i) - ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_NZVC(cpustate); + UINT8 i = FETCH(); + UINT16 r = (REG_B - i) - ((m_ccr & CC_C) ? 1 : 0); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 2); + CYCLES(2); } /* SBCB IND, X 0xE2 */ -static void HC11OP(sbcb_indx)(hc11_state *cpustate) +void HC11OP(sbcb_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); - UINT16 r = (REG_B - i) - ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_NZVC(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); + UINT16 r = (REG_B - i) - ((m_ccr & CC_C) ? 1 : 0); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* SBCB IND, Y 0x18, 0xE2 */ -static void HC11OP(sbcb_indy)(hc11_state *cpustate) +void HC11OP(sbcb_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); - UINT16 r = (REG_B - i) - ((cpustate->ccr & CC_C) ? 1 : 0); - CLEAR_NZVC(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); + UINT16 r = (REG_B - i) - ((m_ccr & CC_C) ? 1 : 0); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 5); + CYCLES(5); } /* SEC 0x0D */ -static void HC11OP(sec)(hc11_state *cpustate) +void HC11OP(sec)() { - cpustate->ccr |= CC_C; - CYCLES(cpustate, 2); + m_ccr |= CC_C; + CYCLES(2); } /* SEI 0x0F */ -static void HC11OP(sei)(hc11_state *cpustate) +void HC11OP(sei)() { - cpustate->ccr |= CC_I; - CYCLES(cpustate, 2); + m_ccr |= CC_I; + CYCLES(2); } /* SEV 0x0B */ -static void HC11OP(sev)(hc11_state *cpustate) +void HC11OP(sev)() { - cpustate->ccr |= CC_V; - CYCLES(cpustate, 2); + m_ccr |= CC_V; + CYCLES(2); } /* STAA DIR 0x97 */ -static void HC11OP(staa_dir)(hc11_state *cpustate) +void HC11OP(staa_dir)() { - UINT8 d = FETCH(cpustate); - CLEAR_NZV(cpustate); + UINT8 d = FETCH(); + CLEAR_NZV(); SET_N8(REG_A); SET_Z8(REG_A); - WRITE8(cpustate, d, REG_A); - CYCLES(cpustate, 3); + WRITE8(d, REG_A); + CYCLES(3); } /* STAA EXT 0xB7 */ -static void HC11OP(staa_ext)(hc11_state *cpustate) +void HC11OP(staa_ext)() { - UINT16 adr = FETCH16(cpustate); - CLEAR_NZV(cpustate); + UINT16 adr = FETCH16(); + CLEAR_NZV(); SET_N8(REG_A); SET_Z8(REG_A); - WRITE8(cpustate, adr, REG_A); - CYCLES(cpustate, 4); + WRITE8(adr, REG_A); + CYCLES(4); } /* STAA IND, X 0xA7 */ -static void HC11OP(staa_indx)(hc11_state *cpustate) +void HC11OP(staa_indx)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + CLEAR_NZV(); SET_N8(REG_A); SET_Z8(REG_A); - WRITE8(cpustate, cpustate->ix + offset, REG_A); - CYCLES(cpustate, 4); + WRITE8(m_ix + offset, REG_A); + CYCLES(4); } /* STAA IND, Y 0x18, 0xA7 */ -static void HC11OP(staa_indy)(hc11_state *cpustate) +void HC11OP(staa_indy)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + CLEAR_NZV(); SET_N8(REG_A); SET_Z8(REG_A); - WRITE8(cpustate, cpustate->iy + offset, REG_A); - CYCLES(cpustate, 5); + WRITE8(m_iy + offset, REG_A); + CYCLES(5); } /* STAB DIR 0xD7 */ -static void HC11OP(stab_dir)(hc11_state *cpustate) +void HC11OP(stab_dir)() { - UINT8 d = FETCH(cpustate); - CLEAR_NZV(cpustate); + UINT8 d = FETCH(); + CLEAR_NZV(); SET_N8(REG_B); SET_Z8(REG_B); - WRITE8(cpustate, d, REG_B); - CYCLES(cpustate, 3); + WRITE8(d, REG_B); + CYCLES(3); } /* STAB EXT 0xF7 */ -static void HC11OP(stab_ext)(hc11_state *cpustate) +void HC11OP(stab_ext)() { - UINT16 adr = FETCH16(cpustate); - CLEAR_NZV(cpustate); + UINT16 adr = FETCH16(); + CLEAR_NZV(); SET_N8(REG_B); SET_Z8(REG_B); - WRITE8(cpustate, adr, REG_B); - CYCLES(cpustate, 4); + WRITE8(adr, REG_B); + CYCLES(4); } /* STAB IND, X 0xE7 */ -static void HC11OP(stab_indx)(hc11_state *cpustate) +void HC11OP(stab_indx)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + CLEAR_NZV(); SET_N8(REG_B); SET_Z8(REG_B); - WRITE8(cpustate, cpustate->ix + offset, REG_B); - CYCLES(cpustate, 4); + WRITE8(m_ix + offset, REG_B); + CYCLES(4); } /* STAB IND, Y 0x18, 0xE7 */ -static void HC11OP(stab_indy)(hc11_state *cpustate) +void HC11OP(stab_indy)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); + UINT8 offset = FETCH(); + CLEAR_NZV(); SET_N8(REG_B); SET_Z8(REG_B); - WRITE8(cpustate, cpustate->iy + offset, REG_B); - CYCLES(cpustate, 5); + WRITE8(m_iy + offset, REG_B); + CYCLES(5); } /* STD DIR 0xDD */ -static void HC11OP(std_dir)(hc11_state *cpustate) +void HC11OP(std_dir)() { - UINT8 d = FETCH(cpustate); - CLEAR_NZV(cpustate); - WRITE16(cpustate, d, REG_D); + UINT8 d = FETCH(); + CLEAR_NZV(); + WRITE16(d, REG_D); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(cpustate, 4); + CYCLES(4); } /* STD EXT 0xFD */ -static void HC11OP(std_ext)(hc11_state *cpustate) +void HC11OP(std_ext)() { - UINT16 adr = FETCH16(cpustate); - CLEAR_NZV(cpustate); - WRITE16(cpustate, adr, REG_D); + UINT16 adr = FETCH16(); + CLEAR_NZV(); + WRITE16(adr, REG_D); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(cpustate, 5); + CYCLES(5); } /* STD IND, X 0xED */ -static void HC11OP(std_indx)(hc11_state *cpustate) +void HC11OP(std_indx)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - WRITE16(cpustate, cpustate->ix + offset, REG_D); + UINT8 offset = FETCH(); + CLEAR_NZV(); + WRITE16(m_ix + offset, REG_D); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(cpustate, 5); + CYCLES(5); } /* STD IND, Y 0x18, 0xED */ -static void HC11OP(std_indy)(hc11_state *cpustate) +void HC11OP(std_indy)() { - UINT8 offset = FETCH(cpustate); - CLEAR_NZV(cpustate); - WRITE16(cpustate, cpustate->iy + offset, REG_D); + UINT8 offset = FETCH(); + CLEAR_NZV(); + WRITE16(m_iy + offset, REG_D); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(cpustate, 6); + CYCLES(6); } /* STS DIR 0x9F */ -static void HC11OP(sts_dir)(hc11_state *cpustate) +void HC11OP(sts_dir)() { - UINT8 d = FETCH(cpustate); - UINT16 r = cpustate->sp; - CLEAR_NZV(cpustate); - WRITE8(cpustate, d, (r & 0xff00) >> 8); - WRITE8(cpustate, d + 1, (r & 0xff)); + UINT8 d = FETCH(); + UINT16 r = m_sp; + CLEAR_NZV(); + WRITE8(d, (r & 0xff00) >> 8); + WRITE8(d + 1, (r & 0xff)); SET_N16(r); SET_Z16(r); - CYCLES(cpustate, 4); + CYCLES(4); } /* STX DIR 0xDF */ -static void HC11OP(stx_dir)(hc11_state *cpustate) +void HC11OP(stx_dir)() { - UINT8 adr = FETCH(cpustate); - UINT16 r = cpustate->ix; - CLEAR_NZV(cpustate); - WRITE8(cpustate, adr, (r & 0xff00) >> 8); - WRITE8(cpustate, adr + 1, (r & 0xff)); + UINT8 adr = FETCH(); + UINT16 r = m_ix; + CLEAR_NZV(); + WRITE8(adr, (r & 0xff00) >> 8); + WRITE8(adr + 1, (r & 0xff)); SET_N16(r); SET_Z16(r); - CYCLES(cpustate, 4); + CYCLES(4); } /* STX EXT 0xFF */ -static void HC11OP(stx_ext)(hc11_state *cpustate) +void HC11OP(stx_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT16 r = cpustate->ix; - CLEAR_NZV(cpustate); - WRITE8(cpustate, adr, (r & 0xff00) >> 8); - WRITE8(cpustate, adr + 1, (r & 0xff)); + UINT16 adr = FETCH16(); + UINT16 r = m_ix; + CLEAR_NZV(); + WRITE8(adr, (r & 0xff00) >> 8); + WRITE8(adr + 1, (r & 0xff)); SET_N16(r); SET_Z16(r); - CYCLES(cpustate, 5); + CYCLES(5); } /* STX INDX 0xEF */ -static void HC11OP(stx_indx)(hc11_state *cpustate) +void HC11OP(stx_indx)() { - UINT16 adr = FETCH(cpustate); - UINT16 r = cpustate->ix; - CLEAR_NZV(cpustate); - WRITE8(cpustate, cpustate->ix + adr, (r & 0xff00) >> 8); - WRITE8(cpustate, cpustate->ix + adr + 1, (r & 0xff)); + UINT16 adr = FETCH(); + UINT16 r = m_ix; + CLEAR_NZV(); + WRITE8(m_ix + adr, (r & 0xff00) >> 8); + WRITE8(m_ix + adr + 1, (r & 0xff)); SET_N16(r); SET_Z16(r); - CYCLES(cpustate, 5); + CYCLES(5); } /* STX INDY 0xCD 0xEF */ -static void HC11OP(stx_indy)(hc11_state *cpustate) +void HC11OP(stx_indy)() { - UINT16 adr = FETCH(cpustate); - UINT16 r = cpustate->ix; - CLEAR_NZV(cpustate); - WRITE8(cpustate, cpustate->iy + adr, (r & 0xff00) >> 8); - WRITE8(cpustate, cpustate->iy + adr + 1, (r & 0xff)); + UINT16 adr = FETCH(); + UINT16 r = m_ix; + CLEAR_NZV(); + WRITE8(m_iy + adr, (r & 0xff00) >> 8); + WRITE8(m_iy + adr + 1, (r & 0xff)); SET_N16(r); SET_Z16(r); - CYCLES(cpustate, 6); + CYCLES(6); } /* STY DIR 0x18 0xDF */ -static void HC11OP(sty_dir)(hc11_state *cpustate) +void HC11OP(sty_dir)() { - UINT8 adr = FETCH(cpustate); - UINT16 r = cpustate->iy; - CLEAR_NZV(cpustate); - WRITE8(cpustate, adr, (r & 0xff00) >> 8); - WRITE8(cpustate, adr + 1, (r & 0xff)); + UINT8 adr = FETCH(); + UINT16 r = m_iy; + CLEAR_NZV(); + WRITE8(adr, (r & 0xff00) >> 8); + WRITE8(adr + 1, (r & 0xff)); SET_N16(r); SET_Z16(r); - CYCLES(cpustate, 5); + CYCLES(5); } /* STY EXT 0x18 0xFF */ -static void HC11OP(sty_ext)(hc11_state *cpustate) +void HC11OP(sty_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT16 r = cpustate->iy; - CLEAR_NZV(cpustate); - WRITE8(cpustate, adr, (r & 0xff00) >> 8); - WRITE8(cpustate, adr + 1, (r & 0xff)); + UINT16 adr = FETCH16(); + UINT16 r = m_iy; + CLEAR_NZV(); + WRITE8(adr, (r & 0xff00) >> 8); + WRITE8(adr + 1, (r & 0xff)); SET_N16(r); SET_Z16(r); - CYCLES(cpustate, 6); + CYCLES(6); } /* STY INDX 0x1A 0xEF */ -static void HC11OP(sty_indx)(hc11_state *cpustate) +void HC11OP(sty_indx)() { - UINT16 adr = FETCH(cpustate); - UINT16 r = cpustate->iy; - CLEAR_NZV(cpustate); - WRITE8(cpustate, cpustate->ix + adr, (r & 0xff00) >> 8); - WRITE8(cpustate, cpustate->ix + adr + 1, (r & 0xff)); + UINT16 adr = FETCH(); + UINT16 r = m_iy; + CLEAR_NZV(); + WRITE8(m_ix + adr, (r & 0xff00) >> 8); + WRITE8(m_ix + adr + 1, (r & 0xff)); SET_N16(r); SET_Z16(r); - CYCLES(cpustate, 6); + CYCLES(6); } /* STY INDY 0x18 0xEF */ -static void HC11OP(sty_indy)(hc11_state *cpustate) +void HC11OP(sty_indy)() { - UINT16 adr = FETCH(cpustate); - UINT16 r = cpustate->iy; - CLEAR_NZV(cpustate); - WRITE8(cpustate, cpustate->iy + adr, (r & 0xff00) >> 8); - WRITE8(cpustate, cpustate->iy + adr + 1, (r & 0xff)); + UINT16 adr = FETCH(); + UINT16 r = m_iy; + CLEAR_NZV(); + WRITE8(m_iy + adr, (r & 0xff00) >> 8); + WRITE8(m_iy + adr + 1, (r & 0xff)); SET_N16(r); SET_Z16(r); - CYCLES(cpustate, 6); + CYCLES(6); } /* STOP 0xCF */ -static void HC11OP(stop)(hc11_state *cpustate) +void HC11OP(stop)() { - if(cpustate->stop_state == 0 && ((cpustate->ccr & CC_S) == 0)) + if(m_stop_state == 0 && ((m_ccr & CC_S) == 0)) { - cpustate->stop_state = 1; + m_stop_state = 1; } - if(cpustate->stop_state == 1) + if(m_stop_state == 1) { - SET_PC(cpustate, cpustate->ppc); // wait for an exception + SET_PC(m_ppc); // wait for an exception } - if(cpustate->stop_state == 2) + if(m_stop_state == 2) { - cpustate->stop_state = 0; + m_stop_state = 0; } - CYCLES(cpustate, 2); + CYCLES(2); } /* SUBA IMM 0x80 */ -static void HC11OP(suba_imm)(hc11_state *cpustate) +void HC11OP(suba_imm)() { - UINT8 i = FETCH(cpustate); + UINT8 i = FETCH(); UINT16 r = REG_A - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 2); + CYCLES(2); } /* SUBA DIR 0xd0 */ -static void HC11OP(suba_dir)(hc11_state *cpustate) +void HC11OP(suba_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); + UINT8 d = FETCH(); + UINT8 i = READ8(d); UINT16 r = REG_A - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 3); + CYCLES(3); } /* SUBA EXT 0xE0 */ -static void HC11OP(suba_ext)(hc11_state *cpustate) +void HC11OP(suba_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); UINT16 r = REG_A - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* SUBA INDX 0xA0 */ -static void HC11OP(suba_indx)(hc11_state *cpustate) +void HC11OP(suba_indx)() { - UINT16 adr = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + adr); + UINT16 adr = FETCH(); + UINT8 i = READ8(m_ix + adr); UINT16 r = REG_A - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* SUBA INDY 0x18 0xA0 */ -static void HC11OP(suba_indy)(hc11_state *cpustate) +void HC11OP(suba_indy)() { - UINT16 adr = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + adr); + UINT16 adr = FETCH(); + UINT8 i = READ8(m_iy + adr); UINT16 r = REG_A - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(cpustate, 5); + CYCLES(5); } /* SUBB IMM 0xC0 */ -static void HC11OP(subb_imm)(hc11_state *cpustate) +void HC11OP(subb_imm)() { - UINT8 i = FETCH(cpustate); + UINT8 i = FETCH(); UINT16 r = REG_B - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 2); + CYCLES(2); } /* SUBB DIR 0xD0 */ -static void HC11OP(subb_dir)(hc11_state *cpustate) +void HC11OP(subb_dir)() { - UINT8 d = FETCH(cpustate); - UINT8 i = READ8(cpustate, d); + UINT8 d = FETCH(); + UINT8 i = READ8(d); UINT16 r = REG_B - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 3); + CYCLES(3); } /* SUBB EXT 0xF0 */ -static void HC11OP(subb_ext)(hc11_state *cpustate) +void HC11OP(subb_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); UINT16 r = REG_B - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* SUBB INDX 0xE0 */ -static void HC11OP(subb_indx)(hc11_state *cpustate) +void HC11OP(subb_indx)() { - UINT16 adr = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + adr); + UINT16 adr = FETCH(); + UINT8 i = READ8(m_ix + adr); UINT16 r = REG_B - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* SUBB INDY 0x18 0xE0 */ -static void HC11OP(subb_indy)(hc11_state *cpustate) +void HC11OP(subb_indy)() { - UINT16 adr = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + adr); + UINT16 adr = FETCH(); + UINT8 i = READ8(m_iy + adr); UINT16 r = REG_B - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(cpustate, 5); + CYCLES(5); } /* SUBD IMM 0x83 */ -static void HC11OP(subd_imm)(hc11_state *cpustate) +void HC11OP(subd_imm)() { - UINT16 i = FETCH16(cpustate); + UINT16 i = FETCH16(); UINT32 r = REG_D - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(cpustate, 4); + CYCLES(4); } /* SUBD DIR 0x93 */ -static void HC11OP(subd_dir)(hc11_state *cpustate) +void HC11OP(subd_dir)() { - UINT8 d = FETCH(cpustate); - UINT16 i = READ16(cpustate, d); + UINT8 d = FETCH(); + UINT16 i = READ16(d); UINT32 r = REG_D - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(cpustate, 5); + CYCLES(5); } /* SUBD EXT 0xB3 */ -static void HC11OP(subd_ext)(hc11_state *cpustate) +void HC11OP(subd_ext)() { - UINT16 addr = FETCH16(cpustate); - UINT16 i = READ16(cpustate, addr); + UINT16 addr = FETCH16(); + UINT16 i = READ16(addr); UINT32 r = REG_D - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(cpustate, 6); + CYCLES(6); } /* SUBD INDX 0xA3 */ -static void HC11OP(subd_indx)(hc11_state *cpustate) +void HC11OP(subd_indx)() { - UINT8 offset = FETCH(cpustate); - UINT16 i = READ16(cpustate, cpustate->ix + offset); + UINT8 offset = FETCH(); + UINT16 i = READ16(m_ix + offset); UINT32 r = REG_D - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(cpustate, 6); + CYCLES(6); } /* SUBD INDY 0x18 0xA3 */ -static void HC11OP(subd_indy)(hc11_state *cpustate) +void HC11OP(subd_indy)() { - UINT8 offset = FETCH(cpustate); - UINT16 i = READ16(cpustate, cpustate->iy + offset); + UINT8 offset = FETCH(); + UINT16 i = READ16(m_iy + offset); UINT32 r = REG_D - i; - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(cpustate, 7); + CYCLES(7); } /* SWI 0x3F */ -static void HC11OP(swi)(hc11_state *cpustate) +void HC11OP(swi)() { UINT16 pc_vector; - //cpustate->pc++; - PUSH16(cpustate, cpustate->pc); - PUSH16(cpustate, cpustate->iy); - PUSH16(cpustate, cpustate->ix); - PUSH8(cpustate, REG_A); - PUSH8(cpustate, REG_B); - PUSH8(cpustate, cpustate->ccr); - pc_vector = READ16(cpustate, 0xfff6); - SET_PC(cpustate, pc_vector); - cpustate->ccr |= CC_I; //irq taken, mask the flag - CYCLES(cpustate, 14); + //m_pc++; + PUSH16(m_pc); + PUSH16(m_iy); + PUSH16(m_ix); + PUSH8(REG_A); + PUSH8(REG_B); + PUSH8(m_ccr); + pc_vector = READ16(0xfff6); + SET_PC(pc_vector); + m_ccr |= CC_I; //irq taken, mask the flag + CYCLES(14); } /* TAB 0x16 */ -static void HC11OP(tab)(hc11_state *cpustate) +void HC11OP(tab)() { - CLEAR_NZV(cpustate); + CLEAR_NZV(); REG_B = REG_A; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 2); + CYCLES(2); } /* TAP 0x06 */ -static void HC11OP(tap)(hc11_state *cpustate) +void HC11OP(tap)() { - UINT8 x_flag = cpustate->ccr & CC_X; - cpustate->ccr = REG_A; - if(x_flag == 0 && cpustate->ccr & CC_X) //X flag cannot do a 0->1 transition with this instruction. - cpustate->ccr &= ~CC_X; + UINT8 x_flag = m_ccr & CC_X; + m_ccr = REG_A; + if(x_flag == 0 && m_ccr & CC_X) //X flag cannot do a 0->1 transition with this instruction. + m_ccr &= ~CC_X; - CYCLES(cpustate, 2); + CYCLES(2); } /* TBA 0x17 */ -static void HC11OP(tba)(hc11_state *cpustate) +void HC11OP(tba)() { - CLEAR_NZV(cpustate); + CLEAR_NZV(); REG_A = REG_B; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 2); + CYCLES(2); } /* TEST 0x00 */ -static void HC11OP(test)(hc11_state *cpustate) +void HC11OP(test)() { -// if(cpustate->test_mode) - SET_PC(cpustate, cpustate->ppc); // Note: docs says "incremented" but the behaviour makes me think that's actually "decremented". +// if(m_test_mode) + SET_PC(m_ppc); // Note: docs says "incremented" but the behaviour makes me think that's actually "decremented". // else // { // TODO: execute an illegal opcode exception here (NMI) // } - CYCLES(cpustate, 1); + CYCLES(1); } /* TPA 0x07 */ -static void HC11OP(tpa)(hc11_state *cpustate) +void HC11OP(tpa)() { - REG_A = cpustate->ccr; - CYCLES(cpustate, 2); + REG_A = m_ccr; + CYCLES(2); } /* TSTA 0x4D */ -static void HC11OP(tsta)(hc11_state *cpustate) +void HC11OP(tsta)() { - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(cpustate, 2); + CYCLES(2); } /* TSTB 0x5D */ -static void HC11OP(tstb)(hc11_state *cpustate) +void HC11OP(tstb)() { - CLEAR_NZVC(cpustate); + CLEAR_NZVC(); SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(cpustate, 2); + CYCLES(2); } /* TST EXT 0x7D */ -static void HC11OP(tst_ext)(hc11_state *cpustate) +void HC11OP(tst_ext)() { - UINT16 adr = FETCH16(cpustate); - UINT8 i = READ8(cpustate, adr); - CLEAR_NZVC(cpustate); + UINT16 adr = FETCH16(); + UINT8 i = READ8(adr); + CLEAR_NZVC(); SET_N8(i); SET_Z8(i); - CYCLES(cpustate, 6); + CYCLES(6); } /* TST IND, X 0x6D */ -static void HC11OP(tst_indx)(hc11_state *cpustate) +void HC11OP(tst_indx)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->ix + offset); - CLEAR_NZVC(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_ix + offset); + CLEAR_NZVC(); SET_N8(i); SET_Z8(i); - CYCLES(cpustate, 6); + CYCLES(6); } /* TST IND, Y 0x18, 0x6D */ -static void HC11OP(tst_indy)(hc11_state *cpustate) +void HC11OP(tst_indy)() { - UINT8 offset = FETCH(cpustate); - UINT8 i = READ8(cpustate, cpustate->iy + offset); - CLEAR_NZVC(cpustate); + UINT8 offset = FETCH(); + UINT8 i = READ8(m_iy + offset); + CLEAR_NZVC(); SET_N8(i); SET_Z8(i); - CYCLES(cpustate, 6); + CYCLES(6); } /* TSX 0x30 */ -static void HC11OP(tsx)(hc11_state *cpustate) +void HC11OP(tsx)() { - cpustate->ix = cpustate->sp + 1; - CYCLES(cpustate, 3); + m_ix = m_sp + 1; + CYCLES(3); } /* TSY 0x18 0x30 */ -static void HC11OP(tsy)(hc11_state *cpustate) +void HC11OP(tsy)() { - cpustate->iy = cpustate->sp + 1; - CYCLES(cpustate, 4); + m_iy = m_sp + 1; + CYCLES(4); } /* TXS 0x35 */ -static void HC11OP(txs)(hc11_state *cpustate) +void HC11OP(txs)() { - cpustate->sp = cpustate->ix - 1; - CYCLES(cpustate, 3); + m_sp = m_ix - 1; + CYCLES(3); } /* TYS 0x18 0x35 */ -static void HC11OP(tys)(hc11_state *cpustate) +void HC11OP(tys)() { - cpustate->sp = cpustate->iy - 1; - CYCLES(cpustate, 4); + m_sp = m_iy - 1; + CYCLES(4); } /* WAI 0x3E */ -static void HC11OP(wai)(hc11_state *cpustate) +void HC11OP(wai)() { - if(cpustate->wait_state == 0) + if(m_wait_state == 0) { /* TODO: the following is bogus, pushes regs HERE in an instruction that wants an irq to go out? */ - PUSH16(cpustate, cpustate->pc); - PUSH16(cpustate, cpustate->iy); - PUSH16(cpustate, cpustate->ix); - PUSH8(cpustate, REG_A); - PUSH8(cpustate, REG_B); - PUSH8(cpustate, cpustate->ccr); - CYCLES(cpustate, 14); - cpustate->wait_state = 1; + PUSH16(m_pc); + PUSH16(m_iy); + PUSH16(m_ix); + PUSH8(REG_A); + PUSH8(REG_B); + PUSH8(m_ccr); + CYCLES(14); + m_wait_state = 1; } - if(cpustate->wait_state == 1) + if(m_wait_state == 1) { - SET_PC(cpustate, cpustate->ppc); // wait for an exception - CYCLES(cpustate, 1); + SET_PC(m_ppc); // wait for an exception + CYCLES(1); } - if(cpustate->wait_state == 2) + if(m_wait_state == 2) { - cpustate->wait_state = 0; - CYCLES(cpustate, 1); + m_wait_state = 0; + CYCLES(1); } } /* XGDX 0x8F */ -static void HC11OP(xgdx)(hc11_state *cpustate) +void HC11OP(xgdx)() { UINT16 tmp = REG_D; - REG_D = cpustate->ix; - cpustate->ix = tmp; - CYCLES(cpustate, 3); + REG_D = m_ix; + m_ix = tmp; + CYCLES(3); } /* XGDY 0x18, 0x8F */ -static void HC11OP(xgdy)(hc11_state *cpustate) +void HC11OP(xgdy)() { UINT16 tmp = REG_D; - REG_D = cpustate->iy; - cpustate->iy = tmp; - CYCLES(cpustate, 4); + REG_D = m_iy; + m_iy = tmp; + CYCLES(4); } /*****************************************************************************/ -static void HC11OP(page2)(hc11_state *cpustate) +void HC11OP(page2)() { - UINT8 op2 = FETCH(cpustate); - hc11_optable_page2[op2](cpustate); + UINT8 op2 = FETCH(); + (this->*hc11_optable_page2[op2])(); } -static void HC11OP(page3)(hc11_state *cpustate) +void HC11OP(page3)() { - UINT8 op2 = FETCH(cpustate); - hc11_optable_page3[op2](cpustate); + UINT8 op2 = FETCH(); + (this->*hc11_optable_page3[op2])(); } -static void HC11OP(page4)(hc11_state *cpustate) +void HC11OP(page4)() { - UINT8 op2 = FETCH(cpustate); - hc11_optable_page4[op2](cpustate); + UINT8 op2 = FETCH(); + (this->*hc11_optable_page4[op2])(); } -static void HC11OP(invalid)(hc11_state *cpustate) +void HC11OP(invalid)() { - fatalerror("HC11: Invalid opcode 0x%02X at %04X\n", READ8(cpustate, cpustate->pc-1), cpustate->pc-1); + fatalerror("HC11: Invalid opcode 0x%02X at %04X\n", READ8(m_pc-1), m_pc-1); } diff --git a/src/emu/cpu/mc68hc11/hc11ops.h b/src/emu/cpu/mc68hc11/hc11ops.h index e814314f189..f2ea9d35a31 100644 --- a/src/emu/cpu/mc68hc11/hc11ops.h +++ b/src/emu/cpu/mc68hc11/hc11ops.h @@ -1,323 +1,317 @@ -struct hc11_opcode_list_struct -{ - int page; - int opcode; - void (*handler)(hc11_state *cpustate); -}; -static const hc11_opcode_list_struct hc11_opcode_list[] = +const mc68hc11_cpu_device::hc11_opcode_list_struct mc68hc11_cpu_device::hc11_opcode_list[] = { /* page opcode handler */ - { 0, 0x1b, HC11OP(aba) }, - { 0, 0x3a, HC11OP(abx) }, - { 0x18, 0x3a, HC11OP(aby) }, - { 0, 0x89, HC11OP(adca_imm) }, - { 0, 0x99, HC11OP(adca_dir) }, - { 0, 0xb9, HC11OP(adca_ext) }, - { 0, 0xa9, HC11OP(adca_indx) }, - { 0x18, 0xa9, HC11OP(adca_indy) }, - { 0, 0xc9, HC11OP(adcb_imm) }, - { 0, 0xd9, HC11OP(adcb_dir) }, - { 0, 0xf9, HC11OP(adcb_ext) }, - { 0, 0xe9, HC11OP(adcb_indx) }, - { 0x18, 0xe9, HC11OP(adcb_indy) }, - { 0, 0x8b, HC11OP(adda_imm) }, - { 0, 0x9b, HC11OP(adda_dir) }, - { 0, 0xbb, HC11OP(adda_ext) }, - { 0, 0xab, HC11OP(adda_indx) }, - { 0x18, 0xab, HC11OP(adda_indy) }, - { 0, 0xcb, HC11OP(addb_imm) }, - { 0, 0xdb, HC11OP(addb_dir) }, - { 0, 0xfb, HC11OP(addb_ext) }, - { 0, 0xeb, HC11OP(addb_indx) }, - { 0x18, 0xeb, HC11OP(addb_indy) }, - { 0, 0xc3, HC11OP(addd_imm) }, - { 0, 0xd3, HC11OP(addd_dir) }, - { 0, 0xf3, HC11OP(addd_ext) }, - { 0, 0xe3, HC11OP(addd_indx) }, - { 0x18, 0xe3, HC11OP(addd_indy) }, - { 0, 0x84, HC11OP(anda_imm) }, - { 0, 0x94, HC11OP(anda_dir) }, - { 0, 0xb4, HC11OP(anda_ext) }, - { 0, 0xa4, HC11OP(anda_indx) }, - { 0x18, 0xa4, HC11OP(anda_indy) }, - { 0, 0xc4, HC11OP(andb_imm) }, - { 0, 0xd4, HC11OP(andb_dir) }, - { 0, 0xf4, HC11OP(andb_ext) }, - { 0, 0xe4, HC11OP(andb_indx) }, - { 0x18, 0xe4, HC11OP(andb_indy) }, - { 0, 0x48, HC11OP(asla) }, - { 0, 0x58, HC11OP(aslb) }, - { 0, 0x78, HC11OP(asl_ext) }, -// { 0, 0x68, HC11OP(asl_indx) }, -// { 0x18, 0x68, HC11OP(asl_indy) }, -// { 0, 0x47, HC11OP(asra) }, -// { 0, 0x57, HC11OP(asrb) }, -// { 0, 0x77, HC11OP(asr_ext) }, -// { 0, 0x67, HC11OP(asr_indx) }, -// { 0x18, 0x67, HC11OP(asr_indy) }, - { 0, 0x24, HC11OP(bcc) }, - { 0, 0x15, HC11OP(bclr_dir) }, - { 0, 0x1d, HC11OP(bclr_indx) }, -// { 0x18, 0x1d, HC11OP(bclr_indy) }, - { 0, 0x25, HC11OP(bcs) }, - { 0, 0x27, HC11OP(beq) }, -// { 0, 0x2c, HC11OP(bge) }, -// { 0, 0x2e, HC11OP(bgt) }, - { 0, 0x22, HC11OP(bhi) }, - { 0, 0x85, HC11OP(bita_imm) }, - { 0, 0x95, HC11OP(bita_dir) }, - { 0, 0xb5, HC11OP(bita_ext) }, - { 0, 0xa5, HC11OP(bita_indx) }, - { 0x18, 0xa5, HC11OP(bita_indy) }, - { 0, 0xc5, HC11OP(bitb_imm) }, - { 0, 0xd5, HC11OP(bitb_dir) }, - { 0, 0xf5, HC11OP(bitb_ext) }, - { 0, 0xe5, HC11OP(bitb_indx) }, - { 0x18, 0xe5, HC11OP(bitb_indy) }, - { 0, 0x2f, HC11OP(ble) }, - { 0, 0x23, HC11OP(bls) }, -// { 0, 0x2d, HC11OP(blt) }, - { 0, 0x2b, HC11OP(bmi) }, - { 0, 0x26, HC11OP(bne) }, - { 0, 0x2a, HC11OP(bpl) }, - { 0, 0x20, HC11OP(bra) }, - { 0, 0x13, HC11OP(brclr_dir) }, - { 0, 0x1f, HC11OP(brclr_indx) }, -// { 0x18, 0x1f, HC11OP(brclr_indy) }, - { 0, 0x21, HC11OP(brn) }, - { 0, 0x12, HC11OP(brset_dir) }, - { 0, 0x1e, HC11OP(brset_indx) }, -// { 0x18, 0x1e, HC11OP(brset_indy) }, - { 0, 0x14, HC11OP(bset_dir) }, - { 0, 0x1c, HC11OP(bset_indx) }, -// { 0x18, 0x1c, HC11OP(bset_indy) }, - { 0, 0x8d, HC11OP(bsr) }, - { 0, 0x28, HC11OP(bvc) }, - { 0, 0x29, HC11OP(bvs) }, - { 0, 0x11, HC11OP(cba) }, - { 0, 0x0c, HC11OP(clc) }, - { 0, 0x0e, HC11OP(cli) }, - { 0, 0x4f, HC11OP(clra) }, - { 0, 0x5f, HC11OP(clrb) }, - { 0, 0x7f, HC11OP(clr_ext) }, - { 0, 0x6f, HC11OP(clr_indx) }, - { 0x18, 0x6f, HC11OP(clr_indy) }, - { 0, 0x0a, HC11OP(clv) }, - { 0, 0x81, HC11OP(cmpa_imm) }, - { 0, 0x91, HC11OP(cmpa_dir) }, - { 0, 0xb1, HC11OP(cmpa_ext) }, - { 0, 0xa1, HC11OP(cmpa_indx) }, - { 0x18, 0xa1, HC11OP(cmpa_indy) }, - { 0, 0xc1, HC11OP(cmpb_imm) }, - { 0, 0xd1, HC11OP(cmpb_dir) }, - { 0, 0xf1, HC11OP(cmpb_ext) }, - { 0, 0xe1, HC11OP(cmpb_indx) }, - { 0x18, 0xe1, HC11OP(cmpb_indy) }, - { 0, 0x43, HC11OP(coma) }, - { 0, 0x53, HC11OP(comb) }, -// { 0, 0x73, HC11OP(com_ext) }, -// { 0, 0x63, HC11OP(com_indx) }, -// { 0x18, 0x63, HC11OP(com_indy) }, - { 0x1a, 0x83, HC11OP(cpd_imm) }, - { 0x1a, 0x93, HC11OP(cpd_dir) }, - { 0x1a, 0xb3, HC11OP(cpd_ext) }, - { 0x1a, 0xa3, HC11OP(cpd_indx) }, - { 0xcd, 0xa3, HC11OP(cpd_indy) }, - { 0, 0x8c, HC11OP(cpx_imm) }, - { 0, 0x9c, HC11OP(cpx_dir) }, - { 0, 0xbc, HC11OP(cpx_ext) }, - { 0, 0xac, HC11OP(cpx_indx) }, - { 0xcd, 0xac, HC11OP(cpx_indy) }, - { 0x18, 0x8c, HC11OP(cpy_imm) }, - { 0x18, 0x9c, HC11OP(cpy_dir) }, - { 0x18, 0xbc, HC11OP(cpy_ext) }, - { 0x1a, 0xac, HC11OP(cpy_indx) }, - { 0x18, 0xac, HC11OP(cpy_indy) }, -// { 0, 0x19, HC11OP(daa) }, - { 0, 0x4a, HC11OP(deca) }, - { 0, 0x5a, HC11OP(decb) }, - { 0, 0x7a, HC11OP(dec_ext) }, - { 0, 0x6a, HC11OP(dec_indx) }, - { 0x18, 0x6a, HC11OP(dec_indy) }, -// { 0, 0x34, HC11OP(des) }, - { 0, 0x09, HC11OP(dex) }, - { 0x18, 0x09, HC11OP(dey) }, - { 0, 0x88, HC11OP(eora_imm) }, - { 0, 0x98, HC11OP(eora_dir) }, - { 0, 0xb8, HC11OP(eora_ext) }, - { 0, 0xa8, HC11OP(eora_indx) }, - { 0x18, 0xa8, HC11OP(eora_indy) }, - { 0, 0xc8, HC11OP(eorb_imm) }, - { 0, 0xd8, HC11OP(eorb_dir) }, - { 0, 0xf8, HC11OP(eorb_ext) }, - { 0, 0xe8, HC11OP(eorb_indx) }, - { 0x18, 0xe8, HC11OP(eorb_indy) }, -// { 0, 0x03, HC11OP(fdiv) }, - { 0, 0x02, HC11OP(idiv) }, - { 0, 0x4c, HC11OP(inca) }, - { 0, 0x5c, HC11OP(incb) }, - { 0, 0x7c, HC11OP(inc_ext) }, - { 0, 0x6c, HC11OP(inc_indx) }, - { 0x18, 0x6c, HC11OP(inc_indy) }, -// { 0, 0x31, HC11OP(ins) }, - { 0, 0x08, HC11OP(inx) }, - { 0x18, 0x08, HC11OP(iny) }, - { 0, 0x7e, HC11OP(jmp_ext) }, - { 0, 0x6e, HC11OP(jmp_indx) }, - { 0x18, 0x6e, HC11OP(jmp_indy) }, - { 0, 0x9d, HC11OP(jsr_dir) }, - { 0, 0xbd, HC11OP(jsr_ext) }, - { 0, 0xad, HC11OP(jsr_indx) }, - { 0x18, 0xad, HC11OP(jsr_indy) }, - { 0, 0x86, HC11OP(ldaa_imm) }, - { 0, 0x96, HC11OP(ldaa_dir) }, - { 0, 0xb6, HC11OP(ldaa_ext) }, - { 0, 0xa6, HC11OP(ldaa_indx) }, - { 0x18, 0xa6, HC11OP(ldaa_indy) }, - { 0, 0xc6, HC11OP(ldab_imm) }, - { 0, 0xd6, HC11OP(ldab_dir) }, - { 0, 0xf6, HC11OP(ldab_ext) }, - { 0, 0xe6, HC11OP(ldab_indx) }, - { 0x18, 0xe6, HC11OP(ldab_indy) }, - { 0, 0xcc, HC11OP(ldd_imm) }, - { 0, 0xdc, HC11OP(ldd_dir) }, - { 0, 0xfc, HC11OP(ldd_ext) }, - { 0, 0xec, HC11OP(ldd_indx) }, - { 0x18, 0xec, HC11OP(ldd_indy) }, - { 0, 0x8e, HC11OP(lds_imm) }, - { 0, 0x9e, HC11OP(lds_dir) }, - { 0, 0xbe, HC11OP(lds_ext) }, - { 0, 0xae, HC11OP(lds_indx) }, - { 0x18, 0xae, HC11OP(lds_indy) }, - { 0, 0xce, HC11OP(ldx_imm) }, - { 0, 0xde, HC11OP(ldx_dir) }, - { 0, 0xfe, HC11OP(ldx_ext) }, - { 0, 0xee, HC11OP(ldx_indx) }, - { 0xcd, 0xee, HC11OP(ldx_indy) }, - { 0x18, 0xce, HC11OP(ldy_imm) }, - { 0x18, 0xde, HC11OP(ldy_dir) }, - { 0x18, 0xfe, HC11OP(ldy_ext) }, - { 0x1a, 0xee, HC11OP(ldy_indx) }, - { 0x18, 0xee, HC11OP(ldy_indy) }, - { 0, 0x05, HC11OP(lsld) }, - { 0, 0x44, HC11OP(lsra) }, - { 0, 0x54, HC11OP(lsrb) }, -// { 0, 0x74, HC11OP(lsr_ext) }, -// { 0, 0x64, HC11OP(lsr_indx) }, -// { 0x18, 0x64, HC11OP(lsr_indy) }, - { 0, 0x04, HC11OP(lsrd) }, - { 0, 0x3d, HC11OP(mul) }, - { 0, 0x40, HC11OP(nega) }, - { 0, 0x50, HC11OP(negb) }, - { 0, 0x70, HC11OP(neg_ext) }, - { 0, 0x60, HC11OP(neg_indx) }, - { 0x18, 0x60, HC11OP(neg_indy) }, - { 0, 0x01, HC11OP(nop) }, - { 0, 0x8a, HC11OP(oraa_imm) }, - { 0, 0x9a, HC11OP(oraa_dir) }, - { 0, 0xba, HC11OP(oraa_ext) }, - { 0, 0xaa, HC11OP(oraa_indx) }, - { 0x18, 0xaa, HC11OP(oraa_indy) }, - { 0, 0xca, HC11OP(orab_imm) }, - { 0, 0xda, HC11OP(orab_dir) }, - { 0, 0xfa, HC11OP(orab_ext) }, - { 0, 0xea, HC11OP(orab_indx) }, - { 0x18, 0xea, HC11OP(orab_indy) }, - { 0, 0x36, HC11OP(psha) }, - { 0, 0x37, HC11OP(pshb) }, - { 0, 0x3c, HC11OP(pshx) }, - { 0x18, 0x3c, HC11OP(pshy) }, - { 0, 0x32, HC11OP(pula) }, - { 0, 0x33, HC11OP(pulb) }, - { 0, 0x38, HC11OP(pulx) }, - { 0x18, 0x38, HC11OP(puly) }, - { 0, 0x49, HC11OP(rola) }, - { 0, 0x59, HC11OP(rolb) }, - { 0, 0x79, HC11OP(rol_ext) }, - { 0, 0x69, HC11OP(rol_indx) }, - { 0x18, 0x69, HC11OP(rol_indy) }, - { 0, 0x46, HC11OP(rora) }, - { 0, 0x56, HC11OP(rorb) }, -// { 0, 0x76, HC11OP(ror_ext) }, -// { 0, 0x66, HC11OP(ror_indx) }, -// { 0x18, 0x66, HC11OP(ror_indy) }, - { 0, 0x3b, HC11OP(rti) }, - { 0, 0x39, HC11OP(rts) }, - { 0, 0x10, HC11OP(sba) }, - { 0, 0x82, HC11OP(sbca_imm) }, -// { 0, 0x92, HC11OP(sbca_dir) }, -// { 0, 0xb2, HC11OP(sbca_ext) }, - { 0, 0xa2, HC11OP(sbca_indx) }, - { 0x18, 0xa2, HC11OP(sbca_indy) }, - { 0, 0xc2, HC11OP(sbcb_imm) }, -// { 0, 0xd2, HC11OP(sbcb_dir) }, -// { 0, 0xf2, HC11OP(sbcb_ext) }, - { 0, 0xe2, HC11OP(sbcb_indx) }, - { 0x18, 0xe2, HC11OP(sbcb_indy) }, - { 0, 0x0d, HC11OP(sec) }, - { 0, 0x0f, HC11OP(sei) }, - { 0, 0x0b, HC11OP(sev) }, - { 0, 0x97, HC11OP(staa_dir) }, - { 0, 0xb7, HC11OP(staa_ext) }, - { 0, 0xa7, HC11OP(staa_indx) }, - { 0x18, 0xa7, HC11OP(staa_indy) }, - { 0, 0xd7, HC11OP(stab_dir) }, - { 0, 0xf7, HC11OP(stab_ext) }, - { 0, 0xe7, HC11OP(stab_indx) }, - { 0x18, 0xe7, HC11OP(stab_indy) }, - { 0, 0xdd, HC11OP(std_dir) }, - { 0, 0xfd, HC11OP(std_ext) }, - { 0, 0xed, HC11OP(std_indx) }, - { 0x18, 0xed, HC11OP(std_indy) }, - { 0, 0x9f, HC11OP(sts_dir) }, -// { 0, 0xbf, HC11OP(sts_ext) }, -// { 0, 0xaf, HC11OP(sts_indx) }, -// { 0x18, 0xaf, HC11OP(sts_indy) }, - { 0, 0xdf, HC11OP(stx_dir) }, - { 0, 0xff, HC11OP(stx_ext) }, - { 0, 0xef, HC11OP(stx_indx) }, - { 0xcd, 0xef, HC11OP(stx_indy) }, - { 0x18, 0xdf, HC11OP(sty_dir) }, - { 0x18, 0xff, HC11OP(sty_ext) }, - { 0x1a, 0xef, HC11OP(sty_indx) }, - { 0x18, 0xef, HC11OP(sty_indy) }, - { 0, 0xcf, HC11OP(stop) }, - { 0, 0x80, HC11OP(suba_imm) }, - { 0, 0x90, HC11OP(suba_dir) }, - { 0, 0xb0, HC11OP(suba_ext) }, - { 0, 0xa0, HC11OP(suba_indx) }, - { 0x18, 0xa0, HC11OP(suba_indy) }, - { 0, 0xc0, HC11OP(subb_imm) }, - { 0, 0xd0, HC11OP(subb_dir) }, - { 0, 0xf0, HC11OP(subb_ext) }, - { 0, 0xe0, HC11OP(subb_indx) }, - { 0x18, 0xe0, HC11OP(subb_indy) }, - { 0, 0x83, HC11OP(subd_imm) }, - { 0, 0x93, HC11OP(subd_dir) }, - { 0, 0xb3, HC11OP(subd_ext) }, - { 0, 0xa3, HC11OP(subd_indx) }, - { 0x18, 0xa3, HC11OP(subd_indy) }, - { 0, 0x3f, HC11OP(swi) }, - { 0, 0x16, HC11OP(tab) }, - { 0, 0x06, HC11OP(tap) }, - { 0, 0x17, HC11OP(tba) }, - { 0, 0x00, HC11OP(test) }, - { 0, 0x07, HC11OP(tpa) }, - { 0, 0x4d, HC11OP(tsta) }, - { 0, 0x5d, HC11OP(tstb) }, - { 0, 0x7d, HC11OP(tst_ext) }, - { 0, 0x6d, HC11OP(tst_indx) }, - { 0x18, 0x6d, HC11OP(tst_indy) }, - { 0, 0x30, HC11OP(tsx) }, - { 0x18, 0x30, HC11OP(tsy) }, - { 0, 0x35, HC11OP(txs) }, - { 0x18, 0x35, HC11OP(tys) }, - { 0, 0x3e, HC11OP(wai) }, - { 0, 0x8f, HC11OP(xgdx) }, - { 0x18, 0x8f, HC11OP(xgdy) }, + { 0, 0x1b, &HC11OP(aba) }, + { 0, 0x3a, &HC11OP(abx) }, + { 0x18, 0x3a, &HC11OP(aby) }, + { 0, 0x89, &HC11OP(adca_imm) }, + { 0, 0x99, &HC11OP(adca_dir) }, + { 0, 0xb9, &HC11OP(adca_ext) }, + { 0, 0xa9, &HC11OP(adca_indx) }, + { 0x18, 0xa9, &HC11OP(adca_indy) }, + { 0, 0xc9, &HC11OP(adcb_imm) }, + { 0, 0xd9, &HC11OP(adcb_dir) }, + { 0, 0xf9, &HC11OP(adcb_ext) }, + { 0, 0xe9, &HC11OP(adcb_indx) }, + { 0x18, 0xe9, &HC11OP(adcb_indy) }, + { 0, 0x8b, &HC11OP(adda_imm) }, + { 0, 0x9b, &HC11OP(adda_dir) }, + { 0, 0xbb, &HC11OP(adda_ext) }, + { 0, 0xab, &HC11OP(adda_indx) }, + { 0x18, 0xab, &HC11OP(adda_indy) }, + { 0, 0xcb, &HC11OP(addb_imm) }, + { 0, 0xdb, &HC11OP(addb_dir) }, + { 0, 0xfb, &HC11OP(addb_ext) }, + { 0, 0xeb, &HC11OP(addb_indx) }, + { 0x18, 0xeb, &HC11OP(addb_indy) }, + { 0, 0xc3, &HC11OP(addd_imm) }, + { 0, 0xd3, &HC11OP(addd_dir) }, + { 0, 0xf3, &HC11OP(addd_ext) }, + { 0, 0xe3, &HC11OP(addd_indx) }, + { 0x18, 0xe3, &HC11OP(addd_indy) }, + { 0, 0x84, &HC11OP(anda_imm) }, + { 0, 0x94, &HC11OP(anda_dir) }, + { 0, 0xb4, &HC11OP(anda_ext) }, + { 0, 0xa4, &HC11OP(anda_indx) }, + { 0x18, 0xa4, &HC11OP(anda_indy) }, + { 0, 0xc4, &HC11OP(andb_imm) }, + { 0, 0xd4, &HC11OP(andb_dir) }, + { 0, 0xf4, &HC11OP(andb_ext) }, + { 0, 0xe4, &HC11OP(andb_indx) }, + { 0x18, 0xe4, &HC11OP(andb_indy) }, + { 0, 0x48, &HC11OP(asla) }, + { 0, 0x58, &HC11OP(aslb) }, + { 0, 0x78, &HC11OP(asl_ext) }, +// { 0, 0x68, &HC11OP(asl_indx) }, +// { 0x18, 0x68, &HC11OP(asl_indy) }, +// { 0, 0x47, &HC11OP(asra) }, +// { 0, 0x57, &HC11OP(asrb) }, +// { 0, 0x77, &HC11OP(asr_ext) }, +// { 0, 0x67, &HC11OP(asr_indx) }, +// { 0x18, 0x67, &HC11OP(asr_indy) }, + { 0, 0x24, &HC11OP(bcc) }, + { 0, 0x15, &HC11OP(bclr_dir) }, + { 0, 0x1d, &HC11OP(bclr_indx) }, +// { 0x18, 0x1d, &HC11OP(bclr_indy) }, + { 0, 0x25, &HC11OP(bcs) }, + { 0, 0x27, &HC11OP(beq) }, +// { 0, 0x2c, &HC11OP(bge) }, +// { 0, 0x2e, &HC11OP(bgt) }, + { 0, 0x22, &HC11OP(bhi) }, + { 0, 0x85, &HC11OP(bita_imm) }, + { 0, 0x95, &HC11OP(bita_dir) }, + { 0, 0xb5, &HC11OP(bita_ext) }, + { 0, 0xa5, &HC11OP(bita_indx) }, + { 0x18, 0xa5, &HC11OP(bita_indy) }, + { 0, 0xc5, &HC11OP(bitb_imm) }, + { 0, 0xd5, &HC11OP(bitb_dir) }, + { 0, 0xf5, &HC11OP(bitb_ext) }, + { 0, 0xe5, &HC11OP(bitb_indx) }, + { 0x18, 0xe5, &HC11OP(bitb_indy) }, + { 0, 0x2f, &HC11OP(ble) }, + { 0, 0x23, &HC11OP(bls) }, +// { 0, 0x2d, &HC11OP(blt) }, + { 0, 0x2b, &HC11OP(bmi) }, + { 0, 0x26, &HC11OP(bne) }, + { 0, 0x2a, &HC11OP(bpl) }, + { 0, 0x20, &HC11OP(bra) }, + { 0, 0x13, &HC11OP(brclr_dir) }, + { 0, 0x1f, &HC11OP(brclr_indx) }, +// { 0x18, 0x1f, &HC11OP(brclr_indy) }, + { 0, 0x21, &HC11OP(brn) }, + { 0, 0x12, &HC11OP(brset_dir) }, + { 0, 0x1e, &HC11OP(brset_indx) }, +// { 0x18, 0x1e, &HC11OP(brset_indy) }, + { 0, 0x14, &HC11OP(bset_dir) }, + { 0, 0x1c, &HC11OP(bset_indx) }, +// { 0x18, 0x1c, &HC11OP(bset_indy) }, + { 0, 0x8d, &HC11OP(bsr) }, + { 0, 0x28, &HC11OP(bvc) }, + { 0, 0x29, &HC11OP(bvs) }, + { 0, 0x11, &HC11OP(cba) }, + { 0, 0x0c, &HC11OP(clc) }, + { 0, 0x0e, &HC11OP(cli) }, + { 0, 0x4f, &HC11OP(clra) }, + { 0, 0x5f, &HC11OP(clrb) }, + { 0, 0x7f, &HC11OP(clr_ext) }, + { 0, 0x6f, &HC11OP(clr_indx) }, + { 0x18, 0x6f, &HC11OP(clr_indy) }, + { 0, 0x0a, &HC11OP(clv) }, + { 0, 0x81, &HC11OP(cmpa_imm) }, + { 0, 0x91, &HC11OP(cmpa_dir) }, + { 0, 0xb1, &HC11OP(cmpa_ext) }, + { 0, 0xa1, &HC11OP(cmpa_indx) }, + { 0x18, 0xa1, &HC11OP(cmpa_indy) }, + { 0, 0xc1, &HC11OP(cmpb_imm) }, + { 0, 0xd1, &HC11OP(cmpb_dir) }, + { 0, 0xf1, &HC11OP(cmpb_ext) }, + { 0, 0xe1, &HC11OP(cmpb_indx) }, + { 0x18, 0xe1, &HC11OP(cmpb_indy) }, + { 0, 0x43, &HC11OP(coma) }, + { 0, 0x53, &HC11OP(comb) }, +// { 0, 0x73, &HC11OP(com_ext) }, +// { 0, 0x63, &HC11OP(com_indx) }, +// { 0x18, 0x63, &HC11OP(com_indy) }, + { 0x1a, 0x83, &HC11OP(cpd_imm) }, + { 0x1a, 0x93, &HC11OP(cpd_dir) }, + { 0x1a, 0xb3, &HC11OP(cpd_ext) }, + { 0x1a, 0xa3, &HC11OP(cpd_indx) }, + { 0xcd, 0xa3, &HC11OP(cpd_indy) }, + { 0, 0x8c, &HC11OP(cpx_imm) }, + { 0, 0x9c, &HC11OP(cpx_dir) }, + { 0, 0xbc, &HC11OP(cpx_ext) }, + { 0, 0xac, &HC11OP(cpx_indx) }, + { 0xcd, 0xac, &HC11OP(cpx_indy) }, + { 0x18, 0x8c, &HC11OP(cpy_imm) }, + { 0x18, 0x9c, &HC11OP(cpy_dir) }, + { 0x18, 0xbc, &HC11OP(cpy_ext) }, + { 0x1a, 0xac, &HC11OP(cpy_indx) }, + { 0x18, 0xac, &HC11OP(cpy_indy) }, +// { 0, 0x19, &HC11OP(daa) }, + { 0, 0x4a, &HC11OP(deca) }, + { 0, 0x5a, &HC11OP(decb) }, + { 0, 0x7a, &HC11OP(dec_ext) }, + { 0, 0x6a, &HC11OP(dec_indx) }, + { 0x18, 0x6a, &HC11OP(dec_indy) }, +// { 0, 0x34, &HC11OP(des) }, + { 0, 0x09, &HC11OP(dex) }, + { 0x18, 0x09, &HC11OP(dey) }, + { 0, 0x88, &HC11OP(eora_imm) }, + { 0, 0x98, &HC11OP(eora_dir) }, + { 0, 0xb8, &HC11OP(eora_ext) }, + { 0, 0xa8, &HC11OP(eora_indx) }, + { 0x18, 0xa8, &HC11OP(eora_indy) }, + { 0, 0xc8, &HC11OP(eorb_imm) }, + { 0, 0xd8, &HC11OP(eorb_dir) }, + { 0, 0xf8, &HC11OP(eorb_ext) }, + { 0, 0xe8, &HC11OP(eorb_indx) }, + { 0x18, 0xe8, &HC11OP(eorb_indy) }, +// { 0, 0x03, &HC11OP(fdiv) }, + { 0, 0x02, &HC11OP(idiv) }, + { 0, 0x4c, &HC11OP(inca) }, + { 0, 0x5c, &HC11OP(incb) }, + { 0, 0x7c, &HC11OP(inc_ext) }, + { 0, 0x6c, &HC11OP(inc_indx) }, + { 0x18, 0x6c, &HC11OP(inc_indy) }, +// { 0, 0x31, &HC11OP(ins) }, + { 0, 0x08, &HC11OP(inx) }, + { 0x18, 0x08, &HC11OP(iny) }, + { 0, 0x7e, &HC11OP(jmp_ext) }, + { 0, 0x6e, &HC11OP(jmp_indx) }, + { 0x18, 0x6e, &HC11OP(jmp_indy) }, + { 0, 0x9d, &HC11OP(jsr_dir) }, + { 0, 0xbd, &HC11OP(jsr_ext) }, + { 0, 0xad, &HC11OP(jsr_indx) }, + { 0x18, 0xad, &HC11OP(jsr_indy) }, + { 0, 0x86, &HC11OP(ldaa_imm) }, + { 0, 0x96, &HC11OP(ldaa_dir) }, + { 0, 0xb6, &HC11OP(ldaa_ext) }, + { 0, 0xa6, &HC11OP(ldaa_indx) }, + { 0x18, 0xa6, &HC11OP(ldaa_indy) }, + { 0, 0xc6, &HC11OP(ldab_imm) }, + { 0, 0xd6, &HC11OP(ldab_dir) }, + { 0, 0xf6, &HC11OP(ldab_ext) }, + { 0, 0xe6, &HC11OP(ldab_indx) }, + { 0x18, 0xe6, &HC11OP(ldab_indy) }, + { 0, 0xcc, &HC11OP(ldd_imm) }, + { 0, 0xdc, &HC11OP(ldd_dir) }, + { 0, 0xfc, &HC11OP(ldd_ext) }, + { 0, 0xec, &HC11OP(ldd_indx) }, + { 0x18, 0xec, &HC11OP(ldd_indy) }, + { 0, 0x8e, &HC11OP(lds_imm) }, + { 0, 0x9e, &HC11OP(lds_dir) }, + { 0, 0xbe, &HC11OP(lds_ext) }, + { 0, 0xae, &HC11OP(lds_indx) }, + { 0x18, 0xae, &HC11OP(lds_indy) }, + { 0, 0xce, &HC11OP(ldx_imm) }, + { 0, 0xde, &HC11OP(ldx_dir) }, + { 0, 0xfe, &HC11OP(ldx_ext) }, + { 0, 0xee, &HC11OP(ldx_indx) }, + { 0xcd, 0xee, &HC11OP(ldx_indy) }, + { 0x18, 0xce, &HC11OP(ldy_imm) }, + { 0x18, 0xde, &HC11OP(ldy_dir) }, + { 0x18, 0xfe, &HC11OP(ldy_ext) }, + { 0x1a, 0xee, &HC11OP(ldy_indx) }, + { 0x18, 0xee, &HC11OP(ldy_indy) }, + { 0, 0x05, &HC11OP(lsld) }, + { 0, 0x44, &HC11OP(lsra) }, + { 0, 0x54, &HC11OP(lsrb) }, +// { 0, 0x74, &HC11OP(lsr_ext) }, +// { 0, 0x64, &HC11OP(lsr_indx) }, +// { 0x18, 0x64, &HC11OP(lsr_indy) }, + { 0, 0x04, &HC11OP(lsrd) }, + { 0, 0x3d, &HC11OP(mul) }, + { 0, 0x40, &HC11OP(nega) }, + { 0, 0x50, &HC11OP(negb) }, + { 0, 0x70, &HC11OP(neg_ext) }, + { 0, 0x60, &HC11OP(neg_indx) }, + { 0x18, 0x60, &HC11OP(neg_indy) }, + { 0, 0x01, &HC11OP(nop) }, + { 0, 0x8a, &HC11OP(oraa_imm) }, + { 0, 0x9a, &HC11OP(oraa_dir) }, + { 0, 0xba, &HC11OP(oraa_ext) }, + { 0, 0xaa, &HC11OP(oraa_indx) }, + { 0x18, 0xaa, &HC11OP(oraa_indy) }, + { 0, 0xca, &HC11OP(orab_imm) }, + { 0, 0xda, &HC11OP(orab_dir) }, + { 0, 0xfa, &HC11OP(orab_ext) }, + { 0, 0xea, &HC11OP(orab_indx) }, + { 0x18, 0xea, &HC11OP(orab_indy) }, + { 0, 0x36, &HC11OP(psha) }, + { 0, 0x37, &HC11OP(pshb) }, + { 0, 0x3c, &HC11OP(pshx) }, + { 0x18, 0x3c, &HC11OP(pshy) }, + { 0, 0x32, &HC11OP(pula) }, + { 0, 0x33, &HC11OP(pulb) }, + { 0, 0x38, &HC11OP(pulx) }, + { 0x18, 0x38, &HC11OP(puly) }, + { 0, 0x49, &HC11OP(rola) }, + { 0, 0x59, &HC11OP(rolb) }, + { 0, 0x79, &HC11OP(rol_ext) }, + { 0, 0x69, &HC11OP(rol_indx) }, + { 0x18, 0x69, &HC11OP(rol_indy) }, + { 0, 0x46, &HC11OP(rora) }, + { 0, 0x56, &HC11OP(rorb) }, +// { 0, 0x76, &HC11OP(ror_ext) }, +// { 0, 0x66, &HC11OP(ror_indx) }, +// { 0x18, 0x66, &HC11OP(ror_indy) }, + { 0, 0x3b, &HC11OP(rti) }, + { 0, 0x39, &HC11OP(rts) }, + { 0, 0x10, &HC11OP(sba) }, + { 0, 0x82, &HC11OP(sbca_imm) }, +// { 0, 0x92, &HC11OP(sbca_dir) }, +// { 0, 0xb2, &HC11OP(sbca_ext) }, + { 0, 0xa2, &HC11OP(sbca_indx) }, + { 0x18, 0xa2, &HC11OP(sbca_indy) }, + { 0, 0xc2, &HC11OP(sbcb_imm) }, +// { 0, 0xd2, &HC11OP(sbcb_dir) }, +// { 0, 0xf2, &HC11OP(sbcb_ext) }, + { 0, 0xe2, &HC11OP(sbcb_indx) }, + { 0x18, 0xe2, &HC11OP(sbcb_indy) }, + { 0, 0x0d, &HC11OP(sec) }, + { 0, 0x0f, &HC11OP(sei) }, + { 0, 0x0b, &HC11OP(sev) }, + { 0, 0x97, &HC11OP(staa_dir) }, + { 0, 0xb7, &HC11OP(staa_ext) }, + { 0, 0xa7, &HC11OP(staa_indx) }, + { 0x18, 0xa7, &HC11OP(staa_indy) }, + { 0, 0xd7, &HC11OP(stab_dir) }, + { 0, 0xf7, &HC11OP(stab_ext) }, + { 0, 0xe7, &HC11OP(stab_indx) }, + { 0x18, 0xe7, &HC11OP(stab_indy) }, + { 0, 0xdd, &HC11OP(std_dir) }, + { 0, 0xfd, &HC11OP(std_ext) }, + { 0, 0xed, &HC11OP(std_indx) }, + { 0x18, 0xed, &HC11OP(std_indy) }, + { 0, 0x9f, &HC11OP(sts_dir) }, +// { 0, 0xbf, &HC11OP(sts_ext) }, +// { 0, 0xaf, &HC11OP(sts_indx) }, +// { 0x18, 0xaf, &HC11OP(sts_indy) }, + { 0, 0xdf, &HC11OP(stx_dir) }, + { 0, 0xff, &HC11OP(stx_ext) }, + { 0, 0xef, &HC11OP(stx_indx) }, + { 0xcd, 0xef, &HC11OP(stx_indy) }, + { 0x18, 0xdf, &HC11OP(sty_dir) }, + { 0x18, 0xff, &HC11OP(sty_ext) }, + { 0x1a, 0xef, &HC11OP(sty_indx) }, + { 0x18, 0xef, &HC11OP(sty_indy) }, + { 0, 0xcf, &HC11OP(stop) }, + { 0, 0x80, &HC11OP(suba_imm) }, + { 0, 0x90, &HC11OP(suba_dir) }, + { 0, 0xb0, &HC11OP(suba_ext) }, + { 0, 0xa0, &HC11OP(suba_indx) }, + { 0x18, 0xa0, &HC11OP(suba_indy) }, + { 0, 0xc0, &HC11OP(subb_imm) }, + { 0, 0xd0, &HC11OP(subb_dir) }, + { 0, 0xf0, &HC11OP(subb_ext) }, + { 0, 0xe0, &HC11OP(subb_indx) }, + { 0x18, 0xe0, &HC11OP(subb_indy) }, + { 0, 0x83, &HC11OP(subd_imm) }, + { 0, 0x93, &HC11OP(subd_dir) }, + { 0, 0xb3, &HC11OP(subd_ext) }, + { 0, 0xa3, &HC11OP(subd_indx) }, + { 0x18, 0xa3, &HC11OP(subd_indy) }, + { 0, 0x3f, &HC11OP(swi) }, + { 0, 0x16, &HC11OP(tab) }, + { 0, 0x06, &HC11OP(tap) }, + { 0, 0x17, &HC11OP(tba) }, + { 0, 0x00, &HC11OP(test) }, + { 0, 0x07, &HC11OP(tpa) }, + { 0, 0x4d, &HC11OP(tsta) }, + { 0, 0x5d, &HC11OP(tstb) }, + { 0, 0x7d, &HC11OP(tst_ext) }, + { 0, 0x6d, &HC11OP(tst_indx) }, + { 0x18, 0x6d, &HC11OP(tst_indy) }, + { 0, 0x30, &HC11OP(tsx) }, + { 0x18, 0x30, &HC11OP(tsy) }, + { 0, 0x35, &HC11OP(txs) }, + { 0x18, 0x35, &HC11OP(tys) }, + { 0, 0x3e, &HC11OP(wai) }, + { 0, 0x8f, &HC11OP(xgdx) }, + { 0x18, 0x8f, &HC11OP(xgdy) }, - { 0, 0x18, HC11OP(page2) }, - { 0, 0x1a, HC11OP(page3) }, - { 0, 0xcd, HC11OP(page4) }, + { 0, 0x18, &HC11OP(page2) }, + { 0, 0x1a, &HC11OP(page3) }, + { 0, 0xcd, &HC11OP(page4) }, }; diff --git a/src/emu/cpu/mc68hc11/mc68hc11.c b/src/emu/cpu/mc68hc11/mc68hc11.c index f96cae94e04..4ed5b4e76af 100644 --- a/src/emu/cpu/mc68hc11/mc68hc11.c +++ b/src/emu/cpu/mc68hc11/mc68hc11.c @@ -36,148 +36,112 @@ enum static const int div_tab[4] = { 1, 4, 8, 16 }; -struct hc11_state + +const device_type MC68HC11 = &device_creator; + + +mc68hc11_cpu_device::mc68hc11_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : cpu_device(mconfig, MC68HC11, "MC68HC11", tag, owner, clock, "mc68hc11", __FILE__) + , m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0 ) + , m_io_config("io", ENDIANNESS_LITTLE, 8, 8, 0) + /* defaults it to the HC11M0 version for now (I might strip this down on a later date) */ + , m_has_extended_io(1) + , m_internal_ram_size(1280) + , m_init_value(0x01) { - union { - struct { -#ifdef LSB_FIRST - UINT8 b; - UINT8 a; -#else - UINT8 a; - UINT8 b; -#endif - } d8; - UINT16 d16; - } d; - - UINT16 ix; - UINT16 iy; - UINT16 sp; - UINT16 pc; - UINT16 ppc; - UINT8 ccr; - - UINT8 adctl; - int ad_channel; - - device_irq_acknowledge_callback irq_callback; - UINT8 irq_state[2]; - legacy_cpu_device *device; - direct_read_data *direct; - address_space *program; - address_space *io; - int icount; - - int ram_position; - int reg_position; - UINT8 *internal_ram; - - int has_extended_io; // extended I/O enable flag - int internal_ram_size; - int init_value; - - UINT8 wait_state,stop_state; - - UINT8 tflg1, tmsk1; - UINT16 toc1; - UINT16 tcnt; -// UINT8 por; - UINT8 pr; - - UINT64 frc_base; -}; - -INLINE hc11_state *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == MC68HC11); - return (hc11_state *)downcast(device)->token(); } -#define HC11OP(XX) hc11_##XX + +offs_t mc68hc11_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + extern CPU_DISASSEMBLE( hc11 ); + return CPU_DISASSEMBLE_NAME(hc11)(this, buffer, pc, oprom, opram, options); +} + + +#define HC11OP(XX) mc68hc11_cpu_device::hc11_##XX /*****************************************************************************/ /* Internal registers */ -static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address) +UINT8 mc68hc11_cpu_device::hc11_regs_r(UINT32 address) { int reg = address & 0xff; switch(reg) { case 0x00: /* PORTA */ - return cpustate->io->read_byte(MC68HC11_IO_PORTA); + return m_io->read_byte(MC68HC11_IO_PORTA); case 0x01: /* DDRA */ return 0; case 0x02: /* PIOC */ return 0; case 0x03: /* PORTC */ - return cpustate->io->read_byte(MC68HC11_IO_PORTC); + return m_io->read_byte(MC68HC11_IO_PORTC); case 0x04: /* PORTB */ - return cpustate->io->read_byte(MC68HC11_IO_PORTB); + return m_io->read_byte(MC68HC11_IO_PORTB); case 0x08: /* PORTD */ - return cpustate->io->read_byte(MC68HC11_IO_PORTD); + return m_io->read_byte(MC68HC11_IO_PORTD); case 0x09: /* DDRD */ return 0; case 0x0a: /* PORTE */ - return cpustate->io->read_byte(MC68HC11_IO_PORTE); + return m_io->read_byte(MC68HC11_IO_PORTE); case 0x0e: /* TCNT */ - return cpustate->tcnt >> 8; + return m_tcnt >> 8; case 0x0f: - return cpustate->tcnt & 0xff; + return m_tcnt & 0xff; case 0x16: /* TOC1 */ - return cpustate->toc1 >> 8; + return m_toc1 >> 8; case 0x17: - return cpustate->toc1 & 0xff; + return m_toc1 & 0xff; case 0x23: - return cpustate->tflg1; + return m_tflg1; case 0x28: /* SPCR1 */ return 0; case 0x30: /* ADCTL */ return 0x80; case 0x31: /* ADR1 */ { - if (cpustate->adctl & 0x10) + if (m_adctl & 0x10) { - return cpustate->io->read_byte((cpustate->adctl & 0x4) + MC68HC11_IO_AD0); + return m_io->read_byte((m_adctl & 0x4) + MC68HC11_IO_AD0); } else { - return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0); + return m_io->read_byte((m_adctl & 0x7) + MC68HC11_IO_AD0); } } case 0x32: /* ADR2 */ { - if (cpustate->adctl & 0x10) + if (m_adctl & 0x10) { - return cpustate->io->read_byte((cpustate->adctl & 0x4) + MC68HC11_IO_AD1); + return m_io->read_byte((m_adctl & 0x4) + MC68HC11_IO_AD1); } else { - return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0); + return m_io->read_byte((m_adctl & 0x7) + MC68HC11_IO_AD0); } } case 0x33: /* ADR3 */ { - if (cpustate->adctl & 0x10) + if (m_adctl & 0x10) { - return cpustate->io->read_byte((cpustate->adctl & 0x4) + MC68HC11_IO_AD2); + return m_io->read_byte((m_adctl & 0x4) + MC68HC11_IO_AD2); } else { - return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0); + return m_io->read_byte((m_adctl & 0x7) + MC68HC11_IO_AD0); } } case 0x34: /* ADR4 */ { - if (cpustate->adctl & 0x10) + if (m_adctl & 0x10) { - return cpustate->io->read_byte((cpustate->adctl & 0x4) + MC68HC11_IO_AD3); + return m_io->read_byte((m_adctl & 0x4) + MC68HC11_IO_AD3); } else { - return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0); + return m_io->read_byte((m_adctl & 0x7) + MC68HC11_IO_AD0); } } case 0x38: /* OPT2 */ @@ -193,9 +157,9 @@ static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address) case 0x74: /* SCSR1 */ return 0x40; case 0x7c: /* PORTH */ - return cpustate->io->read_byte(MC68HC11_IO_PORTH); + return m_io->read_byte(MC68HC11_IO_PORTH); case 0x7e: /* PORTG */ - return cpustate->io->read_byte(MC68HC11_IO_PORTG); + return m_io->read_byte(MC68HC11_IO_PORTG); case 0x7f: /* DDRG */ return 0; @@ -204,7 +168,7 @@ static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address) case 0x89: /* SPSR2 */ return 0x80; case 0x8a: /* SPDR2 */ - return cpustate->io->read_byte(MC68HC11_IO_SPI2_DATA); + return m_io->read_byte(MC68HC11_IO_SPI2_DATA); case 0x8b: /* OPT4 */ return 0; @@ -214,32 +178,32 @@ static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address) return 0; // Dummy } -static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value) +void mc68hc11_cpu_device::hc11_regs_w(UINT32 address, UINT8 value) { int reg = address & 0xff; switch(reg) { case 0x00: /* PORTA */ - cpustate->io->write_byte(MC68HC11_IO_PORTA, value); + m_io->write_byte(MC68HC11_IO_PORTA, value); return; case 0x01: /* DDRA */ //mame_printf_debug("HC11: ddra = %02X\n", value); return; case 0x03: /* PORTC */ - cpustate->io->write_byte(MC68HC11_IO_PORTC, value); + m_io->write_byte(MC68HC11_IO_PORTC, value); return; case 0x04: /* PORTC */ - cpustate->io->write_byte(MC68HC11_IO_PORTB, value); + m_io->write_byte(MC68HC11_IO_PORTB, value); return; case 0x08: /* PORTD */ - cpustate->io->write_byte(MC68HC11_IO_PORTD, value); //mask & 0x3f? + m_io->write_byte(MC68HC11_IO_PORTD, value); //mask & 0x3f? return; case 0x09: /* DDRD */ //mame_printf_debug("HC11: ddrd = %02X\n", value); return; case 0x0a: /* PORTE */ - cpustate->io->write_byte(MC68HC11_IO_PORTE, value); + m_io->write_byte(MC68HC11_IO_PORTE, value); return; case 0x0e: /* TCNT */ case 0x0f: @@ -247,24 +211,24 @@ static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value) return; case 0x16: /* TOC1 */ /* TODO: inhibit for one bus cycle */ - cpustate->toc1 = (value << 8) | (cpustate->toc1 & 0xff); + m_toc1 = (value << 8) | (m_toc1 & 0xff); return; case 0x17: - cpustate->toc1 = (value & 0xff) | (cpustate->toc1 & 0xff00); + m_toc1 = (value & 0xff) | (m_toc1 & 0xff00); return; case 0x22: /* TMSK1 */ - cpustate->tmsk1 = value; + m_tmsk1 = value; return; case 0x23: - cpustate->tflg1 &= ~value; + m_tflg1 &= ~value; return; case 0x24: /* TMSK2 */ - cpustate->pr = value & 3; + m_pr = value & 3; return; case 0x28: /* SPCR1 */ return; case 0x30: /* ADCTL */ - cpustate->adctl = value; + m_adctl = value; return; case 0x38: /* OPT2 */ return; @@ -279,11 +243,11 @@ static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value) int ram_page = (value >> 4) & 0xf; if (reg_page == ram_page) { - cpustate->reg_position = reg_page << 12; - cpustate->ram_position = (ram_page << 12) + ((cpustate->has_extended_io) ? 0x100 : 0x80); + m_reg_position = reg_page << 12; + m_ram_position = (ram_page << 12) + ((m_has_extended_io) ? 0x100 : 0x80); } else { - cpustate->reg_position = reg_page << 12; - cpustate->ram_position = ram_page << 12; + m_reg_position = reg_page << 12; + m_ram_position = ram_page << 12; } return; } @@ -302,16 +266,16 @@ static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value) case 0x77: /* SCDRL */ return; case 0x7c: /* PORTH */ - cpustate->io->write_byte(MC68HC11_IO_PORTH, value); + m_io->write_byte(MC68HC11_IO_PORTH, value); return; case 0x7d: /* DDRH */ - //mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, cpustate->pc); + //mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, m_pc); return; case 0x7e: /* PORTG */ - cpustate->io->write_byte(MC68HC11_IO_PORTG, value); + m_io->write_byte(MC68HC11_IO_PORTG, value); return; case 0x7f: /* DDRG */ - //mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, cpustate->pc); + //mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, m_pc); return; case 0x88: /* SPCR2 */ @@ -319,7 +283,7 @@ static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value) case 0x89: /* SPSR2 */ return; case 0x8a: /* SPDR2 */ - cpustate->io->write_byte(MC68HC11_IO_SPI2_DATA, value); + m_io->write_byte(MC68HC11_IO_SPI2_DATA, value); return; case 0x8b: /* OPT4 */ @@ -332,81 +296,74 @@ static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value) /*****************************************************************************/ -INLINE UINT8 FETCH(hc11_state *cpustate) +UINT8 mc68hc11_cpu_device::FETCH() { - return cpustate->direct->read_decrypted_byte(cpustate->pc++); + return m_direct->read_decrypted_byte(m_pc++); } -INLINE UINT16 FETCH16(hc11_state *cpustate) +UINT16 mc68hc11_cpu_device::FETCH16() { UINT16 w; - w = (cpustate->direct->read_decrypted_byte(cpustate->pc) << 8) | (cpustate->direct->read_decrypted_byte(cpustate->pc+1)); - cpustate->pc += 2; + w = (m_direct->read_decrypted_byte(m_pc) << 8) | (m_direct->read_decrypted_byte(m_pc+1)); + m_pc += 2; return w; } -INLINE UINT8 READ8(hc11_state *cpustate, UINT32 address) +UINT8 mc68hc11_cpu_device::READ8(UINT32 address) { - if(address >= cpustate->reg_position && address < cpustate->reg_position+(cpustate->has_extended_io ? 0x100 : 0x40)) + if(address >= m_reg_position && address < m_reg_position+(m_has_extended_io ? 0x100 : 0x40)) { - return hc11_regs_r(cpustate, address); + return hc11_regs_r(address); } - else if(address >= cpustate->ram_position && address < cpustate->ram_position+cpustate->internal_ram_size) + else if(address >= m_ram_position && address < m_ram_position+m_internal_ram_size) { - return cpustate->internal_ram[address-cpustate->ram_position]; + return m_internal_ram[address-m_ram_position]; } - return cpustate->program->read_byte(address); + return m_program->read_byte(address); } -INLINE void WRITE8(hc11_state *cpustate, UINT32 address, UINT8 value) +void mc68hc11_cpu_device::WRITE8(UINT32 address, UINT8 value) { - if(address >= cpustate->reg_position && address < cpustate->reg_position+(cpustate->has_extended_io ? 0x100 : 0x40)) + if(address >= m_reg_position && address < m_reg_position+(m_has_extended_io ? 0x100 : 0x40)) { - hc11_regs_w(cpustate, address, value); + hc11_regs_w(address, value); return; } - else if(address >= cpustate->ram_position && address < cpustate->ram_position+cpustate->internal_ram_size) + else if(address >= m_ram_position && address < m_ram_position+m_internal_ram_size) { - cpustate->internal_ram[address-cpustate->ram_position] = value; + m_internal_ram[address-m_ram_position] = value; return; } - cpustate->program->write_byte(address, value); + m_program->write_byte(address, value); } -INLINE UINT16 READ16(hc11_state *cpustate, UINT32 address) +UINT16 mc68hc11_cpu_device::READ16(UINT32 address) { - return (READ8(cpustate, address) << 8) | (READ8(cpustate, address+1)); + return (READ8(address) << 8) | (READ8(address+1)); } -INLINE void WRITE16(hc11_state *cpustate, UINT32 address, UINT16 value) +void mc68hc11_cpu_device::WRITE16(UINT32 address, UINT16 value) { - WRITE8(cpustate, address+0, (value >> 8) & 0xff); - WRITE8(cpustate, address+1, (value >> 0) & 0xff); + WRITE8(address+0, (value >> 8) & 0xff); + WRITE8(address+1, (value >> 0) & 0xff); } /*****************************************************************************/ -static void (*hc11_optable[256])(hc11_state *cpustate); -static void (*hc11_optable_page2[256])(hc11_state *cpustate); -static void (*hc11_optable_page3[256])(hc11_state *cpustate); -static void (*hc11_optable_page4[256])(hc11_state *cpustate); #include "hc11ops.c" #include "hc11ops.h" -static CPU_INIT( hc11 ) +void mc68hc11_cpu_device::device_start() { - hc11_state *cpustate = get_safe_token(device); int i; - const hc11_config *conf = (const hc11_config *)device->static_config(); - /* clear the opcode tables */ for(i=0; i < 256; i++) { - hc11_optable[i] = HC11OP(invalid); - hc11_optable_page2[i] = HC11OP(invalid); - hc11_optable_page3[i] = HC11OP(invalid); - hc11_optable_page4[i] = HC11OP(invalid); + hc11_optable[i] = &HC11OP(invalid); + hc11_optable_page2[i] = &HC11OP(invalid); + hc11_optable_page3[i] = &HC11OP(invalid); + hc11_optable_page4[i] = &HC11OP(invalid); } /* fill the opcode tables */ for(i=0; i < sizeof(hc11_opcode_list)/sizeof(hc11_opcode_list_struct); i++) @@ -428,74 +385,98 @@ static CPU_INIT( hc11 ) } } - if(conf) - { - cpustate->has_extended_io = conf->has_extended_io; - cpustate->internal_ram_size = conf->internal_ram_size; - cpustate->init_value = conf->init_value; - } - else - { - /* defaults it to the HC11M0 version for now (I might strip this down on a later date) */ - cpustate->has_extended_io = 1; - cpustate->internal_ram_size = 1280; - cpustate->init_value = 0x01; - } + m_internal_ram = auto_alloc_array(machine(), UINT8, m_internal_ram_size); - cpustate->internal_ram = auto_alloc_array(device->machine(), UINT8, cpustate->internal_ram_size); + m_program = &space(AS_PROGRAM); + m_direct = &m_program->direct(); + m_io = &space(AS_IO); - cpustate->irq_callback = irqcallback; - cpustate->device = device; - cpustate->program = &device->space(AS_PROGRAM); - cpustate->direct = &cpustate->program->direct(); - cpustate->io = &device->space(AS_IO); + save_item(NAME(m_pc)); + save_item(NAME(m_ix)); + save_item(NAME(m_iy)); + save_item(NAME(m_sp)); + save_item(NAME(m_ppc)); + save_item(NAME(m_ccr)); + save_item(NAME(m_d.d8.a)); + save_item(NAME(m_d.d8.b)); + save_item(NAME(m_adctl)); + save_item(NAME(m_ad_channel)); + save_item(NAME(m_ram_position)); + save_item(NAME(m_reg_position)); + save_item(NAME(m_irq_state)); + save_item(NAME(m_icount)); + save_item(NAME(m_has_extended_io)); + save_item(NAME(m_internal_ram_size)); + save_item(NAME(m_init_value)); + save_pointer(NAME(m_internal_ram),m_internal_ram_size); + save_item(NAME(m_wait_state)); + save_item(NAME(m_stop_state)); + save_item(NAME(m_tflg1)); + save_item(NAME(m_tmsk1)); + save_item(NAME(m_toc1)); + save_item(NAME(m_tcnt)); +// save_item(NAME(m_por)); + save_item(NAME(m_pr)); + save_item(NAME(m_frc_base)); - device->save_item(NAME(cpustate->pc)); - device->save_item(NAME(cpustate->ix)); - device->save_item(NAME(cpustate->iy)); - device->save_item(NAME(cpustate->sp)); - device->save_item(NAME(cpustate->ppc)); - device->save_item(NAME(cpustate->ccr)); - device->save_item(NAME(cpustate->d.d8.a)); - device->save_item(NAME(cpustate->d.d8.b)); - device->save_item(NAME(cpustate->adctl)); - device->save_item(NAME(cpustate->ad_channel)); - device->save_item(NAME(cpustate->ram_position)); - device->save_item(NAME(cpustate->reg_position)); - device->save_item(NAME(cpustate->irq_state)); - device->save_item(NAME(cpustate->icount)); - device->save_item(NAME(cpustate->has_extended_io)); - device->save_item(NAME(cpustate->internal_ram_size)); - device->save_item(NAME(cpustate->init_value)); - device->save_pointer(NAME(cpustate->internal_ram),cpustate->internal_ram_size); - device->save_item(NAME(cpustate->wait_state)); - device->save_item(NAME(cpustate->stop_state)); - device->save_item(NAME(cpustate->tflg1)); - device->save_item(NAME(cpustate->tmsk1)); - device->save_item(NAME(cpustate->toc1)); - device->save_item(NAME(cpustate->tcnt)); -// device->save_item(NAME(cpustate->por)); - device->save_item(NAME(cpustate->pr)); - device->save_item(NAME(cpustate->frc_base)); + state_add( HC11_PC, "PC", m_pc).formatstr("%04X"); + state_add( HC11_SP, "SP", m_sp).formatstr("%04X"); + state_add( HC11_A, "A", m_d.d8.a).formatstr("%02X"); + state_add( HC11_B, "B", m_d.d8.b).formatstr("%02X"); + state_add( HC11_IX, "IX", m_ix).formatstr("%04X"); + state_add( HC11_IY, "IY", m_iy).formatstr("%04X"); + + state_add( STATE_GENPC, "GENPC", m_pc).noshow(); + state_add( STATE_GENFLAGS, "GENFLAGS", m_ccr).formatstr("%8s").noshow(); + + m_d.d16 = 0; + m_ix = 0; + m_iy = 0; + m_sp = 0; + m_ppc = 0; + m_adctl = 0; + m_ad_channel = 0; + m_irq_state[0] = m_irq_state[1] = 0; + m_ram_position = 0; + m_reg_position = 0; + m_tflg1 = 0; + m_tmsk1 = 0; + + m_icountptr = &m_icount; } -static CPU_RESET( hc11 ) + +void mc68hc11_cpu_device::state_string_export(const device_state_entry &entry, astring &string) { - hc11_state *cpustate = get_safe_token(device); - cpustate->pc = READ16(cpustate, 0xfffe); - cpustate->wait_state = 0; - cpustate->stop_state = 0; - cpustate->ccr = CC_X | CC_I | CC_S; - hc11_regs_w(cpustate,0x3d,cpustate->init_value); - cpustate->toc1 = 0xffff; - cpustate->tcnt = 0xffff; -// cpustate->por = 1; // for first timer overflow / compare stuff - cpustate->pr = 3; // timer prescale - cpustate->frc_base = 0; + switch (entry.index()) + { + case STATE_GENFLAGS: + string.printf("%c%c%c%c%c%c%c%c", + (m_ccr & CC_S) ? 'S' : '.', + (m_ccr & CC_X) ? 'X' : '.', + (m_ccr & CC_H) ? 'H' : '.', + (m_ccr & CC_I) ? 'I' : '.', + (m_ccr & CC_N) ? 'N' : '.', + (m_ccr & CC_Z) ? 'Z' : '.', + (m_ccr & CC_V) ? 'V' : '.', + (m_ccr & CC_C) ? 'C' : '.'); + break; + } } -static CPU_EXIT( hc11 ) + +void mc68hc11_cpu_device::device_reset() { + m_pc = READ16(0xfffe); + m_wait_state = 0; + m_stop_state = 0; + m_ccr = CC_X | CC_I | CC_S; + hc11_regs_w(0x3d,m_init_value); + m_toc1 = 0xffff; + m_tcnt = 0xffff; +// m_por = 1; // for first timer overflow / compare stuff + m_pr = 3; // timer prescale + m_frc_base = 0; } /* @@ -523,200 +504,95 @@ IRQ table vectors: 0xfffe: RESET */ -static void check_irq_lines(hc11_state *cpustate) +void mc68hc11_cpu_device::check_irq_lines() { - if( cpustate->irq_state[MC68HC11_IRQ_LINE]!=CLEAR_LINE && (!(cpustate->ccr & CC_I)) ) + if( m_irq_state[MC68HC11_IRQ_LINE]!=CLEAR_LINE && (!(m_ccr & CC_I)) ) { UINT16 pc_vector; - if(cpustate->wait_state == 0) + if(m_wait_state == 0) { - PUSH16(cpustate, cpustate->pc); - PUSH16(cpustate, cpustate->iy); - PUSH16(cpustate, cpustate->ix); - PUSH8(cpustate, REG_A); - PUSH8(cpustate, REG_B); - PUSH8(cpustate, cpustate->ccr); + PUSH16(m_pc); + PUSH16(m_iy); + PUSH16(m_ix); + PUSH8(REG_A); + PUSH8(REG_B); + PUSH8(m_ccr); } - pc_vector = READ16(cpustate, 0xfff2); - SET_PC(cpustate, pc_vector); - cpustate->ccr |= CC_I; //irq taken, mask the flag - if(cpustate->wait_state == 1) { cpustate->wait_state = 2; } - if(cpustate->stop_state == 1) { cpustate->stop_state = 2; } - (void)(*cpustate->irq_callback)(cpustate->device, MC68HC11_IRQ_LINE); + pc_vector = READ16(0xfff2); + SET_PC(pc_vector); + m_ccr |= CC_I; //irq taken, mask the flag + if(m_wait_state == 1) { m_wait_state = 2; } + if(m_stop_state == 1) { m_stop_state = 2; } + standard_irq_callback(MC68HC11_IRQ_LINE); } /* check timers here */ { - int divider = div_tab[cpustate->pr & 3]; - UINT64 cur_time = cpustate->device->total_cycles(); - UINT32 add = (cur_time - cpustate->frc_base) / divider; + int divider = div_tab[m_pr & 3]; + UINT64 cur_time = total_cycles(); + UINT32 add = (cur_time - m_frc_base) / divider; if (add > 0) { for(UINT32 i=0;itcnt++; - if(cpustate->tcnt == cpustate->toc1) + m_tcnt++; + if(m_tcnt == m_toc1) { - cpustate->tflg1 |= 0x80; - cpustate->irq_state[MC68HC11_TOC1_LINE] = ASSERT_LINE; + m_tflg1 |= 0x80; + m_irq_state[MC68HC11_TOC1_LINE] = ASSERT_LINE; } } - cpustate->frc_base = cur_time; + m_frc_base = cur_time; } } - if( cpustate->irq_state[MC68HC11_TOC1_LINE]!=CLEAR_LINE && (!(cpustate->ccr & CC_I)) && cpustate->tmsk1 & 0x80) + if( m_irq_state[MC68HC11_TOC1_LINE]!=CLEAR_LINE && (!(m_ccr & CC_I)) && m_tmsk1 & 0x80) { UINT16 pc_vector; - if(cpustate->wait_state == 0) + if(m_wait_state == 0) { - PUSH16(cpustate, cpustate->pc); - PUSH16(cpustate, cpustate->iy); - PUSH16(cpustate, cpustate->ix); - PUSH8(cpustate, REG_A); - PUSH8(cpustate, REG_B); - PUSH8(cpustate, cpustate->ccr); + PUSH16(m_pc); + PUSH16(m_iy); + PUSH16(m_ix); + PUSH8(REG_A); + PUSH8(REG_B); + PUSH8(m_ccr); } - pc_vector = READ16(cpustate, 0xffe8); - SET_PC(cpustate, pc_vector); - cpustate->ccr |= CC_I; //irq taken, mask the flag - if(cpustate->wait_state == 1) { cpustate->wait_state = 2; } - if(cpustate->stop_state == 1) { cpustate->stop_state = 2; } - (void)(*cpustate->irq_callback)(cpustate->device, MC68HC11_TOC1_LINE); - cpustate->irq_state[MC68HC11_TOC1_LINE] = CLEAR_LINE; // auto-ack irq + pc_vector = READ16(0xffe8); + SET_PC(pc_vector); + m_ccr |= CC_I; //irq taken, mask the flag + if(m_wait_state == 1) { m_wait_state = 2; } + if(m_stop_state == 1) { m_stop_state = 2; } + standard_irq_callback(MC68HC11_TOC1_LINE); + m_irq_state[MC68HC11_TOC1_LINE] = CLEAR_LINE; // auto-ack irq } } -static void set_irq_line(hc11_state *cpustate, int irqline, int state) +void mc68hc11_cpu_device::execute_set_input(int inputnum, int state) { - cpustate->irq_state[irqline] = state; + m_irq_state[inputnum] = state; if (state == CLEAR_LINE) return; - check_irq_lines(cpustate); + check_irq_lines(); } -static CPU_EXECUTE( hc11 ) +void mc68hc11_cpu_device::execute_run() { - hc11_state *cpustate = get_safe_token(device); - - while(cpustate->icount > 0) + while(m_icount > 0) { UINT8 op; - check_irq_lines(cpustate); + check_irq_lines(); - cpustate->ppc = cpustate->pc; - debugger_instruction_hook(device, cpustate->pc); + m_ppc = m_pc; + debugger_instruction_hook(this, m_pc); - op = FETCH(cpustate); - hc11_optable[op](cpustate); + op = FETCH(); + (this->*hc11_optable[op])(); } } -/*****************************************************************************/ - -static CPU_SET_INFO( mc68hc11 ) -{ - hc11_state *cpustate = get_safe_token(device); - - switch (state) - { - case CPUINFO_INT_INPUT_STATE + MC68HC11_IRQ_LINE: set_irq_line(cpustate, MC68HC11_IRQ_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + MC68HC11_TOC1_LINE: set_irq_line(cpustate, MC68HC11_TOC1_LINE, info->i); break; - - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_PC: cpustate->pc = info->i; break; - case CPUINFO_INT_REGISTER + HC11_PC: cpustate->pc = info->i; break; - case CPUINFO_INT_REGISTER + HC11_SP: cpustate->sp = info->i; break; - case CPUINFO_INT_REGISTER + HC11_A: cpustate->d.d8.a = info->i; break; - case CPUINFO_INT_REGISTER + HC11_B: cpustate->d.d8.b = info->i; break; - case CPUINFO_INT_REGISTER + HC11_IX: cpustate->ix = info->i; break; - case CPUINFO_INT_REGISTER + HC11_IY: cpustate->iy = info->i; break; - } -} - -CPU_GET_INFO( mc68hc11 ) -{ - hc11_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch(state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hc11_state); break; - case CPUINFO_INT_INPUT_LINES: info->i = 1; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 41; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + MC68HC11_IRQ_LINE: info->i = cpustate->irq_state[MC68HC11_IRQ_LINE]; break; - case CPUINFO_INT_INPUT_STATE + MC68HC11_TOC1_LINE: info->i = cpustate->irq_state[MC68HC11_TOC1_LINE]; break; - - case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; - - case CPUINFO_INT_PC: /* intentional fallthrough */ - case CPUINFO_INT_REGISTER + HC11_PC: info->i = cpustate->pc; break; - case CPUINFO_INT_REGISTER + HC11_SP: info->i = cpustate->sp; break; - case CPUINFO_INT_REGISTER + HC11_A: info->i = cpustate->d.d8.a; break; - case CPUINFO_INT_REGISTER + HC11_B: info->i = cpustate->d.d8.b; break; - case CPUINFO_INT_REGISTER + HC11_IX: info->i = cpustate->ix; break; - case CPUINFO_INT_REGISTER + HC11_IY: info->i = cpustate->iy; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mc68hc11); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(hc11); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(hc11); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(hc11); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(hc11); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(hc11); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "MC68HC11"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "mc68hc11"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Motorola MC68HC11"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Ville Linde & Angelo Salese"); break; - - case CPUINFO_STR_FLAGS: - sprintf(info->s, "%c%c%c%c%c%c%c%c", - (cpustate->ccr & CC_S) ? 'S' : '.', - (cpustate->ccr & CC_X) ? 'X' : '.', - (cpustate->ccr & CC_H) ? 'H' : '.', - (cpustate->ccr & CC_I) ? 'I' : '.', - (cpustate->ccr & CC_N) ? 'N' : '.', - (cpustate->ccr & CC_Z) ? 'Z' : '.', - (cpustate->ccr & CC_V) ? 'V' : '.', - (cpustate->ccr & CC_C) ? 'C' : '.'); - break; - - case CPUINFO_STR_REGISTER + HC11_PC: sprintf(info->s, "PC: %04X", cpustate->pc); break; - case CPUINFO_STR_REGISTER + HC11_SP: sprintf(info->s, "SP: %04X", cpustate->sp); break; - case CPUINFO_STR_REGISTER + HC11_A: sprintf(info->s, "A: %02X", cpustate->d.d8.a); break; - case CPUINFO_STR_REGISTER + HC11_B: sprintf(info->s, "B: %02X", cpustate->d.d8.b); break; - case CPUINFO_STR_REGISTER + HC11_IX: sprintf(info->s, "IX: %04X", cpustate->ix); break; - case CPUINFO_STR_REGISTER + HC11_IY: sprintf(info->s, "IY: %04X", cpustate->iy); break; - } -} - -DEFINE_LEGACY_CPU_DEVICE(MC68HC11, mc68hc11); diff --git a/src/emu/cpu/mc68hc11/mc68hc11.h b/src/emu/cpu/mc68hc11/mc68hc11.h index 1fa4cd7a1a9..b2a377b17e1 100644 --- a/src/emu/cpu/mc68hc11/mc68hc11.h +++ b/src/emu/cpu/mc68hc11/mc68hc11.h @@ -4,11 +4,6 @@ #define __MC68HC11_H__ -CPU_DISASSEMBLE( hc11 ); - -DECLARE_LEGACY_CPU_DEVICE(MC68HC11, mc68hc11); - - #define MC68HC11_IO_PORTA 0x00 #define MC68HC11_IO_PORTB 0x01 #define MC68HC11_IO_PORTC 0x02 @@ -31,11 +26,415 @@ DECLARE_LEGACY_CPU_DEVICE(MC68HC11, mc68hc11); #define MC68HC11_IRQ_LINE 0 #define MC68HC11_TOC1_LINE 1 -struct hc11_config + +extern const device_type MC68HC11; + + +#define MCFG_MC68HC11_CONFIG(_has_extended_io, _internal_ram_size, _init_value) \ + mc68hc11_cpu_device::set_has_extended_io(*device, _has_extended_io); \ + mc68hc11_cpu_device::set_internal_ram_size(*device, _internal_ram_size); \ + mc68hc11_cpu_device::set_init_value(*device, _init_value); + + +class mc68hc11_cpu_device : public cpu_device { - int has_extended_io; // I/O enable flag - int internal_ram_size; - int init_value; // default value for INIT register +public: + // construction/destruction + mc68hc11_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + // I/O enable flag + static void set_has_extended_io(device_t &device, int has_extended_io) { downcast(device).m_has_extended_io = has_extended_io; } + static void set_internal_ram_size(device_t &device, int internal_ram_size) { downcast(device).m_internal_ram_size = internal_ram_size; } + // default value for INIT register + static void set_init_value(device_t &device, int init_value) { downcast(device).m_init_value = init_value; } + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 1; } + virtual UINT32 execute_max_cycles() const { return 41; } + virtual UINT32 execute_input_lines() const { return 2; } + virtual UINT32 execute_default_irq_vector() const { return 0; } + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const + { + return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); + } + + // device_state_interface overrides + void state_string_export(const device_state_entry &entry, astring &string); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 1; } + virtual UINT32 disasm_max_opcode_bytes() const { return 5; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + +private: + address_space_config m_program_config; + address_space_config m_io_config; + + union { + struct { +#ifdef LSB_FIRST + UINT8 b; + UINT8 a; +#else + UINT8 a; + UINT8 b; +#endif + } d8; + UINT16 d16; + } m_d; + + UINT16 m_ix; + UINT16 m_iy; + UINT16 m_sp; + UINT16 m_pc; + UINT16 m_ppc; + UINT8 m_ccr; + + UINT8 m_adctl; + int m_ad_channel; + + UINT8 m_irq_state[2]; + direct_read_data *m_direct; + address_space *m_program; + address_space *m_io; + int m_icount; + + int m_ram_position; + int m_reg_position; + UINT8 *m_internal_ram; + + int m_has_extended_io; // extended I/O enable flag + int m_internal_ram_size; + int m_init_value; + + UINT8 m_wait_state; + UINT8 m_stop_state; + + UINT8 m_tflg1; + UINT8 m_tmsk1; + UINT16 m_toc1; + UINT16 m_tcnt; +// UINT8 m_por; + UINT8 m_pr; + + UINT64 m_frc_base; + + typedef void (mc68hc11_cpu_device::*ophandler)(); + struct hc11_opcode_list_struct + { + int page; + int opcode; + ophandler handler; + }; + static const hc11_opcode_list_struct hc11_opcode_list[]; + + ophandler hc11_optable[256]; + ophandler hc11_optable_page2[256]; + ophandler hc11_optable_page3[256]; + ophandler hc11_optable_page4[256]; + + UINT8 hc11_regs_r(UINT32 address); + void hc11_regs_w(UINT32 address, UINT8 value); + UINT8 FETCH(); + UINT16 FETCH16(); + UINT8 READ8(UINT32 address); + void WRITE8(UINT32 address, UINT8 value); + UINT16 READ16(UINT32 address); + void WRITE16(UINT32 address, UINT16 value); + void CYCLES(int cycles); + void SET_PC(int pc); + void PUSH8(UINT8 value); + void PUSH16(UINT16 value); + UINT8 POP8(); + UINT16 POP16(); + void hc11_aba(); + void hc11_abx(); + void hc11_aby(); + void hc11_adca_imm(); + void hc11_adca_dir(); + void hc11_adca_ext(); + void hc11_adca_indx(); + void hc11_adca_indy(); + void hc11_adcb_imm(); + void hc11_adcb_dir(); + void hc11_adcb_ext(); + void hc11_adcb_indx(); + void hc11_adcb_indy(); + void hc11_adda_imm(); + void hc11_adda_dir(); + void hc11_adda_ext(); + void hc11_adda_indx(); + void hc11_adda_indy(); + void hc11_addb_imm(); + void hc11_addb_dir(); + void hc11_addb_ext(); + void hc11_addb_indx(); + void hc11_addb_indy(); + void hc11_addd_imm(); + void hc11_addd_dir(); + void hc11_addd_ext(); + void hc11_addd_indx(); + void hc11_addd_indy(); + void hc11_anda_imm(); + void hc11_anda_dir(); + void hc11_anda_ext(); + void hc11_anda_indx(); + void hc11_anda_indy(); + void hc11_andb_imm(); + void hc11_andb_dir(); + void hc11_andb_ext(); + void hc11_andb_indx(); + void hc11_andb_indy(); + void hc11_asla(); + void hc11_aslb(); + void hc11_asl_ext(); + void hc11_bita_imm(); + void hc11_bita_dir(); + void hc11_bita_ext(); + void hc11_bita_indx(); + void hc11_bita_indy(); + void hc11_bitb_imm(); + void hc11_bitb_dir(); + void hc11_bitb_ext(); + void hc11_bitb_indx(); + void hc11_bitb_indy(); + void hc11_bcc(); + void hc11_bclr_dir(); + void hc11_bclr_indx(); + void hc11_bcs(); + void hc11_beq(); + void hc11_bhi(); + void hc11_bne(); + void hc11_ble(); + void hc11_bls(); + void hc11_bmi(); + void hc11_bpl(); + void hc11_bra(); + void hc11_brclr_dir(); + void hc11_brclr_indx(); + void hc11_brset_dir(); + void hc11_brset_indx(); + void hc11_brn(); + void hc11_bset_dir(); + void hc11_bset_indx(); + void hc11_bsr(); + void hc11_bvc(); + void hc11_bvs(); + void hc11_cba(); + void hc11_clc(); + void hc11_cli(); + void hc11_clra(); + void hc11_clrb(); + void hc11_clr_ext(); + void hc11_clr_indx(); + void hc11_clr_indy(); + void hc11_clv(); + void hc11_cmpa_imm(); + void hc11_cmpa_dir(); + void hc11_cmpa_ext(); + void hc11_cmpa_indx(); + void hc11_cmpa_indy(); + void hc11_cmpb_imm(); + void hc11_cmpb_dir(); + void hc11_cmpb_ext(); + void hc11_cmpb_indx(); + void hc11_cmpb_indy(); + void hc11_coma(); + void hc11_comb(); + void hc11_cpd_imm(); + void hc11_cpd_dir(); + void hc11_cpd_ext(); + void hc11_cpd_indx(); + void hc11_cpd_indy(); + void hc11_cpx_imm(); + void hc11_cpx_dir(); + void hc11_cpx_ext(); + void hc11_cpx_indx(); + void hc11_cpx_indy(); + void hc11_cpy_imm(); + void hc11_cpy_dir(); + void hc11_cpy_ext(); + void hc11_cpy_indx(); + void hc11_cpy_indy(); + void hc11_deca(); + void hc11_decb(); + void hc11_dec_ext(); + void hc11_dec_indx(); + void hc11_dec_indy(); + void hc11_dex(); + void hc11_dey(); + void hc11_eora_imm(); + void hc11_eora_dir(); + void hc11_eora_ext(); + void hc11_eora_indx(); + void hc11_eora_indy(); + void hc11_eorb_imm(); + void hc11_eorb_dir(); + void hc11_eorb_ext(); + void hc11_eorb_indx(); + void hc11_eorb_indy(); + void hc11_idiv(); + void hc11_inca(); + void hc11_incb(); + void hc11_inc_ext(); + void hc11_inc_indx(); + void hc11_inc_indy(); + void hc11_inx(); + void hc11_iny(); + void hc11_jmp_indx(); + void hc11_jmp_indy(); + void hc11_jmp_ext(); + void hc11_jsr_dir(); + void hc11_jsr_ext(); + void hc11_jsr_indx(); + void hc11_jsr_indy(); + void hc11_ldaa_imm(); + void hc11_ldaa_dir(); + void hc11_ldaa_ext(); + void hc11_ldaa_indx(); + void hc11_ldaa_indy(); + void hc11_ldab_imm(); + void hc11_ldab_dir(); + void hc11_ldab_ext(); + void hc11_ldab_indx(); + void hc11_ldab_indy(); + void hc11_ldd_imm(); + void hc11_ldd_dir(); + void hc11_ldd_ext(); + void hc11_ldd_indx(); + void hc11_ldd_indy(); + void hc11_lds_imm(); + void hc11_lds_dir(); + void hc11_lds_ext(); + void hc11_lds_indx(); + void hc11_lds_indy(); + void hc11_ldx_imm(); + void hc11_ldx_dir(); + void hc11_ldx_ext(); + void hc11_ldx_indx(); + void hc11_ldx_indy(); + void hc11_ldy_imm(); + void hc11_ldy_dir(); + void hc11_ldy_ext(); + void hc11_ldy_indx(); + void hc11_ldy_indy(); + void hc11_lsld(); + void hc11_lsra(); + void hc11_lsrb(); + void hc11_lsrd(); + void hc11_mul(); + void hc11_nega(); + void hc11_negb(); + void hc11_neg_ext(); + void hc11_neg_indx(); + void hc11_neg_indy(); + void hc11_nop(); + void hc11_psha(); + void hc11_oraa_imm(); + void hc11_oraa_dir(); + void hc11_oraa_ext(); + void hc11_oraa_indx(); + void hc11_oraa_indy(); + void hc11_orab_imm(); + void hc11_orab_dir(); + void hc11_orab_ext(); + void hc11_orab_indx(); + void hc11_orab_indy(); + void hc11_pshb(); + void hc11_pshx(); + void hc11_pshy(); + void hc11_pula(); + void hc11_pulb(); + void hc11_pulx(); + void hc11_puly(); + void hc11_rola(); + void hc11_rolb(); + void hc11_rol_ext(); + void hc11_rol_indx(); + void hc11_rol_indy(); + void hc11_rora(); + void hc11_rorb(); + void hc11_rti(); + void hc11_rts(); + void hc11_sba(); + void hc11_sbca_imm(); + void hc11_sbca_indx(); + void hc11_sbca_indy(); + void hc11_sbcb_imm(); + void hc11_sbcb_indx(); + void hc11_sbcb_indy(); + void hc11_sec(); + void hc11_sei(); + void hc11_sev(); + void hc11_staa_dir(); + void hc11_staa_ext(); + void hc11_staa_indx(); + void hc11_staa_indy(); + void hc11_stab_dir(); + void hc11_stab_ext(); + void hc11_stab_indx(); + void hc11_stab_indy(); + void hc11_std_dir(); + void hc11_std_ext(); + void hc11_std_indx(); + void hc11_std_indy(); + void hc11_sts_dir(); + void hc11_stx_dir(); + void hc11_stx_ext(); + void hc11_stx_indx(); + void hc11_stx_indy(); + void hc11_sty_dir(); + void hc11_sty_ext(); + void hc11_sty_indx(); + void hc11_sty_indy(); + void hc11_stop(); + void hc11_suba_imm(); + void hc11_suba_dir(); + void hc11_suba_ext(); + void hc11_suba_indx(); + void hc11_suba_indy(); + void hc11_subb_imm(); + void hc11_subb_dir(); + void hc11_subb_ext(); + void hc11_subb_indx(); + void hc11_subb_indy(); + void hc11_subd_imm(); + void hc11_subd_dir(); + void hc11_subd_ext(); + void hc11_subd_indx(); + void hc11_subd_indy(); + void hc11_swi(); + void hc11_tab(); + void hc11_tap(); + void hc11_tba(); + void hc11_test(); + void hc11_tpa(); + void hc11_tsta(); + void hc11_tstb(); + void hc11_tst_ext(); + void hc11_tst_indx(); + void hc11_tst_indy(); + void hc11_tsx(); + void hc11_tsy(); + void hc11_txs(); + void hc11_tys(); + void hc11_wai(); + void hc11_xgdx(); + void hc11_xgdy(); + void hc11_page2(); + void hc11_page3(); + void hc11_page4(); + void hc11_invalid(); + void check_irq_lines(); }; diff --git a/src/mame/drivers/30test.c b/src/mame/drivers/30test.c index d5e7867d931..c2a82d73ba3 100644 --- a/src/mame/drivers/30test.c +++ b/src/mame/drivers/30test.c @@ -232,13 +232,6 @@ void namco_30test_state::machine_reset() { } -static const hc11_config namco_30test_config = -{ - 0, //has extended internal I/O - 768, //internal RAM size - 0x00 //registers are at 0-0x100 -}; - static MACHINE_CONFIG_START( 30test, namco_30test_state ) @@ -246,7 +239,7 @@ static MACHINE_CONFIG_START( 30test, namco_30test_state ) MCFG_CPU_ADD("maincpu", MC68HC11,MAIN_CLOCK/4) MCFG_CPU_PROGRAM_MAP(namco_30test_map) MCFG_CPU_IO_MAP(namco_30test_io) - MCFG_CPU_CONFIG(namco_30test_config) + MCFG_MC68HC11_CONFIG( 0, 768, 0x00 ) /* no video! */ diff --git a/src/mame/drivers/hitpoker.c b/src/mame/drivers/hitpoker.c index b6f335b596f..e7d4195e798 100644 --- a/src/mame/drivers/hitpoker.c +++ b/src/mame/drivers/hitpoker.c @@ -480,12 +480,6 @@ static const ay8910_interface ay8910_config = DEVCB_NULL }; -static const hc11_config hitpoker_config = -{ - 0, //has extended internal I/O - 0x100, //internal RAM size - 0x01 //INIT defaults to 0x01 -}; INTERRUPT_GEN_MEMBER(hitpoker_state::hitpoker_irq) { @@ -496,7 +490,7 @@ static MACHINE_CONFIG_START( hitpoker, hitpoker_state ) MCFG_CPU_ADD("maincpu", MC68HC11,1000000) MCFG_CPU_PROGRAM_MAP(hitpoker_map) MCFG_CPU_IO_MAP(hitpoker_io) - MCFG_CPU_CONFIG(hitpoker_config) + MCFG_MC68HC11_CONFIG(0, 0x100, 0x01) MCFG_CPU_VBLANK_INT_DRIVER("screen", hitpoker_state, hitpoker_irq) MCFG_NVRAM_ADD_0FILL("nvram") diff --git a/src/mame/drivers/skeetsht.c b/src/mame/drivers/skeetsht.c index ece9832661b..a5deb53cac6 100644 --- a/src/mame/drivers/skeetsht.c +++ b/src/mame/drivers/skeetsht.c @@ -213,21 +213,6 @@ static INPUT_PORTS_START( skeetsht ) INPUT_PORTS_END -/************************************* - * - * 68HC11A1 configuration - * - *************************************/ - -static const hc11_config skeetsht_hc11_config = -{ - 0, - 0x100, /* 256 bytes RAM */ - 0x01, -// 0x200, /* 512 bytes EEPROM */ -}; - - /************************************* * * TMS34010 configuration @@ -260,7 +245,7 @@ static MACHINE_CONFIG_START( skeetsht, skeetsht_state ) MCFG_CPU_ADD("68hc11", MC68HC11, 4000000) // ? MCFG_CPU_PROGRAM_MAP(hc11_pgm_map) MCFG_CPU_IO_MAP(hc11_io_map) - MCFG_CPU_CONFIG(skeetsht_hc11_config) + MCFG_MC68HC11_CONFIG( 0, 0x100, 0x01 ) // And 512 bytes EEPROM? (68HC11A1) MCFG_CPU_ADD("tms", TMS34010, 48000000) MCFG_CPU_CONFIG(tms_config) diff --git a/src/mame/drivers/taitojc.c b/src/mame/drivers/taitojc.c index 538714e6dd9..675d9689154 100644 --- a/src/mame/drivers/taitojc.c +++ b/src/mame/drivers/taitojc.c @@ -1248,12 +1248,6 @@ static const tc0640fio_interface taitojc_io_intf = DEVCB_INPUT_PORT("START"), DEVCB_INPUT_PORT("UNUSED"), DEVCB_INPUT_PORT("BUTTONS") }; -static const hc11_config taitojc_hc11_config = -{ - 1, // has extended I/O - 1280, // internal RAM size - 0x00 // INIT defaults to 0x00 -}; static MACHINE_CONFIG_START( taitojc, taitojc_state ) @@ -1265,7 +1259,7 @@ static MACHINE_CONFIG_START( taitojc, taitojc_state ) MCFG_CPU_ADD("sub", MC68HC11, XTAL_16MHz/2) // 8MHz, MC68HC11M0 MCFG_CPU_PROGRAM_MAP(hc11_pgm_map) MCFG_CPU_IO_MAP(hc11_io_map) - MCFG_CPU_CONFIG(taitojc_hc11_config) + MCFG_MC68HC11_CONFIG( 1, 1280, 0x00 ) MCFG_CPU_ADD("dsp", TMS32051, XTAL_10MHz*4) // 40MHz, clock source = CY7C991 MCFG_CPU_PROGRAM_MAP(tms_program_map) diff --git a/src/mess/drivers/alphasma.c b/src/mess/drivers/alphasma.c index 3e87dd4f6e1..24d713a31fd 100644 --- a/src/mess/drivers/alphasma.c +++ b/src/mess/drivers/alphasma.c @@ -368,19 +368,12 @@ void alphasmart_state::machine_reset() m_port_d = 0; } -static const hc11_config alphasmart_hc11_config = -{ - 0, // has extended internal I/O - 0, // FIXME: should be 192, but the 68hc11 core doesn't handle internal RAM correctly - 0x00 // registers are at 0-0x3f -}; - static MACHINE_CONFIG_START( alphasmart, alphasmart_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", MC68HC11, XTAL_8MHz/2) // MC68HC11D0, XTAL is 8 Mhz, unknown divider MCFG_CPU_PROGRAM_MAP(alphasmart_mem) MCFG_CPU_IO_MAP(alphasmart_io) - MCFG_CPU_CONFIG(alphasmart_hc11_config) + MCFG_MC68HC11_CONFIG(0, 0, 0x00) // FIXME: internal ram should be 192, but the 68hc11 core doesn't handle internal RAM correctly MCFG_KS0066_F05_ADD("ks0066_0") MCFG_HD44780_LCD_SIZE(2, 40)