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h8_intc: base h8 does not have ISR

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This commit is contained in:
hap 2024-02-14 11:55:19 +01:00
parent 896f08157c
commit ecd1a49b2e
5 changed files with 29 additions and 33 deletions
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2
src/devices/cpu/h8/gt913.cpp
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@ -149,7 +149,7 @@ uint8_t gt913_device::uart_control_r(offs_t offset)
void gt913_device::syscr_w(uint8_t data)
{
// NMI active edge
m_intc->set_nmi_type(BIT(data, 2) ? h8_intc_device::EDGE_RISE : h8_intc_device::EDGE_FALL);
m_intc->set_nmi_edge(BIT(data, 2));
m_syscr = data;
}

2
src/devices/cpu/h8/h8325.cpp
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@ -221,7 +221,7 @@ void h8325_device::syscr_w(uint8_t data)
m_ram_view.disable();
// NMIEG
m_intc->set_nmi_type((data & 4) ? h8325_intc_device::EDGE_RISE : h8325_intc_device::EDGE_FALL);
m_intc->set_nmi_edge(BIT(data, 2));
// SSBY
m_standby_pending = bool(data & 0x80);

28
src/devices/cpu/h8/h8_intc.cpp
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@ -6,9 +6,6 @@
H8 interrupt controllers family
TODO:
- why is ISR in the base class? original H8 does not have this register
***************************************************************************/
#include "emu.h"
@ -32,7 +29,7 @@ h8_intc_device::h8_intc_device(const machine_config &mconfig, const char *tag, d
}
h8_intc_device::h8_intc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
device_t(mconfig, type, tag, owner, clock), m_irq_vector_base(0), m_irq_vector_count(0), m_irq_vector_nmi(0),
device_t(mconfig, type, tag, owner, clock), m_irq_vector_base(0), m_irq_vector_count(0), m_irq_vector_nmi(0), m_has_isr(false),
m_cpu(*this, finder_base::DUMMY_TAG), m_nmi_type(EDGE_FALL), m_nmi_input(false), m_irq_input(0), m_ier(0), m_isr(0), m_iscr(0), m_icr_filter(0), m_ipr_filter(0)
{
}
@ -121,6 +118,10 @@ void h8_intc_device::set_input(int inputnum, int state)
m_isr |= 1 << inputnum;
update_irq_state();
}
if(!m_has_isr) {
m_isr = 0;
check_level_irqs(!set);
}
}
}
@ -143,18 +144,17 @@ void h8_intc_device::ier_w(uint8_t data)
update_irq_state();
}
void h8_intc_device::check_level_irqs(bool force_update)
void h8_intc_device::check_level_irqs(bool update)
{
logerror("irq_input=%02x\n", m_irq_input);
bool update = force_update;
bool set = false;
for(int i=0; i<m_irq_vector_count; i++) {
uint8_t mask = 1 << i;
if(m_irq_type[i] == LEVEL_LOW && (m_irq_input & mask) && !(m_isr & mask)) {
m_isr |= mask;
update = true;
set = true;
}
}
if(update)
if(set && update)
update_irq_state();
}
@ -182,7 +182,7 @@ void h8_intc_device::update_irq_types()
m_irq_type[i] = EDGE_FALL;
break;
}
check_level_irqs();
check_level_irqs(true);
}
void h8_intc_device::update_irq_state()
@ -248,7 +248,7 @@ void h8325_intc_device::update_irq_types()
m_irq_type[i] = EDGE_RISE;
break;
}
check_level_irqs();
check_level_irqs(true);
}
@ -271,6 +271,7 @@ void h8h_intc_device::device_start()
{
h8_intc_device::device_start();
save_item(NAME(m_icr));
m_has_isr = true;
}
void h8h_intc_device::device_reset()
@ -288,7 +289,8 @@ void h8h_intc_device::isr_w(uint8_t data)
{
m_isr &= data; // edge/level
logerror("isr = %02x / %02x\n", data, m_isr);
check_level_irqs(true);
check_level_irqs(false);
update_irq_state();
}
uint8_t h8h_intc_device::icr_r(offs_t offset)
@ -419,7 +421,7 @@ void h8s_intc_device::update_irq_types()
m_irq_type[i] = EDGE_DUAL;
break;
}
check_level_irqs();
check_level_irqs(true);
}
const int h8s_intc_device::vector_to_slot[92] = {

18
src/devices/cpu/h8/h8_intc.h
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@ -17,13 +17,6 @@ class h8_device;
class h8_intc_device : public device_t {
public:
enum {
LEVEL_LOW, // ASSERT
EDGE_FALL, // CLEAR->ASSERT
EDGE_RISE, // ASSERT->CLEAR
EDGE_DUAL
};
h8_intc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
template<typename T> h8_intc_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu) :
h8_intc_device(mconfig, tag, owner)
@ -35,7 +28,7 @@ public:
void internal_interrupt(int vector);
void set_input(int inputnum, int state);
void set_filter(int icr_filter, int ipr_filter);
void set_nmi_type(int type) { m_nmi_type = type; }
void set_nmi_edge(int state) { m_nmi_type = state ? EDGE_RISE : EDGE_FALL; }
uint8_t ier_r();
void ier_w(uint8_t data);
@ -43,11 +36,18 @@ public:
void iscr_w(uint8_t data);
protected:
enum {
LEVEL_LOW, // ASSERT
EDGE_FALL, // CLEAR->ASSERT
EDGE_RISE, // ASSERT->CLEAR
EDGE_DUAL
};
enum { MAX_VECTORS = 256 };
int m_irq_vector_base;
int m_irq_vector_count;
int m_irq_vector_nmi;
bool m_has_isr;
required_device<h8_device> m_cpu;
@ -69,7 +69,7 @@ protected:
virtual void get_priority(int vect, int &icr_pri, int &ipr_pri) const;
void update_irq_state();
virtual void update_irq_types();
void check_level_irqs(bool force_update = false);
void check_level_irqs(bool update);
};
class h8325_intc_device : public h8_intc_device {

12
src/mame/saitek/gk2000.cpp
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@ -73,7 +73,6 @@ private:
void p4_w(u8 data);
u8 p5_r();
void p5_w(u8 data);
u8 p6_r();
void p6_w(u8 data);
u8 p7_r();
void p7_w(u8 data);
@ -190,12 +189,6 @@ void gk2000_state::p5_w(u8 data)
m_inp_mux = (m_inp_mux & 0xff) | (~data << 5 & 0x700);
}
u8 gk2000_state::p6_r()
{
//printf("r6 ");
return 0xff;
}
void gk2000_state::p6_w(u8 data)
{
//printf("w6_%X ",data);
@ -261,7 +254,8 @@ static INPUT_PORTS_START( gk2000 )
PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_K)
PORT_START("POWER")
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_Z) PORT_CHANGED_MEMBER(DEVICE_SELF, gk2000_state, go_button, 0) PORT_NAME("Go / Stop")
PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_Z) PORT_CHANGED_MEMBER(DEVICE_SELF, gk2000_state, go_button, 0) PORT_NAME("Go / Stop")
PORT_BIT(0xef, IP_ACTIVE_HIGH, IPT_UNUSED)
INPUT_PORTS_END
@ -287,7 +281,7 @@ void gk2000_state::gk2000(machine_config &config)
m_maincpu->write_port4().set(FUNC(gk2000_state::p4_w));
m_maincpu->read_port5().set(FUNC(gk2000_state::p5_r));
m_maincpu->write_port5().set(FUNC(gk2000_state::p5_w));
m_maincpu->read_port6().set(FUNC(gk2000_state::p6_r));
m_maincpu->read_port6().set_ioport("POWER").invert();
m_maincpu->write_port6().set(FUNC(gk2000_state::p6_w));
m_maincpu->read_port7().set(FUNC(gk2000_state::p7_r));
m_maincpu->write_port7().set(FUNC(gk2000_state::p7_w));