Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-24 17:30:55 +03:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

i386.cpp: correct pentium_smi (nw)

Browse Source 
In the poentium_smi() routine all calls to WRITE32 have the parameters swapped !
This commit is contained in:
S.Z 2017-12-10 12:17:52 +01:00 committed by GitHub
parent 35ae26c6b4
commit ed3bee03a7
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 51 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

102
src/devices/cpu/i386/i386.cpp
View File

@ -3788,59 +3788,59 @@ void i386_device::pentium_smi()
m_smi_latched = false;
// save state
WRITE32(m_cr[4], smram_state+SMRAM_IP5_CR4);
WRITE32(m_sreg[ES].limit, smram_state+SMRAM_IP5_ESLIM);
WRITE32(m_sreg[ES].base, smram_state+SMRAM_IP5_ESBASE);
WRITE32(m_sreg[ES].flags, smram_state+SMRAM_IP5_ESACC);
WRITE32(m_sreg[CS].limit, smram_state+SMRAM_IP5_CSLIM);
WRITE32(m_sreg[CS].base, smram_state+SMRAM_IP5_CSBASE);
WRITE32(m_sreg[CS].flags, smram_state+SMRAM_IP5_CSACC);
WRITE32(m_sreg[SS].limit, smram_state+SMRAM_IP5_SSLIM);
WRITE32(m_sreg[SS].base, smram_state+SMRAM_IP5_SSBASE);
WRITE32(m_sreg[SS].flags, smram_state+SMRAM_IP5_SSACC);
WRITE32(m_sreg[DS].limit, smram_state+SMRAM_IP5_DSLIM);
WRITE32(m_sreg[DS].base, smram_state+SMRAM_IP5_DSBASE);
WRITE32(m_sreg[DS].flags, smram_state+SMRAM_IP5_DSACC);
WRITE32(m_sreg[FS].limit, smram_state+SMRAM_IP5_FSLIM);
WRITE32(m_sreg[FS].base, smram_state+SMRAM_IP5_FSBASE);
WRITE32(m_sreg[FS].flags, smram_state+SMRAM_IP5_FSACC);
WRITE32(m_sreg[GS].limit, smram_state+SMRAM_IP5_GSLIM);
WRITE32(m_sreg[GS].base, smram_state+SMRAM_IP5_GSBASE);
WRITE32(m_sreg[GS].flags, smram_state+SMRAM_IP5_GSACC);
WRITE32(m_ldtr.flags, smram_state+SMRAM_IP5_LDTACC);
WRITE32(m_ldtr.limit, smram_state+SMRAM_IP5_LDTLIM);
WRITE32(m_ldtr.base, smram_state+SMRAM_IP5_LDTBASE);
WRITE32(m_gdtr.limit, smram_state+SMRAM_IP5_GDTLIM);
WRITE32(m_gdtr.base, smram_state+SMRAM_IP5_GDTBASE);
WRITE32(m_idtr.limit, smram_state+SMRAM_IP5_IDTLIM);
WRITE32(m_idtr.base, smram_state+SMRAM_IP5_IDTBASE);
WRITE32(m_task.limit, smram_state+SMRAM_IP5_TRLIM);
WRITE32(m_task.base, smram_state+SMRAM_IP5_TRBASE);
WRITE32(m_task.flags, smram_state+SMRAM_IP5_TRACC);
WRITE32(smram_state + SMRAM_IP5_CR4, m_cr[4]);
WRITE32(smram_state + SMRAM_IP5_ESLIM, m_sreg[ES].limit);
WRITE32(smram_state + SMRAM_IP5_ESBASE, m_sreg[ES].base);
WRITE32(smram_state + SMRAM_IP5_ESACC, m_sreg[ES].flags);
WRITE32(smram_state + SMRAM_IP5_CSLIM, m_sreg[CS].limit);
WRITE32(smram_state + SMRAM_IP5_CSBASE, m_sreg[CS].base);
WRITE32(smram_state + SMRAM_IP5_CSACC, m_sreg[CS].flags);
WRITE32(smram_state + SMRAM_IP5_SSLIM, m_sreg[SS].limit);
WRITE32(smram_state + SMRAM_IP5_SSBASE, m_sreg[SS].base);
WRITE32(smram_state + SMRAM_IP5_SSACC, m_sreg[SS].flags);
WRITE32(smram_state + SMRAM_IP5_DSLIM, m_sreg[DS].limit);
WRITE32(smram_state + SMRAM_IP5_DSBASE, m_sreg[DS].base);
WRITE32(smram_state + SMRAM_IP5_DSACC, m_sreg[DS].flags);
WRITE32(smram_state + SMRAM_IP5_FSLIM, m_sreg[FS].limit);
WRITE32(smram_state + SMRAM_IP5_FSBASE, m_sreg[FS].base);
WRITE32(smram_state + SMRAM_IP5_FSACC, m_sreg[FS].flags);
WRITE32(smram_state + SMRAM_IP5_GSLIM, m_sreg[GS].limit);
WRITE32(smram_state + SMRAM_IP5_GSBASE, m_sreg[GS].base);
WRITE32(smram_state + SMRAM_IP5_GSACC, m_sreg[GS].flags);
WRITE32(smram_state + SMRAM_IP5_LDTACC, m_ldtr.flags);
WRITE32(smram_state + SMRAM_IP5_LDTLIM, m_ldtr.limit);
WRITE32(smram_state + SMRAM_IP5_LDTBASE, m_ldtr.base);
WRITE32(smram_state + SMRAM_IP5_GDTLIM, m_gdtr.limit);
WRITE32(smram_state + SMRAM_IP5_GDTBASE, m_gdtr.base);
WRITE32(smram_state + SMRAM_IP5_IDTLIM, m_idtr.limit);
WRITE32(smram_state + SMRAM_IP5_IDTBASE, m_idtr.base);
WRITE32(smram_state + SMRAM_IP5_TRLIM, m_task.limit);
WRITE32(smram_state + SMRAM_IP5_TRBASE, m_task.base);
WRITE32(smram_state + SMRAM_IP5_TRACC, m_task.flags);
WRITE32(m_sreg[ES].selector, smram_state+SMRAM_ES);
WRITE32(m_sreg[CS].selector, smram_state+SMRAM_CS);
WRITE32(m_sreg[SS].selector, smram_state+SMRAM_SS);
WRITE32(m_sreg[DS].selector, smram_state+SMRAM_DS);
WRITE32(m_sreg[FS].selector, smram_state+SMRAM_FS);
WRITE32(m_sreg[GS].selector, smram_state+SMRAM_GS);
WRITE32(m_ldtr.segment, smram_state+SMRAM_LDTR);
WRITE32(m_task.segment, smram_state+SMRAM_TR);
WRITE32(smram_state + SMRAM_ES, m_sreg[ES].selector);
WRITE32(smram_state + SMRAM_CS, m_sreg[CS].selector);
WRITE32(smram_state + SMRAM_SS, m_sreg[SS].selector);
WRITE32(smram_state + SMRAM_DS, m_sreg[DS].selector);
WRITE32(smram_state + SMRAM_FS, m_sreg[FS].selector);
WRITE32(smram_state + SMRAM_GS, m_sreg[GS].selector);
WRITE32(smram_state + SMRAM_LDTR, m_ldtr.segment);
WRITE32(smram_state + SMRAM_TR, m_task.segment);
WRITE32(m_dr[7], smram_state+SMRAM_DR7);
WRITE32(m_dr[6], smram_state+SMRAM_DR6);
WRITE32(REG32(EAX), smram_state+SMRAM_EAX);
WRITE32(REG32(ECX), smram_state+SMRAM_ECX);
WRITE32(REG32(EDX), smram_state+SMRAM_EDX);
WRITE32(REG32(EBX), smram_state+SMRAM_EBX);
WRITE32(REG32(ESP), smram_state+SMRAM_ESP);
WRITE32(REG32(EBP), smram_state+SMRAM_EBP);
WRITE32(REG32(ESI), smram_state+SMRAM_ESI);
WRITE32(REG32(EDI), smram_state+SMRAM_EDI);
WRITE32(m_eip, smram_state+SMRAM_EIP);
WRITE32(old_flags, smram_state+SMRAM_EFLAGS);
WRITE32(m_cr[3], smram_state+SMRAM_CR3);
WRITE32(old_cr0, smram_state+SMRAM_CR0);
WRITE32(smram_state + SMRAM_DR7, m_dr[7]);
WRITE32(smram_state + SMRAM_DR6, m_dr[6]);
WRITE32(smram_state + SMRAM_EAX, REG32(EAX));
WRITE32(smram_state + SMRAM_ECX, REG32(ECX));
WRITE32(smram_state + SMRAM_EDX, REG32(EDX));
WRITE32(smram_state + SMRAM_EBX, REG32(EBX));
WRITE32(smram_state + SMRAM_ESP, REG32(ESP));
WRITE32(smram_state + SMRAM_EBP, REG32(EBP));
WRITE32(smram_state + SMRAM_ESI, REG32(ESI));
WRITE32(smram_state + SMRAM_EDI, REG32(EDI));
WRITE32(smram_state + SMRAM_EIP, m_eip);
WRITE32(smram_state + SMRAM_EFLAGS, old_flags);
WRITE32(smram_state + SMRAM_CR3, m_cr[3]);
WRITE32(smram_state + SMRAM_CR0, old_cr0);
m_sreg[DS].selector = m_sreg[ES].selector = m_sreg[FS].selector = m_sreg[GS].selector = m_sreg[SS].selector = 0;
m_sreg[DS].base = m_sreg[ES].base = m_sreg[FS].base = m_sreg[GS].base = m_sreg[SS].base = 0x00000000;