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Merge pull request #5543 from yukaritamura/chinagat_comment2
Add PCB layout for the second board, and information on TRJ-100
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R. Belmont
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@ -14,17 +14,16 @@ A couple of things unaccounted for:
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No backgrounds ROMs from the original board...
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No backgrounds ROMs from the original board...
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- TOSHIBA TRJ-100 installed at the second board should contain the image
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- TOSHIBA TRJ-100 installed at the second board should contain the image
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as U.S. Championship V'Ball has a TRJ-101 that contains it. A custom made
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as U.S. Championship V'Ball has a TRJ-101 that contains it. It also contains
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adapter is needed to dump it.
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related logic to generate 16-bits address and to decode pixels at 6MHz pixel
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clock, based on given attributes in multicycles, screen flip flag, and clocks.
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It seems almost equivalent to Double Dragon's IC38, 39, 40, 53, 54, and all
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logic in the page 9 of the schematics for the second board.
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- Got two bootleg sets with background gfx roms. Using those on the
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- Got two bootleg sets with background gfx roms. Using those on the
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original games for now.
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original games for now.
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OBVIOUS SPEED PROBLEMS...
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OBVIOUS SPEED PROBLEMS...
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- Timers are too fast and/or too slow, and the whole thing's moving too fast
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- Timers are too fast and/or too slow, and the whole thing's moving too fast
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- TRJ-100 is accessed at about 3MHz speed, but seems to generate 5MHz clock
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internally. This clock is exposed at the pin 22, and used as a clock at least
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for some shifter ICs, such as IC110, 111, 112, and 113. Timers might be based
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on this 5MHz clock, too?
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Port 0x2800 on the Sub CPU.
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Port 0x2800 on the Sub CPU.
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- All those I/O looking ports on the main CPU (0x3exx and 0x3fxx)
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- All those I/O looking ports on the main CPU (0x3exx and 0x3fxx)
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@ -69,6 +68,114 @@ Input is unique but has a few similarities to DD2 (the coin inputs)
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2008-07
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2008-07
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Dip locations and factory settings verified with China Gate US manual.
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Dip locations and factory settings verified with China Gate US manual.
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PCB Layout
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----------
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TA-0023-P2-03 (Video Board)
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|-----------------------------------------------------|
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| | J2 | | J1 | |
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| ---------------- ---------------- |
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| 23JB-0 IC7 |
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| X1 |
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| IC40 |
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| |------------|
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| IC70 |1 |
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| IC78 IC75 | TRJ-100 |
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| |32 |
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| |------------|
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| IC106 23J7-0 23J8-0 23J9-0 23JA-0 |
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|-----------------------------------------------------|
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Clock
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X1 - 12MHz
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PROM
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23JB-0 - user1 (82S131)
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ROMs
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23J7-0 - gfx2 mask ROM
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23J8-0 - gfx2 mask ROM
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23J9-0 - gfx2 mask ROM
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23JA-0 - gfx2 mask ROM
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TJR-100 - gfx3 custom ROM (undump)
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SRAMs (2KBx8bits) Motorola MCM2016HN55, SANYO LC3517?
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IC7 - ?
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IC40 - bgvideoram
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IC70 - ?
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IC75 - ?
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IC78 - ?
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IC106 - ?
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Connectors
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J1, J2 - 50pins, almost same assignments with ones for Double Dragon.
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At this moment, 17pin is known to be used for TRJ-100.
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TRJ-100 pin assigns
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-------------------
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Following assignments are estimated based on the circuit around the TRJ-100 in
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comparison with one for Double Dragon.
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/M2H2 clock is special for this PCB, and M2H is used in Double Dragon instead.
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This signal is created by NAND with M2H (1.5MHz) and MH (3MHz).
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Following pictures show each clock timing. '%' is the timing to latch AT[7:0]
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by these clocks.
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_ ________
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/M2H2 - _\__/% _____\ duty 1:3, 1.5MHz
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/M2H - \_____/% \ duty 1:1, 1.5MHz, inverted
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_____
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M2H - /% \_____/ duty 1:1, 1.5MHz
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1 - VCC
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2 I /M2H - inverted 1.5MHz, used to latch AT[7:0] for A[13:6]
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3 I AT0 - connected with bgvideoram d0, used as A6 and A14
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4 I AT1 - connected with bgvideoram d1, used as A7 and A15
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5 I AT2 - connected with bgvideoram d2, used as A8 and A16
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6 I AT3 - connected with bgvideoram d3, used as A9 and BPL0
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7 I AT4 - connected with bgvideoram d4, used as A10 and BPL1
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8 I AT5 - connected with bgvideoram d5, used as A11 and BPL2
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9 I AT6 - connected with bgvideoram d6, used as A12 and BINV
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10 I AT7 - connected with bgvideoram d7, used as A13 and BPA
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11 I /M2H2 - /(M2H & MH), used to latch AT[7:0] for A[16:14], BPL, BIN, and BPA
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12 O BPAL0 - connected with J2 26pin
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13 O BPAL1 - connected with J2 24pin
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14 O BPAL2 - connected with J2 22pin
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15 O BPRT - connected with J2 20pin
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16 I /CE? - connected with J1 17pin, always LOW as far as it's observed
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17 I BHP3 - back horizontal (y) position 0, used to select output
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18 I /1P - screen flip
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19 I BHP0 - back horizontal (y) position 1, used to select output
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20 I BHP1 - back horizontal (y) position 2, used as A5
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21 I BHP2 - back horizontal (y) position 3, used as A6
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22 I /HCLK - inverted 6MHZ clock, used as a pixel clock to shift output
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23 I BVP0 - back vertical (x) position 0, used as A0
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24 I BVP1 - back vertical (x) position 1, used as A1
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25 I BVP2 - back vertical (x) position 2, used as A2
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26 I BVP3 - back vertical (x) position 3, used as A3
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27 O BCOL0 - connected with J2 34pin
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28 O BCOL1 - connected with J2 32pin
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29 O BCOL2 - connected with J2 30pin
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30 O BCOL3 - connected with J2 28pin
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31 GND
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32 GND
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*/
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*/
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#include "emu.h"
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#include "emu.h"
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