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video/pc_vga_paradise.cpp: convert EGASW/CNF(15)-CNF(12) as externally settable pins

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This commit is contained in:
angelosa 2024-09-01 14:37:43 +02:00
parent 1fed840710
commit ed6cccf74a
5 changed files with 60 additions and 9 deletions
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2
src/devices/bus/isa/svga_paradise.cpp
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@ -10,7 +10,7 @@ TODO:
that aren't covered in current dumps;
\- Specifically they do:
000C03AB: cmp word ptr [10h],0h ; wd90c00 == 0x3000
000C03B0: 75 09 jne 0C03BBh
000C03B0: jne 0C03BBh
000C03B2: cmp byte ptr [12h],7Eh ; wd90c00 == 0x00
000C03B7: jne 0C03BBh
000C03B9: pop ds

3
src/devices/bus/isa/svga_paradise.h
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@ -89,6 +89,9 @@ public:
// construction/destruction
isa16_wd90c00_jk_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// resets itself at card POST for accessing $c6xxx area, plays with input sense later
static constexpr feature_type unemulated_features() { return feature::PROTECTION; }
protected:
// device-level overrides
virtual void device_start() override;

6
src/devices/bus/pci/geforce.h
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@ -17,6 +17,9 @@ class geforce256_device : public rivatnt2_device
public:
geforce256_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// ELSA protection
static constexpr feature_type unemulated_features() { return feature::PROTECTION; }
protected:
geforce256_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
@ -38,6 +41,9 @@ class quadro_device : public geforce256_device
public:
quadro_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// ELSA protection
static constexpr feature_type unemulated_features() { return feature::PROTECTION; }
protected:
virtual const tiny_rom_entry *device_rom_region() const override;
};

37
src/devices/video/pc_vga_paradise.cpp
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@ -277,8 +277,8 @@ void pvga1a_vga_device::video_control_w(offs_t offset, u8 data)
/*
* [0x0f] PR5 Lock/Status
*
* xxxx ---- MD7/MD4 config reads
* ---- x--- MD8 config read (on later chipsets)
* xxxx ---- CNF(7)-CNF(4) / MD7/MD4 config reads
* ---- x--- CNF(8) / MD8 config read (on later chipsets)
* ---- -xxx lock register
* ---- -101 unlock, any other value locks r/w to the extensions
*/
@ -301,6 +301,10 @@ void pvga1a_vga_device::ext_gc_unlock_w(offs_t offset, u8 data)
wd90c00_vga_device::wd90c00_vga_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: pvga1a_vga_device(mconfig, type, tag, owner, clock)
, m_cnf15_read_cb(*this, 1)
, m_cnf14_read_cb(*this, 1)
, m_cnf13_read_cb(*this, 1)
, m_cnf12_read_cb(*this, 1)
{
m_crtc_space_config = address_space_config("crtc_regs", ENDIANNESS_LITTLE, 8, 8, 0, address_map_constructor(FUNC(wd90c00_vga_device::crtc_map), this));
}
@ -317,13 +321,32 @@ void wd90c00_vga_device::device_reset()
m_pr10_scratch = 0;
m_ext_crtc_read_unlock = false;
m_ext_crtc_write_unlock = false;
m_egasw = 0xf0;
// egasw
m_pr11 = (m_cnf15_read_cb() << 7) | (m_cnf14_read_cb() << 6) | m_cnf13_read_cb() << 5 | m_cnf12_read_cb() << 4;
m_interlace_start = 0;
m_interlace_end = 0;
m_interlace_mode = false;
m_pr15 = 0;
}
CUSTOM_INPUT_MEMBER(wd90c00_vga_device::egasw1_r) { return BIT(m_pr11, 4); }
CUSTOM_INPUT_MEMBER(wd90c00_vga_device::egasw2_r) { return BIT(m_pr11, 5); }
CUSTOM_INPUT_MEMBER(wd90c00_vga_device::egasw3_r) { return BIT(m_pr11, 6); }
CUSTOM_INPUT_MEMBER(wd90c00_vga_device::egasw4_r) { return BIT(m_pr11, 7); }
static INPUT_PORTS_START(paradise_vga_sense)
PORT_START("VGA_SENSE")
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_CUSTOM_MEMBER(wd90c00_vga_device, egasw1_r)
PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_CUSTOM_MEMBER(wd90c00_vga_device, egasw2_r)
PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_CUSTOM_MEMBER(wd90c00_vga_device, egasw3_r)
PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_CUSTOM_MEMBER(wd90c00_vga_device, egasw4_r)
INPUT_PORTS_END
ioport_constructor wd90c00_vga_device::device_input_ports() const
{
return INPUT_PORTS_NAME(paradise_vga_sense);
}
u8 wd90c00_vga_device::crtc_data_r(offs_t offset)
{
if (!m_ext_crtc_read_unlock && vga.crtc.index >= 0x2a && !machine().side_effects_disabled())
@ -415,6 +438,7 @@ void wd90c00_vga_device::ext_crtc_unlock_w(offs_t offset, u8 data)
* [0x2a] PR11 EGA Switches
*
* xxxx ---- EGA switches (MD15-MD12), latches high if written to.
* CONF15-12 on 'C26 for panel support. Pulling up will latch high these pins.
* ---- x--- EGA emulation on Analog Display
* ---- -x-- Lock Clock Select (disables external chip select for VCLK1)
* ---- --x- Locks GC $5 bits 6:5, sequencer $1 bits 5:2, sequencer $3 bits 5:0
@ -422,15 +446,14 @@ void wd90c00_vga_device::ext_crtc_unlock_w(offs_t offset, u8 data)
*/
u8 wd90c00_vga_device::egasw_r(offs_t offset)
{
const u8 ega_config = (m_input_sense->read() << 4);
LOG("PR11 EGA Switch R (%02x | %02x)\n", ega_config, m_egasw);
return (ega_config | m_egasw);
LOG("PR11 EGA Switch R (%02x)\n", m_pr11);
return m_pr11;
}
void wd90c00_vga_device::egasw_w(offs_t offset, u8 data)
{
LOG("PR11 EGA Switch W %02x\n", data);
m_egasw = data & 0xff;
m_pr11 = data & 0xff;
}
/*

21
src/devices/video/pc_vga_paradise.h
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@ -54,6 +54,18 @@ class wd90c00_vga_device : public pvga1a_vga_device
public:
wd90c00_vga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// TODO: backport to original PVGA1A
// claims these as CNF(7)-CNF(4), which implies input sense read from GC register instead.
auto read_cnf15_callback() { return m_cnf15_read_cb.bind(); }
auto read_cnf14_callback() { return m_cnf14_read_cb.bind(); }
auto read_cnf13_callback() { return m_cnf13_read_cb.bind(); }
auto read_cnf12_callback() { return m_cnf12_read_cb.bind(); }
// NOTE: these are internal shadows, for the input sense.
CUSTOM_INPUT_MEMBER(egasw4_r);
CUSTOM_INPUT_MEMBER(egasw3_r);
CUSTOM_INPUT_MEMBER(egasw2_r);
CUSTOM_INPUT_MEMBER(egasw1_r);
protected:
wd90c00_vga_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
@ -64,6 +76,8 @@ protected:
virtual bool get_interlace_mode() override { return m_interlace_mode; }
virtual ioport_constructor device_input_ports() const override;
private:
virtual u8 crtc_data_r(offs_t offset) override;
virtual void crtc_data_w(offs_t offset, u8 data) override;
@ -80,11 +94,16 @@ private:
bool m_ext_crtc_read_unlock = false;
bool m_ext_crtc_write_unlock = false;
u8 m_pr10_scratch = 0;
u8 m_egasw = 0;
u8 m_pr11 = 0;
u8 m_interlace_start = 0;
u8 m_interlace_end = 0;
bool m_interlace_mode = 0;
u8 m_pr15 = 0;
devcb_read_line m_cnf15_read_cb;
devcb_read_line m_cnf14_read_cb;
devcb_read_line m_cnf13_read_cb;
devcb_read_line m_cnf12_read_cb;
};
class wd90c11a_vga_device : public wd90c00_vga_device