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i386: Fixed BSR/BSF and CMPS based on test-i386 output.
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3b305c1800
commit
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@ -1060,7 +1060,7 @@ static void i286_task_switch(i386_state *cpustate, UINT16 selector, UINT8 nested
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CHANGE_PC(cpustate,cpustate->eip);
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CHANGE_PC(cpustate,cpustate->eip);
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cpustate->CPL = cpustate->sreg[CS].selector & 0x03;
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cpustate->CPL = cpustate->sreg[CS].selector & 0x03;
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printf("286 Task Switch from selector %04x to %04x\n",old_task,selector);
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// printf("286 Task Switch from selector %04x to %04x\n",old_task,selector);
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}
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}
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static void i386_task_switch(i386_state *cpustate, UINT16 selector, UINT8 nested)
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static void i386_task_switch(i386_state *cpustate, UINT16 selector, UINT8 nested)
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@ -1175,7 +1175,7 @@ static void i386_task_switch(i386_state *cpustate, UINT16 selector, UINT8 nested
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CHANGE_PC(cpustate,cpustate->eip);
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CHANGE_PC(cpustate,cpustate->eip);
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cpustate->CPL = cpustate->sreg[CS].selector & 0x03;
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cpustate->CPL = cpustate->sreg[CS].selector & 0x03;
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printf("386 Task Switch from selector %04x to %04x\n",old_task,selector);
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// printf("386 Task Switch from selector %04x to %04x\n",old_task,selector);
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}
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}
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static void i386_check_irq_line(i386_state *cpustate)
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static void i386_check_irq_line(i386_state *cpustate)
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@ -287,9 +287,9 @@ static void I386OP(bsf_r16_rm16)(i386_state *cpustate) // Opcode 0x0f bc
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dst = temp;
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dst = temp;
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CYCLES(cpustate,CYCLES_BSF);
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CYCLES(cpustate,CYCLES_BSF);
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}
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}
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STORE_REG16(modrm, dst);
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}
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}
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CYCLES(cpustate,CYCLES_BSF_BASE);
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CYCLES(cpustate,CYCLES_BSF_BASE);
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STORE_REG16(modrm, dst);
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}
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}
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static void I386OP(bsr_r16_rm16)(i386_state *cpustate) // Opcode 0x0f bd
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static void I386OP(bsr_r16_rm16)(i386_state *cpustate) // Opcode 0x0f bd
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@ -316,9 +316,9 @@ static void I386OP(bsr_r16_rm16)(i386_state *cpustate) // Opcode 0x0f bd
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dst = temp;
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dst = temp;
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CYCLES(cpustate,CYCLES_BSR);
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CYCLES(cpustate,CYCLES_BSR);
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}
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}
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STORE_REG16(modrm, dst);
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}
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}
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CYCLES(cpustate,CYCLES_BSR_BASE);
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CYCLES(cpustate,CYCLES_BSR_BASE);
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STORE_REG16(modrm, dst);
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}
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}
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@ -552,7 +552,7 @@ static void I386OP(cmpsw)(i386_state *cpustate) // Opcode 0xa7
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ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) );
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ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) );
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src = READ16(cpustate,eas);
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src = READ16(cpustate,eas);
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dst = READ16(cpustate,ead);
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dst = READ16(cpustate,ead);
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SUB16(cpustate,dst, src);
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SUB16(cpustate,src,dst);
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BUMP_SI(cpustate,2);
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BUMP_SI(cpustate,2);
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BUMP_DI(cpustate,2);
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BUMP_DI(cpustate,2);
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CYCLES(cpustate,CYCLES_CMPS);
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CYCLES(cpustate,CYCLES_CMPS);
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@ -289,9 +289,9 @@ static void I386OP(bsf_r32_rm32)(i386_state *cpustate) // Opcode 0x0f bc
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dst = temp;
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dst = temp;
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CYCLES(cpustate,CYCLES_BSF);
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CYCLES(cpustate,CYCLES_BSF);
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}
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}
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STORE_REG32(modrm, dst);
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}
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}
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CYCLES(cpustate,CYCLES_BSF_BASE);
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CYCLES(cpustate,CYCLES_BSF_BASE);
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STORE_REG32(modrm, dst);
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}
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}
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static void I386OP(bsr_r32_rm32)(i386_state *cpustate) // Opcode 0x0f bd
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static void I386OP(bsr_r32_rm32)(i386_state *cpustate) // Opcode 0x0f bd
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@ -318,9 +318,9 @@ static void I386OP(bsr_r32_rm32)(i386_state *cpustate) // Opcode 0x0f bd
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dst = temp;
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dst = temp;
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CYCLES(cpustate,CYCLES_BSR);
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CYCLES(cpustate,CYCLES_BSR);
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}
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}
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STORE_REG32(modrm, dst);
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}
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}
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CYCLES(cpustate,CYCLES_BSR_BASE);
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CYCLES(cpustate,CYCLES_BSR_BASE);
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STORE_REG32(modrm, dst);
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}
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}
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static void I386OP(bt_rm32_r32)(i386_state *cpustate) // Opcode 0x0f a3
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static void I386OP(bt_rm32_r32)(i386_state *cpustate) // Opcode 0x0f a3
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@ -548,7 +548,7 @@ static void I386OP(cmpsd)(i386_state *cpustate) // Opcode 0xa7
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ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) );
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ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) );
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src = READ32(cpustate,eas);
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src = READ32(cpustate,eas);
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dst = READ32(cpustate,ead);
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dst = READ32(cpustate,ead);
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SUB32(cpustate,dst, src);
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SUB32(cpustate,src,dst);
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BUMP_SI(cpustate,4);
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BUMP_SI(cpustate,4);
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BUMP_DI(cpustate,4);
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BUMP_DI(cpustate,4);
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CYCLES(cpustate,CYCLES_CMPS);
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CYCLES(cpustate,CYCLES_CMPS);
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