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https://github.com/holub/mame
synced 2025-06-04 20:06:28 +03:00
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This commit is contained in:
Angelo Salese
parent
c32493ce46
commit
edb88ffe18
@ -13,7 +13,6 @@
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const device_type SCUDSP = &device_creator<scudsp_cpu_device>;
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/* FLAGS */
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#define PRF m_flags & 0x04000000
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#define EPF m_flags & 0x02000000
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@ -27,14 +26,117 @@ const device_type SCUDSP = &device_creator<scudsp_cpu_device>;
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#define EXF m_flags & 0x00010000 // execute flag (basically tied to RESET pin)
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#define LEF m_flags & 0x00008000 // change PC value
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#define FLAGS_MASK 0x06ff8000
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#define scudsp_readop(A) m_program->read_dword(A << 2)
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#define scudsp_writeop(A, B) m_program->write_dword(A << 2, B)
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#define scudsp_readmem(A,MD) m_data->read_dword((A | MD << 6) << 2)
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#define scudsp_writemem(A,MD,B) m_data->write_dword((A | MD << 6) << 2, B)
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UINT32 scudsp_cpu_device::scudsp_get_source_mem_value(UINT8 mode)
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{
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UINT32 value = 0;
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switch( mode )
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{
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case 0x0: /* M0 */
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value = scudsp_readmem(m_ct0,0);
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break;
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case 0x1: /* M1 */
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value = scudsp_readmem(m_ct1,1);
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break;
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case 0x2: /* M2 */
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value = scudsp_readmem(m_ct2,2);
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break;
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case 0x3: /* M3 */
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value = scudsp_readmem(m_ct3,3);
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break;
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case 0x4: /* MC0 */
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value = scudsp_readmem(m_ct0++,0);
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m_ct0 &= 0x3f;
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break;
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case 0x5: /* MC1 */
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value = scudsp_readmem(m_ct1++,1);
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m_ct1 &= 0x3f;
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break;
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case 0x6: /* MC2 */
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value = scudsp_readmem(m_ct2++,2);
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m_ct2 &= 0x3f;
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break;
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case 0x7: /* MC3 */
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value = scudsp_readmem(m_ct3++,3);
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m_ct3 &= 0x3f;
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break;
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}
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return value;
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}
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void scudsp_cpu_device::scudsp_set_dest_mem_reg( UINT32 mode, UINT32 value )
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{
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switch( mode )
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{
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case 0x0: /* MC0 */
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scudsp_writemem(m_ct0++,0,value);
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m_ct0 &= 0x3f;
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break;
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case 0x1: /* MC1 */
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scudsp_writemem(m_ct1++,1,value);
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m_ct1 &= 0x3f;
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break;
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case 0x2: /* MC2 */
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scudsp_writemem(m_ct2++,2,value);
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m_ct2 &= 0x3f;
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break;
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case 0x3: /* MC3 */
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scudsp_writemem(m_ct3++,3,value);
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m_ct3 &= 0x3f;
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break;
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#if 0
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case 0x4: /* RX */
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dsp_reg.rx.ui = value;
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update_mul = 1;
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break;
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case 0x5: /* PL */
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dsp_reg.pl.ui = value;
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dsp_reg.ph.si = (dsp_reg.pl.si < 0) ? -1 : 0;
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break;
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case 0x6: /* RA0 */
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dsp_reg.ra0 = value;
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break;
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case 0x7: /* WA0 */
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dsp_reg.wa0 = value;
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break;
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case 0x8:
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case 0x9:
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/* ??? */
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break;
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case 0xa: /* LOP */
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dsp_reg.lop = value;
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break;
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case 0xb: /* TOP */
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dsp_reg.top = value;
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break;
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case 0xc: /* CT0 */
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dsp_reg.ct0 = value & 0x3f;
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break;
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case 0xd: /* CT1 */
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dsp_reg.ct1 = value & 0x3f;
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break;
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case 0xe: /* CT2 */
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dsp_reg.ct2 = value & 0x3f;
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break;
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case 0xf: /* CT3 */
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dsp_reg.ct3 = value & 0x3f;
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break;
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#endif
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}
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}
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#define scudsp_readop(A) m_program->read_dword(A)
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#define scudsp_readmem16(A) m_data->read_dword(A)
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#define scudsp_writemem16(A,B) m_data->write_dword((A),B)
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READ32_MEMBER( scudsp_cpu_device::program_control_r )
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{
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return (m_pc & 0xff) | (m_flags & 0xffffff00);
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return (m_pc & 0xff) | (m_flags & FLAGS_MASK);
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}
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WRITE32_MEMBER( scudsp_cpu_device::program_control_w )
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@ -45,14 +147,49 @@ WRITE32_MEMBER( scudsp_cpu_device::program_control_w )
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newval = oldval;
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COMBINE_DATA(&newval);
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m_flags = newval & 0xffffff00;
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m_flags = newval & FLAGS_MASK;
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if(LEF)
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m_pc = newval & 0xff;
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//printf("%08x PRG CTRL\n",data);
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set_input_line(INPUT_LINE_RESET, (EXF) ? CLEAR_LINE : ASSERT_LINE);
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}
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WRITE32_MEMBER( scudsp_cpu_device::program_w )
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{
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//printf("%02x %08x PRG\n",m_pc,data);
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scudsp_writeop(m_pc++, data);
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}
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WRITE32_MEMBER( scudsp_cpu_device::ram_address_control_w )
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{
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//printf("%02x %08x PRG\n",m_pc,data);
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m_ra = data & 0xff;
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switch((m_ra & 0xc0) >> 6)
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{
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case 0: m_ct0 = (m_ra & 0x3f); break;
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case 1: m_ct1 = (m_ra & 0x3f); break;
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case 2: m_ct2 = (m_ra & 0x3f); break;
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case 3: m_ct3 = (m_ra & 0x3f); break;
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}
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}
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READ32_MEMBER( scudsp_cpu_device::ram_address_r )
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{
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UINT32 data;
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data = scudsp_get_source_mem_value( ((m_ra & 0xc0) >> 6) + 4 );
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return data;
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}
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WRITE32_MEMBER( scudsp_cpu_device::ram_address_w )
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{
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scudsp_set_dest_mem_reg( (m_ra & 0xc0) >> 6, data );
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}
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/***********************************
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* illegal opcodes
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***********************************/
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@ -91,22 +228,31 @@ void scudsp_cpu_device::device_start()
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m_data = &space(AS_DATA);
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save_item(NAME(m_pc));
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save_item(NAME(m_ra));
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save_item(NAME(m_ct0));
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save_item(NAME(m_ct1));
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save_item(NAME(m_ct2));
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save_item(NAME(m_ct3));
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save_item(NAME(m_flags));
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save_item(NAME(m_reset_state));
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// Register state for debugger
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state_add( SCUDSP_PC, "PC", m_pc ).formatstr("%02X");
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state_add( SCUDSP_FLAGS, "SR", m_flags ).formatstr("%08X");
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state_add( SCUDSP_RA, "RA", m_ra ).formatstr("%02X");
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state_add( SCUDSP_CT0, "CT0", m_ct0 ).formatstr("%02X");
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state_add( SCUDSP_CT1, "CT1", m_ct1 ).formatstr("%02X");
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state_add( SCUDSP_CT2, "CT2", m_ct2 ).formatstr("%02X");
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state_add( SCUDSP_CT3, "CT3", m_ct3 ).formatstr("%02X");
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state_add( STATE_GENPC, "curpc", m_pc ).noshow();
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state_add( STATE_GENFLAGS, "GENFLAGS", m_flags ).noshow();
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state_add( STATE_GENFLAGS, "GENFLAGS", m_flags ).formatstr("%17s").noshow();
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m_icountptr = &m_icount;
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}
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void scudsp_cpu_device::device_reset()
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{
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/* This is how we set the reset vector */
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//set_input_line(CP1610_RESET, PULSE_LINE);
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}
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void scudsp_cpu_device::execute_set_input(int irqline, int state)
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@ -122,7 +268,7 @@ void scudsp_cpu_device::execute_set_input(int irqline, int state)
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scudsp_cpu_device::scudsp_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: cpu_device(mconfig, SCUDSP, "SCUDSP", tag, owner, clock, "scudsp", __FILE__)
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, m_program_config("program", ENDIANNESS_BIG, 32, 8, -2)
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, m_data_config("data", ENDIANNESS_BIG, 32, 8, 0)
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, m_data_config("data", ENDIANNESS_BIG, 32, 8, -2)
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{
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}
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@ -132,11 +278,18 @@ void scudsp_cpu_device::state_string_export(const device_state_entry &entry, ast
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switch (entry.index())
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{
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case STATE_GENFLAGS:
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string.printf("%c%c%c%c",
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m_flags & 0x80 ? 'S':'.',
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m_flags & 0x40 ? 'Z':'.',
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m_flags & 0x20 ? 'V':'.',
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m_flags & 0x10 ? 'C':'.');
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string.printf("%s%s%s%c%c%c%c%c%s%s%s",
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m_flags & 0x4000000 ? "PR":"..",
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m_flags & 0x2000000 ? "EP":"..",
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m_flags & 0x800000 ? "T0":"..",
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m_flags & 0x400000 ? 'S':'.',
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m_flags & 0x200000 ? 'Z':'.',
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m_flags & 0x100000 ? 'C':'.',
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m_flags & 0x80000 ? 'V':'.',
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m_flags & 0x40000 ? 'E':'.',
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m_flags & 0x20000 ? "ES":"..",
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m_flags & 0x10000 ? "EX":"..",
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m_flags & 0x8000 ? "LE":"..");
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break;
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}
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}
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@ -13,7 +13,9 @@
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enum
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{
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SCUDSP_PC=1, SCUDSP_FLAGS
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SCUDSP_RA=1,
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SCUDSP_CT0, SCUDSP_CT1, SCUDSP_CT2, SCUDSP_CT3,
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SCUDSP_PC, SCUDSP_FLAGS
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};
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#define SCUDSP_RESET INPUT_LINE_RESET /* Non-Maskable */
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@ -25,9 +27,16 @@ public:
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// construction/destruction
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scudsp_cpu_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
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/* port 0 */
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DECLARE_READ32_MEMBER( program_control_r );
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DECLARE_WRITE32_MEMBER( program_control_w );
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/* port 1 */
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DECLARE_WRITE32_MEMBER( program_w );
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/* port 2 */
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DECLARE_WRITE32_MEMBER( ram_address_control_w );
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/* port 3 */
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DECLARE_READ32_MEMBER( ram_address_r );
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DECLARE_WRITE32_MEMBER( ram_address_w );
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// virtual DECLARE_ADDRESS_MAP(map, 32) = 0;
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protected:
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@ -59,13 +68,16 @@ private:
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UINT8 m_pc; /* registers */
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UINT32 m_flags; /* flags */
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UINT8 m_ra;
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UINT8 m_ct0,m_ct1,m_ct2,m_ct3; /*Index for RAM*/ /*6-bits */
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int m_reset_state;
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address_space *m_program;
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address_space *m_data;
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int m_icount;
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UINT32 scudsp_get_source_mem_value(UINT8 mode);
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void scudsp_set_dest_mem_reg( UINT32 mode, UINT32 value );
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void scudsp_illegal();
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};
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@ -2,19 +2,324 @@
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#include "debugger.h"
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#include "scudsp.h"
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static const char *const ALU_Commands[] =
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{
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"", /* 0000 */
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"AND", /* 0001 */
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"OR", /* 0010 */
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"XOR", /* 0011 */
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"ADD", /* 0100 */
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"SUB", /* 0101 */
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"AD2", /* 0110 */
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"???", /* 0111 */
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"SR", /* 1000 */
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"RR", /* 1001 */
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"SL", /* 1010 */
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"RL", /* 1011 */
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"???", /* 1100 */
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"???", /* 1101 */
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"???", /* 1110 */
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"RL8", /* 1111 */
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};
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static const char *const X_Commands[] =
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{
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"", /* 000 */
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"", /* 001 */ /* NOP? check instruction @ 0x0B */
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"MOV MUL,P", /* 010 */
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"MOV %s,P", /* 011 */
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"MOV %s,X", /* 100 */
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};
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static const char *const Y_Commands[] =
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{
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"", /* 000 */
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"CLR A", /* 001 */
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"MOV ALU,A", /* 010 */
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"MOV %s,A", /* 011 */
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"MOV %s,Y", /* 100 */
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};
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static const char *const D1_Commands[] =
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{
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"", /* 00 */
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"MOV %I8,%d", /* 01 */
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"???", /* 10 */
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"MOV %S,%d", /* 11 */
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};
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static const char *const SourceMemory[] =
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{
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"M0", /* 000 */
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"M1", /* 001 */
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"M2", /* 010 */
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"M3", /* 011 */
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"MC0", /* 100 */
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"MC1", /* 101 */
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"MC2", /* 110 */
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"MC3", /* 111 */
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};
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static const char *const SourceMemory2[] =
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{
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"M0", /* 0000 */
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"M1", /* 0001 */
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"M2", /* 0010 */
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"M3", /* 0011 */
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"MC0", /* 0100 */
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"MC1", /* 0101 */
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"MC2", /* 0110 */
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"MC3", /* 0111 */
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"???", /* 1000 */
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"ALL", /* 1001 */
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"ALH", /* 1010 */
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"???", /* 1011 */
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"???", /* 1100 */
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"???", /* 1101 */
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"???", /* 1110 */
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"???", /* 1111 */
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};
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static const char *const DestMemory[] =
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{
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"MC0", /* 0000 */
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"MC1", /* 0001 */
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"MC2", /* 0010 */
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"MC3", /* 0011 */
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"RX", /* 0100 */
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"PL", /* 0101 */
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"RA0", /* 0110 */
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"WA0", /* 0111 */
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"???", /* 1000 */
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"???", /* 1001 */
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"LOP", /* 1010 */
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"TOP", /* 1011 */
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"CT0", /* 1100 */
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"CT1", /* 1101 */
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"CT2", /* 1110 */
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"CT3", /* 1111 */
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};
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static const char *const DestDMAMemory[] =
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{
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"M0", /* 000 */
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"M1", /* 001 */
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"M2", /* 010 */
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"M3", /* 011 */
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"PRG", /* 100 */
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"???", /* 101 */
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"???", /* 110 */
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"???", /* 111 */
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};
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static const char *const MVI_Command[] =
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{
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"MVI %I,%d", /* 0 */
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"MVI %I,%d,%f", /* 1 */
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};
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static const char *const JMP_Command[] =
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{
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"JMP %IA",
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"JMP %f,%IA",
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};
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static const char *const DMA_Command[] =
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{
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"DMA%H%A D0,%M,%I",
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"DMA%H%A %s,D0,%I",
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"DMA%H%A D0,%M,%s",
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"DMA%H%A %s,D0,%s",
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};
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static void scudsp_dasm_prefix( const char* format, char* buffer, UINT32 *data )
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{
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for ( ; *format; format++ )
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{
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if ( *format == '%' )
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{
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switch( *++format )
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{
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case 'H':
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if ( *data )
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{
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strcpy( buffer, "H" );
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}
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else
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{
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*buffer = 0;
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}
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break;
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case 'A':
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if ( *data == 0 )
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{
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strcpy( buffer, "0" );
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}
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else if ( *data == 1 )
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{
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*buffer = 0;
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}
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else
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{
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sprintf( buffer, "%d", 1 << (*data - 1) );
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}
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break;
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case 's':
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strcpy( buffer, SourceMemory[ *data & 0x7 ] );
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break;
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case 'd':
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strcpy( buffer, DestMemory[ *data & 0xf ] );
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break;
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case 'S':
|
||||
strcpy( buffer, SourceMemory2[ *data & 0xf ] );
|
||||
break;
|
||||
case 'I':
|
||||
++format;
|
||||
if ( *format == '8' )
|
||||
{
|
||||
sprintf( buffer, "#$%x", *data );
|
||||
}
|
||||
else if ( *format == 'A' )
|
||||
{
|
||||
sprintf( buffer, "$%X", *data );
|
||||
}
|
||||
else
|
||||
{
|
||||
--format;
|
||||
sprintf( buffer, "#$%X", *data );
|
||||
}
|
||||
break;
|
||||
case 'f':
|
||||
if ( !(*data & 0x20) )
|
||||
{
|
||||
strcpy( buffer, "N" );
|
||||
buffer++;
|
||||
}
|
||||
switch( *data & 0xf )
|
||||
{
|
||||
case 0x3:
|
||||
strcpy( buffer, "ZS" );
|
||||
break;
|
||||
case 0x2:
|
||||
strcpy( buffer, "S" );
|
||||
break;
|
||||
case 0x4:
|
||||
strcpy( buffer, "C" );
|
||||
break;
|
||||
case 0x8:
|
||||
strcpy( buffer, "T0" );
|
||||
break;
|
||||
case 0x1:
|
||||
strcpy( buffer, "Z" );
|
||||
break;
|
||||
default:
|
||||
strcpy( buffer, "?" );
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 'M':
|
||||
strcpy( buffer, DestDMAMemory[ *data ] );
|
||||
break;
|
||||
|
||||
}
|
||||
data++;
|
||||
buffer += strlen( buffer );
|
||||
}
|
||||
else
|
||||
{
|
||||
*buffer++ = *format;
|
||||
}
|
||||
}
|
||||
*buffer = 0;
|
||||
}
|
||||
|
||||
|
||||
CPU_DISASSEMBLE( scudsp )
|
||||
{
|
||||
UINT32 op = oprom[0]<<24|oprom[1]<<16|oprom[2]<<8|oprom[3]<<0;
|
||||
unsigned size = 1;
|
||||
// const char *sym, *sym2;
|
||||
char *my_buffer = buffer;
|
||||
char temp_buffer[64];
|
||||
UINT32 data[2];
|
||||
|
||||
switch( op >> 30 )
|
||||
{
|
||||
case 0:
|
||||
sprintf(buffer, "ALU OP");
|
||||
if ( (op & 0x3F8E3000) == 0 )
|
||||
{
|
||||
sprintf( buffer, "%-10s", "NOP" );
|
||||
break;
|
||||
}
|
||||
|
||||
/* ALU */
|
||||
sprintf(my_buffer, "%-10s", ALU_Commands[ (op & 0x3c000000) >> 26] );
|
||||
my_buffer += strlen( my_buffer );
|
||||
|
||||
/* X-Bus */
|
||||
data[0] = (op & 0x700000) >> 20;
|
||||
if ( op & 0x2000000 )
|
||||
{
|
||||
scudsp_dasm_prefix( X_Commands[ 4 ], temp_buffer, data );
|
||||
}
|
||||
else
|
||||
{
|
||||
*temp_buffer = 0;
|
||||
}
|
||||
sprintf( my_buffer, "%-10s", temp_buffer );
|
||||
my_buffer += strlen( my_buffer );
|
||||
|
||||
scudsp_dasm_prefix( X_Commands[ (op & 0x1800000) >> 23 ], temp_buffer, data );
|
||||
sprintf( my_buffer, "%-10s", temp_buffer );
|
||||
my_buffer += strlen( my_buffer );
|
||||
|
||||
data[0] = (op & 0x1C000 ) >> 14 ;
|
||||
if ( op & 0x80000 )
|
||||
{
|
||||
scudsp_dasm_prefix( Y_Commands[4], temp_buffer, data );
|
||||
}
|
||||
else
|
||||
{
|
||||
*temp_buffer = 0;
|
||||
}
|
||||
sprintf( my_buffer, "%-8s", temp_buffer );
|
||||
my_buffer += strlen( my_buffer );
|
||||
|
||||
scudsp_dasm_prefix( Y_Commands[ (op & 0x60000) >> 17 ], temp_buffer, data );
|
||||
sprintf( my_buffer, "%-8s", temp_buffer );
|
||||
my_buffer += strlen( my_buffer );
|
||||
|
||||
/* D1-Bus */
|
||||
switch( (op & 0x3000) >> 12 )
|
||||
{
|
||||
case 0x1:
|
||||
data[0] = (op & 0xFF);
|
||||
data[1] = ((op & 0xF00) >> 8);
|
||||
break;
|
||||
case 0x3:
|
||||
data[0] = (op & 0xF);
|
||||
data[1] = ((op & 0xF00) >> 8);
|
||||
break;
|
||||
}
|
||||
|
||||
scudsp_dasm_prefix( D1_Commands[ (op & 0x3000) >> 12 ], temp_buffer, data );
|
||||
sprintf( my_buffer, "%-8s", temp_buffer );
|
||||
break;
|
||||
case 2:
|
||||
sprintf(buffer, "MVI");
|
||||
if ( (op & 0x2000000) )
|
||||
{
|
||||
data[0] = op & 0x7FFFF;
|
||||
data[1] = (op & 0x3C000000) >> 26;
|
||||
data[2] = (op & 0x3F80000 ) >> 19;
|
||||
scudsp_dasm_prefix( MVI_Command[1], buffer, data ); /* TODO: bad mem*/
|
||||
}
|
||||
else
|
||||
{
|
||||
data[0] = op & 0x1FFFFFF;
|
||||
data[1] = (op & 0x3C000000) >> 26;
|
||||
scudsp_dasm_prefix( MVI_Command[0], buffer, data ); /* TODO: bad mem*/
|
||||
}
|
||||
break;
|
||||
case 3:
|
||||
switch((op >> 28) & 3)
|
||||
@ -23,7 +328,17 @@ CPU_DISASSEMBLE( scudsp )
|
||||
sprintf(buffer, "DMA");
|
||||
break;
|
||||
case 1:
|
||||
sprintf(buffer, "JMP");
|
||||
if ( op & 0x3F80000 )
|
||||
{
|
||||
data[0] = (op & 0x3F80000) >> 19;
|
||||
data[1] = op & 0xff;
|
||||
scudsp_dasm_prefix( JMP_Command[1], buffer, data );
|
||||
}
|
||||
else
|
||||
{
|
||||
data[0] = op & 0xff;
|
||||
scudsp_dasm_prefix( JMP_Command[0], buffer, data );
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
sprintf(buffer, op & 0x8000000 ? "LPS" : "BTM");
|
||||
|
||||
@ -221,6 +221,8 @@ void saturn_state::scu_test_pending_irq()
|
||||
}
|
||||
}
|
||||
|
||||
#define USE_NEW_SCUDSP 1
|
||||
|
||||
READ32_MEMBER(saturn_state::saturn_scu_r)
|
||||
{
|
||||
UINT32 res;
|
||||
@ -238,12 +240,19 @@ READ32_MEMBER(saturn_state::saturn_scu_r)
|
||||
res = m_scu.status;
|
||||
break;
|
||||
case 0x80/4:
|
||||
#if USE_NEW_SCUDSP
|
||||
res = m_scudsp->program_control_r(space, 0, mem_mask);
|
||||
#else
|
||||
res = dsp_prg_ctrl_r(space);
|
||||
#endif
|
||||
break;
|
||||
case 0x8c/4:
|
||||
if(LOG_SCU && !space.debugger_access()) logerror( "DSP mem read at %08X\n", m_scu_regs[34]);
|
||||
#if USE_NEW_SCUDSP
|
||||
res = m_scudsp->ram_address_r(space, 0, mem_mask);
|
||||
#else
|
||||
res = dsp_ram_addr_r();
|
||||
#endif
|
||||
break;
|
||||
case 0xa0/4:
|
||||
if(LOG_SCU && !space.debugger_access()) logerror("(PC=%08x) IRQ mask reg read %08x MASK=%08x\n",space.device().safe_pc(),mem_mask,m_scu_regs[0xa0/4]);
|
||||
@ -313,20 +322,35 @@ WRITE32_MEMBER(saturn_state::saturn_scu_w)
|
||||
/*DSP section*/
|
||||
case 0x80/4:
|
||||
/* TODO: you can't overwrite some flags with this */
|
||||
#if USE_NEW_SCUDSP
|
||||
m_scudsp->program_control_w(space, 0, m_scu_regs[offset], mem_mask);
|
||||
#else
|
||||
dsp_prg_ctrl_w(space, m_scu_regs[offset]);
|
||||
m_scudsp->program_control_w(space, 0, mem_mask,data);
|
||||
#endif
|
||||
if(LOG_SCU) logerror("SCU DSP: Program Control Port Access %08x\n",data);
|
||||
break;
|
||||
case 0x84/4:
|
||||
#if USE_NEW_SCUDSP
|
||||
m_scudsp->program_w(space, 0, m_scu_regs[offset], mem_mask);
|
||||
#else
|
||||
dsp_prg_data(m_scu_regs[offset]);
|
||||
#endif
|
||||
if(LOG_SCU) logerror("SCU DSP: Program RAM Data Port Access %08x\n",data);
|
||||
break;
|
||||
case 0x88/4:
|
||||
#if USE_NEW_SCUDSP
|
||||
m_scudsp->ram_address_control_w(space, 0,m_scu_regs[offset], mem_mask);
|
||||
#else
|
||||
dsp_ram_addr_ctrl(m_scu_regs[offset]);
|
||||
#endif
|
||||
if(LOG_SCU) logerror("SCU DSP: Data RAM Address Port Access %08x\n",data);
|
||||
break;
|
||||
case 0x8c/4:
|
||||
#if USE_NEW_SCUDSP
|
||||
m_scudsp->ram_address_w(space, 0, m_scu_regs[offset], mem_mask);
|
||||
#else
|
||||
dsp_ram_addr_w(m_scu_regs[offset]);
|
||||
#endif
|
||||
if(LOG_SCU) logerror("SCU DSP: Data RAM Data Port Access %08x\n",data);
|
||||
break;
|
||||
case 0x90/4: /*if(LOG_SCU) logerror("timer 0 compare data = %03x\n",m_scu_regs[36]);*/ break;
|
||||
|
||||
@ -961,6 +961,14 @@ static ADDRESS_MAP_START( sound_mem, AS_PROGRAM, 16, stv_state )
|
||||
AM_RANGE(0x100000, 0x100fff) AM_DEVREADWRITE_LEGACY("scsp", scsp_r, scsp_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( scudsp_mem, AS_PROGRAM, 32, sat_console_state )
|
||||
AM_RANGE(0x00, 0xff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( scudsp_data, AS_DATA, 32, sat_console_state )
|
||||
AM_RANGE(0x00, 0xff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static MACHINE_CONFIG_START( stv, stv_state )
|
||||
|
||||
/* basic machine hardware */
|
||||
|
||||
@ -2316,7 +2316,7 @@ READ16_MEMBER(pc9801_state::pc9801rs_ide_io_1_r)
|
||||
|
||||
WRITE16_MEMBER(pc9801_state::pc9801rs_ide_io_1_w)
|
||||
{
|
||||
m_ide->write_cs0(space, offset, mem_mask);
|
||||
m_ide->write_cs0(space, offset, data, mem_mask);
|
||||
}
|
||||
|
||||
READ16_MEMBER(pc9801_state::pc9801rs_ide_io_2_r)
|
||||
@ -2326,7 +2326,7 @@ READ16_MEMBER(pc9801_state::pc9801rs_ide_io_2_r)
|
||||
|
||||
WRITE16_MEMBER(pc9801_state::pc9801rs_ide_io_2_w)
|
||||
{
|
||||
m_ide->write_cs1(space, offset + 6, mem_mask);
|
||||
m_ide->write_cs1(space, offset + 6, data, mem_mask);
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( pc9801rs_map, AS_PROGRAM, 32, pc9801_state )
|
||||
|
||||
@ -184,7 +184,6 @@ static ADDRESS_MAP_START( sound_mem, AS_PROGRAM, 16, sat_console_state )
|
||||
AM_RANGE(0x100000, 0x100fff) AM_DEVREADWRITE_LEGACY("scsp", scsp_r, scsp_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
#if 1
|
||||
static ADDRESS_MAP_START( scudsp_mem, AS_PROGRAM, 32, sat_console_state )
|
||||
AM_RANGE(0x00, 0xff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
@ -192,7 +191,6 @@ ADDRESS_MAP_END
|
||||
static ADDRESS_MAP_START( scudsp_data, AS_DATA, 32, sat_console_state )
|
||||
AM_RANGE(0x00, 0xff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
#endif
|
||||
|
||||
|
||||
/* keyboard code */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user