mirror of
https://github.com/holub/mame
synced 2025-10-07 09:25:34 +03:00
(MESS) s100: devcb2. (nw)
This commit is contained in:
Curt Coder
parent
56c45f6176
commit
edd1b11b4d
@ -94,7 +94,7 @@ void s100_dj2db_device::fdc_intrq_w(bool state)
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case 5: m_bus->vi5_w(state); break;
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case 6: m_bus->vi6_w(state); break;
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case 7: m_bus->vi7_w(state); break;
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case 8: m_bus->int_w(state); break;
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case 8: m_bus->irq_w(state); break;
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}
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}
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@ -9,27 +9,38 @@
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**********************************************************************/
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#include "emu.h"
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#include "emuopts.h"
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#include "s100.h"
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//**************************************************************************
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// GLOBAL VARIABLES
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// DEVICE DEFINITIONS
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//**************************************************************************
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const device_type S100_SLOT = &device_creator<s100_slot_device>;
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const device_type S100_BUS = &device_creator<s100_bus_t>;
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const device_type S100_SLOT = &device_creator<s100_slot_t>;
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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//-------------------------------------------------
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// s100_slot_device - constructor
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// device_s100_card_interface - constructor
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//-------------------------------------------------
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s100_slot_device::s100_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
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device_t(mconfig, S100_SLOT, "S100 slot", tag, owner, clock, "s100_slot", __FILE__),
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device_slot_interface(mconfig, *this)
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device_s100_card_interface::device_s100_card_interface(const machine_config &mconfig, device_t &device)
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: device_slot_card_interface(mconfig, device)
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{
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}
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//-------------------------------------------------
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// s100_slot_t - constructor
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//-------------------------------------------------
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s100_slot_t::s100_slot_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
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device_t(mconfig, S100_SLOT, "S100 slot", tag, owner, clock, "s100_slot", __FILE__),
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device_slot_interface(mconfig, *this)
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{
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}
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@ -38,72 +49,37 @@ s100_slot_device::s100_slot_device(const machine_config &mconfig, const char *ta
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// device_start - device-specific startup
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//-------------------------------------------------
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void s100_slot_device::device_start()
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void s100_slot_t::device_start()
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{
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m_bus = machine().device<s100_device>(S100_TAG);
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m_bus = machine().device<s100_bus_t>(S100_TAG);
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device_s100_card_interface *dev = dynamic_cast<device_s100_card_interface *>(get_card_device());
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if (dev) m_bus->add_s100_card(dev);
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if (dev) m_bus->add_card(dev);
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}
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//**************************************************************************
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// GLOBAL VARIABLES
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//**************************************************************************
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const device_type S100 = &device_creator<s100_device>;
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//-------------------------------------------------
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// device_config_complete - perform any
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// operations now that the configuration is
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// complete
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// s100_bus_t - constructor
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//-------------------------------------------------
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void s100_device::device_config_complete()
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{
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// inherit a copy of the static data
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const s100_bus_interface *intf = reinterpret_cast<const s100_bus_interface *>(static_config());
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if (intf != NULL)
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{
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*static_cast<s100_bus_interface *>(this) = *intf;
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}
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// or initialize to defaults if none provided
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else
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{
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memset(&m_out_int_cb, 0, sizeof(m_out_int_cb));
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memset(&m_out_nmi_cb, 0, sizeof(m_out_nmi_cb));
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memset(&m_out_vi0_cb, 0, sizeof(m_out_vi0_cb));
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memset(&m_out_vi1_cb, 0, sizeof(m_out_vi1_cb));
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memset(&m_out_vi2_cb, 0, sizeof(m_out_vi2_cb));
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memset(&m_out_vi3_cb, 0, sizeof(m_out_vi3_cb));
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memset(&m_out_vi4_cb, 0, sizeof(m_out_vi4_cb));
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memset(&m_out_vi5_cb, 0, sizeof(m_out_vi5_cb));
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memset(&m_out_vi6_cb, 0, sizeof(m_out_vi6_cb));
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memset(&m_out_vi7_cb, 0, sizeof(m_out_vi7_cb));
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memset(&m_out_dma0_cb, 0, sizeof(m_out_dma0_cb));
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memset(&m_out_dma1_cb, 0, sizeof(m_out_dma1_cb));
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memset(&m_out_dma2_cb, 0, sizeof(m_out_dma2_cb));
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memset(&m_out_dma3_cb, 0, sizeof(m_out_dma3_cb));
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memset(&m_out_rdy_cb, 0, sizeof(m_out_rdy_cb));
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memset(&m_out_hold_cb, 0, sizeof(m_out_hold_cb));
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memset(&m_out_error_cb, 0, sizeof(m_out_error_cb));
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}
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}
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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//-------------------------------------------------
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// s100_device - constructor
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//-------------------------------------------------
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s100_device::s100_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
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device_t(mconfig, S100, "S100", tag, owner, clock, "s100", __FILE__)
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s100_bus_t::s100_bus_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
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device_t(mconfig, S100_BUS, "S100", tag, owner, clock, "s100", __FILE__),
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m_write_irq(*this),
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m_write_nmi(*this),
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m_write_vi0(*this),
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m_write_vi1(*this),
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m_write_vi2(*this),
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m_write_vi3(*this),
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m_write_vi4(*this),
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m_write_vi5(*this),
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m_write_vi6(*this),
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m_write_vi7(*this),
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m_write_dma0(*this),
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m_write_dma1(*this),
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m_write_dma2(*this),
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m_write_dma3(*this),
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m_write_rdy(*this),
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m_write_hold(*this),
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m_write_error(*this)
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{
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}
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@ -112,26 +88,26 @@ s100_device::s100_device(const machine_config &mconfig, const char *tag, device_
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// device_start - device-specific startup
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//-------------------------------------------------
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void s100_device::device_start()
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void s100_bus_t::device_start()
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{
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// resolve callbacks
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m_out_int_func.resolve(m_out_int_cb, *this);
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m_out_nmi_func.resolve(m_out_nmi_cb, *this);
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m_out_vi0_func.resolve(m_out_vi0_cb, *this);
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m_out_vi1_func.resolve(m_out_vi1_cb, *this);
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m_out_vi2_func.resolve(m_out_vi2_cb, *this);
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m_out_vi3_func.resolve(m_out_vi3_cb, *this);
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m_out_vi4_func.resolve(m_out_vi4_cb, *this);
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m_out_vi5_func.resolve(m_out_vi5_cb, *this);
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m_out_vi6_func.resolve(m_out_vi6_cb, *this);
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m_out_vi7_func.resolve(m_out_vi7_cb, *this);
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m_out_dma0_func.resolve(m_out_dma0_cb, *this);
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m_out_dma1_func.resolve(m_out_dma1_cb, *this);
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m_out_dma2_func.resolve(m_out_dma2_cb, *this);
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m_out_dma3_func.resolve(m_out_dma3_cb, *this);
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m_out_rdy_func.resolve(m_out_rdy_cb, *this);
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m_out_hold_func.resolve(m_out_hold_cb, *this);
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m_out_error_func.resolve(m_out_error_cb, *this);
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m_write_irq.resolve_safe();
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m_write_nmi.resolve_safe();
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m_write_vi0.resolve_safe();
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m_write_vi1.resolve_safe();
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m_write_vi2.resolve_safe();
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m_write_vi3.resolve_safe();
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m_write_vi4.resolve_safe();
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m_write_vi5.resolve_safe();
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m_write_vi6.resolve_safe();
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m_write_vi7.resolve_safe();
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m_write_dma0.resolve_safe();
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m_write_dma1.resolve_safe();
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m_write_dma2.resolve_safe();
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m_write_dma3.resolve_safe();
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m_write_rdy.resolve_safe();
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m_write_hold.resolve_safe();
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m_write_error.resolve_safe();
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}
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@ -139,16 +115,16 @@ void s100_device::device_start()
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// device_reset - device-specific reset
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//-------------------------------------------------
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void s100_device::device_reset()
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void s100_bus_t::device_reset()
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{
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}
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//-------------------------------------------------
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// add_s100_card - add S100 card
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// add_card - add card
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//-------------------------------------------------
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void s100_device::add_s100_card(device_s100_card_interface *card)
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void s100_bus_t::add_card(device_s100_card_interface *card)
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{
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card->m_bus = this;
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m_device_list.append(*card);
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@ -159,7 +135,7 @@ void s100_device::add_s100_card(device_s100_card_interface *card)
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// smemr_r - memory read
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//-------------------------------------------------
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READ8_MEMBER( s100_device::smemr_r )
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READ8_MEMBER( s100_bus_t::smemr_r )
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{
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UINT8 data = 0;
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@ -179,7 +155,7 @@ READ8_MEMBER( s100_device::smemr_r )
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// mwrt_w - memory write
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//-------------------------------------------------
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WRITE8_MEMBER( s100_device::mwrt_w )
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WRITE8_MEMBER( s100_bus_t::mwrt_w )
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{
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device_s100_card_interface *entry = m_device_list.first();
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@ -195,7 +171,7 @@ WRITE8_MEMBER( s100_device::mwrt_w )
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// sinp_r - I/O read
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//-------------------------------------------------
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READ8_MEMBER( s100_device::sinp_r )
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READ8_MEMBER( s100_bus_t::sinp_r )
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{
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UINT8 data = 0;
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@ -215,7 +191,7 @@ READ8_MEMBER( s100_device::sinp_r )
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// sout_w - I/O write
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//-------------------------------------------------
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WRITE8_MEMBER( s100_device::sout_w )
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WRITE8_MEMBER( s100_bus_t::sout_w )
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{
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device_s100_card_interface *entry = m_device_list.first();
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@ -225,46 +201,3 @@ WRITE8_MEMBER( s100_device::sout_w )
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entry = entry->next();
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}
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}
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WRITE_LINE_MEMBER( s100_device::int_w ) { m_out_nmi_func(state); }
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WRITE_LINE_MEMBER( s100_device::nmi_w ) { m_out_nmi_func(state); }
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WRITE_LINE_MEMBER( s100_device::vi0_w ) { m_out_vi0_func(state); }
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WRITE_LINE_MEMBER( s100_device::vi1_w ) { m_out_vi1_func(state); }
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WRITE_LINE_MEMBER( s100_device::vi2_w ) { m_out_vi2_func(state); }
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WRITE_LINE_MEMBER( s100_device::vi3_w ) { m_out_vi3_func(state); }
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WRITE_LINE_MEMBER( s100_device::vi4_w ) { m_out_vi4_func(state); }
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WRITE_LINE_MEMBER( s100_device::vi5_w ) { m_out_vi5_func(state); }
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WRITE_LINE_MEMBER( s100_device::vi6_w ) { m_out_vi6_func(state); }
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WRITE_LINE_MEMBER( s100_device::vi7_w ) { m_out_vi7_func(state); }
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WRITE_LINE_MEMBER( s100_device::dma0_w ) { m_out_dma0_func(state); }
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WRITE_LINE_MEMBER( s100_device::dma1_w ) { m_out_dma1_func(state); }
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WRITE_LINE_MEMBER( s100_device::dma2_w ) { m_out_dma2_func(state); }
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WRITE_LINE_MEMBER( s100_device::dma3_w ) { m_out_dma3_func(state); }
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WRITE_LINE_MEMBER( s100_device::rdy_w ) { m_out_rdy_func(state); }
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WRITE_LINE_MEMBER( s100_device::hold_w ) { m_out_hold_func(state); }
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WRITE_LINE_MEMBER( s100_device::error_w ) { m_out_error_func(state); }
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//**************************************************************************
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// DEVICE S100 CARD INTERFACE
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//**************************************************************************
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//-------------------------------------------------
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// device_s100_card_interface - constructor
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//-------------------------------------------------
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device_s100_card_interface::device_s100_card_interface(const machine_config &mconfig, device_t &device)
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: device_slot_card_interface(mconfig, device)
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{
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}
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//-------------------------------------------------
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// ~device_s100_card_interface - destructor
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//-------------------------------------------------
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device_s100_card_interface::~device_s100_card_interface()
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{
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}
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@ -83,154 +83,83 @@
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// INTERFACE CONFIGURATION MACROS
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//**************************************************************************
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#define MCFG_S100_BUS_ADD(_config) \
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MCFG_DEVICE_ADD(S100_TAG, S100, 0) \
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MCFG_DEVICE_CONFIG(_config)
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#define S100_INTERFACE(_name) \
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const s100_bus_interface (_name) =
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#define MCFG_S100_BUS_ADD() \
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MCFG_DEVICE_ADD(S100_TAG, S100_BUS, 0)
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#define MCFG_S100_SLOT_ADD(_tag, _slot_intf, _def_slot) \
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MCFG_DEVICE_ADD(_tag, S100_SLOT, 0) \
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MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
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#define MCFG_S100_IRQ_CALLBACK(_write) \
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devcb = &s100_bus_t::set_irq_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_NMI_CALLBACK(_write) \
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devcb = &s100_bus_t::set_nmi_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_VI0_CALLBACK(_write) \
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devcb = &s100_bus_t::set_vi0_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_VI1_CALLBACK(_write) \
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devcb = &s100_bus_t::set_vi1_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_VI2_CALLBACK(_write) \
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devcb = &s100_bus_t::set_vi2_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_VI3_CALLBACK(_write) \
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devcb = &s100_bus_t::set_vi3_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_VI4_CALLBACK(_write) \
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devcb = &s100_bus_t::set_vi4_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_VI5_CALLBACK(_write) \
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devcb = &s100_bus_t::set_vi5_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_VI6_CALLBACK(_write) \
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devcb = &s100_bus_t::set_vi6_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_VI7_CALLBACK(_write) \
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devcb = &s100_bus_t::set_vi7_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_DMA0_CALLBACK(_write) \
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devcb = &s100_bus_t::set_dma0_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_DMA1_CALLBACK(_write) \
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devcb = &s100_bus_t::set_dma1_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_DMA2_CALLBACK(_write) \
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devcb = &s100_bus_t::set_dma2_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_DMA3_CALLBACK(_write) \
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devcb = &s100_bus_t::set_dma3_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_RDY_CALLBACK(_write) \
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devcb = &s100_bus_t::set_rdy_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_HOLD_CALLBACK(_write) \
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devcb = &s100_bus_t::set_hold_wr_callback(*device, DEVCB2_##_write);
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#define MCFG_S100_ERROR_CALLBACK(_write) \
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devcb = &s100_bus_t::set_error_wr_callback(*device, DEVCB2_##_write);
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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// ======================> s100_slot_device
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class s100_device;
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class s100_slot_device : public device_t,
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public device_slot_interface
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{
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public:
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// construction/destruction
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s100_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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// device-level overrides
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virtual void device_start();
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private:
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s100_device *m_bus;
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};
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// device type definition
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extern const device_type S100_SLOT;
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// ======================> s100_bus_interface
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struct s100_bus_interface
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{
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devcb_write_line m_out_int_cb;
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devcb_write_line m_out_nmi_cb;
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devcb_write_line m_out_vi0_cb;
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devcb_write_line m_out_vi1_cb;
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devcb_write_line m_out_vi2_cb;
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devcb_write_line m_out_vi3_cb;
|
||||
devcb_write_line m_out_vi4_cb;
|
||||
devcb_write_line m_out_vi5_cb;
|
||||
devcb_write_line m_out_vi6_cb;
|
||||
devcb_write_line m_out_vi7_cb;
|
||||
devcb_write_line m_out_dma0_cb;
|
||||
devcb_write_line m_out_dma1_cb;
|
||||
devcb_write_line m_out_dma2_cb;
|
||||
devcb_write_line m_out_dma3_cb;
|
||||
devcb_write_line m_out_rdy_cb;
|
||||
devcb_write_line m_out_hold_cb;
|
||||
devcb_write_line m_out_error_cb;
|
||||
};
|
||||
|
||||
class device_s100_card_interface;
|
||||
|
||||
|
||||
// ======================> s100_device
|
||||
|
||||
class s100_device : public device_t,
|
||||
public s100_bus_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
s100_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
~s100_device() { m_device_list.detach_all(); }
|
||||
|
||||
void add_s100_card(device_s100_card_interface *card);
|
||||
|
||||
DECLARE_READ8_MEMBER( smemr_r );
|
||||
DECLARE_WRITE8_MEMBER( mwrt_w );
|
||||
|
||||
DECLARE_READ8_MEMBER( sinp_r );
|
||||
DECLARE_WRITE8_MEMBER( sout_w );
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( int_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( nmi_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( vi0_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( vi1_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( vi2_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( vi3_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( vi4_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( vi5_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( vi6_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( vi7_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( dma0_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( dma1_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( dma2_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( dma3_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( rdy_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( hold_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( error_w );
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual void device_config_complete();
|
||||
|
||||
private:
|
||||
devcb_resolved_write_line m_out_int_func;
|
||||
devcb_resolved_write_line m_out_nmi_func;
|
||||
devcb_resolved_write_line m_out_vi0_func;
|
||||
devcb_resolved_write_line m_out_vi1_func;
|
||||
devcb_resolved_write_line m_out_vi2_func;
|
||||
devcb_resolved_write_line m_out_vi3_func;
|
||||
devcb_resolved_write_line m_out_vi4_func;
|
||||
devcb_resolved_write_line m_out_vi5_func;
|
||||
devcb_resolved_write_line m_out_vi6_func;
|
||||
devcb_resolved_write_line m_out_vi7_func;
|
||||
devcb_resolved_write_line m_out_dma0_func;
|
||||
devcb_resolved_write_line m_out_dma1_func;
|
||||
devcb_resolved_write_line m_out_dma2_func;
|
||||
devcb_resolved_write_line m_out_dma3_func;
|
||||
devcb_resolved_write_line m_out_rdy_func;
|
||||
devcb_resolved_write_line m_out_hold_func;
|
||||
devcb_resolved_write_line m_out_error_func;
|
||||
|
||||
simple_list<device_s100_card_interface> m_device_list;
|
||||
};
|
||||
|
||||
|
||||
// device type definition
|
||||
extern const device_type S100;
|
||||
|
||||
class s100_bus_t;
|
||||
|
||||
// ======================> device_s100_card_interface
|
||||
|
||||
// class representing interface-specific live s100 card
|
||||
class device_s100_card_interface : public device_slot_card_interface
|
||||
{
|
||||
friend class s100_device;
|
||||
friend class s100_bus_t;
|
||||
|
||||
public:
|
||||
// construction/destruction
|
||||
device_s100_card_interface(const machine_config &mconfig, device_t &device);
|
||||
virtual ~device_s100_card_interface();
|
||||
virtual ~device_s100_card_interface() { }
|
||||
|
||||
device_s100_card_interface *next() const { return m_next; }
|
||||
|
||||
@ -270,9 +199,116 @@ public:
|
||||
virtual void s100_slave_clr_w(int state) { }
|
||||
|
||||
public:
|
||||
s100_device *m_bus;
|
||||
s100_bus_t *m_bus;
|
||||
device_s100_card_interface *m_next;
|
||||
};
|
||||
|
||||
|
||||
|
||||
// ======================> s100_bus_t
|
||||
|
||||
class s100_bus_t : public device_t
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
s100_bus_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
~s100_bus_t() { m_device_list.detach_all(); }
|
||||
|
||||
template<class _Object> static devcb2_base &set_irq_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_irq.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_nmi_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_nmi.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_vi0_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_vi0.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_vi1_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_vi1.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_vi2_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_vi2.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_vi3_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_vi3.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_vi4_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_vi4.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_vi5_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_vi5.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_vi6_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_vi6.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_vi7_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_vi7.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_dma0_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_dma0.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_dma1_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_dma1.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_dma2_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_dma2.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_dma3_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_dma3.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_rdy_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_rdy.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_hold_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_hold.set_callback(object); }
|
||||
template<class _Object> static devcb2_base &set_error_wr_callback(device_t &device, _Object object) { return downcast<s100_bus_t &>(device).m_write_error.set_callback(object); }
|
||||
|
||||
void add_card(device_s100_card_interface *card);
|
||||
|
||||
DECLARE_READ8_MEMBER( smemr_r );
|
||||
DECLARE_WRITE8_MEMBER( mwrt_w );
|
||||
|
||||
DECLARE_READ8_MEMBER( sinp_r );
|
||||
DECLARE_WRITE8_MEMBER( sout_w );
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( irq_w ) { m_write_irq(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( nmi_w ) { m_write_nmi(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( vi0_w ) { m_write_vi0(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( vi1_w ) { m_write_vi1(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( vi2_w ) { m_write_vi2(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( vi3_w ) { m_write_vi3(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( vi4_w ) { m_write_vi4(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( vi5_w ) { m_write_vi5(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( vi6_w ) { m_write_vi6(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( vi7_w ) { m_write_vi7(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( dma0_w ) { m_write_dma0(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( dma1_w ) { m_write_dma1(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( dma2_w ) { m_write_dma2(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( dma3_w ) { m_write_dma3(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rdy_w ) { m_write_rdy(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( hold_w ) { m_write_hold(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( error_w ) { m_write_error(state); }
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
|
||||
private:
|
||||
devcb2_write_line m_write_irq;
|
||||
devcb2_write_line m_write_nmi;
|
||||
devcb2_write_line m_write_vi0;
|
||||
devcb2_write_line m_write_vi1;
|
||||
devcb2_write_line m_write_vi2;
|
||||
devcb2_write_line m_write_vi3;
|
||||
devcb2_write_line m_write_vi4;
|
||||
devcb2_write_line m_write_vi5;
|
||||
devcb2_write_line m_write_vi6;
|
||||
devcb2_write_line m_write_vi7;
|
||||
devcb2_write_line m_write_dma0;
|
||||
devcb2_write_line m_write_dma1;
|
||||
devcb2_write_line m_write_dma2;
|
||||
devcb2_write_line m_write_dma3;
|
||||
devcb2_write_line m_write_rdy;
|
||||
devcb2_write_line m_write_hold;
|
||||
devcb2_write_line m_write_error;
|
||||
|
||||
simple_list<device_s100_card_interface> m_device_list;
|
||||
};
|
||||
|
||||
|
||||
// ======================> s100_slot_t
|
||||
|
||||
class s100_slot_t : public device_t,
|
||||
public device_slot_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
s100_slot_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
|
||||
private:
|
||||
s100_bus_t *m_bus;
|
||||
};
|
||||
|
||||
|
||||
|
||||
// device type definition
|
||||
extern const device_type S100_BUS;
|
||||
extern const device_type S100_SLOT;
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@ -57,7 +57,7 @@ const device_type S100_WUNDERBUS = &device_creator<s100_wunderbus_device>;
|
||||
|
||||
WRITE_LINE_MEMBER( s100_wunderbus_device::pic_int_w )
|
||||
{
|
||||
m_bus->int_w(state);
|
||||
m_bus->irq_w(state);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -127,27 +127,6 @@ static SLOT_INTERFACE_START( horizon_s100_cards )
|
||||
//SLOT_INTERFACE("fpb", S100_FPB)
|
||||
SLOT_INTERFACE_END
|
||||
|
||||
static S100_INTERFACE( s100_intf )
|
||||
{
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_CPU_INPUT_LINE(Z80_TAG, Z80_INPUT_LINE_WAIT),
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL
|
||||
};
|
||||
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
@ -185,7 +164,8 @@ static MACHINE_CONFIG_START( horizon, horizon_state )
|
||||
MCFG_RS232_DSR_HANDLER(DEVWRITELINE(I8251_R_TAG, i8251_device, write_dsr))
|
||||
|
||||
// S-100
|
||||
MCFG_S100_BUS_ADD(s100_intf)
|
||||
MCFG_S100_BUS_ADD()
|
||||
MCFG_S100_RDY_CALLBACK(INPUTLINE(Z80_TAG, Z80_INPUT_LINE_WAIT))
|
||||
//MCFG_S100_SLOT_ADD("s100_1", horizon_s100_cards, NULL, NULL) // CPU
|
||||
MCFG_S100_SLOT_ADD("s100_2", horizon_s100_cards, NULL) // RAM
|
||||
MCFG_S100_SLOT_ADD("s100_3", horizon_s100_cards, "mdsad") // MDS
|
||||
|
||||
@ -651,27 +651,6 @@ WRITE_LINE_MEMBER( mpz80_state::s100_nmi_w )
|
||||
check_interrupt();
|
||||
}
|
||||
|
||||
static S100_INTERFACE( s100_intf )
|
||||
{
|
||||
DEVCB_DRIVER_LINE_MEMBER(mpz80_state, s100_pint_w),
|
||||
DEVCB_DRIVER_LINE_MEMBER(mpz80_state, s100_nmi_w),
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_CPU_INPUT_LINE(Z80_TAG, Z80_INPUT_LINE_WAIT),
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL
|
||||
};
|
||||
|
||||
// slot devices
|
||||
#include "bus/s100/dj2db.h"
|
||||
#include "bus/s100/djdma.h"
|
||||
@ -734,7 +713,10 @@ static MACHINE_CONFIG_START( mpz80, mpz80_state )
|
||||
MCFG_CPU_IO_MAP(mpz80_io)
|
||||
|
||||
// S-100
|
||||
MCFG_S100_BUS_ADD(s100_intf)
|
||||
MCFG_S100_BUS_ADD()
|
||||
MCFG_S100_IRQ_CALLBACK(WRITELINE(mpz80_state, s100_pint_w))
|
||||
MCFG_S100_NMI_CALLBACK(WRITELINE(mpz80_state, s100_nmi_w))
|
||||
MCFG_S100_RDY_CALLBACK(INPUTLINE(Z80_TAG, Z80_INPUT_LINE_WAIT))
|
||||
MCFG_S100_SLOT_ADD("s100_1", mpz80_s100_cards, "mm65k16s")
|
||||
MCFG_S100_SLOT_ADD("s100_2", mpz80_s100_cards, "wunderbus")
|
||||
MCFG_S100_SLOT_ADD("s100_3", mpz80_s100_cards, "dj2db")
|
||||
|
||||
@ -482,28 +482,6 @@ static DEVICE_INPUT_DEFAULTS_START( terminal )
|
||||
DEVICE_INPUT_DEFAULTS( "TERM_STOPBITS", 0xff, 0x01 ) // 1
|
||||
DEVICE_INPUT_DEFAULTS_END
|
||||
|
||||
|
||||
static S100_INTERFACE( s100_intf )
|
||||
{
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_CPU_INPUT_LINE(Z80_TAG, Z80_INPUT_LINE_WAIT),
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
};
|
||||
|
||||
static SLOT_INTERFACE_START( xor100_s100_cards )
|
||||
SLOT_INTERFACE_END
|
||||
|
||||
@ -586,7 +564,8 @@ static MACHINE_CONFIG_START( xor100, xor100_state )
|
||||
MCFG_CENTRONICS_OUTPUT_LATCH_ADD("cent_data_out", "centronics")
|
||||
|
||||
// S-100
|
||||
MCFG_S100_BUS_ADD(s100_intf)
|
||||
MCFG_S100_BUS_ADD()
|
||||
MCFG_S100_RDY_CALLBACK(INPUTLINE(Z80_TAG, Z80_INPUT_LINE_WAIT))
|
||||
MCFG_S100_SLOT_ADD("s100_1", xor100_s100_cards, NULL)
|
||||
MCFG_S100_SLOT_ADD("s100_2", xor100_s100_cards, NULL)
|
||||
MCFG_S100_SLOT_ADD("s100_3", xor100_s100_cards, NULL)
|
||||
|
||||
@ -39,7 +39,7 @@ public:
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<ram_device> m_ram;
|
||||
required_device<s100_device> m_s100;
|
||||
required_device<s100_bus_t> m_s100;
|
||||
required_memory_region m_rom;
|
||||
optional_shared_ptr<UINT8> m_map_ram;
|
||||
required_ioport m_16c;
|
||||
|
||||
@ -57,7 +57,7 @@ public:
|
||||
required_device<z80ctc_device> m_ctc;
|
||||
required_device<ram_device> m_ram;
|
||||
required_device<centronics_device> m_centronics;
|
||||
required_device<s100_device> m_s100;
|
||||
required_device<s100_bus_t> m_s100;
|
||||
required_device<floppy_connector> m_floppy0;
|
||||
required_device<floppy_connector> m_floppy1;
|
||||
required_device<floppy_connector> m_floppy2;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user