diff --git a/.gitattributes b/.gitattributes index f19aad187b9..bbfbd010791 100644 --- a/.gitattributes +++ b/.gitattributes @@ -2587,6 +2587,8 @@ src/emu/machine/hd63450.c svneol=native#text/plain src/emu/machine/hd63450.h svneol=native#text/plain src/emu/machine/hd64610.c svneol=native#text/plain src/emu/machine/hd64610.h svneol=native#text/plain +src/emu/machine/hdc9234.c svneol=native#text/plain +src/emu/machine/hdc9234.h svneol=native#text/plain src/emu/machine/i2cmem.c svneol=native#text/plain src/emu/machine/i2cmem.h svneol=native#text/plain src/emu/machine/i80130.c svneol=native#text/plain diff --git a/src/emu/machine/hdc9234.c b/src/emu/machine/hdc9234.c new file mode 100644 index 00000000000..d56d5edc584 --- /dev/null +++ b/src/emu/machine/hdc9234.c @@ -0,0 +1,65 @@ +/* + HDC9234 Hard and Floppy Disk Controller + + This controller handles MFM and FM encoded floppy disks and hard disks. + The SMC9224 is used in some DEC systems. The HDC9234 is used in the + Myarc HFDC card for the TI99/4A. + + References: + * SMC HDC9234 preliminary data book (1988) + + Michael Zapf, June 2014 +*/ + +#include "emu.h" +#include "hdc9234.h" + +hdc9234_device::hdc9234_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : device_t(mconfig, HDC9234, "SMC HDC9234 Universal Disk Controller", tag, owner, clock, "hdc9234", __FILE__), + m_out_intrq(*this), + m_out_dip(*this), + m_out_auxbus(*this), + m_in_auxbus(*this), + m_in_dma(*this), + m_out_dma(*this) +{ +} + +/* + Read a byte of data from the controller + The address (offset) encodes the C/D* line (command and /data) +*/ +READ8_MEMBER( hdc9234_device::read ) +{ + logerror("%s: Read access to %04x\n", tag(), offset & 0xffff); + return 0; +} + +/* + Write a byte to the controller + The address (offset) encodes the C/D* line (command and /data) +*/ +WRITE8_MEMBER( hdc9234_device::write ) +{ + logerror("%s: Write access to %04x: %d\n", tag(), offset & 0xffff, data); +} + +void hdc9234_device::device_start() +{ + logerror("%s: start\n", tag()); + m_out_intrq.resolve_safe(); + m_out_dip.resolve_safe(); + m_out_auxbus.resolve_safe(); + m_in_auxbus.resolve_safe(0); + m_out_dma.resolve_safe(); + m_in_dma.resolve_safe(0); + + // allocate timers +} + +void hdc9234_device::device_reset() +{ + logerror("%s: reset\n", tag()); +} + +const device_type HDC9234 = &device_creator; diff --git a/src/emu/machine/hdc9234.h b/src/emu/machine/hdc9234.h new file mode 100644 index 00000000000..98300918687 --- /dev/null +++ b/src/emu/machine/hdc9234.h @@ -0,0 +1,78 @@ +// license:BSD-3-Clause +// copyright-holders:Michael Zapf +/* + HDC9234 Hard and Floppy Disk Controller + For details see hdc9234.c +*/ +#ifndef __HDC9234_H__ +#define __HDC9234_H__ + +#include "emu.h" + +extern const device_type HDC9234; + +//=================================================================== + +/* Interrupt line. To be connected with the controller PCB. */ +#define MCFG_HDC9234_INTRQ_CALLBACK(_write) \ + devcb = &hdc9234_device::set_intrq_wr_callback(*device, DEVCB_##_write); + +/* DMA in progress line. To be connected with the controller PCB. */ +#define MCFG_HDC9234_DIP_CALLBACK(_write) \ + devcb = &hdc9234_device::set_dip_wr_callback(*device, DEVCB_##_write); + +/* Auxiliary Bus. These 8 lines need to be connected to external latches + and to a counter circuitry which works together with the external RAM. + We use the S0/S1 lines as address lines. */ +#define MCFG_HDC9234_AUXBUS_OUT_CALLBACK(_write) \ + devcb = &hdc9234_device::set_auxbus_wr_callback(*device, DEVCB_##_write); + +/* Auxiliary Bus. This is only used for S0=S1=0. */ +#define MCFG_HDC9234_AUXBUS_IN_CALLBACK(_read) \ + devcb = &hdc9234_device::set_auxbus_rd_callback(*device, DEVCB_##_read); + +/* Callback to read the contents of the external RAM via the data bus. + Note that the address must be set and automatically increased + by external circuitry. */ +#define MCFG_HDC9234_DMA_IN_CALLBACK(_read) \ + devcb = &hdc9234_device::set_dma_rd_callback(*device, DEVCB_##_read); + +/* Callback to write the contents of the external RAM via the data bus. + Note that the address must be set and automatically increased + by external circuitry. */ +#define MCFG_HDC9234_DMA_OUT_CALLBACK(_write) \ + devcb = &hdc9234_device::set_dma_wr_callback(*device, DEVCB_##_write); + +//=================================================================== + +class hdc9234_device : public device_t +{ +public: + hdc9234_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + // Accesors from the CPU side + DECLARE_READ8_MEMBER( read ); + DECLARE_WRITE8_MEMBER( write ); + + // Callbacks + template static devcb_base &set_intrq_wr_callback(device_t &device, _Object object) { return downcast(device).m_out_intrq.set_callback(object); } + template static devcb_base &set_dip_wr_callback(device_t &device, _Object object) { return downcast(device).m_out_dip.set_callback(object); } + template static devcb_base &set_auxbus_wr_callback(device_t &device, _Object object) { return downcast(device).m_out_auxbus.set_callback(object); } + template static devcb_base &set_auxbus_rd_callback(device_t &device, _Object object) { return downcast(device).m_in_auxbus.set_callback(object); } + template static devcb_base &set_dma_rd_callback(device_t &device, _Object object) { return downcast(device).m_in_dma.set_callback(object); } + template static devcb_base &set_dma_wr_callback(device_t &device, _Object object) { return downcast(device).m_out_dma.set_callback(object); } + +protected: + void device_start(); + void device_reset(); + +private: + devcb_write_line m_out_intrq; // INT line + devcb_write_line m_out_dip; // DMA in progress line + devcb_write8 m_out_auxbus; // AB0-7 lines (using S0,S1 as address) + devcb_read8 m_in_auxbus; // AB0-7 lines (S0=S1=0) + devcb_read8 m_in_dma; // DMA read access to the cache buffer + devcb_write8 m_out_dma; // DMA write access to the cache buffer +}; + +#endif