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(MESS) c64: some optimizations [Alex Jackson]
* read_pla() leaves the PLA outputs packed, instead of using eight output parameters to return them * flatten nested switch statements in read_memory() and write_memory() * mos6566: inline bus_r() and various READ_LINE_MEMBERs (nw) from 285% to 300% idling at basic prompt with default slot devices (c1541, no cartridge) About half the speedup comes from read_pla() refactoring, the other half comes from flattening the switch()es.
This commit is contained in:
Alex W. Jackson
parent
872d736df0
commit
ee2361327f
@ -2838,43 +2838,3 @@ WRITE_LINE_MEMBER( mos6566_device::lp_w )
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m_lp = state;
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}
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//-------------------------------------------------
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// phi0_r - phi 0
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//-------------------------------------------------
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READ_LINE_MEMBER( mos6566_device::phi0_r )
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{
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return m_phi0;
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}
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//-------------------------------------------------
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// ba_r - bus available
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//-------------------------------------------------
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READ_LINE_MEMBER( mos6566_device::ba_r )
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{
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return m_ba;
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}
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//-------------------------------------------------
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// aec_r - address enable control
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//-------------------------------------------------
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READ_LINE_MEMBER( mos6566_device::aec_r )
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{
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return m_aec;
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}
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//-------------------------------------------------
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// bus_r - data bus read
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//-------------------------------------------------
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UINT8 mos6566_device::bus_r()
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{
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return m_last_data;
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}
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@ -228,11 +228,11 @@ public:
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DECLARE_WRITE_LINE_MEMBER( lp_w );
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DECLARE_READ_LINE_MEMBER( phi0_r );
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DECLARE_READ_LINE_MEMBER( ba_r );
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DECLARE_READ_LINE_MEMBER( aec_r );
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DECLARE_READ_LINE_MEMBER( phi0_r ) { return m_phi0; } // phi 0
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DECLARE_READ_LINE_MEMBER( ba_r ) { return m_ba; } // bus available
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DECLARE_READ_LINE_MEMBER( aec_r ) { return m_aec; } // address enable control
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UINT8 bus_r();
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UINT8 bus_r() { return m_last_data; }
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UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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@ -32,6 +32,19 @@
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#define VA13 BIT(va, 13)
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#define VA12 BIT(va, 12)
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enum
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{
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PLA_OUT_CASRAM = 0,
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PLA_OUT_BASIC = 1,
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PLA_OUT_KERNAL = 2,
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PLA_OUT_CHAROM = 3,
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PLA_OUT_GRW = 4,
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PLA_OUT_IO = 5,
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PLA_OUT_ROML = 6,
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PLA_OUT_ROMH = 7
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};
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QUICKLOAD_LOAD_MEMBER( c64_state, cbm_c64 )
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{
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return general_cbm_loadsnap(image, file_type, quickload_size, m_maincpu->space(AS_PROGRAM), 0, cbm_quick_sethiaddress);
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@ -66,7 +79,7 @@ void c64_state::check_interrupts()
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// read_pla -
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//-------------------------------------------------
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void c64_state::read_pla(offs_t offset, offs_t va, int rw, int aec, int ba, int *casram, int *basic, int *kernal, int *charom, int *grw, int *io, int *roml, int *romh)
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int c64_state::read_pla(offs_t offset, offs_t va, int rw, int aec, int ba)
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{
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//int ba = m_vic->ba_r();
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//int aec = !m_vic->aec_r();
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@ -78,16 +91,7 @@ void c64_state::read_pla(offs_t offset, offs_t va, int rw, int aec, int ba, int
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UINT32 input = VA12 << 15 | VA13 << 14 | game << 13 | exrom << 12 | rw << 11 | aec << 10 | ba << 9 | A12 << 8 |
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A13 << 7 | A14 << 6 | A15 << 5 | m_va14 << 4 | m_charen << 3 | m_hiram << 2 | m_loram << 1 | cas;
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UINT32 data = m_pla->read(input);
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*casram = BIT(data, 0);
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*basic = BIT(data, 1);
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*kernal = BIT(data, 2);
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*charom = BIT(data, 3);
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*grw = BIT(data, 4);
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*io = BIT(data, 5);
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*roml = BIT(data, 6);
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*romh = BIT(data, 7);
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return m_pla->read(input);
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}
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@ -98,11 +102,10 @@ void c64_state::read_pla(offs_t offset, offs_t va, int rw, int aec, int ba, int
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UINT8 c64_state::read_memory(address_space &space, offs_t offset, offs_t va, int aec, int ba)
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{
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int rw = 1;
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int casram, basic, kernal, charom, grw, io, roml, romh;
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int io1 = 1, io2 = 1;
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int sphi2 = m_vic->phi0_r();
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read_pla(offset, va, rw, !aec, ba, &casram, &basic, &kernal, &charom, &grw, &io, &roml, &romh);
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int plaout = read_pla(offset, va, rw, !aec, ba);
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UINT8 data = 0xff;
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@ -111,7 +114,7 @@ UINT8 c64_state::read_memory(address_space &space, offs_t offset, offs_t va, int
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data = m_vic->bus_r();
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}
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if (!casram)
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if (!BIT(plaout, PLA_OUT_CASRAM))
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{
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if (aec)
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{
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@ -122,7 +125,7 @@ UINT8 c64_state::read_memory(address_space &space, offs_t offset, offs_t va, int
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data = m_ram->pointer()[(!m_va15 << 15) | (!m_va14 << 14) | va];
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}
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}
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if (!basic)
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if (!BIT(plaout, PLA_OUT_BASIC))
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{
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if (m_basic != NULL)
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{
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@ -133,7 +136,7 @@ UINT8 c64_state::read_memory(address_space &space, offs_t offset, offs_t va, int
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data = m_kernal->base()[offset & 0x1fff];
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}
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}
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if (!kernal)
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if (!BIT(plaout, PLA_OUT_KERNAL))
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{
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if (m_basic != NULL)
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{
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@ -144,49 +147,55 @@ UINT8 c64_state::read_memory(address_space &space, offs_t offset, offs_t va, int
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data = m_kernal->base()[0x2000 | (offset & 0x1fff)];
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}
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}
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if (!charom)
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if (!BIT(plaout, PLA_OUT_CHAROM))
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{
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data = m_charom->base()[offset & 0xfff];
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}
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if (!io)
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if (!BIT(plaout, PLA_OUT_IO))
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{
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switch ((offset >> 10) & 0x03)
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switch ((offset >> 8) & 0x0f)
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{
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case 0: // VIC
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case 0:
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case 1:
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case 2:
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case 3: // VIC
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data = m_vic->read(space, offset & 0x3f);
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break;
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case 1: // SID
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case 4:
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case 5:
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case 6:
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case 7: // SID
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data = m_sid->read(space, offset & 0x1f);
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break;
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case 2: // COLOR
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case 0x8:
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case 0x9:
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case 0xa:
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case 0xb: // COLOR
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data = m_color_ram[offset & 0x3ff] & 0x0f;
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break;
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case 3: // CIAS
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switch ((offset >> 8) & 0x03)
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{
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case 0: // CIA1
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case 0xc: // CIA1
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data = m_cia1->read(space, offset & 0x0f);
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break;
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case 1: // CIA2
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case 0xd: // CIA2
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data = m_cia2->read(space, offset & 0x0f);
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break;
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case 2: // I/O1
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case 0xe: // I/O1
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io1 = 0;
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break;
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case 3: // I/O2
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case 0xf: // I/O2
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io2 = 0;
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break;
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}
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break;
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}
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}
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int roml = BIT(plaout, PLA_OUT_ROML);
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int romh = BIT(plaout, PLA_OUT_ROMH);
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return m_exp->cd_r(space, offset, data, sphi2, ba, roml, romh, io1, io2);
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}
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@ -198,12 +207,11 @@ UINT8 c64_state::read_memory(address_space &space, offs_t offset, offs_t va, int
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void c64_state::write_memory(address_space &space, offs_t offset, UINT8 data, int aec, int ba)
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{
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int rw = 0;
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int casram, basic, kernal, charom, grw, io, roml, romh;
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offs_t va = 0;
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int io1 = 1, io2 = 1;
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int sphi2 = m_vic->phi0_r();
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read_pla(offset, va, rw, !aec, ba, &casram, &basic, &kernal, &charom, &grw, &io, &roml, &romh);
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int plaout = read_pla(offset, va, rw, !aec, ba);
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if (offset < 0x0002)
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{
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@ -211,49 +219,55 @@ void c64_state::write_memory(address_space &space, offs_t offset, UINT8 data, in
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data = m_vic->bus_r();
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}
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if (!casram)
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if (!BIT(plaout, PLA_OUT_CASRAM))
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{
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m_ram->pointer()[offset] = data;
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}
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if (!io)
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if (!BIT(plaout, PLA_OUT_IO))
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{
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switch ((offset >> 10) & 0x03)
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switch ((offset >> 8) & 0x0f)
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{
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case 0: // VIC
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case 0:
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case 1:
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case 2:
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case 3: // VIC
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m_vic->write(space, offset & 0x3f, data);
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break;
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case 1: // SID
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case 4:
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case 5:
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case 6:
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case 7: // SID
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m_sid->write(space, offset & 0x1f, data);
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break;
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case 2: // COLOR
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if (!grw) m_color_ram[offset & 0x3ff] = data & 0x0f;
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case 0x8:
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case 0x9:
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case 0xa:
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case 0xb: // COLOR
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if (!BIT(plaout, PLA_OUT_GRW)) m_color_ram[offset & 0x3ff] = data & 0x0f;
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break;
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case 3: // CIAS
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switch ((offset >> 8) & 0x03)
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{
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case 0: // CIA1
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case 0xc: // CIA1
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m_cia1->write(space, offset & 0x0f, data);
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break;
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case 1: // CIA2
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case 0xd: // CIA2
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m_cia2->write(space, offset & 0x0f, data);
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break;
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case 2: // I/O1
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case 0xe: // I/O1
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io1 = 0;
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break;
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case 3: // I/O2
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case 0xf: // I/O2
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io2 = 0;
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break;
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}
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break;
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}
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}
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int roml = BIT(plaout, PLA_OUT_ROML);
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int romh = BIT(plaout, PLA_OUT_ROMH);
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m_exp->cd_w(space, offset, data, sphi2, ba, roml, romh, io1, io2);
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}
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@ -106,7 +106,7 @@ public:
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virtual void machine_reset();
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void check_interrupts();
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void read_pla(offs_t offset, offs_t va, int rw, int aec, int ba, int *casram, int *basic, int *kernal, int *charom, int *grw, int *io, int *roml, int *romh);
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int read_pla(offs_t offset, offs_t va, int rw, int aec, int ba);
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UINT8 read_memory(address_space &space, offs_t offset, offs_t va, int aec, int ba);
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void write_memory(address_space &space, offs_t offset, UINT8 data, int aec, int ba);
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