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-39in1: Split Intel XScale PXA255 peripherals into a separate device. [Ryan Holtz]

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note: will apply this change to any drivers using copy/pasted PXA255 code tomorrow.
This commit is contained in:
mooglyguy 2018-06-21 23:17:39 +02:00
parent 3776f3d0a8
commit ee604f4454
7 changed files with 1546 additions and 1513 deletions
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13
scripts/src/machine.lua
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@ -2254,6 +2254,19 @@ if (MACHINES["PLA"]~=null) then
}
end
---------------------------------------------------
--
--@src/devices/machine/pla.h,MACHINES["PXA255"] = true
---------------------------------------------------
if (MACHINES["PXA255"]~=null) then
files {
MAME_DIR .. "src/devices/machine/pxa255.cpp",
MAME_DIR .. "src/devices/machine/pxa255.h",
MAME_DIR .. "src/devices/machine/pxa255defs.h",
}
end
---------------------------------------------------
--
--@src/devices/machine/r10696.h,MACHINES["R10696"] = true

1
scripts/target/mame/arcade.lua
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@ -536,6 +536,7 @@ MACHINES["PIT8253"] = true
MACHINES["PLA"] = true
--MACHINES["PROFILE"] = true
--MACHINES["PROM82S129"] = true
MACHINES["PXA255"] = true
MACHINES["R10696"] = true
MACHINES["R10788"] = true
MACHINES["RA17XX"] = true

1
scripts/target/mame/mess.lua
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@ -534,6 +534,7 @@ MACHINES["PIT8253"] = true
MACHINES["PLA"] = true
--MACHINES["PROFILE"] = true
MACHINES["PROM82S129"] = true
MACHINES["PXA255"] = true
MACHINES["R64H156"] = true
MACHINES["RF5C296"] = true
MACHINES["RIOT6532"] = true

1240
src/devices/machine/pxa255.cpp Normal file
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235
src/devices/machine/pxa255.h Normal file
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@ -0,0 +1,235 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/**************************************************************************
*
* Intel XScale PXA255 peripheral emulation
*
* TODO:
* Most things
*
**************************************************************************/
#ifndef DEVICES_MACHINE_PXA255
#define DEVICES_MACHINE_PXA255
#pragma once
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "sound/dmadac.h"
#include "emupal.h"
#include "pxa255defs.h"
#define MCFG_PXA255_GPIO0_SET_CALLBACK(_devcb) \
devcb = &downcast<pxa255_periphs_device &>(*device).set_gpio0_set_cb(DEVCB_##_devcb);
#define MCFG_PXA255_GPIO0_CLEAR_CALLBACK(_devcb) \
devcb = &downcast<pxa255_periphs_device &>(*device).set_gpio0_clear_cb(DEVCB_##_devcb);
#define MCFG_PXA255_GPIO0_IN_CALLBACK(_devcb) \
devcb = &downcast<pxa255_periphs_device &>(*device).set_gpio0_in_cb(DEVCB_##_devcb);
class pxa255_periphs_device : public device_t
{
public:
template <typename T>
pxa255_periphs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag)
: pxa255_periphs_device(mconfig, tag, owner, clock)
{
m_maincpu.set_tag(std::forward<T>(cpu_tag));
}
pxa255_periphs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
template <class Object> devcb_base &set_gpio0_set_cb(Object &&cb) { return m_gpio0_set_func.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_gpio0_clear_cb(Object &&cb) { return m_gpio0_clear_func.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_gpio0_in_cb(Object &&cb) { return m_gpio0_in_func.set_callback(std::forward<Object>(cb)); }
DECLARE_READ32_MEMBER(pxa255_i2s_r);
DECLARE_WRITE32_MEMBER(pxa255_i2s_w);
DECLARE_READ32_MEMBER(pxa255_dma_r);
DECLARE_WRITE32_MEMBER(pxa255_dma_w);
DECLARE_READ32_MEMBER(pxa255_ostimer_r);
DECLARE_WRITE32_MEMBER(pxa255_ostimer_w);
DECLARE_READ32_MEMBER(pxa255_intc_r);
DECLARE_WRITE32_MEMBER(pxa255_intc_w);
DECLARE_READ32_MEMBER(pxa255_gpio_r);
DECLARE_WRITE32_MEMBER(pxa255_gpio_w);
DECLARE_READ32_MEMBER(pxa255_lcd_r);
DECLARE_WRITE32_MEMBER(pxa255_lcd_w);
protected:
virtual void device_add_mconfig(machine_config &config) override;
virtual void device_start() override;
virtual void device_reset() override;
void pxa255_dma_irq_check();
void pxa255_dma_load_descriptor_and_start(int channel);
void pxa255_ostimer_irq_check();
void pxa255_update_interrupts();
void pxa255_set_irq_line(uint32_t line, int state);
void pxa255_lcd_load_dma_descriptor(address_space & space, uint32_t address, int channel);
void pxa255_lcd_irq_check();
void pxa255_lcd_dma_kickoff(int channel);
void pxa255_lcd_check_load_next_branch(int channel);
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
TIMER_CALLBACK_MEMBER(pxa255_dma_dma_end);
TIMER_CALLBACK_MEMBER(pxa255_ostimer_match);
TIMER_CALLBACK_MEMBER(pxa255_lcd_dma_eof);
struct dma_regs_t
{
uint32_t dcsr[16];
uint32_t pad0[44];
uint32_t dint;
uint32_t pad1[3];
uint32_t drcmr[40];
uint32_t pad2[24];
uint32_t ddadr[16];
uint32_t dsadr[16];
uint32_t dtadr[16];
uint32_t dcmd[16];
emu_timer* timer[16];
};
struct i2s_regs_t
{
uint32_t sacr0;
uint32_t sacr1;
uint32_t pad0;
uint32_t sasr0;
uint32_t pad1;
uint32_t saimr;
uint32_t saicr;
uint32_t pad2[17];
uint32_t sadiv;
uint32_t pad3[6];
uint32_t sadr;
};
struct ostmr_regs_t
{
uint32_t osmr[4];
uint32_t oscr;
uint32_t ossr;
uint32_t ower;
uint32_t oier;
emu_timer* timer[4];
};
struct intc_regs_t
{
uint32_t icip;
uint32_t icmr;
uint32_t iclr;
uint32_t icfp;
uint32_t icpr;
uint32_t iccr;
};
struct gpio_regs_t
{
uint32_t gplr0; // GPIO Pin-Level
uint32_t gplr1;
uint32_t gplr2;
uint32_t gpdr0;
uint32_t gpdr1;
uint32_t gpdr2;
uint32_t gpsr0;
uint32_t gpsr1;
uint32_t gpsr2;
uint32_t gpcr0;
uint32_t gpcr1;
uint32_t gpcr2;
uint32_t grer0;
uint32_t grer1;
uint32_t grer2;
uint32_t gfer0;
uint32_t gfer1;
uint32_t gfer2;
uint32_t gedr0;
uint32_t gedr1;
uint32_t gedr2;
uint32_t gafr0l;
uint32_t gafr0u;
uint32_t gafr1l;
uint32_t gafr1u;
uint32_t gafr2l;
uint32_t gafr2u;
};
struct lcd_dma_regs_t
{
uint32_t fdadr;
uint32_t fsadr;
uint32_t fidr;
uint32_t ldcmd;
emu_timer *eof;
};
struct lcd_regs_t
{
uint32_t lccr0;
uint32_t lccr1;
uint32_t lccr2;
uint32_t lccr3;
uint32_t pad0[4];
uint32_t fbr[2];
uint32_t pad1[4];
uint32_t lcsr;
uint32_t liidr;
uint32_t trgbr;
uint32_t tcr;
uint32_t pad2[110];
lcd_dma_regs_t dma[2];
};
dma_regs_t m_dma_regs;
i2s_regs_t m_i2s_regs;
ostmr_regs_t m_ostimer_regs;
intc_regs_t m_intc_regs;
gpio_regs_t m_gpio_regs;
lcd_regs_t m_lcd_regs;
devcb_write32 m_gpio0_set_func;
devcb_write32 m_gpio0_clear_func;
devcb_read32 m_gpio0_in_func;
required_device<cpu_device> m_maincpu;
required_device_array<dmadac_sound_device, 2> m_dmadac;
required_device<palette_device> m_palette;
std::unique_ptr<uint32_t[]> m_pxa255_lcd_palette; // 0x100
std::unique_ptr<uint8_t[]> m_pxa255_lcd_framebuffer; // 0x100000
std::unique_ptr<uint32_t[]> m_words; // 0x800
std::unique_ptr<int16_t[]> m_samples; // 0x1000
inline void ATTR_PRINTF(3,4) verboselog(int n_level, const char *s_fmt, ... );
};
DECLARE_DEVICE_TYPE(PXA255_PERIPHERALS, pxa255_periphs_device)
#endif // DEVICES_MACHINE_PXA255

144
src/mame/machine/pxa255.h → src/devices/machine/pxa255defs.h
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@ -2,12 +2,14 @@
// copyright-holders:Ryan Holtz
/**************************************************************************
*
* Intel PXA255 on-chip peripheral emulation
*
* Mostly-incomplete implementation by Ryan Holtz
* Intel XScale PXA255 peripheral emulation defines
*
**************************************************************************/
#ifndef DEVICES_MACHINE_PXA255DEFS
#define DEVICES_MACHINE_PXA255DEFS
#pragma once
/*
PXA255 DMA controller
@ -165,28 +167,6 @@
#define PXA255_DCMD_WIDTH_2 (0x00008000)
#define PXA255_DCMD_WIDTH_4 (0x0000c000)
struct PXA255_DMA_Regs
{
uint32_t dcsr[16];
uint32_t pad0[44];
uint32_t dint;
uint32_t pad1[3];
uint32_t drcmr[40];
uint32_t pad2[24];
uint32_t ddadr[16];
uint32_t dsadr[16];
uint32_t dtadr[16];
uint32_t dcmd[16];
emu_timer* timer[16];
};
/*
PXA255 Inter-Integrated-Circuit Sound (I2S) Controller
@ -232,29 +212,6 @@ struct PXA255_DMA_Regs
#define PXA255_SADIV (PXA255_I2S_BASE_ADDR + 0x00000060)
#define PXA255_SADR (PXA255_I2S_BASE_ADDR + 0x00000080)
struct PXA255_I2S_Regs
{
uint32_t sacr0;
uint32_t sacr1;
uint32_t pad0;
uint32_t sasr0;
uint32_t pad1;
uint32_t saimr;
uint32_t saicr;
uint32_t pad2[17];
uint32_t sadiv;
uint32_t pad3[6];
uint32_t sadr;
};
/*
PXA255 OS Timer register
@ -281,17 +238,6 @@ struct PXA255_I2S_Regs
#define PXA255_OIER_E2 (0x00000004)
#define PXA255_OIER_E3 (0x00000008)
struct PXA255_OSTMR_Regs
{
uint32_t osmr[4];
uint32_t oscr;
uint32_t ossr;
uint32_t ower;
uint32_t oier;
emu_timer* timer[4];
};
/*
PXA255 Interrupt registers
@ -333,16 +279,6 @@ struct PXA255_OSTMR_Regs
#define PXA255_INT_RTC_HZ (1 << 30)
#define PXA255_INT_RTC_ALARM (1 << 31)
struct PXA255_INTC_Regs
{
uint32_t icip;
uint32_t icmr;
uint32_t iclr;
uint32_t icfp;
uint32_t icpr;
uint32_t iccr;
};
/*
PXA255 General-Purpose I/O registers
@ -380,44 +316,6 @@ struct PXA255_INTC_Regs
#define PXA255_GAFR2_L (PXA255_GPIO_BASE_ADDR + 0x00000064)
#define PXA255_GAFR2_U (PXA255_GPIO_BASE_ADDR + 0x00000068)
struct PXA255_GPIO_Regs
{
uint32_t gplr0; // GPIO Pin-Leve
uint32_t gplr1;
uint32_t gplr2;
uint32_t gpdr0;
uint32_t gpdr1;
uint32_t gpdr2;
uint32_t gpsr0;
uint32_t gpsr1;
uint32_t gpsr2;
uint32_t gpcr0;
uint32_t gpcr1;
uint32_t gpcr2;
uint32_t grer0;
uint32_t grer1;
uint32_t grer2;
uint32_t gfer0;
uint32_t gfer1;
uint32_t gfer2;
uint32_t gedr0;
uint32_t gedr1;
uint32_t gedr2;
uint32_t gafr0l;
uint32_t gafr0u;
uint32_t gafr1l;
uint32_t gafr1u;
uint32_t gafr2l;
uint32_t gafr2u;
};
/*
PXA255 LCD Controller
@ -478,34 +376,4 @@ struct PXA255_GPIO_Regs
#define PXA255_FIDR1 (PXA255_LCD_BASE_ADDR + 0x00000218)
#define PXA255_LDCMD1 (PXA255_LCD_BASE_ADDR + 0x0000021c)
struct PXA255_LCD_DMA_Regs
{
uint32_t fdadr;
uint32_t fsadr;
uint32_t fidr;
uint32_t ldcmd;
emu_timer *eof;
};
struct PXA255_LCD_Regs
{
uint32_t lccr0;
uint32_t lccr1;
uint32_t lccr2;
uint32_t lccr3;
uint32_t pad0[4];
uint32_t fbr[2];
uint32_t pad1[4];
uint32_t lcsr;
uint32_t liidr;
uint32_t trgbr;
uint32_t tcr;
uint32_t pad2[110];
PXA255_LCD_DMA_Regs dma[2];
};
#endif // DEVICES_MACHINE_PXA255DEFS

1425
src/mame/drivers/39in1.cpp
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