mirror of
https://github.com/holub/mame
synced 2025-05-22 21:58:57 +03:00
Merged DS5002FP into MCS51
* Merged DS5002FP * Disassembler now uses type specific memory names * Merged DS5002FP disasm * added 83C751 memory names to disassembler * delete DS5002FP specific files * removed unnecessary cpu callback in wrally * DATA_MAP ==> IO_MAP in wrally
This commit is contained in:
Couriersud
parent
109198d018
commit
eed3bdac15
4
.gitattributes
vendored
4
.gitattributes
vendored
@ -74,10 +74,6 @@ src/emu/cpu/drcfe.h svneol=native#text/plain
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src/emu/cpu/drcuml.c svneol=native#text/plain
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src/emu/cpu/drcuml.h svneol=native#text/plain
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src/emu/cpu/drcumlsh.h svneol=native#text/plain
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src/emu/cpu/ds5002fp/ds5002fp.c svneol=native#text/plain
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src/emu/cpu/ds5002fp/ds5002fp.h svneol=native#text/plain
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src/emu/cpu/ds5002fp/ds5002fpdasm.c svneol=native#text/plain
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src/emu/cpu/ds5002fp/ds5002fpops.c svneol=native#text/plain
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src/emu/cpu/dsp32/dsp32.c svneol=native#text/plain
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src/emu/cpu/dsp32/dsp32.h svneol=native#text/plain
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src/emu/cpu/dsp32/dsp32dis.c svneol=native#text/plain
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@ -663,8 +663,9 @@ CPUDEFS += -DHAS_I80C52=$(if $(filter I80C52,$(CPUS)),1,0)
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CPUDEFS += -DHAS_I87C51=$(if $(filter I87C51,$(CPUS)),1,0)
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CPUDEFS += -DHAS_I87C52=$(if $(filter I87C52,$(CPUS)),1,0)
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CPUDEFS += -DHAS_AT89C4051=$(if $(filter AT89C4051,$(CPUS)),1,0)
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CPUDEFS += -DHAS_DS5002FP=$(if $(filter DS5002FP,$(CPUS)),1,0)
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ifneq ($(filter I8031 I8032 I8051 I8052 I8751 I8752 I80C31 I80C32 I80C51 I80C52 I87C51 I87C52 AT89C4051,$(CPUS)),)
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ifneq ($(filter DS5002FP I8031 I8032 I8051 I8052 I8751 I8752 I80C31 I80C32 I80C51 I80C52 I87C51 I87C52 AT89C4051,$(CPUS)),)
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OBJDIRS += $(CPUOBJ)/mcs51
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CPUOBJS += $(CPUOBJ)/mcs51/mcs51.o
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DBGOBJS += $(CPUOBJ)/mcs51/mcs51dasm.o
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@ -674,22 +675,6 @@ $(CPUOBJ)/mcs51/mcs51.o: $(CPUSRC)/mcs51/mcs51.c \
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$(CPUSRC)/mcs51/mcs51.h \
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$(CPUSRC)/mcs51/mcs51ops.c
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#-------------------------------------------------
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# DS5002FP
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#-------------------------------------------------
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CPUDEFS += -DHAS_DS5002FP=$(if $(filter DS5002FP,$(CPUS)),1,0)
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ifneq ($(filter DS5002FP,$(CPUS)),)
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OBJDIRS += $(CPUOBJ)/ds5002fp
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CPUOBJS += $(CPUOBJ)/ds5002fp/ds5002fp.o
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DBGOBJS += $(CPUOBJ)/ds5002fp/ds5002fpdasm.o
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endif
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#-------------------------------------------------
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# Intel 80x86 series
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#-------------------------------------------------
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File diff suppressed because it is too large
Load Diff
@ -1,138 +0,0 @@
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/*****************************************************************************
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* DS5002FP emulator
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*
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* The emulator is just a modified version of the MCS-51 Family Emulator by Steve Ellenoff
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*
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*****************************************************************************/
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/*****************************************************************************
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*
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* i8051.h
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* Portable MCS-51 Family Emulator
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*
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* Chips in the family:
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* 8051 Product Line (8031,8051,8751)
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* 8052 Product Line (8032,8052,8752)
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* 8054 Product Line (8054)
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* 8058 Product Line (8058)
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*
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* Copyright Steve Ellenoff, all rights reserved.
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*
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* - This source code is released as freeware for non-commercial purposes.
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* - You are free to use and redistribute this code in modified or
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* unmodified form, provided you list me in the credits.
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* - If you modify this source code, you must add a notice to each modified
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* source file that it has been changed. If you're a nice person, you
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* will clearly mark each change too. :)
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* - If you wish to use this for commercial purposes, please contact me at
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* sellenoff@hotmail.com
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* - The author of this copywritten work reserves the right to change the
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* terms of its usage and license at any time, including retroactively
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* - This entire notice must remain in the source code.
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*
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* This work is based on:
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* #1) 'Intel(tm) MC51 Microcontroller Family Users Manual' and
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* #2) 8051 simulator by Travis Marlatte
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* #3) Portable UPI-41/8041/8741/8042/8742 emulator V0.1 by Juergen Buchmueller (MAME CORE)
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*
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*****************************************************************************/
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#pragma once
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#ifndef __DS5002FP_H__
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#define __DS5002FP_H__
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#include "cpuintrf.h"
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enum
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{
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DS5002FP_PC=1, DS5002FP_SP, DS5002FP_PSW, DS5002FP_ACC, DS5002FP_B, DS5002FP_DPH, DS5002FP_DPL, DS5002FP_IE,
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DS5002FP_PCON, DS5002FP_MCON, DS5002FP_RPCTL, DS5002FP_CRC,
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DS5002FP_R0, DS5002FP_R1, DS5002FP_R2, DS5002FP_R3, DS5002FP_R4, DS5002FP_R5, DS5002FP_R6, DS5002FP_R7, DS5002FP_RB
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};
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#define DS5002FP_INT0_LINE 0 /* External Interrupt 0 */
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#define DS5002FP_INT1_LINE 1 /* External Interrupt 1 */
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#define DS5002FP_T0_LINE 2 /* Timer 0 External Input */
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#define DS5002FP_T1_LINE 3 /* Timer 1 External Input */
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#define DS5002FP_RX_LINE 4 /* Serial Port Receive Line */
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#define DS5002FP_PFI_LINE 5 /* Power Fail Interrupt */
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/* definition of the special function registers. Note that the values are */
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/* the same as the internal memory address in the DS5002FP */
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#define P0 0x80
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#define SP 0x81
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#define DPL 0x82
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#define DPH 0x83
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#define PCON 0x87
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#define TCON 0x88
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#define TMOD 0x89
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#define TL0 0x8a
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#define TL1 0x8b
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#define TH0 0x8c
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#define TH1 0x8d
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#define P1 0x90
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#define SCON 0x98
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#define SBUF 0x99
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#define P2 0xa0
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#define IE 0xa8
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#define P3 0xb0
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#define IP 0xb8
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#define CRCR 0xc1
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#define CRCL 0xc2
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#define CRCH 0xc3
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#define MCON 0xc6
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#define TA 0xc7
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#define RNR 0xcf
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#define PSW 0xd0
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#define RPCTL 0xd8
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#define RPS 0xda
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#define ACC 0xe0
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#define B 0xf0
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/* commonly used bit address for the DS5002FP */
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#define C 0xd7
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#define P 0xd0
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#define AC 0xd6
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#define OV 0xd2
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#define PFW 0x8d
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#define TF1 0x8f
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#define IE0 0x89
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#define IE1 0x8b
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#define TI 0x99
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#define RI 0x98
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#define TI_FLAG 1
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#define RI_FLAG 2
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/* configuration of the DS5002FP */
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typedef struct _ds5002fp_config ds5002fp_config;
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struct _ds5002fp_config
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{
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UINT8 mcon; /* bootstrap loader MCON register */
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UINT8 rpctl; /* bootstrap loader RPCTL register */
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UINT8 crc; /* bootstrap loader CRC register */
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};
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extern void ds5002fp_get_context (void *dst); /* Get registers, return context size */
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extern void ds5002fp_set_context (void *src); /* Set registers */
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extern unsigned ds5002fp_get_intram (int offset);
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extern unsigned ds5002fp_get_reg (int regnum);
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extern void ds5002fp_set_reg (int regnum, unsigned val);
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extern void ds5002fp_set_irq_line(int irqline, int state);
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extern void ds5002fp_set_irq_callback(cpu_irq_callback callback);
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extern void ds5002fp_state_save(void *file);
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extern void ds5002fp_state_load(void *file);
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WRITE8_HANDLER( ds5002fp_internal_w );
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READ8_HANDLER( ds5002fp_internal_r );
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extern void ds5002fp_set_serial_tx_callback(void (*callback)(int data));
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extern void ds5002fp_set_serial_rx_callback(int (*callback)(void));
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extern void ds5002fp_set_ebram_iaddr_callback(READ32_HANDLER((*callback)));
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extern offs_t ds5002fp_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
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void ds5002fp_get_info(UINT32 state, cpuinfo *info);
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#endif /* __DS5002FP_H__ */
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File diff suppressed because it is too large
Load Diff
@ -1,960 +0,0 @@
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/*******************************************************************************************
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NOTE: All registers are accessed directly, instead of using the SFR_R() function for speed
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Direct register access is availabe from the R_(register name) macros.. ex: R_ACC for the ACC
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with the exception of the PC
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********************************************************************************************/
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//ACALL code addr /* 1: aaa1 0001 */
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INLINE void acall(void)
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{
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UINT8 op = ROP(PC-1); //Grab the opcode for ACALL
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UINT8 addr = ROP_ARG(PC++); //Grab code address byte
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PUSH_PC //Save PC to the stack
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//Thanks Gerrit for help with this! :)
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PC = (PC & 0xf800) | ((op & 0xe0) << 3) | addr;
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}
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//ADD A, #data /* 1: 0010 0100 */
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INLINE void add_a_byte(void)
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{
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UINT8 data = ROP_ARG(PC++); //Grab data
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UINT8 result = R_ACC + data; //Add data to accumulator
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DO_ADD_FLAGS(R_ACC,data,0) //Set Flags
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SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
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}
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//ADD A, data addr /* 1: 0010 0101 */
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INLINE void add_a_mem(void)
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{
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UINT8 addr = ROP_ARG(PC++); //Grab data address
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UINT8 data = IRAM_R(addr); //Grab data from data address
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UINT8 result = R_ACC + data; //Add data to accumulator
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DO_ADD_FLAGS(R_ACC,data,0); //Set Flags
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SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
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}
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//ADD A, @R0/@R1 /* 1: 0010 011i */
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INLINE void add_a_ir(int r)
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{
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UINT8 data = IRAM_IR(R_R(r)); //Grab data from memory pointed to by R0 or R1
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UINT8 result = R_ACC + data; //Add data to accumulator
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DO_ADD_FLAGS(R_ACC,data,0); //Set Flags
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SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
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}
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//ADD A, R0 to R7 /* 1: 0010 1rrr */
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INLINE void add_a_r(int r)
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{
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UINT8 data = R_R(r); //Grab data from R0 - R7
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UINT8 result = R_ACC + data; //Add data to accumulator
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DO_ADD_FLAGS(R_ACC,data,0); //Set Flags
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SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
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}
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//ADDC A, #data /* 1: 0011 0100 */
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INLINE void addc_a_byte(void)
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{
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UINT8 data = ROP_ARG(PC++); //Grab data
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UINT8 result = R_ACC + data + GET_CY; //Add data + carry flag to accumulator
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DO_ADD_FLAGS(R_ACC,data,GET_CY); //Set Flags
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SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
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}
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//ADDC A, data addr /* 1: 0011 0101 */
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INLINE void addc_a_mem(void)
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{
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UINT8 addr = ROP_ARG(PC++); //Grab data address
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UINT8 data = IRAM_R(addr); //Grab data from data address
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UINT8 result = R_ACC + data + GET_CY; //Add data + carry flag to accumulator
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DO_ADD_FLAGS(R_ACC,data,GET_CY); //Set Flags
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SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
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}
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//ADDC A, @R0/@R1 /* 1: 0011 011i */
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INLINE void addc_a_ir(int r)
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{
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UINT8 data = IRAM_IR(R_R(r)); //Grab data from memory pointed to by R0 or R1
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UINT8 result = R_ACC + data + GET_CY; //Add data + carry flag to accumulator
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DO_ADD_FLAGS(R_ACC,data,GET_CY); //Set Flags
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SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
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}
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//ADDC A, R0 to R7 /* 1: 0011 1rrr */
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INLINE void addc_a_r(int r)
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{
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UINT8 data = R_R(r); //Grab data from R0 - R7
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UINT8 result = R_ACC + data + GET_CY; //Add data + carry flag to accumulator
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DO_ADD_FLAGS(R_ACC,data,GET_CY); //Set Flags
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SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
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}
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//AJMP code addr /* 1: aaa0 0001 */
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INLINE void ajmp(void)
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{
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UINT8 op = ROP(PC-1); //Grab the opcode for AJMP
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UINT8 addr = ROP_ARG(PC++); //Grab code address byte
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//Thanks Gerrit for help with this! :)
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PC = (PC & 0xf800) | ((op & 0xe0) << 3) | addr;
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}
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//ANL data addr, A /* 1: 0101 0010 */
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INLINE void anl_mem_a(void)
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{
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UINT8 addr = ROP_ARG(PC++); //Grab data address
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UINT8 data = IRAM_R(addr); //Grab data from data address
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IRAM_W(addr,data & R_ACC); //Set data address value to it's value Logical AND with ACC
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}
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//ANL data addr, #data /* 1: 0101 0011 */
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INLINE void anl_mem_byte(void)
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{
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UINT8 addr = ROP_ARG(PC++); //Grab data address
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UINT8 data = ROP_ARG(PC++); //Grab data
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UINT8 srcdata = IRAM_R(addr); //Grab data from data address
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IRAM_W(addr,srcdata & data); //Set data address value to it's value Logical AND with Data
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}
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//ANL A, #data /* 1: 0101 0100 */
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INLINE void anl_a_byte(void)
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{
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UINT8 data = ROP_ARG(PC++); //Grab data
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SFR_W(ACC,R_ACC & data); //Set ACC to value of ACC Logical AND with Data
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}
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//ANL A, data addr /* 1: 0101 0101 */
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INLINE void anl_a_mem(void)
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{
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UINT8 addr = ROP_ARG(PC++); //Grab data address
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UINT8 data = IRAM_R(addr); //Grab data from data address
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SFR_W(ACC,R_ACC & data); //Set ACC to value of ACC Logical AND with Data
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}
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//ANL A, @RO/@R1 /* 1: 0101 011i */
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INLINE void anl_a_ir(int r)
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{
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UINT8 data = IRAM_IR(R_R(r)); //Grab data from address R0 or R1 points to
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SFR_W(ACC,R_ACC & data); //Set ACC to value of ACC Logical AND with Data
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}
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//ANL A, RO to R7 /* 1: 0101 1rrr */
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INLINE void anl_a_r(int r)
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{
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UINT8 data = R_R(r); //Grab data from R0 - R7
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SFR_W(ACC,R_ACC & data); //Set ACC to value of ACC Logical AND with Data
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}
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//ANL C, bit addr /* 1: 1000 0010 */
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INLINE void anl_c_bitaddr(void)
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{
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int cy = GET_CY;
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UINT8 addr = ROP_ARG(PC++); //Grab bit address
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UINT8 bit = BIT_R(addr); //Grab bit data from bit address
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SET_CY( (cy & bit) ); //Set Carry flag to Carry Flag Value Logical AND with Bit
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}
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//ANL C,/bit addr /* 1: 1011 0000 */
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INLINE void anl_c_nbitaddr(void)
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{
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int cy = GET_CY;
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UINT8 addr = ROP_ARG(PC++); //Grab bit address
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UINT8 bit = BIT_R(addr); //Grab bit data from bit address
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bit = ((~bit)&1); //Complement bit
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SET_CY( (cy & bit) ); //Set Carry flag to Carry Flag Value Logical AND with Complemented Bit
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}
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//CJNE A, #data, code addr /* 1: 1011 0100 */
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INLINE void cjne_a_byte(void)
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{
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UINT8 data = ROP_ARG(PC++); //Grab data
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INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
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if(R_ACC != data) //Jump if values are not equal
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PC = PC + rel_addr;
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//Set carry flag to 1 if 1st compare value is < 2nd compare value
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SET_CY( (R_ACC < data) );
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}
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//CJNE A, data addr, code addr /* 1: 1011 0101 */
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INLINE void cjne_a_mem(void)
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{
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UINT8 addr = ROP_ARG(PC++); //Grab data address
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INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
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UINT8 data = IRAM_R(addr); //Pull value from data address
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if(R_ACC != data) //Jump if values are not equal
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PC = PC + rel_addr;
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//Set carry flag to 1 if 1st compare value is < 2nd compare value
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SET_CY( (R_ACC < data) );
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}
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//CJNE @R0/@R1, #data, code addr /* 1: 1011 011i */
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INLINE void cjne_ir_byte(int r)
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{
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UINT8 data = ROP_ARG(PC++); //Grab data
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INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
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UINT8 srcdata = IRAM_IR(R_R(r)); //Grab value pointed to by R0 or R1
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if(srcdata != data) //Jump if values are not equal
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PC = PC + rel_addr;
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//Set carry flag to 1 if 1st compare value is < 2nd compare value
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SET_CY( (srcdata < data) );
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}
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//CJNE R0 to R7, #data, code addr /* 1: 1011 1rrr */
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INLINE void cjne_r_byte(int r)
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{
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UINT8 data = ROP_ARG(PC++); //Grab data
|
||||
INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
|
||||
UINT8 srcdata = R_R(r); //Grab value of R0 - R7
|
||||
|
||||
if(srcdata != data) //Jump if values are not equal
|
||||
PC = PC + rel_addr;
|
||||
|
||||
//Set carry flag to 1 if 1st compare value is < 2nd compare value
|
||||
SET_CY( (srcdata < data) );
|
||||
}
|
||||
|
||||
//CLR bit addr /* 1: 1100 0010 */
|
||||
INLINE void clr_bitaddr(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab bit address
|
||||
BIT_W(addr,0); //Clear bit at specified bit address
|
||||
}
|
||||
|
||||
//CLR C /* 1: 1100 0011 */
|
||||
INLINE void clr_c(void)
|
||||
{
|
||||
SET_CY(0); //Clear Carry Flag
|
||||
}
|
||||
|
||||
//CLR A /* 1: 1110 0100 */
|
||||
INLINE void clr_a(void)
|
||||
{
|
||||
SFR_W(ACC,0); //Clear Accumulator
|
||||
}
|
||||
|
||||
//CPL bit addr /* 1: 1011 0010 */
|
||||
INLINE void cpl_bitaddr(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab bit address
|
||||
UINT8 data = (~BIT_R(addr))&1;
|
||||
BIT_W(addr,data); //Complement bit at specified bit address
|
||||
}
|
||||
|
||||
//CPL C /* 1: 1011 0011 */
|
||||
INLINE void cpl_c(void)
|
||||
{
|
||||
UINT8 bit = (~GET_CY)&1; //Complement Carry Flag
|
||||
SET_CY(bit);
|
||||
}
|
||||
|
||||
//CPL A /* 1: 1111 0100 */
|
||||
INLINE void cpl_a(void)
|
||||
{
|
||||
UINT8 data = ((~R_ACC)&0xff);
|
||||
SFR_W(ACC,data); //Complement Accumulator
|
||||
}
|
||||
|
||||
//DA A /* 1: 1101 0100 */
|
||||
INLINE void da_a(void)
|
||||
{
|
||||
/*From several sources, since none said the same thing:
|
||||
The decimal adjust instruction is associated with the use of the ADD and ADDC instructions.
|
||||
The eight-bit value in the accumulator is adjusted to form two BCD digits of four bits each.
|
||||
If the accumulator contents bits 0-3 are greater than 9, OR the AC flag is set, then six is added to
|
||||
produce a proper BCD digit.
|
||||
If the carry is set, OR the four high bits 4-7 exceed nine, six is added to the value of these bits.
|
||||
The carry flag will be set if the result is > 0x99, but not cleared otherwise */
|
||||
|
||||
UINT16 new_acc = R_ACC & 0xff;
|
||||
if(GET_AC || (new_acc & 0x0f) > 0x09)
|
||||
new_acc += 0x06;
|
||||
if(GET_CY || ((new_acc & 0xf0) > 0x90) || (new_acc & ~0xff))
|
||||
new_acc += 0x60;
|
||||
SFR_W(ACC,new_acc&0xff);
|
||||
if(new_acc & ~0xff)
|
||||
SET_CY(1);
|
||||
}
|
||||
|
||||
//DEC A /* 1: 0001 0100 */
|
||||
INLINE void dec_a(void)
|
||||
{
|
||||
SFR_W(ACC,R_ACC-1);
|
||||
}
|
||||
|
||||
//DEC data addr /* 1: 0001 0101 */
|
||||
INLINE void dec_mem(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
UINT8 data = IRAM_R(addr);
|
||||
IRAM_W(addr,data-1);
|
||||
}
|
||||
|
||||
//DEC @R0/@R1 /* 1: 0001 011i */
|
||||
INLINE void dec_ir(int r)
|
||||
{
|
||||
UINT8 data = IRAM_IR(R_R(r));
|
||||
IRAM_W(R_R(r),data-1);
|
||||
}
|
||||
|
||||
//DEC R0 to R7 /* 1: 0001 1rrr */
|
||||
INLINE void dec_r(int r)
|
||||
{
|
||||
R_R(r) = R_R(r) - 1;
|
||||
}
|
||||
|
||||
//DIV AB /* 1: 1000 0100 */
|
||||
INLINE void div_ab(void)
|
||||
{
|
||||
if( R_B == 0 ) {
|
||||
//Overflow flag is set!
|
||||
SET_OV(1);
|
||||
//Really the values are undefined according to the manual, but we'll just leave them as is..
|
||||
//SFR_W(ACC,0xff);
|
||||
//SFR_W(B,0xff);
|
||||
}
|
||||
else {
|
||||
int a = (int)R_ACC/R_B;
|
||||
int b = (int)R_ACC%R_B;
|
||||
//A gets quotient byte, B gets remainder byte
|
||||
SFR_W(ACC,a);
|
||||
SFR_W(B, b);
|
||||
//Overflow flag is cleared
|
||||
SET_OV(0);
|
||||
}
|
||||
//Carry Flag is always cleared
|
||||
SET_CY(0);
|
||||
}
|
||||
|
||||
//DJNZ data addr, code addr /* 1: 1101 0101 */
|
||||
INLINE void djnz_mem(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
|
||||
IRAM_W(addr,IRAM_R(addr) - 1); //Decrement value contained at data address
|
||||
if(IRAM_R(addr) != 0) //Branch if contents of data address is not 0
|
||||
PC = PC + rel_addr;
|
||||
}
|
||||
|
||||
//DJNZ R0 to R7,code addr /* 1: 1101 1rrr */
|
||||
INLINE void djnz_r(int r)
|
||||
{
|
||||
INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
|
||||
R_R(r) = R_R(r) - 1; //Decrement value
|
||||
if(R_R(r) != 0) //Branch if contents of R0 - R7 is not 0
|
||||
PC = PC + rel_addr;
|
||||
}
|
||||
|
||||
//INC A /* 1: 0000 0100 */
|
||||
INLINE void inc_a(void)
|
||||
{
|
||||
SFR_W(ACC,R_ACC+1);
|
||||
}
|
||||
|
||||
//INC data addr /* 1: 0000 0101 */
|
||||
INLINE void inc_mem(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
UINT8 data = IRAM_R(addr);
|
||||
IRAM_W(addr,data+1);
|
||||
}
|
||||
|
||||
//INC @R0/@R1 /* 1: 0000 011i */
|
||||
INLINE void inc_ir(int r)
|
||||
{
|
||||
UINT8 data = IRAM_IR(R_R(r));
|
||||
IRAM_W(R_R(r),data+1);
|
||||
}
|
||||
|
||||
//INC R0 to R7 /* 1: 0000 1rrr */
|
||||
INLINE void inc_r(int r)
|
||||
{
|
||||
UINT8 data = R_R(r);
|
||||
R_R(r) = data + 1;
|
||||
}
|
||||
|
||||
//INC DPTR /* 1: 1010 0011 */
|
||||
INLINE void inc_dptr(void)
|
||||
{
|
||||
UINT16 dptr = (R_DPTR)+1;
|
||||
DPTR_W(dptr);
|
||||
}
|
||||
|
||||
//JB bit addr, code addr /* 1: 0010 0000 */
|
||||
INLINE void jb(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab bit address
|
||||
INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
|
||||
if(BIT_R(addr)) //If bit set at specified bit address, jump
|
||||
PC = PC + rel_addr;
|
||||
}
|
||||
|
||||
//JBC bit addr, code addr /* 1: 0001 0000 */
|
||||
INLINE void jbc(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab bit address
|
||||
INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
|
||||
if(BIT_R(addr)) { //If bit set at specified bit address, jump
|
||||
PC = PC + rel_addr;
|
||||
BIT_W(addr,0); //Clear Bit also
|
||||
}
|
||||
}
|
||||
|
||||
//JC code addr /* 1: 0100 0000 */
|
||||
INLINE void jc(void)
|
||||
{
|
||||
INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
|
||||
if(GET_CY) //Jump if Carry Flag Set
|
||||
PC = PC + rel_addr;
|
||||
}
|
||||
|
||||
//JMP @A+DPTR /* 1: 0111 0011 */
|
||||
INLINE void jmp_iadptr(void)
|
||||
{
|
||||
PC = R_ACC+R_DPTR;
|
||||
}
|
||||
|
||||
//JNB bit addr, code addr /* 1: 0011 0000 */
|
||||
INLINE void jnb(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab bit address
|
||||
INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
|
||||
if(!BIT_R(addr)) //If bit NOT set at specified bit address, jump
|
||||
PC = PC + rel_addr;
|
||||
}
|
||||
|
||||
//JNC code addr /* 1: 0101 0000 */
|
||||
INLINE void jnc(void)
|
||||
{
|
||||
INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
|
||||
if(!GET_CY) //Jump if Carry Flag not set
|
||||
PC = PC + rel_addr;
|
||||
}
|
||||
|
||||
//JNZ code addr /* 1: 0111 0000 */
|
||||
INLINE void jnz(void)
|
||||
{
|
||||
INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
|
||||
if(R_ACC != 0) //Branch if ACC is not 0
|
||||
PC = PC+rel_addr;
|
||||
}
|
||||
|
||||
//JZ code addr /* 1: 0110 0000 */
|
||||
INLINE void jz(void)
|
||||
{
|
||||
INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
|
||||
if(R_ACC == 0) //Branch if ACC is 0
|
||||
PC = PC+rel_addr;
|
||||
}
|
||||
|
||||
//LCALL code addr /* 1: 0001 0010 */
|
||||
INLINE void lcall(void)
|
||||
{
|
||||
UINT8 addr_hi, addr_lo;
|
||||
addr_hi = ROP_ARG(PC++);
|
||||
addr_lo = ROP_ARG(PC++);
|
||||
PUSH_PC
|
||||
PC = (UINT16)((addr_hi<<8) | addr_lo);
|
||||
}
|
||||
|
||||
//LJMP code addr /* 1: 0000 0010 */
|
||||
INLINE void ljmp(void)
|
||||
{
|
||||
UINT8 addr_hi, addr_lo;
|
||||
addr_hi = ROP_ARG(PC++);
|
||||
addr_lo = ROP_ARG(PC++);
|
||||
PC = (UINT16)((addr_hi<<8) | addr_lo);
|
||||
}
|
||||
|
||||
//MOV A, #data /* 1: 0111 0100 */
|
||||
INLINE void mov_a_byte(void)
|
||||
{
|
||||
UINT8 data = ROP_ARG(PC++); //Grab data
|
||||
SFR_W(ACC,data); //Store data to ACC
|
||||
}
|
||||
|
||||
//MOV A, data addr /* 1: 1110 0101 */
|
||||
INLINE void mov_a_mem(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
SFR_W(ACC,IRAM_R(addr)); //Store contents of data address to ACC
|
||||
}
|
||||
|
||||
//MOV A,@RO/@R1 /* 1: 1110 011i */
|
||||
INLINE void mov_a_ir(int r)
|
||||
{
|
||||
SFR_W(ACC,IRAM_IR(R_R(r))); //Store contents of address pointed by R0 or R1 to ACC
|
||||
}
|
||||
|
||||
//MOV A,R0 to R7 /* 1: 1110 1rrr */
|
||||
INLINE void mov_a_r(int r)
|
||||
{
|
||||
SFR_W(ACC,R_R(r)); //Store contents of R0 - R7 to ACC
|
||||
}
|
||||
|
||||
//MOV data addr, #data /* 1: 0111 0101 */
|
||||
INLINE void mov_mem_byte(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
UINT8 data = ROP_ARG(PC++); //Grab data
|
||||
IRAM_W(addr,data); //Store data to data address location
|
||||
}
|
||||
|
||||
//MOV data addr, data addr /* 1: 1000 0101 */
|
||||
INLINE void mov_mem_mem(void)
|
||||
{
|
||||
//1st address is src, 2nd is dst, but the mov command works as mov dst,src)
|
||||
UINT8 src,dst;
|
||||
src = ROP_ARG(PC++); //Grab source data address
|
||||
dst = ROP_ARG(PC++); //Grab destination data address
|
||||
IRAM_W(dst,IRAM_R(src)); //Read source address contents and store to destination address
|
||||
}
|
||||
|
||||
//MOV @R0/@R1, #data /* 1: 0111 011i */
|
||||
INLINE void mov_ir_byte(int r)
|
||||
{
|
||||
UINT8 data = ROP_ARG(PC++); //Grab data
|
||||
IRAM_IW(R_R(r),data); //Store data to address pointed by R0 or R1
|
||||
}
|
||||
|
||||
//MOV R0 to R7, #data /* 1: 0111 1rrr */
|
||||
INLINE void mov_r_byte(int r)
|
||||
{
|
||||
UINT8 data = ROP_ARG(PC++); //Grab data
|
||||
R_R(r) = data; //Store to R0 - R7
|
||||
}
|
||||
|
||||
//MOV data addr, @R0/@R1 /* 1: 1000 011i */
|
||||
INLINE void mov_mem_ir(int r)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
IRAM_W(addr,IRAM_IR(R_R(r))); //Store contents pointed to by R0 or R1 to data address
|
||||
}
|
||||
|
||||
//MOV data addr,R0 to R7 /* 1: 1000 1rrr */
|
||||
INLINE void mov_mem_r(int r)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
IRAM_W(addr,R_R(r)); //Store contents of R0 - R7 to data address
|
||||
}
|
||||
|
||||
//MOV DPTR, #data16 /* 1: 1001 0000 */
|
||||
INLINE void mov_dptr_byte(void)
|
||||
{
|
||||
UINT8 data_hi, data_lo;
|
||||
data_hi = ROP_ARG(PC++); //Grab hi byte
|
||||
data_lo = ROP_ARG(PC++); //Grab lo byte
|
||||
DPTR_W((UINT16)((data_hi<<8)|data_lo)); //Store to DPTR
|
||||
}
|
||||
|
||||
//MOV bit addr, C /* 1: 1001 0010 */
|
||||
INLINE void mov_bitaddr_c(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab bit address
|
||||
BIT_W(addr,GET_CY); //Store Carry Flag to Bit Address
|
||||
}
|
||||
|
||||
//MOV @R0/@R1, data addr /* 1: 1010 011i */
|
||||
INLINE void mov_ir_mem(int r)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
IRAM_IW(R_R(r),IRAM_R(addr)); //Store data from data address to address pointed to by R0 or R1
|
||||
}
|
||||
|
||||
//MOV R0 to R7, data addr /* 1: 1010 1rrr */
|
||||
INLINE void mov_r_mem(int r)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
R_R(r) = IRAM_R(addr); //Store to R0 - R7
|
||||
}
|
||||
|
||||
//MOV data addr, A /* 1: 1111 0101 */
|
||||
INLINE void mov_mem_a(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
IRAM_W(addr,R_ACC); //Store A to data address
|
||||
}
|
||||
|
||||
//MOV @R0/@R1, A /* 1: 1111 011i */
|
||||
INLINE void mov_ir_a(int r)
|
||||
{
|
||||
IRAM_IW(R_R(r),R_ACC); //Store A to location pointed to by R0 or R1
|
||||
}
|
||||
|
||||
//MOV R0 to R7, A /* 1: 1111 1rrr */
|
||||
INLINE void mov_r_a(int r)
|
||||
{
|
||||
R_R(r) = R_ACC; //Store A to R0-R7
|
||||
}
|
||||
|
||||
//MOVC A, @A + PC /* 1: 1000 0011 */
|
||||
INLINE void movc_a_iapc(void)
|
||||
{
|
||||
UINT8 data;
|
||||
data = CODEMEM_R(R_ACC+PC); //Move a byte from CODE(Program) Memory and store to ACC
|
||||
SFR_W(ACC,data);
|
||||
}
|
||||
|
||||
//MOV C, bit addr /* 1: 1010 0010 */
|
||||
INLINE void mov_c_bitaddr(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab bit address
|
||||
SET_CY( (BIT_R(addr)) ); //Store Bit from Bit Address to Carry Flag
|
||||
}
|
||||
|
||||
//MOVC A, @A + DPTR /* 1: 1001 0011 */
|
||||
INLINE void movc_a_iadptr(void)
|
||||
{
|
||||
UINT8 data;
|
||||
data = CODEMEM_R(R_ACC+R_DPTR); //Move a byte from CODE(Program) Memory and store to ACC
|
||||
SFR_W(ACC,data);
|
||||
}
|
||||
|
||||
//MOVX A,@DPTR /* 1: 1110 0000 */
|
||||
//(Move External Ram 16 bit address to A)
|
||||
INLINE void movx_a_idptr(void)
|
||||
{
|
||||
// UINT8 byte = DATAMEM_R(R_DPTR); //Grab 1 byte from External DATA memory pointed to by dptr
|
||||
UINT32 addr = ERAM_ADDR(R_DPTR,0xFFFF);
|
||||
UINT8 byte = DATAMEM_R(addr); //Grab 1 byte from External DATA memory pointed to by dptr
|
||||
SFR_W(ACC,byte); //Store to ACC
|
||||
}
|
||||
|
||||
//MOVX A, @R0/@R1 /* 1: 1110 001i */
|
||||
//(Move External Ram 8 bit address to A)
|
||||
INLINE void movx_a_ir(int r)
|
||||
{
|
||||
UINT32 addr = ERAM_ADDR(R_R(r),0xFF); //Grab address by reading location pointed to by R0 or R1
|
||||
UINT8 byte = DATAMEM_R(addr); //Grab 1 byte from External DATA memory pointed to by address
|
||||
SFR_W(ACC,byte); //Store to ACC
|
||||
}
|
||||
|
||||
//MOVX @DPTR,A /* 1: 1111 0000 */
|
||||
//(Move A to External Ram 16 bit address)
|
||||
INLINE void movx_idptr_a(void)
|
||||
{
|
||||
// DATAMEM_W(R_DPTR, R_ACC); //Store ACC to External DATA memory address pointed to by DPTR
|
||||
UINT32 addr = ERAM_ADDR(R_DPTR,0xFFFF);
|
||||
DATAMEM_W(addr, R_ACC); //Store ACC to External DATA memory address pointed to by DPTR
|
||||
}
|
||||
|
||||
//MOVX @R0/@R1,A /* 1: 1111 001i */
|
||||
//(Move A to External Ram 8 bit address)
|
||||
INLINE void movx_ir_a(int r)
|
||||
{
|
||||
UINT32 addr = ERAM_ADDR(R_R(r),0xFF); //Grab address by reading location pointed to by R0 or R1
|
||||
DATAMEM_W(addr, R_ACC); //Store ACC to External DATA memory address
|
||||
}
|
||||
|
||||
//MUL AB /* 1: 1010 0100 */
|
||||
INLINE void mul_ab(void)
|
||||
{
|
||||
UINT16 result = R_ACC * R_B;
|
||||
//A gets lo bits, B gets hi bits of result
|
||||
SFR_W(B,(UINT8)((result & 0xFF00) >> 8));
|
||||
SFR_W(ACC,(UINT8)(result & 0x00FF));
|
||||
//Set flags
|
||||
SET_OV( ((result & 0x100) >> 8) ); //Set/Clear Overflow Flag if result > 255
|
||||
SET_CY(0); //Carry Flag always cleared
|
||||
}
|
||||
|
||||
//NOP /* 1: 0000 0000 */
|
||||
INLINE void nop(void)
|
||||
{
|
||||
}
|
||||
|
||||
//ORL data addr, A /* 1: 0100 0010 */
|
||||
INLINE void orl_mem_a(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
UINT8 data = IRAM_R(addr); //Grab data from data address
|
||||
IRAM_W(addr,data | R_ACC); //Set data address value to it's value Logical OR with ACC
|
||||
}
|
||||
|
||||
//ORL data addr, #data /* 1: 0100 0011 */
|
||||
INLINE void orl_mem_byte(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
UINT8 data = ROP_ARG(PC++); //Grab data
|
||||
UINT8 srcdata = IRAM_R(addr); //Grab data from data address
|
||||
IRAM_W(addr,srcdata | data); //Set data address value to it's value Logical OR with Data
|
||||
}
|
||||
|
||||
//ORL A, #data /* 1: 0100 0100 */
|
||||
INLINE void orl_a_byte(void)
|
||||
{
|
||||
UINT8 data = ROP_ARG(PC++); //Grab data
|
||||
SFR_W(ACC,R_ACC | data); //Set ACC to value of ACC Logical OR with Data
|
||||
}
|
||||
|
||||
//ORL A, data addr /* 1: 0100 0101 */
|
||||
INLINE void orl_a_mem(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
UINT8 data = IRAM_R(addr); //Grab data from data address
|
||||
SFR_W(ACC,R_ACC | data); //Set ACC to value of ACC Logical OR with Data
|
||||
}
|
||||
|
||||
//ORL A, @RO/@R1 /* 1: 0100 011i */
|
||||
INLINE void orl_a_ir(int r)
|
||||
{
|
||||
UINT8 data = IRAM_IR(R_R(r)); //Grab data from address R0 or R1 points to
|
||||
SFR_W(ACC,R_ACC | data); //Set ACC to value of ACC Logical OR with Data
|
||||
}
|
||||
|
||||
//ORL A, RO to R7 /* 1: 0100 1rrr */
|
||||
INLINE void orl_a_r(int r)
|
||||
{
|
||||
UINT8 data = R_R(r); //Grab data from R0 - R7
|
||||
SFR_W(ACC,R_ACC | data); //Set ACC to value of ACC Logical OR with Data
|
||||
}
|
||||
|
||||
//ORL C, bit addr /* 1: 0111 0010 */
|
||||
INLINE void orl_c_bitaddr(void)
|
||||
{
|
||||
int cy = GET_CY;
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab bit address
|
||||
UINT8 bit = BIT_R(addr); //Grab bit data from bit address
|
||||
SET_CY( (cy | bit) ); //Set Carry flag to Carry Flag Value Logical OR with Bit
|
||||
}
|
||||
|
||||
//ORL C, /bit addr /* 1: 1010 0000 */
|
||||
INLINE void orl_c_nbitaddr(void)
|
||||
{
|
||||
int cy = GET_CY;
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab bit address
|
||||
UINT8 bit = BIT_R(addr); //Grab bit data from bit address
|
||||
bit = ((~bit)&1); //Complement bit
|
||||
SET_CY( (cy | bit) ); //Set Carry flag to Carry Flag Value Logical OR with Complemented Bit
|
||||
}
|
||||
|
||||
//POP data addr /* 1: 1101 0000 */
|
||||
INLINE void pop(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
IRAM_W(addr, IRAM_IR(R_SP)); //Store to contents of data addr, data pointed to by Stack - IRAM_IR needed to access upper 128 bytes of stack
|
||||
//IRAM_IW(addr, IRAM_IR(R_SP)); //Store to contents of data addr, data pointed to by Stack - doesn't work, sfr's are not restored this way and it's not an indirect access anyway
|
||||
SFR_W(SP,R_SP-1); //Decrement SP
|
||||
}
|
||||
|
||||
//PUSH data addr /* 1: 1100 0000 */
|
||||
INLINE void push(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
UINT8 tmpSP = R_SP; //Grab and Increment Stack Pointer
|
||||
tmpSP++; // ""
|
||||
SFR_W(SP,tmpSP); // ""
|
||||
if (tmpSP == R_SP) //Ensure it was able to write to new stack location
|
||||
IRAM_IW(tmpSP, IRAM_R(addr)); //Store to stack contents of data address - IRAM_IW needed to store to upper 128 bytes of stack, however, can't use IRAM_IR because that won't store the sfrs and it's not an indirect access anyway
|
||||
}
|
||||
|
||||
//RET /* 1: 0010 0010 */
|
||||
INLINE void ret(void)
|
||||
{
|
||||
POP_PC
|
||||
}
|
||||
|
||||
//RETI /* 1: 0011 0010 */
|
||||
INLINE void reti(void)
|
||||
{
|
||||
POP_PC
|
||||
CLEAR_CURRENT_IRQ
|
||||
}
|
||||
|
||||
//RL A /* 1: 0010 0011 */
|
||||
INLINE void rl_a(void)
|
||||
{
|
||||
//Left Shift A, Bit 7 carries to Bit 0
|
||||
int carry = ((R_ACC & 0x80) >> 7);
|
||||
int data = (R_ACC<<1) & 0xfe;
|
||||
SFR_W(ACC, data | carry);
|
||||
}
|
||||
|
||||
//RLC A /* 1: 0011 0011 */
|
||||
INLINE void rlc_a(void)
|
||||
{
|
||||
//Left Shift A, Bit 7 goes to Carry Flag, Original Carry Flag goes to Bit 0 of ACC
|
||||
int carry = ((R_ACC & 0x80) >> 7);
|
||||
int data = ((R_ACC<<1) & 0xfe) | GET_CY;
|
||||
SFR_W(ACC, data);
|
||||
SET_CY(carry);
|
||||
}
|
||||
|
||||
//RR A /* 1: 0000 0011 */
|
||||
INLINE void rr_a(void)
|
||||
{
|
||||
//Right Shift A, Bit 0 carries to Bit 7
|
||||
int carry = ((R_ACC & 1) << 7);
|
||||
int data = (R_ACC>>1) & 0x7f;
|
||||
SFR_W(ACC, data | carry);
|
||||
}
|
||||
|
||||
//RRC A /* 1: 0001 0011 */
|
||||
INLINE void rrc_a(void)
|
||||
{
|
||||
//Right Shift A, Bit 0 goes to Carry Flag, Bit 7 of ACC gets set to original Carry Flag
|
||||
int carry = (R_ACC & 1);
|
||||
int data = ((R_ACC>>1) & 0x7f) | (GET_CY<<7);
|
||||
SFR_W(ACC, data);
|
||||
SET_CY(carry);
|
||||
}
|
||||
|
||||
//SETB C /* 1: 1101 0011 */
|
||||
INLINE void setb_c(void)
|
||||
{
|
||||
SET_CY(1); //Set Carry Flag
|
||||
}
|
||||
|
||||
//SETB bit addr /* 1: 1101 0010 */
|
||||
INLINE void setb_bitaddr(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab bit address
|
||||
BIT_W(addr,1); //Set Bit at Bit Address
|
||||
}
|
||||
|
||||
//SJMP code addr /* 1: 1000 0000 */
|
||||
INLINE void sjmp(void)
|
||||
{
|
||||
INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
|
||||
PC = PC + rel_addr; //Update PC
|
||||
}
|
||||
|
||||
//SUBB A, #data /* 1: 1001 0100 */
|
||||
INLINE void subb_a_byte(void)
|
||||
{
|
||||
UINT8 data = ROP_ARG(PC++); //Grab data
|
||||
UINT8 result = R_ACC - data - GET_CY; //Subtract data & carry flag from accumulator
|
||||
DO_SUB_FLAGS(R_ACC,data,GET_CY); //Set Flags
|
||||
SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
|
||||
|
||||
}
|
||||
|
||||
//SUBB A, data addr /* 1: 1001 0101 */
|
||||
INLINE void subb_a_mem(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
UINT8 data = IRAM_R(addr); //Grab data from data address
|
||||
UINT8 result = R_ACC - data - GET_CY; //Subtract data & carry flag from accumulator
|
||||
DO_SUB_FLAGS(R_ACC,data,GET_CY); //Set Flags
|
||||
SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
|
||||
}
|
||||
|
||||
//SUBB A, @R0/@R1 /* 1: 1001 011i */
|
||||
INLINE void subb_a_ir(int r)
|
||||
{
|
||||
UINT8 data = IRAM_IR(R_R(r)); //Grab data from memory pointed to by R0 or R1
|
||||
UINT8 result = R_ACC - data - GET_CY; //Subtract data & carry flag from accumulator
|
||||
DO_SUB_FLAGS(R_ACC,data,GET_CY); //Set Flags
|
||||
SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
|
||||
}
|
||||
|
||||
//SUBB A, R0 to R7 /* 1: 1001 1rrr */
|
||||
INLINE void subb_a_r(int r)
|
||||
{
|
||||
UINT8 data = R_R(r); //Grab data from R0 - R7
|
||||
UINT8 result = R_ACC - data - GET_CY; //Subtract data & carry flag from accumulator
|
||||
DO_SUB_FLAGS(R_ACC,data,GET_CY); //Set Flags
|
||||
SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
|
||||
}
|
||||
|
||||
//SWAP A /* 1: 1100 0100 */
|
||||
INLINE void swap_a(void)
|
||||
{
|
||||
UINT8 a_nib_lo, a_nib_hi;
|
||||
a_nib_hi = (R_ACC & 0x0f) << 4; //Grab lo byte of ACC and move to hi
|
||||
a_nib_lo = (R_ACC & 0xf0) >> 4; //Grab hi byte of ACC and move to lo
|
||||
SFR_W(ACC, a_nib_hi | a_nib_lo);
|
||||
}
|
||||
|
||||
//XCH A, data addr /* 1: 1100 0101 */
|
||||
INLINE void xch_a_mem(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
UINT8 data = IRAM_R(addr); //Grab data
|
||||
UINT8 oldACC = R_ACC; //Hold value of ACC
|
||||
SFR_W(ACC,data); //Sets ACC to data
|
||||
IRAM_W(addr,oldACC); //Sets data address to old value of ACC
|
||||
}
|
||||
|
||||
//XCH A, @RO/@R1 /* 1: 1100 011i */
|
||||
INLINE void xch_a_ir(int r)
|
||||
{
|
||||
UINT8 data = IRAM_IR(R_R(r)); //Grab data pointed to by R0 or R1
|
||||
UINT8 oldACC = R_ACC; //Hold value of ACC
|
||||
SFR_W(ACC,data); //Sets ACC to data
|
||||
IRAM_W(R_R(r),oldACC); //Sets data address to old value of ACC
|
||||
}
|
||||
|
||||
//XCH A, RO to R7 /* 1: 1100 1rrr */
|
||||
INLINE void xch_a_r(int r)
|
||||
{
|
||||
UINT8 data = R_R(r); //Grab data from R0-R7
|
||||
UINT8 oldACC = R_ACC; //Hold value of ACC
|
||||
SFR_W(ACC,data); //Sets ACC to data
|
||||
R_R(r) = oldACC; //Sets data address to old value of ACC
|
||||
}
|
||||
|
||||
//XCHD A, @R0/@R1 /* 1: 1101 011i */
|
||||
INLINE void xchd_a_ir(int r)
|
||||
{
|
||||
UINT8 acc, ir_data;
|
||||
ir_data = IRAM_IR(R_R(r)); //Grab data pointed to by R0 or R1
|
||||
acc = R_ACC; //Grab ACC value
|
||||
SFR_W(ACC, (acc & 0xf0) | (ir_data & 0x0f) ); //Set ACC to lower nibble of data pointed to by R0 or R1
|
||||
IRAM_W(R_R(r), (ir_data & 0xf0) | (acc & 0x0f) ); //Set data pointed to by R0 or R1 to lower nibble of ACC
|
||||
}
|
||||
|
||||
//XRL data addr, A /* 1: 0110 0010 */
|
||||
INLINE void xrl_mem_a(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
UINT8 data = IRAM_R(addr); //Grab data from data address
|
||||
IRAM_W(addr,data ^ R_ACC); //Set data address value to it's value Logical XOR with ACC
|
||||
}
|
||||
|
||||
//XRL data addr, #data /* 1: 0110 0011 */
|
||||
INLINE void xrl_mem_byte(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
UINT8 data = ROP_ARG(PC++); //Grab data
|
||||
UINT8 srcdata = IRAM_R(addr); //Grab data from data address
|
||||
IRAM_W(addr,srcdata ^ data); //Set data address value to it's value Logical XOR with Data
|
||||
}
|
||||
|
||||
//XRL A, #data /* 1: 0110 0100 */
|
||||
INLINE void xrl_a_byte(void)
|
||||
{
|
||||
UINT8 data = ROP_ARG(PC++); //Grab data
|
||||
SFR_W(ACC,R_ACC ^ data); //Set ACC to value of ACC Logical XOR with Data
|
||||
}
|
||||
|
||||
//XRL A, data addr /* 1: 0110 0101 */
|
||||
INLINE void xrl_a_mem(void)
|
||||
{
|
||||
UINT8 addr = ROP_ARG(PC++); //Grab data address
|
||||
UINT8 data = IRAM_R(addr); //Grab data from data address
|
||||
SFR_W(ACC,R_ACC ^ data); //Set ACC to value of ACC Logical XOR with Data
|
||||
}
|
||||
|
||||
//XRL A, @R0/@R1 /* 1: 0110 011i */
|
||||
INLINE void xrl_a_ir(int r)
|
||||
{
|
||||
UINT8 data = IRAM_IR(R_R(r)); //Grab data from address R0 or R1 points to
|
||||
SFR_W(ACC,R_ACC ^ data); //Set ACC to value of ACC Logical XOR with Data
|
||||
}
|
||||
|
||||
//XRL A, R0 to R7 /* 1: 0110 1rrr */
|
||||
INLINE void xrl_a_r(int r)
|
||||
{
|
||||
UINT8 data = R_R(r); //Grab data from R0 - R7
|
||||
SFR_W(ACC,R_ACC ^ data); //Set ACC to value of ACC Logical XOR with Data
|
||||
}
|
||||
|
||||
//illegal opcodes
|
||||
INLINE void illegal(void)
|
||||
{
|
||||
LOG(("ds5002fp #%d: illegal opcode at 0x%03x: %02x\n", cpu_getactivecpu(), PC, ROP(PC)));
|
||||
}
|
||||
@ -30,11 +30,51 @@
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* DS5002FP emulator by Manuel Abadia
|
||||
*
|
||||
* October 2008, couriersud: Merged back in mcs51
|
||||
*
|
||||
* What has been added?
|
||||
* - Extra SFRs
|
||||
* - Bytewide Bus Support
|
||||
* - Memory Partition and Memory Range
|
||||
* - Bootstrap Configuration
|
||||
* - Power Fail Interrupt
|
||||
* - Timed Access
|
||||
* - Stop Mode
|
||||
* - Idle Mode
|
||||
*
|
||||
* What is not implemented?
|
||||
* - Peripherals and Reprogrammable Peripheral Controller
|
||||
* - CRC-16
|
||||
* - Watchdog timer
|
||||
*
|
||||
* The main features of the DS5002FP are:
|
||||
* - 100% code-compatible with 8051
|
||||
* - Directly addresses 64kB program/64kB data memory
|
||||
* - Nonvolatile memory control circuitry
|
||||
* - 10-year data retention in the absence of power
|
||||
* - In-system reprogramming via serial port
|
||||
* - Dedicated memory bus, preserving four 8-bit ports for general purpose I/O
|
||||
* - Power-fail reset
|
||||
* - Early warning power-fail interrupt
|
||||
* - Watchdog timer
|
||||
* - Accesses up to 128kB on the bytewide bus
|
||||
* - Decodes memory for 32kB x 8 or 128kB x 8 SRAMs
|
||||
* - Four additional decoded peripheral-chip enables
|
||||
* - CRC hardware for checking memory validity
|
||||
* - Optionally emulates an 8042-style slave interface
|
||||
* - Memory encryption using an 80-bit encryption key
|
||||
* - Automatic random generation of encryption keys
|
||||
* - Self-destruct input for tamper protection
|
||||
* - Optional top-coating prevents microprobe
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* Notes:
|
||||
* *Important*: Internal ROM needs to be treated the same as external rom by the programmer
|
||||
* creating the driver (ie, use standard cpu rom region)
|
||||
*
|
||||
*
|
||||
* The term cycles is used here to really refer to clock oscilations, because 1 machine cycle
|
||||
* actually takes 12 oscilations.
|
||||
*
|
||||
@ -53,12 +93,6 @@
|
||||
* July 28,2004: Fixed MOVX command and added External Ram Paging Support
|
||||
* July 31,2004: Added Serial Mode 0 Support & Fixed Interrupt Flags for Serial Port
|
||||
*
|
||||
* NOW Implemented: RAM paging using hardware configured addressing...
|
||||
* (July 28,2004) the "MOVX a,@R0/R1" and "MOVX @R0/R1,a" commands can use any of the other ports
|
||||
* to output a page offset into external ram, but it is totally based on the hardware setup.
|
||||
*
|
||||
* Timing needs to be implemented via MAME timers perhaps?
|
||||
*
|
||||
* October, 2008, Couriersud - Major rewrite
|
||||
*
|
||||
*****************************************************************************/
|
||||
@ -69,17 +103,20 @@
|
||||
* - T0 output clock ?
|
||||
*
|
||||
* - Implement 80C52 extended serial capabilities
|
||||
* - Full Timer support (all modes)
|
||||
* - Fix serial communication - This is a big hack (but working) right now.
|
||||
* - Implement 83C751 in sslam.c
|
||||
* - Fix cardline.c
|
||||
* - Fix sslam.c and cardline.c
|
||||
* most likely due to different behaviour of I/O pins. The boards
|
||||
* actually use 80CXX, i.e. CMOS versions.
|
||||
* "Normal" 805X will return a 0 if reading from a output port which has
|
||||
* a 0 written to it's latch. At least cardline expects a 1 here.
|
||||
*
|
||||
* Done:
|
||||
* Done: (Couriersud)
|
||||
* - Merged DS5002FP
|
||||
* - Disassembler now uses type specific memory names
|
||||
* - Merged DS5002FP disasm
|
||||
* - added 83C751 memory names to disassembler
|
||||
* - Pointer-ified
|
||||
* - Implemented cmos features
|
||||
* - Implemented 80C52 interrupt handling
|
||||
* - Fix segas18.c (segaic16.c) memory handling.
|
||||
@ -592,19 +629,6 @@ struct _mcs51_regs
|
||||
#define PUSH_PC() push_pc(mcs51)
|
||||
#define POP_PC() pop_pc(mcs51)
|
||||
|
||||
#if 0
|
||||
/* Any pending IRQ */
|
||||
#define SERIALPORT_IRQ ((R_SCON & 0x03) && GET_ES)
|
||||
#define TIMERS_IRQ ((GET_TF0 && GET_ET0) || (GET_TF1 && GET_ET1))
|
||||
#define EXTERNAL_IRQ ((GET_IE0 && GET_EX0) || (GET_IE1 && GET_EX1))
|
||||
|
||||
#if (HAS_I8052 || HAS_I8752)
|
||||
#define NO_PENDING_IRQ !(TIMERS_IRQ) && !(EXTERNAL_IRQ) && !(SERIALPORT_IRQ) && !(GET_ET2 && (GET_TF2 || GET_EXF2))
|
||||
#else
|
||||
#define NO_PENDING_IRQ !(TIMERS_IRQ) && !(EXTERNAL_IRQ) && !(SERIALPORT_IRQ)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Clear Current IRQ */
|
||||
#define CLEAR_CURRENT_IRQ() clear_current_irq(mcs51)
|
||||
|
||||
@ -712,12 +736,6 @@ INLINE offs_t external_ram_iaddr(mcs51_regs *mcs51, offs_t offset, offs_t mem_ma
|
||||
if (mem_mask == 0x00ff)
|
||||
return (offset & mem_mask) | (P2 << 8);
|
||||
}
|
||||
#if 0
|
||||
if(mcs51->eram_iaddr_callback)
|
||||
return mcs51->eram_iaddr_callback(machine,offset,mem_mask);
|
||||
else
|
||||
if (mem_mask <= 0x100) LOG(("mcs51 #%d: external ram address requested (8 bit offset=%02x), but no callback available! at PC:%04x\n", cpu_getactivecpu(), offset, PC));
|
||||
#endif
|
||||
return offset;
|
||||
}
|
||||
|
||||
@ -1961,7 +1979,6 @@ static void mcs51_sfr_write(mcs51_regs *mcs51, size_t offset, UINT8 data)
|
||||
/* update register */
|
||||
assert(offset >= 0x80 && offset <= 0xff);
|
||||
|
||||
/* TODO: Move to memory map */
|
||||
switch (offset)
|
||||
{
|
||||
case ADDR_P0: OUT(MCS51_PORT_P0,data); break;
|
||||
@ -2278,7 +2295,7 @@ static CPU_INIT( i80c31 )
|
||||
/****************************************************************************
|
||||
* DS5002FP Section
|
||||
****************************************************************************/
|
||||
#ifdef MCS51_TO_BE_ENABLED_LATER
|
||||
#if 1 //#ifdef MCS51_TO_BE_ENABLED_LATER
|
||||
|
||||
|
||||
#define DS5_LOGW(a, d) LOG(("ds5002fp #%d: write to " # a " register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, d))
|
||||
@ -2331,19 +2348,19 @@ static UINT8 ds5002fp_sfr_read(mcs51_regs *mcs51, size_t offset)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
case ADDR_CRCR: DS5_LOGR(CRCR, data); break;
|
||||
case ADDR_CRCR: DS5_LOGR(CRCR, data); break;
|
||||
case ADDR_CRCL: DS5_LOGR(CRCL, data); break;
|
||||
case ADDR_CRCH: DS5_LOGR(CRCH, data); break;
|
||||
case ADDR_CRCH: DS5_LOGR(CRCH, data); break;
|
||||
case ADDR_MCON: DS5_LOGR(MCON, data); break;
|
||||
case ADDR_TA: DS5_LOGR(TA, data); break;
|
||||
case ADDR_TA: DS5_LOGR(TA, data); break;
|
||||
case ADDR_RNR: DS5_LOGR(RNR, data); break;
|
||||
case ADDR_RPCTL: DS5_LOGR(RPCTL, data); break;
|
||||
case ADDR_RPCTL: DS5_LOGR(RPCTL, data); break;
|
||||
case ADDR_RPS: DS5_LOGR(RPS, data); break;
|
||||
case ADDR_PCON:
|
||||
SET_PFW(0); /* reset PFW flag */
|
||||
return mcs51_sfr_read(mcs51, offset); /* FIXME: cmos features ??? */
|
||||
return mcs51_sfr_read(mcs51, offset);
|
||||
default:
|
||||
return mcs51_sfr_read(mcs51, offset); /* FIXME: cmos features ??? */
|
||||
return mcs51_sfr_read(mcs51, offset);
|
||||
}
|
||||
return data_read_byte_8le((size_t) offset | 0x100);
|
||||
}
|
||||
@ -2355,7 +2372,7 @@ static CPU_INIT( ds5002fp )
|
||||
const ds5002fp_config *sconfig = config ? config : &default_config;
|
||||
mcs51_regs *mcs51 = device->token;
|
||||
|
||||
mcs51_init(index, clock, config, irqcallback);
|
||||
CPU_INIT_CALL( mcs51 );
|
||||
|
||||
mcs51->ds5002fp.config = sconfig;
|
||||
mcs51->features |= (FEATURE_DS5002FP | FEATURE_CMOS);
|
||||
@ -2373,8 +2390,6 @@ static CPU_INIT( ds5002fp )
|
||||
ADDRESS MAPS
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
/* FIXME: the memory maps should probably support rom banking for EA */
|
||||
static ADDRESS_MAP_START(program_12bit, ADDRESS_SPACE_PROGRAM, 8)
|
||||
AM_RANGE(0x00, 0x0fff) AM_ROM
|
||||
ADDRESS_MAP_END
|
||||
@ -2467,69 +2482,69 @@ static void mcs51_get_info(UINT32 state, cpuinfo *info)
|
||||
switch (state)
|
||||
{
|
||||
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
||||
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(mcs51_regs); break;
|
||||
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
|
||||
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
|
||||
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
|
||||
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 12; break;
|
||||
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
|
||||
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break;
|
||||
case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
|
||||
case CPUINFO_INT_MAX_CYCLES: info->i = 20; /* rough guess */ break;
|
||||
case CPUINFO_INT_INPUT_LINES: info->i = 3; break;
|
||||
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(mcs51_regs); break;
|
||||
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
|
||||
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
|
||||
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
|
||||
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 12; break;
|
||||
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
|
||||
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break;
|
||||
case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
|
||||
case CPUINFO_INT_MAX_CYCLES: info->i = 20; /* rough guess */ break;
|
||||
case CPUINFO_INT_INPUT_LINES: info->i = 3; break;
|
||||
|
||||
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 8; break;
|
||||
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 16; break;
|
||||
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break;
|
||||
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 8; break;
|
||||
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 8; break;
|
||||
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 16; break;
|
||||
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break;
|
||||
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 8; break;
|
||||
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 9; /* due to sfr mapping */ break;
|
||||
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break;
|
||||
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 8; break;
|
||||
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 17; break;
|
||||
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
|
||||
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break;
|
||||
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 8; break;
|
||||
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 18; /* 128k for ds5002fp */ break;
|
||||
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
|
||||
|
||||
case CPUINFO_INT_PREVIOUSPC: info->i = PPC; break;
|
||||
case CPUINFO_INT_PC: info->i = PC; break;
|
||||
case CPUINFO_INT_SP: info->i = SP; break;
|
||||
|
||||
case CPUINFO_INT_PREVIOUSPC: info->i = PPC; break;
|
||||
case CPUINFO_INT_PC: info->i = PC; break;
|
||||
case CPUINFO_INT_SP: info->i = SP; break;
|
||||
|
||||
case CPUINFO_INT_REGISTER + MCS51_PC: info->i = PC; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_SP: info->i = SP; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_PSW: info->i = PSW; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_ACC: info->i = ACC; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_B: info->i = B; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_DPH: info->i = DPH; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_DPL: info->i = DPL; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_IE: info->i = IE; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R0: info->i = R_REG(0); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R1: info->i = R_REG(1); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R2: info->i = R_REG(2); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R3: info->i = R_REG(3); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R4: info->i = R_REG(4); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R5: info->i = R_REG(5); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R6: info->i = R_REG(6); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R7: info->i = R_REG(7); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_RB: info->i = R_REG(8); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_PC: info->i = PC; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_SP: info->i = SP; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_PSW: info->i = PSW; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_ACC: info->i = ACC; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_B: info->i = B; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_DPH: info->i = DPH; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_DPL: info->i = DPL; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_IE: info->i = IE; break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R0: info->i = R_REG(0); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R1: info->i = R_REG(1); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R2: info->i = R_REG(2); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R3: info->i = R_REG(3); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R4: info->i = R_REG(4); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R5: info->i = R_REG(5); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R6: info->i = R_REG(6); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_R7: info->i = R_REG(7); break;
|
||||
case CPUINFO_INT_REGISTER + MCS51_RB: info->i = R_REG(8); break;
|
||||
|
||||
/* --- the following bits of info are returned as pointers to data or functions --- */
|
||||
case CPUINFO_PTR_SET_INFO: info->setinfo = mcs51_set_info; break;
|
||||
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = mcs51_get_context; break;
|
||||
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = mcs51_set_context; break;
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(mcs51); break;
|
||||
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(mcs51); break;
|
||||
case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(mcs51); break;
|
||||
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(mcs51); break;
|
||||
case CPUINFO_PTR_BURN: info->burn = NULL; break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = i8051_dasm; break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &mcs51->icount; break;
|
||||
case CPUINFO_PTR_SET_INFO: info->setinfo = mcs51_set_info; break;
|
||||
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = mcs51_get_context; break;
|
||||
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = mcs51_set_context; break;
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(mcs51); break;
|
||||
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(mcs51); break;
|
||||
case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(mcs51); break;
|
||||
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(mcs51); break;
|
||||
case CPUINFO_PTR_BURN: info->burn = NULL; break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = i8051_dasm; break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &mcs51->icount; break;
|
||||
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map8 = NULL; break;
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map8 = NULL; break;
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_IO: info->internal_map8 = NULL; break;
|
||||
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8051"); break;
|
||||
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "MCS-51"); break;
|
||||
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.0"); break;
|
||||
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8051"); break;
|
||||
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "MCS-51"); break;
|
||||
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.0"); break;
|
||||
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
|
||||
case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Copyright Steve Ellenoff"); break;
|
||||
|
||||
case CPUINFO_STR_FLAGS:
|
||||
@ -2545,21 +2560,21 @@ static void mcs51_get_info(UINT32 state, cpuinfo *info)
|
||||
break;
|
||||
|
||||
case CPUINFO_STR_REGISTER + MCS51_PC: sprintf(info->s, "PC:%04X", mcs51->pc); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_SP: sprintf(info->s, "SP:%02X", SP); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_PSW: sprintf(info->s, "PSW:%02X", PSW); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_ACC: sprintf(info->s, "A:%02X", ACC); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_B: sprintf(info->s, "B:%02X", B); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_DPH: sprintf(info->s, "DPH:%02X", DPH); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_DPL: sprintf(info->s, "DPL:%02X", DPL); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_IE: sprintf(info->s, "IE:%02X", IE); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R0: sprintf(info->s, "R0:%02X", R_REG(0)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R1: sprintf(info->s, "R1:%02X", R_REG(1)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R2: sprintf(info->s, "R2:%02X", R_REG(2)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R3: sprintf(info->s, "R3:%02X", R_REG(3)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R4: sprintf(info->s, "R4:%02X", R_REG(4)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R5: sprintf(info->s, "R5:%02X", R_REG(5)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R6: sprintf(info->s, "R6:%02X", R_REG(6)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R7: sprintf(info->s, "R7:%02X", R_REG(7)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_SP: sprintf(info->s, "SP:%02X", SP); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_PSW: sprintf(info->s, "PSW:%02X", PSW); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_ACC: sprintf(info->s, "A:%02X", ACC); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_B: sprintf(info->s, "B:%02X", B); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_DPH: sprintf(info->s, "DPH:%02X", DPH); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_DPL: sprintf(info->s, "DPL:%02X", DPL); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_IE: sprintf(info->s, "IE:%02X", IE); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R0: sprintf(info->s, "R0:%02X", R_REG(0)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R1: sprintf(info->s, "R1:%02X", R_REG(1)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R2: sprintf(info->s, "R2:%02X", R_REG(2)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R3: sprintf(info->s, "R3:%02X", R_REG(3)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R4: sprintf(info->s, "R4:%02X", R_REG(4)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R5: sprintf(info->s, "R5:%02X", R_REG(5)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R6: sprintf(info->s, "R6:%02X", R_REG(6)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_R7: sprintf(info->s, "R7:%02X", R_REG(7)); break;
|
||||
case CPUINFO_STR_REGISTER + MCS51_RB: sprintf(info->s, "RB:%02X", ((PSW & 0x18)>>3)); break;
|
||||
}
|
||||
}
|
||||
@ -2573,9 +2588,8 @@ void i8031_get_info(UINT32 state, cpuinfo *info)
|
||||
switch (state)
|
||||
{
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map8 = address_map_data_7bit; break;
|
||||
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8031"); break;
|
||||
default: mcs51_get_info(state, info); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8031"); break;
|
||||
default: mcs51_get_info(state, info); break;
|
||||
}
|
||||
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
||||
}
|
||||
@ -2586,9 +2600,8 @@ void i8051_get_info(UINT32 state, cpuinfo *info)
|
||||
{
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map8 = address_map_program_12bit; break;
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map8 = address_map_data_7bit; break;
|
||||
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8051"); break;
|
||||
default: mcs51_get_info(state, info); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8051"); break;
|
||||
default: mcs51_get_info(state, info); break;
|
||||
}
|
||||
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
||||
}
|
||||
@ -2597,13 +2610,11 @@ void i8032_get_info(UINT32 state, cpuinfo *info)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i8052); break;
|
||||
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i8052); break;
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map8 = address_map_data_8bit; break;
|
||||
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8032"); break;
|
||||
|
||||
default: mcs51_get_info(state, info); break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = i8052_dasm; break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8032"); break;
|
||||
default: mcs51_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2611,14 +2622,12 @@ void i8052_get_info(UINT32 state, cpuinfo *info)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i8052); break;
|
||||
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i8052); break;
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map8 = address_map_program_13bit; break;
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map8 = address_map_data_8bit; break;
|
||||
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8052"); break;
|
||||
|
||||
default: mcs51_get_info(state, info); break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = i8052_dasm; break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8052"); break;
|
||||
default: mcs51_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2628,10 +2637,8 @@ void i8751_get_info(UINT32 state, cpuinfo *info)
|
||||
{
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map8 = address_map_program_12bit; break;
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map8 = address_map_data_7bit; break;
|
||||
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8751"); break;
|
||||
|
||||
default: mcs51_get_info(state, info); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8751"); break;
|
||||
default: mcs51_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2639,14 +2646,12 @@ void i8752_get_info(UINT32 state, cpuinfo *info)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i8052); break;
|
||||
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i8052); break;
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map8 = address_map_program_13bit; break;
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map8 = address_map_data_8bit; break;
|
||||
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8752"); break;
|
||||
|
||||
default: mcs51_get_info(state, info); break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = i8052_dasm; break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I8752"); break;
|
||||
default: mcs51_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2660,13 +2665,12 @@ void i80c31_get_info(UINT32 state, cpuinfo *info)
|
||||
* of i80c52 with 128 bytes internal ram */
|
||||
switch (state)
|
||||
{
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c31); break;
|
||||
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c31); break;
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map8 = NULL; break;
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map8 = address_map_data_7bit; break;
|
||||
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I80C31"); break;
|
||||
default: i8031_get_info(state, info); break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = i80c51_dasm; break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I80C31"); break;
|
||||
default: i8031_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2674,9 +2678,10 @@ void i80c51_get_info(UINT32 state, cpuinfo *info)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c51); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I80C51"); break;
|
||||
default: i8051_get_info(state, info); break;
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c51); break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = i80c51_dasm; break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I80C51"); break;
|
||||
default: i8051_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2684,9 +2689,10 @@ void i80c32_get_info(UINT32 state, cpuinfo *info)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c52); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I80C32"); break;
|
||||
default: i8032_get_info(state, info); break;
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c52); break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = i80c52_dasm; break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I80C32"); break;
|
||||
default: i8032_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2694,9 +2700,10 @@ void i80c52_get_info(UINT32 state, cpuinfo *info)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c52); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I80C52"); break;
|
||||
default: i8052_get_info(state, info); break;
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c52); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I80C52"); break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = i80c52_dasm; break;
|
||||
default: i8052_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2704,9 +2711,10 @@ void i87c51_get_info(UINT32 state, cpuinfo *info)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c51); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I87C51"); break;
|
||||
default: i8751_get_info(state, info); break;
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c51); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I87C51"); break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = i80c51_dasm; break;
|
||||
default: i8751_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2714,9 +2722,10 @@ void i87c52_get_info(UINT32 state, cpuinfo *info)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c52); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I87C52"); break;
|
||||
default: i8752_get_info(state, info); break;
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c52); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "I87C52"); break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = i80c52_dasm; break;
|
||||
default: i8752_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2728,8 +2737,24 @@ void at89c4051_get_info(UINT32 state, cpuinfo *info)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c51); break;
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80c51); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "AT89C4051"); break;
|
||||
default: i8051_get_info(state, info); break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = i80c51_dasm; break;
|
||||
default: i8051_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
void ds5002fp_get_info(UINT32 state, cpuinfo *info)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(ds5002fp); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "DS5002FP"); break;
|
||||
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Dallas"); break;
|
||||
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.0"); break;
|
||||
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
|
||||
case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Copyright Manuel Abadia"); break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = ds5002fp_dasm; break;
|
||||
default: i8051_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -66,11 +66,11 @@ enum
|
||||
|
||||
enum
|
||||
{
|
||||
MCS51_PORT_P0 = 0x10000,
|
||||
MCS51_PORT_P1 = 0x10001,
|
||||
MCS51_PORT_P2 = 0x10002,
|
||||
MCS51_PORT_P3 = 0x10003,
|
||||
MCS51_PORT_TX = 0x10004, /* P3.1 */
|
||||
MCS51_PORT_P0 = 0x20000,
|
||||
MCS51_PORT_P1 = 0x20001,
|
||||
MCS51_PORT_P2 = 0x20002,
|
||||
MCS51_PORT_P3 = 0x20003,
|
||||
MCS51_PORT_TX = 0x20004, /* P3.1 */
|
||||
};
|
||||
|
||||
/***************************************************************************
|
||||
@ -119,10 +119,33 @@ void i87c52_get_info(UINT32 state, cpuinfo *info);
|
||||
/* 4k internal perom and 128 internal ram and 2 analog comparators */
|
||||
void at89c4051_get_info(UINT32 state, cpuinfo *info);
|
||||
|
||||
/*
|
||||
* The DS5002FP has 2 16 bits data address buses (the byte-wide bus and the expanded bus). The exact memory position accessed depends on the
|
||||
* partition mode, the memory range and the expanded bus select. The partition mode and the expanded bus select can be changed at any time.
|
||||
*
|
||||
* In order to simplify memory mapping to the data address bus, the following address map is assumed for partitioned mode:
|
||||
|
||||
* 0x00000-0x0ffff -> data memory on the expanded bus
|
||||
* 0x10000-0x1ffff -> data memory on the byte-wide bus
|
||||
|
||||
* For non-partitioned mode the following memory map is assumed:
|
||||
|
||||
* 0x0000-0xffff -> data memory (the bus used to access it does not matter)
|
||||
*
|
||||
* Internal ram 128k and security features
|
||||
*/
|
||||
|
||||
void ds5002fp_get_info(UINT32 state, cpuinfo *info);
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Disassembler
|
||||
****************************************************************************/
|
||||
|
||||
offs_t i8051_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
|
||||
offs_t i80c51_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
|
||||
offs_t i8052_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
|
||||
offs_t i80c52_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
|
||||
offs_t ds5002fp_dasm(char *dst, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
|
||||
|
||||
#endif /* __MCS51_H__ */
|
||||
|
||||
@ -36,6 +36,17 @@
|
||||
#include "debugger.h"
|
||||
#include "mcs51.h"
|
||||
|
||||
enum
|
||||
{
|
||||
FEATURE_NONE = 0x00,
|
||||
FEATURE_I8052 = 0x01,
|
||||
FEATURE_CMOS = 0x02,
|
||||
FEATURE_I80C52 = 0x04,
|
||||
FEATURE_DS5002FP = 0x08,
|
||||
FEATURE_I83C751 = 0x08,
|
||||
};
|
||||
|
||||
|
||||
#define SHOW_MEMORY_NAMES 1
|
||||
|
||||
#ifdef SHOW_MEMORY_NAMES
|
||||
@ -43,143 +54,244 @@
|
||||
/*Display the memory address names for data & bit address access*/
|
||||
|
||||
//SFR Names
|
||||
static const char sfr[128][7] = {
|
||||
"p0", "sp", "dpl", "dph", /* 80 - 83 */
|
||||
"adat", "85h", "86h", "pcon", /* 84 - 87 */
|
||||
"tcon", "tmod", "tl0", "tl1", /* 88 - 8b */
|
||||
"th0", "th1", "pwcm", "pwmp", /* 8a - 8f */
|
||||
"p1", "91h", "92h", "93h", /* 90 - 93 */
|
||||
"94h", "95h", "96h", "97h", /* 94 - 97 */
|
||||
"scon", "sbuf", "9ah", "9bh", /* 98 - 9b */
|
||||
"9ch", "9dh", "9eh", "9fh", /* 9c - 9f */
|
||||
"p2", "0a1h", "0a2h", "0a3h", /* a0 - a3 */
|
||||
"0a4h", "0a5h", "0a6h", "0a7h", /* a4 - a7 */
|
||||
"ie", "cml0", "cml1", "cml2", /* a8 - ab */
|
||||
"ctl0", "ctl1", "ctl2", "ctl3", /* ac - af */
|
||||
"p3", "0b1h", "0b2h", "0b3h", /* b0 - b3 */
|
||||
"0b4h", "0b5h", "0b6h", "0b7h", /* b4 - b7 */
|
||||
"ip", "0b9h", "0bah", "0bbh", /* b8 - bb */
|
||||
"0bch", "0bdh", "0beh", "0bfh", /* bc - bf */
|
||||
"p4", "0c1h", "0c2h", "0c3h", /* c0 - c3 */
|
||||
"p5", "adcon", "adch", "0c7h", /* c4 - c7 */
|
||||
"t2con", "cmh0", "rcap2l", "rcap2h", /* c8 - cb */
|
||||
"tl2", "th2", "cth2", "cth3", /* cc - cf */
|
||||
"psw", "0d1h", "0d2h", "0d3h", /* d0 - d3 */
|
||||
"0d4h", "0d5h", "0d6h", "0d7h", /* d4 - d7 */
|
||||
"i2cfg", "s1sta", "s1dat", "s1adr", /* d8 - db */
|
||||
"0dch", "0ddh", "0deh", "0dfh", /* dc - df */
|
||||
"acc", "0e1h", "0e2h", "0e3h", /* e0 - e3 */
|
||||
"0e4h", "0e5h", "0e6h", "0e7h", /* e4 - e7 */
|
||||
"csr", "0e9h", "tm2con", "ctcon", /* e8 - eb */
|
||||
"tml2", "tmh2", "ste", "rte", /* ec - ef */
|
||||
"b", "0f1h", "0f2h", "0f3h", /* f0 - f3 */
|
||||
"0f4h", "0f5h", "0f6h", "0f7h", /* f4 - f7 */
|
||||
"i2sta", "0f9h", "0fah", "0fbh", /* f8 - fb */
|
||||
"pwm0", "pwm1", "pwena", "t3" /* fc - ff */
|
||||
|
||||
static struct {
|
||||
int feature;
|
||||
int addr;
|
||||
const char *name;
|
||||
} mem_name_feature[] =
|
||||
{
|
||||
{ FEATURE_NONE, 0x00, "rb0r0" },
|
||||
{ FEATURE_NONE, 0x01, "rb0r1" },
|
||||
{ FEATURE_NONE, 0x02, "rb0r2" },
|
||||
{ FEATURE_NONE, 0x03, "rb0r3" },
|
||||
{ FEATURE_NONE, 0x04, "rb0r4" },
|
||||
{ FEATURE_NONE, 0x05, "rb0r5" },
|
||||
{ FEATURE_NONE, 0x06, "rb0r6" },
|
||||
{ FEATURE_NONE, 0x07, "rb0r7" },
|
||||
{ FEATURE_NONE, 0x08, "rb1r0" },
|
||||
{ FEATURE_NONE, 0x09, "rb1r1" },
|
||||
{ FEATURE_NONE, 0x0a, "rb1r2" },
|
||||
{ FEATURE_NONE, 0x0b, "rb1r3" },
|
||||
{ FEATURE_NONE, 0x0c, "rb1r4" },
|
||||
{ FEATURE_NONE, 0x0d, "rb1r5" },
|
||||
{ FEATURE_NONE, 0x0e, "rb1r6" },
|
||||
{ FEATURE_NONE, 0x0f, "rb1r7" },
|
||||
{ FEATURE_NONE, 0x10, "rb2r0" },
|
||||
{ FEATURE_NONE, 0x11, "rb2r1" },
|
||||
{ FEATURE_NONE, 0x12, "rb2r2" },
|
||||
{ FEATURE_NONE, 0x13, "rb2r3" },
|
||||
{ FEATURE_NONE, 0x14, "rb2r4" },
|
||||
{ FEATURE_NONE, 0x15, "rb2r5" },
|
||||
{ FEATURE_NONE, 0x16, "rb2r6" },
|
||||
{ FEATURE_NONE, 0x17, "rb2r7" },
|
||||
{ FEATURE_NONE, 0x18, "rb3r0" },
|
||||
{ FEATURE_NONE, 0x19, "rb3r1" },
|
||||
{ FEATURE_NONE, 0x1a, "rb3r2" },
|
||||
{ FEATURE_NONE, 0x1b, "rb3r3" },
|
||||
{ FEATURE_NONE, 0x1c, "rb3r4" },
|
||||
{ FEATURE_NONE, 0x1d, "rb3r5" },
|
||||
{ FEATURE_NONE, 0x1e, "rb3r6" },
|
||||
{ FEATURE_NONE, 0x1f, "rb3r7" },
|
||||
|
||||
{ FEATURE_NONE, 0x80, "p0" },
|
||||
{ FEATURE_NONE, 0x81, "sp" },
|
||||
{ FEATURE_NONE, 0x82, "dpl" },
|
||||
{ FEATURE_NONE, 0x83, "dph" },
|
||||
{ FEATURE_NONE, 0x87, "pcon" },
|
||||
{ FEATURE_NONE, 0x88, "tcon" },
|
||||
{ FEATURE_NONE, 0x89, "tmod" },
|
||||
{ FEATURE_NONE, 0x8a, "tl0" },
|
||||
{ FEATURE_NONE, 0x8b, "tl1" },
|
||||
{ FEATURE_NONE, 0x8c, "th0" },
|
||||
{ FEATURE_NONE, 0x8d, "th1" },
|
||||
{ FEATURE_NONE, 0x90, "p1" },
|
||||
{ FEATURE_NONE, 0x98, "scon" },
|
||||
{ FEATURE_NONE, 0x99, "sbuf" },
|
||||
{ FEATURE_NONE, 0xa0, "p2" },
|
||||
{ FEATURE_NONE, 0xa8, "ie" },
|
||||
{ FEATURE_NONE, 0xb0, "p3" },
|
||||
{ FEATURE_NONE, 0xb8, "ip" },
|
||||
{ FEATURE_NONE, 0xd0, "psw" },
|
||||
{ FEATURE_NONE, 0xe0, "acc" },
|
||||
{ FEATURE_NONE, 0xf0, "b" },
|
||||
|
||||
{ FEATURE_I8052, 0xc8, "t2con" },
|
||||
{ FEATURE_I8052, 0xca, "rcap2l" },
|
||||
{ FEATURE_I8052, 0xcb, "rcap2h" },
|
||||
{ FEATURE_I8052, 0xcc, "tl2" },
|
||||
{ FEATURE_I8052, 0xcd, "th2" },
|
||||
|
||||
{ FEATURE_I80C52, 0xb7, "iph" },
|
||||
{ FEATURE_I80C52, 0xa9, "saddr" },
|
||||
{ FEATURE_I80C52, 0xb9, "saden" },
|
||||
|
||||
{ FEATURE_DS5002FP, 0x8e, "pwcm" },
|
||||
{ FEATURE_DS5002FP, 0x8f, "pwmp" },
|
||||
{ FEATURE_DS5002FP, 0xc1, "crcr" },
|
||||
{ FEATURE_DS5002FP, 0xc2, "crcl" },
|
||||
{ FEATURE_DS5002FP, 0xc3, "crch" },
|
||||
{ FEATURE_DS5002FP, 0xc6, "mcon" },
|
||||
{ FEATURE_DS5002FP, 0xc7, "ta" },
|
||||
{ FEATURE_DS5002FP, 0xcf, "rnr" },
|
||||
{ FEATURE_DS5002FP, 0xd8, "rpctl" },
|
||||
{ FEATURE_DS5002FP, 0xd9, "rps" },
|
||||
|
||||
{ FEATURE_I83C751, 0x98, "i2con" },
|
||||
{ FEATURE_I83C751, 0x99, "i2dat" },
|
||||
{ FEATURE_I83C751, 0xd8, "i2cfg" },
|
||||
{ FEATURE_I83C751, 0xf8, "i2sta" }, /* read only */
|
||||
|
||||
/* bit addresses */
|
||||
|
||||
{ FEATURE_NONE, 0x188, "it0" },
|
||||
{ FEATURE_NONE, 0x189, "ie0" },
|
||||
{ FEATURE_NONE, 0x18a, "it1" },
|
||||
{ FEATURE_NONE, 0x18b, "ie1" },
|
||||
{ FEATURE_NONE, 0x18c, "tr0" },
|
||||
{ FEATURE_NONE, 0x18d, "tf0" },
|
||||
{ FEATURE_NONE, 0x18e, "tr1" },
|
||||
{ FEATURE_NONE, 0x18f, "tf1" },
|
||||
|
||||
{ FEATURE_NONE, 0x198, "ri" },
|
||||
{ FEATURE_NONE, 0x199, "ti" },
|
||||
{ FEATURE_NONE, 0x19a, "rb8" },
|
||||
{ FEATURE_NONE, 0x19b, "tb8" },
|
||||
{ FEATURE_NONE, 0x19c, "ren" },
|
||||
{ FEATURE_NONE, 0x19d, "sm2" },
|
||||
{ FEATURE_NONE, 0x19e, "sm1" },
|
||||
{ FEATURE_NONE, 0x19f, "sm0" },
|
||||
|
||||
{ FEATURE_I83C751, 0x198, "xstp" }, /* read: no function */
|
||||
{ FEATURE_I83C751, 0x199, "xstr" }, /* read: MASTER */
|
||||
{ FEATURE_I83C751, 0x19a, "cstp" }, /* read: STP */
|
||||
{ FEATURE_I83C751, 0x19b, "cstr" }, /* read: STR */
|
||||
{ FEATURE_I83C751, 0x19c, "carl" }, /* read: ARL */
|
||||
{ FEATURE_I83C751, 0x19d, "cdr" }, /* read: DRDY */
|
||||
{ FEATURE_I83C751, 0x19e, "idle" }, /* read: ATN */
|
||||
{ FEATURE_I83C751, 0x19f, "cxa" }, /* read: RDAT */
|
||||
|
||||
{ FEATURE_NONE, 0x1a8, "ex0" },
|
||||
{ FEATURE_NONE, 0x1a9, "et0" },
|
||||
{ FEATURE_NONE, 0x1aa, "ex1" },
|
||||
{ FEATURE_NONE, 0x1ab, "et1" },
|
||||
{ FEATURE_NONE, 0x1ac, "es" },
|
||||
{ FEATURE_NONE, 0x1ad, "ie.5" },
|
||||
{ FEATURE_NONE, 0x1ae, "ie.6" },
|
||||
{ FEATURE_NONE, 0x1af, "ea" },
|
||||
|
||||
{ FEATURE_I83C751, 0x1ac, "ei2" },
|
||||
{ FEATURE_I8052, 0x1ad, "et2" },
|
||||
|
||||
/* FIXME: port 3 - depends on external circuits and not really
|
||||
* implemented in the core. TBD */
|
||||
{ FEATURE_NONE, 0x1b0, "rxd" },
|
||||
{ FEATURE_NONE, 0x1b1, "txd" },
|
||||
{ FEATURE_NONE, 0x1b2, "int0" },
|
||||
{ FEATURE_NONE, 0x1b3, "int1" },
|
||||
{ FEATURE_NONE, 0x1b4, "t0" },
|
||||
{ FEATURE_NONE, 0x1b5, "t1" },
|
||||
{ FEATURE_NONE, 0x1b6, "wr" },
|
||||
{ FEATURE_NONE, 0x1b7, "rd" },
|
||||
|
||||
{ FEATURE_NONE, 0x1b8, "px0" },
|
||||
{ FEATURE_NONE, 0x1b9, "pt0" },
|
||||
{ FEATURE_NONE, 0x1ba, "px1" },
|
||||
{ FEATURE_NONE, 0x1bb, "pt1" },
|
||||
{ FEATURE_NONE, 0x1bc, "ps" },
|
||||
{ FEATURE_NONE, 0x1bd, "ip.5" },
|
||||
{ FEATURE_NONE, 0x1be, "ip.6" },
|
||||
{ FEATURE_NONE, 0x1bf, "ip.7" },
|
||||
|
||||
{ FEATURE_I8052, 0x1bd, "pt2" },
|
||||
{ FEATURE_I83C751, 0x1bc, "pi2" },
|
||||
|
||||
{ FEATURE_I8052, 0x1c8, "cprl2" },
|
||||
{ FEATURE_I8052, 0x1c9, "ct2" },
|
||||
{ FEATURE_I8052, 0x1ca, "tr2" },
|
||||
{ FEATURE_I8052, 0x1cb, "exen2" },
|
||||
{ FEATURE_I8052, 0x1cc, "tclk" },
|
||||
{ FEATURE_I8052, 0x1cd, "rclk" },
|
||||
{ FEATURE_I8052, 0x1ce, "exf2" },
|
||||
{ FEATURE_I8052, 0x1cf, "tf2" },
|
||||
|
||||
{ FEATURE_NONE, 0x1d0, "p" },
|
||||
{ FEATURE_NONE, 0x1d1, "psw.1" },
|
||||
{ FEATURE_NONE, 0x1d2, "ov" },
|
||||
{ FEATURE_NONE, 0x1d3, "rs0" },
|
||||
{ FEATURE_NONE, 0x1d4, "rs1" },
|
||||
{ FEATURE_NONE, 0x1d5, "f0" },
|
||||
{ FEATURE_NONE, 0x1d6, "ac" },
|
||||
{ FEATURE_NONE, 0x1d7, "cy" },
|
||||
|
||||
{ FEATURE_DS5002FP, 0x1d8, "rg0" },
|
||||
{ FEATURE_DS5002FP, 0x1d9, "rpc" },
|
||||
{ FEATURE_DS5002FP, 0x1da, "dma" },
|
||||
{ FEATURE_DS5002FP, 0x1db, "ibi" },
|
||||
{ FEATURE_DS5002FP, 0x1dc, "ae" },
|
||||
{ FEATURE_DS5002FP, 0x1dd, "exbs" },
|
||||
{ FEATURE_DS5002FP, 0x1de, "d8.6" },
|
||||
{ FEATURE_DS5002FP, 0x1df, "rnr" },
|
||||
|
||||
{ FEATURE_I83C751, 0x1d8, "ct0" },
|
||||
{ FEATURE_I83C751, 0x1d9, "ct1" },
|
||||
{ FEATURE_I83C751, 0x1da, "i2cfg.2" },
|
||||
{ FEATURE_I83C751, 0x1db, "i2cfg.3" },
|
||||
{ FEATURE_I83C751, 0x1dc, "tirun" },
|
||||
{ FEATURE_I83C751, 0x1dd, "clrti" },
|
||||
{ FEATURE_I83C751, 0x1de, "masterq" },
|
||||
{ FEATURE_I83C751, 0x1df, "slaven" },
|
||||
|
||||
{ FEATURE_I83C751, 0x1f8, "xstp" },
|
||||
{ FEATURE_I83C751, 0x1f9, "xstr" },
|
||||
{ FEATURE_I83C751, 0x1fa, "makstp" },
|
||||
{ FEATURE_I83C751, 0x1fb, "makstr" },
|
||||
{ FEATURE_I83C751, 0x1fc, "xactv" },
|
||||
{ FEATURE_I83C751, 0x1fd, "xdata" },
|
||||
{ FEATURE_I83C751, 0x1fe, "idle" },
|
||||
{ FEATURE_I83C751, 0x1ff, "i2sta.7" },
|
||||
|
||||
/* unkown
|
||||
* "ibf", "obf", "idsm", "obfc", e8 - eb
|
||||
* "ma0", "ma1", "mb0", "mb1", ec - ef
|
||||
*/
|
||||
|
||||
{ -1 }
|
||||
};
|
||||
|
||||
//SFR Addressable bits
|
||||
static const char sfrbits[128][8] = {
|
||||
"p0.0", "p0.1", "p0.2", "p0.3", /* 80 - 83 */
|
||||
"p0.4", "p0.5", "p0.6", "p0.7", /* 84 - 87 */
|
||||
"it0", "ie0", "it1", "ie1", /* 88 - 8b */
|
||||
"tr0", "tf0", "tr1", "tf1", /* 8c - 8f */
|
||||
"p1.0", "p1.1", "p1.2", "p1.3", /* 90 - 93 */
|
||||
"p1.4", "p1.5", "p1.6", "p1.7", /* 94 - 97 */
|
||||
"ri", "ti", "rb8", "tb8", /* 98 - 9b */
|
||||
"ren", "sm2", "sm1", "sm0", /* 9c - 9f */
|
||||
"p2.0", "p2.1", "p2.2", "p2.3", /* a0 - a3 */
|
||||
"p2.4", "p2.5", "p2.6", "p2.7", /* a4 - a7 */
|
||||
"ex0", "et0", "ex1", "et1", /* a8 - ab */
|
||||
"es", "ie.5", "ie.6", "ea", /* ac - af */
|
||||
"rxd", "txd", "int0", "int1", /* b0 - b3 */
|
||||
"t0", "t1", "wr", "rd", /* b4 - b7 */
|
||||
"px0", "pt0", "px1", "pt1", /* b8 - bb */
|
||||
"ps", "ip.5", "ip.6", "ip.7", /* bc - bf */
|
||||
"0c0h.0", "0c0h.1", "0c0h.2", "0c0h.3", /* c0 - c3 */
|
||||
"0c0h.4", "0c0h.5", "0c0h.6", "0c0h.7", /* c4 - c7 */
|
||||
"cprl2", "ct2", "tr2", "exen2", /* c8 - cb */
|
||||
"tclk", "rclk", "exf2", "tf2", /* cc - cf */
|
||||
"p", "psw.1", "ov", "rs0", /* d0 - d3 */
|
||||
"rs1", "f0", "ac", "cy", /* d4 - d7 */
|
||||
"ct0", "ct1", "i2cfg.2","i2cfg.3",/* d8 - db */
|
||||
"tirun", "clrti", "mastrq", "slaven", /* dc - df */
|
||||
"acc.0", "acc.1", "acc.2", "acc.3", /* e0 - e3 */
|
||||
"acc.4", "acc.5", "acc.6", "acc.7", /* e4 - e7 */
|
||||
"ibf", "obf", "idsm", "obfc", /* e8 - eb */
|
||||
"ma0", "ma1", "mb0", "mb1", /* ec - ef */
|
||||
"b.0", "b.1", "b.2", "b.3", /* f0 - f3 */
|
||||
"b.4", "b.5", "b.6", "b.7", /* f4 - f7 */
|
||||
"xstp", "xstr", "makstp", "makstr", /* f8 - fb */
|
||||
"xactv", "xdata", "idle", "i2sta.7" /* fc - ff */
|
||||
} ;
|
||||
static void init_mem_names(int feature_set, const char **mem_names)
|
||||
{
|
||||
int i;
|
||||
int feature;
|
||||
|
||||
/* Set defaults / i8051 */
|
||||
for (i = 0; feature = mem_name_feature[i].feature, feature >= 0; i++)
|
||||
{
|
||||
if ( feature == FEATURE_NONE )
|
||||
mem_names[mem_name_feature[i].addr] = mem_name_feature[i].name;
|
||||
}
|
||||
|
||||
//Names for bit addressable memory
|
||||
static const char membits[128][6] = {
|
||||
"20h.0", "20h.1", "20h.2", "20h.3",
|
||||
"20h.4", "20h.5", "20h.6", "20h.7",
|
||||
"21h.0", "21h.1", "21h.2", "21h.3",
|
||||
"21h.4", "21h.5", "21h.6", "21h.7",
|
||||
"22h.0", "22h.1", "22h.2", "22h.3",
|
||||
"22h.4", "22h.5", "22h.6", "22h.7",
|
||||
"23h.0", "23h.1", "23h.2", "23h.3",
|
||||
"23h.4", "23h.5", "23h.6", "23h.7",
|
||||
"24h.0", "24h.1", "24h.2", "24h.3",
|
||||
"24h.4", "24h.5", "24h.6", "24h.7",
|
||||
"25h.0", "25h.1", "25h.2", "25h.3",
|
||||
"25h.4", "25h.5", "25h.6", "25h.7",
|
||||
"26h.0", "26h.1", "26h.2", "26h.3",
|
||||
"26h.4", "26h.5", "26h.6", "26h.7",
|
||||
"27h.0", "27h.1", "27h.2", "27h.3",
|
||||
"27h.4", "27h.5", "27h.6", "27h.7",
|
||||
"28h.0", "28h.1", "28h.2", "28h.3",
|
||||
"28h.4", "28h.5", "28h.6", "28h.7",
|
||||
"29h.0", "29h.1", "29h.2", "29h.3",
|
||||
"29h.4", "29h.5", "29h.6", "29h.7",
|
||||
"2ah.0", "2ah.1", "2ah.2", "2ah.3",
|
||||
"2ah.4", "2ah.5", "2ah.6", "2ah.7",
|
||||
"2bh.0", "2bh.1", "2bh.2", "2bh.3",
|
||||
"2bh.4", "2bh.5", "2bh.6", "2bh.7",
|
||||
"2ch.0", "2ch.1", "2ch.2", "2ch.3",
|
||||
"2ch.4", "2ch.5", "2ch.6", "2ch.7",
|
||||
"2dh.0", "2dh.1", "2dh.2", "2dh.3",
|
||||
"2dh.4", "2dh.5", "2dh.6", "2dh.7",
|
||||
"2eh.0", "2eh.1", "2eh.2", "2eh.3",
|
||||
"2eh.4", "2eh.5", "2eh.6", "2eh.7",
|
||||
"2fh.0", "2fh.1", "2fh.2", "2fh.3",
|
||||
"2fh.4", "2fh.5", "2fh.6", "2fh.7"
|
||||
};
|
||||
/* Set specific memory names */
|
||||
for (i = 0; feature = mem_name_feature[i].feature, feature >= 0; i++)
|
||||
{
|
||||
if (feature & feature_set)
|
||||
mem_names[mem_name_feature[i].addr] = mem_name_feature[i].name;
|
||||
}
|
||||
|
||||
//Regiser Bank memory names
|
||||
static const char regbank[][6] = {
|
||||
"rb0r0", "rb0r1", "rb0r2", "rb0r3",
|
||||
"rb0r4", "rb0r5", "rb0r6", "rb0r7",
|
||||
"rb1r0", "rb1r1", "rb1r2", "rb1r3",
|
||||
"rb1r4", "rb1r5", "rb1r6", "rb1r7",
|
||||
"rb2r0", "rb2r1", "rb2r2", "rb2r3",
|
||||
"rb2r4", "rb2r5", "rb2r6", "rb2r7",
|
||||
"rb3r0", "rb3r1", "rb3r2", "rb3r3",
|
||||
"rb3r4", "rb3r5", "rb3r6", "rb3r7"
|
||||
};
|
||||
}
|
||||
|
||||
static const char *get_data_address( UINT8 arg )
|
||||
static const char *get_data_address( const char **mem_names, UINT8 arg )
|
||||
{
|
||||
char *buffer = cpuintrf_temp_str();
|
||||
|
||||
if(arg < 0x80)
|
||||
{
|
||||
//Ram locations 0-0x1F are considered register access in 3 banks
|
||||
if(arg < 0x1f)
|
||||
sprintf(buffer,"%s",regbank[arg]);
|
||||
else
|
||||
sprintf(buffer,"$%02X",arg);
|
||||
}
|
||||
if (mem_names[arg] == NULL)
|
||||
sprintf(buffer,"$%02X",arg);
|
||||
else
|
||||
sprintf(buffer,"%s",sfr[arg-0x80]);
|
||||
sprintf(buffer,"%s", mem_names[arg]);
|
||||
return buffer;
|
||||
}
|
||||
|
||||
static const char *get_bit_address( UINT8 arg )
|
||||
static const char *get_bit_address( const char **mem_names, UINT8 arg )
|
||||
{
|
||||
char *buffer = cpuintrf_temp_str();
|
||||
|
||||
@ -187,12 +299,22 @@ static const char *get_bit_address( UINT8 arg )
|
||||
{
|
||||
//Bit address 0-7F can be referred to as 20.0, 20.1, to 20.7 for address 0, and 2f.0,2f.1 to 2f.7 for address 7f
|
||||
if(arg < 0x7f)
|
||||
sprintf(buffer,"%s",membits[arg]);
|
||||
sprintf(buffer,"$%02X.%d",(arg >> 3) | 0x20, arg & 0x07);
|
||||
else
|
||||
sprintf(buffer,"$%02X",arg);
|
||||
}
|
||||
else
|
||||
sprintf(buffer,"%s",sfrbits[arg-0x80]);
|
||||
{
|
||||
if (mem_names[arg | 0x100] == NULL)
|
||||
{
|
||||
if (mem_names[arg & 0xf8] == NULL)
|
||||
sprintf(buffer,"$%02X.%d", arg & 0xf8, arg & 0x07);
|
||||
else
|
||||
sprintf(buffer,"%s.%d", mem_names[arg & 0xf8], arg & 0x07);
|
||||
}
|
||||
else
|
||||
sprintf(buffer,"%s", mem_names[arg | 0x100]);
|
||||
}
|
||||
return buffer;
|
||||
}
|
||||
|
||||
@ -216,8 +338,7 @@ static const char *get_bit_address( UINT8 arg )
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opram)
|
||||
static offs_t mcs51_dasm( const char **mem_names, char *dst, offs_t pc, const UINT8 *oprom, const UINT8 *opram)
|
||||
{
|
||||
UINT32 flags = 0;
|
||||
unsigned PC = pc;
|
||||
@ -267,7 +388,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//INC data addr
|
||||
case 0x05: /* 1: 0000 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "inc %s", sym);
|
||||
break;
|
||||
|
||||
@ -291,7 +412,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//JBC bit addr, code addr
|
||||
case 0x10: /* 1: 0001 0000 */
|
||||
sym = get_bit_address(opram[PC++ - pc]);
|
||||
sym = get_bit_address(mem_names, opram[PC++ - pc]);
|
||||
rel = opram[PC++ - pc];
|
||||
sprintf(dst, "jbc %s,$%04X", sym, PC + rel);
|
||||
break;
|
||||
@ -330,7 +451,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//DEC data addr
|
||||
case 0x15: /* 1: 0001 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "dec %s", sym);
|
||||
break;
|
||||
|
||||
@ -355,7 +476,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//JB bit addr, code addr
|
||||
case 0x20: /* 1: 0010 0000 */
|
||||
sym = get_bit_address(opram[PC++ - pc]);
|
||||
sym = get_bit_address(mem_names, opram[PC++ - pc]);
|
||||
rel = opram[PC++ - pc];
|
||||
sprintf(dst, "jb %s,$%04X", sym, (PC + rel));
|
||||
break;
|
||||
@ -378,7 +499,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//ADD A, data addr
|
||||
case 0x25: /* 1: 0010 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "add a,%s", sym);
|
||||
break;
|
||||
|
||||
@ -403,7 +524,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//JNB bit addr, code addr
|
||||
case 0x30: /* 1: 0011 0000 */
|
||||
sym = get_bit_address(opram[PC++ - pc]);
|
||||
sym = get_bit_address(mem_names, opram[PC++ - pc]);
|
||||
rel = opram[PC++ - pc];
|
||||
sprintf(dst, "jnb %s,$%04X", sym, (PC + rel));
|
||||
break;
|
||||
@ -426,7 +547,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//ADDC A, data addr
|
||||
case 0x35: /* 1: 0011 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "addc a,%s", sym);
|
||||
break;
|
||||
|
||||
@ -456,13 +577,13 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//ORL data addr, A
|
||||
case 0x42: /* 1: 0100 0010 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "orl %s,a", sym);
|
||||
break;
|
||||
|
||||
//ORL data addr, #data
|
||||
case 0x43: /* 1: 0100 0011 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "orl %s,#$%02X", sym, opram[PC++ - pc]);
|
||||
break;
|
||||
|
||||
@ -474,7 +595,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//ORL A, data addr
|
||||
case 0x45: /* 1: 0100 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "orl a,%s", sym);
|
||||
break;
|
||||
|
||||
@ -505,14 +626,14 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
//Unable to test
|
||||
//ANL data addr, A
|
||||
case 0x52: /* 1: 0101 0010 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "anl %s,a", sym);
|
||||
break;
|
||||
|
||||
//Unable to test
|
||||
//ANL data addr, #data
|
||||
case 0x53: /* 1: 0101 0011 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "anl %s,#$%02X", sym, opram[PC++ - pc]);
|
||||
break;
|
||||
|
||||
@ -523,7 +644,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//ANL A, data addr
|
||||
case 0x55: /* 1: 0101 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "anl a,%s", sym);
|
||||
break;
|
||||
|
||||
@ -555,13 +676,13 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
//Unable to test
|
||||
//XRL data addr, A
|
||||
case 0x62: /* 1: 0110 0010 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "xrl %s,a", sym);
|
||||
break;
|
||||
|
||||
//XRL data addr, #data
|
||||
case 0x63: /* 1: 0110 0011 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "xrl %s,#$%02X", sym, opram[PC++ - pc]);
|
||||
break;
|
||||
|
||||
@ -572,7 +693,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//XRL A, data addr
|
||||
case 0x65: /* 1: 0110 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "xrl a,%s", sym);
|
||||
break;
|
||||
|
||||
@ -604,7 +725,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
//Unable to test
|
||||
//ORL C, bit addr
|
||||
case 0x72: /* 1: 0111 0010 */
|
||||
sym = get_bit_address(opram[PC++ - pc]);
|
||||
sym = get_bit_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "orl c,%s", sym);
|
||||
break;
|
||||
|
||||
@ -621,7 +742,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//MOV data addr, #data
|
||||
case 0x75: /* 1: 0111 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "mov %s,#$%02X", sym, opram[PC++ - pc]);
|
||||
break;
|
||||
|
||||
@ -652,7 +773,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//ANL C, bit addr
|
||||
case 0x82: /* 1: 1000 0010 */
|
||||
sym = get_bit_address(opram[PC++ - pc]);
|
||||
sym = get_bit_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "anl c,%s", sym);
|
||||
break;
|
||||
|
||||
@ -668,8 +789,8 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//MOV data addr, data addr (Note: 1st address is src, 2nd is dst, but the mov command works as mov dst,src)
|
||||
case 0x85: /* 1: 1000 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym2 = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sym2 = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "mov %s,%s", sym2, sym);
|
||||
break;
|
||||
|
||||
@ -677,7 +798,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
//MOV data addr, @R0/@R1/* 1: 1000 011i */
|
||||
case 0x86:
|
||||
case 0x87:
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "mov %s,@r%d", sym, op&1);
|
||||
break;
|
||||
|
||||
@ -690,7 +811,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
case 0x8d:
|
||||
case 0x8e:
|
||||
case 0x8f:
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "mov %s,r%d", sym, op&7);
|
||||
break;
|
||||
|
||||
@ -703,7 +824,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//MOV bit addr, C
|
||||
case 0x92: /* 1: 1001 0010 */
|
||||
sym = get_bit_address(opram[PC++ - pc]);
|
||||
sym = get_bit_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "mov %s,c", sym);
|
||||
break;
|
||||
|
||||
@ -719,7 +840,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//SUBB A, data addr
|
||||
case 0x95: /* 1: 1001 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "subb a,%s", sym);
|
||||
break;
|
||||
|
||||
@ -745,13 +866,13 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
//Unable to test
|
||||
//ORL C, /bit addr
|
||||
case 0xa0: /* 1: 1010 0000 */
|
||||
sym = get_bit_address(opram[PC++ - pc]);
|
||||
sym = get_bit_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "orl c,/%s", sym);
|
||||
break;
|
||||
|
||||
//MOV C, bit addr
|
||||
case 0xa2: /* 1: 1010 0010 */
|
||||
sym = get_bit_address(opram[PC++ - pc]);
|
||||
sym = get_bit_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "mov c,%s", sym);
|
||||
break;
|
||||
|
||||
@ -774,7 +895,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
//MOV @R0/@R1, data addr /* 1: 1010 011i */
|
||||
case 0xa6:
|
||||
case 0xa7:
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "mov @r%d,%s", op&1, sym);
|
||||
break;
|
||||
|
||||
@ -787,19 +908,19 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
case 0xad:
|
||||
case 0xae:
|
||||
case 0xaf:
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "mov r%d,%s", op&7, sym);
|
||||
break;
|
||||
|
||||
//ANL C,/bit addr
|
||||
case 0xb0: /* 1: 1011 0000 */
|
||||
sym = get_bit_address(opram[PC++ - pc]);
|
||||
sym = get_bit_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "anl c,/%s", sym);
|
||||
break;
|
||||
|
||||
//CPL bit addr
|
||||
case 0xb2: /* 1: 1011 0010 */
|
||||
sym = get_bit_address(opram[PC++ - pc]);
|
||||
sym = get_bit_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "cpl %s", sym);
|
||||
break;
|
||||
|
||||
@ -818,7 +939,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//CJNE A, data addr, code addr
|
||||
case 0xb5: /* 1: 1011 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
rel = opram[PC++ - pc];
|
||||
sprintf(dst, "cjne a,%s,$%04X", sym, PC + rel);
|
||||
break;
|
||||
@ -848,13 +969,13 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//PUSH data addr
|
||||
case 0xc0: /* 1: 1100 0000 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "push %s", sym);
|
||||
break;
|
||||
|
||||
//CLR bit addr
|
||||
case 0xc2: /* 1: 1100 0010 */
|
||||
sym = get_bit_address(opram[PC++ - pc]);
|
||||
sym = get_bit_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "clr %s", sym);
|
||||
break;
|
||||
|
||||
@ -870,7 +991,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//XCH A, data addr
|
||||
case 0xc5: /* 1: 1100 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "xch a,%s", sym);
|
||||
break;
|
||||
|
||||
@ -894,13 +1015,13 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//POP data addr
|
||||
case 0xd0: /* 1: 1101 0000 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "pop %s", sym);
|
||||
break;
|
||||
|
||||
//SETB bit addr
|
||||
case 0xd2: /* 1: 1101 0010 */
|
||||
sym = get_bit_address(opram[PC++ - pc]);
|
||||
sym = get_bit_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "setb %s", sym);
|
||||
break;
|
||||
|
||||
@ -917,7 +1038,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//DJNZ data addr, code addr
|
||||
case 0xd5: /* 1: 1101 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
rel = opram[PC++ - pc];
|
||||
sprintf(dst, "djnz %s,$%04X", sym, PC + rel);
|
||||
flags = DASMFLAG_STEP_OVER;
|
||||
@ -962,7 +1083,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//MOV A, data addr
|
||||
case 0xe5: /* 1: 1110 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "mov a,%s", sym);
|
||||
break;
|
||||
|
||||
@ -1004,7 +1125,7 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
|
||||
//MOV data addr, A
|
||||
case 0xf5: /* 1: 1111 0101 */
|
||||
sym = get_data_address(opram[PC++ - pc]);
|
||||
sym = get_data_address(mem_names, opram[PC++ - pc]);
|
||||
sprintf(dst, "mov %s,a", sym);
|
||||
break;
|
||||
|
||||
@ -1030,4 +1151,70 @@ unsigned i8051_dasm(char *dst, unsigned pc, const UINT8 *oprom, const UINT8 *opr
|
||||
sprintf(dst, "illegal");
|
||||
}
|
||||
return (PC - pc) | flags | DASMFLAG_SUPPORTED;
|
||||
|
||||
}
|
||||
|
||||
offs_t i8051_dasm(char *dst, offs_t pc, const UINT8 *oprom, const UINT8 *opram)
|
||||
{
|
||||
static const char *mem_names[0x200];
|
||||
static int mem_names_initialized = 0;
|
||||
|
||||
if (!mem_names_initialized)
|
||||
{
|
||||
init_mem_names( FEATURE_NONE, mem_names);
|
||||
mem_names_initialized = 1;
|
||||
}
|
||||
return mcs51_dasm(mem_names, dst, pc, oprom, opram);
|
||||
}
|
||||
|
||||
offs_t i8052_dasm(char *dst, offs_t pc, const UINT8 *oprom, const UINT8 *opram)
|
||||
{
|
||||
static const char *mem_names[0x200];
|
||||
static int mem_names_initialized = 0;
|
||||
|
||||
if (!mem_names_initialized)
|
||||
{
|
||||
init_mem_names( FEATURE_I8052, mem_names);
|
||||
mem_names_initialized = 1;
|
||||
}
|
||||
return mcs51_dasm(mem_names, dst, pc, oprom, opram);
|
||||
}
|
||||
|
||||
offs_t i80c51_dasm(char *dst, offs_t pc, const UINT8 *oprom, const UINT8 *opram)
|
||||
{
|
||||
static const char *mem_names[0x200];
|
||||
static int mem_names_initialized = 0;
|
||||
|
||||
if (!mem_names_initialized)
|
||||
{
|
||||
init_mem_names( FEATURE_CMOS, mem_names);
|
||||
mem_names_initialized = 1;
|
||||
}
|
||||
return mcs51_dasm(mem_names, dst, pc, oprom, opram);
|
||||
}
|
||||
|
||||
offs_t i80c52_dasm(char *dst, offs_t pc, const UINT8 *oprom, const UINT8 *opram)
|
||||
{
|
||||
static const char *mem_names[0x200];
|
||||
static int mem_names_initialized = 0;
|
||||
|
||||
if (!mem_names_initialized)
|
||||
{
|
||||
init_mem_names( FEATURE_I8052 | FEATURE_CMOS | FEATURE_I80C52, mem_names);
|
||||
mem_names_initialized = 1;
|
||||
}
|
||||
return mcs51_dasm(mem_names, dst, pc, oprom, opram);
|
||||
}
|
||||
|
||||
offs_t ds5002fp_dasm(char *dst, offs_t pc, const UINT8 *oprom, const UINT8 *opram)
|
||||
{
|
||||
static const char *mem_names[0x200];
|
||||
static int mem_names_initialized = 0;
|
||||
|
||||
if (!mem_names_initialized)
|
||||
{
|
||||
init_mem_names( FEATURE_DS5002FP | FEATURE_CMOS, mem_names);
|
||||
mem_names_initialized = 1;
|
||||
}
|
||||
return mcs51_dasm(mem_names, dst, pc, oprom, opram);
|
||||
}
|
||||
|
||||
@ -96,7 +96,7 @@ produces a high clock frequency, slow movements a low freq.
|
||||
|
||||
#include "driver.h"
|
||||
#include "cpu/m68000/m68000.h"
|
||||
#include "cpu/ds5002fp/ds5002fp.h"
|
||||
#include "cpu/mcs51/mcs51.h"
|
||||
#include "sound/okim6295.h"
|
||||
#include "includes/wrally.h"
|
||||
|
||||
@ -127,21 +127,21 @@ static READ8_HANDLER( dallas_share_r )
|
||||
{
|
||||
UINT8 *shareram = (UINT8 *)wrally_shareram;
|
||||
|
||||
return shareram[BYTE_XOR_LE(offset)];
|
||||
return shareram[BYTE_XOR_LE(offset) ^ 1];
|
||||
}
|
||||
|
||||
static WRITE8_HANDLER( dallas_share_w )
|
||||
{
|
||||
UINT8 *shareram = (UINT8 *)wrally_shareram;
|
||||
|
||||
shareram[BYTE_XOR_LE(offset)] = data;
|
||||
shareram[BYTE_XOR_LE(offset) ^ 1] = data;
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( dallas_rom, ADDRESS_SPACE_PROGRAM, 8 )
|
||||
AM_RANGE(0x0000, 0x7fff) AM_ROM /* Code in NVRAM */
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( dallas_ram, ADDRESS_SPACE_DATA, 8 )
|
||||
static ADDRESS_MAP_START( dallas_ram, ADDRESS_SPACE_IO, 8 )
|
||||
AM_RANGE(0x0000, 0xffff) AM_READWRITE(dallas_share_r, dallas_share_w) AM_MASK(0x3fff) /* Shared RAM with the main CPU */
|
||||
ADDRESS_MAP_END
|
||||
|
||||
@ -254,10 +254,9 @@ static MACHINE_DRIVER_START( wrally )
|
||||
MDRV_CPU_ADD("mcu", DS5002FP, XTAL_24MHz/2) /* verified on pcb */
|
||||
MDRV_CPU_CONFIG(dallas_config)
|
||||
MDRV_CPU_PROGRAM_MAP(dallas_rom, 0)
|
||||
MDRV_CPU_DATA_MAP(dallas_ram, 0)
|
||||
MDRV_CPU_IO_MAP(dallas_ram, 0)
|
||||
|
||||
MDRV_INTERLEAVE(640) /* heavy sync */
|
||||
MDRV_MACHINE_RESET(wrally)
|
||||
|
||||
/* video hardware */
|
||||
MDRV_SCREEN_ADD("main", RASTER)
|
||||
@ -363,6 +362,6 @@ ROM_START( wrallyb ) /* Board Marked 930217, Atari License */
|
||||
ROM_END
|
||||
|
||||
|
||||
GAME( 1993, wrally, 0, wrally, wrally, wrally, ROT0, "Gaelco", "World Rally (set 1)", 0 ) /* Dallas DS5002FP power failure shows as: "Tension baja " */
|
||||
GAME( 1993, wrallya, wrally, wrally, wrally, wrally, ROT0, "Gaelco", "World Rally (set 2)", 0 ) /* Dallas DS5002FP power failure shows as: "Power Failure" */
|
||||
GAME( 1993, wrallyb, wrally, wrally, wrally, wrally, ROT0, "Gaelco (Atari license)", "World Rally (US, 930217)", 0 )
|
||||
GAME( 1993, wrally, 0, wrally, wrally, 0, ROT0, "Gaelco", "World Rally (set 1)", 0 ) /* Dallas DS5002FP power failure shows as: "Tension baja " */
|
||||
GAME( 1993, wrallya, wrally, wrally, wrally, 0, ROT0, "Gaelco", "World Rally (set 2)", 0 ) /* Dallas DS5002FP power failure shows as: "Power Failure" */
|
||||
GAME( 1993, wrallyb, wrally, wrally, wrally, 0, ROT0, "Gaelco (Atari license)", "World Rally (US, 930217)", 0 )
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
***************************************************************************/
|
||||
|
||||
#include "driver.h"
|
||||
#include "cpu/ds5002fp/ds5002fp.h"
|
||||
#include "cpu/mcs51/mcs51.h"
|
||||
#include "gaelcrpt.h"
|
||||
#include "includes/wrally.h"
|
||||
|
||||
@ -50,24 +50,3 @@ WRITE16_HANDLER( wrally_coin_lockout_w )
|
||||
coin_lockout_w( (offset >> 3) & 0x01, ~data & 0x01);
|
||||
}
|
||||
|
||||
/* Converts memory offsets to the format expected by the Dallas */
|
||||
static READ32_HANDLER( wrally_external_ram_iaddr )
|
||||
{
|
||||
return offset ^= 0x0001;
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
|
||||
World Rally init/reset machine
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
DRIVER_INIT( wrally )
|
||||
{
|
||||
}
|
||||
|
||||
MACHINE_RESET( wrally )
|
||||
{
|
||||
/* sets the function to convert addresses for shared memory with the dallas */
|
||||
ds5002fp_set_ebram_iaddr_callback(wrally_external_ram_iaddr);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user