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pci: Add save state support. (nw)
pci-ide: Allow for setting the top 12 decode address bits in legacy mode. (nw) pci-ide: Add save state support. (nw) pci9050: Add save state support. (nw) vrc4373: Add save state support. (nw) gt64xxx: Remove address map trampolines. (nw) gt64xxx: Add save state support. (nw) atlantis: Add save state support. (nw)
This commit is contained in:
Ted Green
parent
c61e1ba31a
commit
eef01e78d6
@ -24,6 +24,9 @@ DEVICE_ADDRESS_MAP_START(cpu_map, 32, gt64xxx_device)
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AM_RANGE(0x00000000, 0x00000cff) AM_READWRITE( cpu_if_r, cpu_if_w)
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ADDRESS_MAP_END
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DEVICE_ADDRESS_MAP_START(empty, 32, gt64xxx_device)
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ADDRESS_MAP_END
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gt64xxx_device::gt64xxx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: pci_host_device(mconfig, GT64XXX, "Galileo GT-64XXX System Controller", tag, owner, clock, "gt64xxx", __FILE__),
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m_be(0), m_autoconfig(0), m_irq_num(-1),
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@ -32,14 +35,15 @@ gt64xxx_device::gt64xxx_device(const machine_config &mconfig, const char *tag, d
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m_romRegion(*this, "rom"),
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m_updateRegion(*this, "update")
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{
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for (int csIndex = 0; csIndex < 4; csIndex++) {
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m_cs_devices[csIndex] = nullptr;
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}
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}
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void gt64xxx_device::set_cs_map(int id, address_map_constructor map, const char *name, device_t *device)
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void gt64xxx_device::set_map(int id, const address_map_delegate &map, device_t *device)
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{
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m_cs_map[id].enable = true;
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m_cs_map[id].name = name;
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m_cs_map[id].device = device;
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m_cs_map[id].map = map;
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m_cs_maps[id] = map;
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m_cs_devices[id] = device;
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}
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const address_space_config *gt64xxx_device::memory_space_config(address_spacenum spacenum) const
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@ -68,6 +72,10 @@ void gt64xxx_device::device_start()
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// Leave the timer disabled.
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m_dma_timer->adjust(attotime::never, 0, DMA_TIMER_PERIOD);
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// Reserve 8MB RAM
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m_ram[0].reserve(0x00800000 / 4);
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m_ram[0].resize(0x00800000 / 4);
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// ROM
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uint32_t romSize = m_romRegion->bytes();
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m_cpu_space->install_rom (0x1fc00000, 0x1fc00000 + romSize - 1, m_romRegion->base());
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@ -89,6 +97,31 @@ void gt64xxx_device::device_start()
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m_timer[1].timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(gt64xxx_device::timer_callback), this));
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m_timer[2].timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(gt64xxx_device::timer_callback), this));
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m_timer[3].timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(gt64xxx_device::timer_callback), this));
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// Save states
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save_item(NAME(m_pci_stall_state));
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save_item(NAME(m_retry_count));
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save_item(NAME(m_pci_cpu_stalled));
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save_item(NAME(m_cpu_stalled_offset));
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save_item(NAME(m_cpu_stalled_data));
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save_item(NAME(m_cpu_stalled_mem_mask));
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save_item(NAME(m_prev_addr));
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save_item(NAME(m_reg));
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for (int i = 0; i < ARRAY_LENGTH(m_timer); i++) {
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save_item(NAME(m_timer[i].active), i);
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save_item(NAME(m_timer[i].count), i);
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}
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save_item(NAME(m_dma_active));
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// m_ram[4]
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save_pointer(NAME(m_ram[0].data()), 0x00800000 / 4);
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save_item(NAME(m_last_dma));
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machine().save().register_postload(save_prepost_delegate(FUNC(gt64xxx_device::map_cpu_space), this));
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}
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void gt64xxx_device::postload()
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{
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map_cpu_space();
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remap_cb();
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}
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void gt64xxx_device::device_reset()
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@ -170,12 +203,14 @@ void gt64xxx_device::map_cpu_space()
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logerror("%s: map_cpu_space cpu_reg start: %08X end: %08X\n", tag(), winStart, winEnd);
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// RAS[0:3]
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m_ram[0].resize(0x00800000 / 4);
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for (int ramIndex = 0; ramIndex < 4; ++ramIndex)
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{
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winStart = (m_reg[GREG_RAS_1_0_LO + 0x10 / 4 * (ramIndex/2)] << 21) | (m_reg[GREG_RAS0_LO + 0x8 / 4 * ramIndex] << 20);
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winEnd = (m_reg[GREG_RAS_1_0_LO + 0x10 / 4 * (ramIndex / 2)] << 21) | (m_reg[GREG_RAS0_HI + 0x8 / 4 * ramIndex] << 20) | 0xfffff;
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m_ram[ramIndex].resize((winEnd + 1 - winStart) / 4);
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m_cpu_space->install_ram(winStart, winEnd, m_ram[ramIndex].data());
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//m_ram[ramIndex].resize((winEnd + 1 - winStart) / 4);
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if (m_ram[ramIndex].size()>0)
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m_cpu_space->install_ram(winStart, winEnd, m_ram[ramIndex].data());
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//m_cpu->add_fastram(winStart, m_ram[ramIndex].size() * sizeof(m_ram[ramIndex][0]), false, &m_ram[ramIndex][0]);
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//m_cpu->add_fastram(winStart, m_ram[ramIndex].size() * sizeof(uint32_t), false, m_ram[ramIndex].data());
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if (LOG_GALILEO)
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@ -183,27 +218,15 @@ void gt64xxx_device::map_cpu_space()
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}
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// CS[0:3]
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//m_cpu_space->install_device_delegate(0x16000000, 0x17ffffff, machine().root_device(), m_cs_map[3].map);
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typedef void (gt64xxx_device::*tramp_t)(::address_map &);
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static const tramp_t trampolines[4] = {
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>64xxx_device::map_trampoline<0>,
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>64xxx_device::map_trampoline<1>,
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>64xxx_device::map_trampoline<2>,
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>64xxx_device::map_trampoline<3>
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};
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for (int ramIndex = 0; ramIndex < 4; ++ramIndex)
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for (int csIndex = 0; csIndex < 4; ++csIndex)
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{
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if (m_cs_map[ramIndex].enable)
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{
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winStart = (m_reg[GREG_CS_2_0_LO + 0x10 / 4 * (ramIndex / 3)] << 21) | (m_reg[GREG_CS0_LO + 0x8 / 4 * ramIndex] << 20);
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winEnd = (m_reg[GREG_CS_2_0_LO + 0x10 / 4 * (ramIndex / 3)] << 21) | (m_reg[GREG_CS0_HI + 0x8 / 4 * ramIndex] << 20) | 0xfffff;
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install_cs_map(winStart, winEnd, trampolines[ramIndex], m_cs_map[ramIndex].name);
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if (LOG_GALILEO)
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logerror("%s: map_cpu_space cs[%i] start: %08X end: %08X\n", tag(), ramIndex, winStart, winEnd);
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}
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winStart = (m_reg[GREG_CS_2_0_LO + 0x10 / 4 * (csIndex / 3)] << 21) | (m_reg[GREG_CS0_LO + 0x8 / 4 * csIndex] << 20);
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winEnd = (m_reg[GREG_CS_2_0_LO + 0x10 / 4 * (csIndex / 3)] << 21) | (m_reg[GREG_CS0_HI + 0x8 / 4 * csIndex] << 20) | 0xfffff;
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m_cpu_space->install_device_delegate(winStart, winEnd, *m_cs_devices[csIndex], m_cs_maps[csIndex]);
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if (LOG_GALILEO)
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logerror("%s: map_cpu_space cs[%i] start: %08X end: %08X\n", tag(), csIndex, winStart, winEnd);
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}
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// PCI IO Window
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winStart = m_reg[GREG_PCI_IO_LO]<<21;
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winEnd = (m_reg[GREG_PCI_IO_LO]<<21) | (m_reg[GREG_PCI_IO_HI]<<21) | 0x1fffff;
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@ -388,7 +411,7 @@ WRITE32_MEMBER (gt64xxx_device::master_mem1_w)
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// PCI Master IO
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READ32_MEMBER (gt64xxx_device::master_io_r)
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{
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uint32_t result = this->space(AS_IO).read_dword((m_reg[GREG_PCI_IO_LO]<<21) | (offset*4), mem_mask);
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uint32_t result = this->space(AS_IO).read_dword((m_reg[GREG_PCI_IO_LO] << 21) | (offset * 4), mem_mask);
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if (LOG_PCI && m_prev_addr != offset) {
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m_prev_addr = offset;
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logerror("%06X:galileo pci io read from offset %08X = %08X & %08X\n", space.device().safe_pc(), (m_reg[GREG_PCI_IO_LO] << 21) | (offset * 4), result, mem_mask);
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@ -397,10 +420,10 @@ READ32_MEMBER (gt64xxx_device::master_io_r)
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}
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WRITE32_MEMBER (gt64xxx_device::master_io_w)
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{
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this->space(AS_IO).write_dword((m_reg[GREG_PCI_IO_LO]<<21) | (offset*4), data, mem_mask);
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this->space(AS_IO).write_dword((m_reg[GREG_PCI_IO_LO] << 21) | (offset * 4), data, mem_mask);
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if (LOG_PCI && m_prev_addr != offset) {
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m_prev_addr = offset;
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logerror("%06X:galileo pciio write to offset %08X = %08X & %08X\n", space.device().safe_pc(), (m_reg[GREG_PCI_IO_LO] << 21) | (offset * 4), data, mem_mask);
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logerror("%06X:galileo pci io write to offset %08X = %08X & %08X\n", space.device().safe_pc(), (m_reg[GREG_PCI_IO_LO] << 21) | (offset * 4), data, mem_mask);
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}
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}
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@ -14,7 +14,7 @@
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// Supports R4600/4650/4700/R5000 CPUs
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#define MCFG_GT64010_ADD(_tag, _cpu_tag, _clock, _irq_num) \
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MCFG_PCI_HOST_ADD(_tag, GT64XXX, 0x014611ab, 0x03, 0x00000000) \
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MCFG_PCI_HOST_ADD(_tag, GT64XXX, 0x11ab0146, 0x03, 0x00000000) \
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downcast<gt64xxx_device *>(device)->set_cpu_tag(_cpu_tag); \
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downcast<gt64xxx_device *>(device)->set_clock(_clock); \
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downcast<gt64xxx_device *>(device)->set_irq_num(_irq_num);
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@ -36,7 +36,7 @@
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downcast<gt64xxx_device *>(device)->set_irq_info(_irq_num);
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#define MCFG_GT64XXX_SET_CS(_cs_num, _map) \
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downcast<gt64xxx_device *>(device)->set_cs_map(_cs_num, ADDRESS_MAP_NAME(_map), #_map, owner);
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downcast<gt64xxx_device *>(device)->set_map(_cs_num, address_map_delegate(ADDRESS_MAP_NAME(_map), #_map), owner);
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/*************************************
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*
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@ -166,36 +166,26 @@
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#define GINT_TARABORT_SHIFT (19)
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#define GINT_RETRYCTR_SHIFT (20)
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/*************************************
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* Structures
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*************************************/
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struct galileo_timer
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{
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emu_timer * timer;
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uint32_t count;
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uint8_t active;
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};
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struct galileo_addr_map
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{
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uint32_t low_addr;
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uint32_t high_addr;
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address_space* space;
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galileo_addr_map() : low_addr(0xffffffff), high_addr(0x0) {}
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};
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struct galileo_device_map
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{
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bool enable;
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const char *name;
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device_t *device;
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address_map_constructor map;
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galileo_device_map() : enable(false), device(nullptr) {}
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};
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class gt64xxx_device : public pci_host_device {
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public:
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struct galileo_timer
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{
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emu_timer * timer;
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uint32_t count;
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uint8_t active;
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};
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struct galileo_addr_map
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{
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uint32_t low_addr;
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uint32_t high_addr;
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address_space* space;
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galileo_addr_map() : low_addr(0xffffffff), high_addr(0x0) {}
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};
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gt64xxx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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virtual void reset_all_mappings() override;
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@ -243,8 +233,8 @@ public:
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// Enums
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enum proc_addr_bank {ADDR_RAS1_0, ADDR_RAS3_2, ADDR_CS2_0, ADDR_CS3_BCS, ADDR_PCI_IO, ADDR_PCI_MEM0, ADDR_PCI_MEM1, ADDR_NUM};
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void set_cs_map(int id, address_map_constructor map, const char *name, device_t *device);
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void set_map(int id, const address_map_delegate &map, device_t *device);
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void postload(void);
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protected:
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address_space *m_cpu_space;
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virtual const address_space_config *memory_space_config(address_spacenum spacenum) const override;
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@ -272,6 +262,7 @@ private:
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optional_memory_region m_updateRegion;
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DECLARE_ADDRESS_MAP(cpu_map, 32);
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DECLARE_ADDRESS_MAP(empty, 32);
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void map_cpu_space();
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@ -290,16 +281,8 @@ private:
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std::vector<uint32_t> m_ram[4];
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// Chip Select
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galileo_device_map m_cs_map[4];
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template<int id> void map_trampoline(::address_map &map) {
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m_cs_map[id].map(map);
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}
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template <typename T> void install_cs_map(offs_t addrstart, offs_t addrend, void (T::*map)(::address_map &map), const char *name) {
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//address_map_delegate delegate(map, name, static_cast<T *>(this));
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address_map_delegate delegate(map, name, static_cast<T *>(this));
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m_cpu_space->install_device_delegate(addrstart, addrend, *this, delegate);
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}
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device_t *m_cs_devices[4];
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address_map_delegate m_cs_maps[4];
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void update_irqs();
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@ -10,7 +10,8 @@ ide_pci_device::ide_pci_device(const machine_config &mconfig, const char *tag, d
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m_ide(*this, "ide"),
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m_ide2(*this, "ide2"),
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m_irq_num(-1),
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m_irq_handler(*this)
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m_irq_handler(*this),
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m_legacy_top(0x000)
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{
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}
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@ -74,13 +75,13 @@ void ide_pci_device::device_start()
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pci_device::device_start();
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add_map(8, M_IO, FUNC(ide_pci_device::chan1_data_command_map));
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bank_infos[0].adr = 0x1f0;
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bank_infos[0].adr = (m_legacy_top << 20) | 0x1f0;
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add_map(4, M_IO, FUNC(ide_pci_device::chan1_control_map));
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bank_infos[1].adr = 0x3f4;
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bank_infos[1].adr = (m_legacy_top << 20) | 0x3f4;
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add_map(8, M_IO, FUNC(ide_pci_device::chan2_data_command_map));
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bank_infos[2].adr = 0x170;
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bank_infos[2].adr = (m_legacy_top << 20) | 0x170;
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add_map(4, M_IO, FUNC(ide_pci_device::chan2_control_map));
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bank_infos[3].adr = 0x374;
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bank_infos[3].adr = (m_legacy_top << 20) | 0x374;
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add_map(16, M_IO, FUNC(ide_pci_device::bus_master_map));
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bank_infos[4].adr = 0xf00;
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@ -171,16 +172,12 @@ WRITE8_MEMBER(ide_pci_device::prog_if_w)
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// Map Primary IDE Channel
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if (pclass & 0x1) {
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// PCI Mode
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// Enabling BAR 4 in legacy mode
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bank_infos[4].flags &= ~M_DISABLED;
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pci_device::address_base_w(space, 0, pci_bar[0]);
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pci_device::address_base_w(space, 1, pci_bar[1]);
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} else {
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// Legacy Mode
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// Disabling BAR 4 in legacy mode
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bank_infos[4].flags |= M_DISABLED;
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pci_device::address_base_w(space, 0, 0x1f0);
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pci_device::address_base_w(space, 1, 0x3f4);
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pci_device::address_base_w(space, 0, (m_legacy_top << 20) | 0x1f0);
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pci_device::address_base_w(space, 1, (m_legacy_top << 20) | 0x3f4);
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}
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// Map Primary IDE Channel
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if (pclass & 0x4) {
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@ -190,8 +187,8 @@ WRITE8_MEMBER(ide_pci_device::prog_if_w)
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}
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else {
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// Legacy Mode
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pci_device::address_base_w(space, 2, 0x170);
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pci_device::address_base_w(space, 3, 0x374);
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pci_device::address_base_w(space, 2, (m_legacy_top << 20) | 0x170);
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pci_device::address_base_w(space, 3, (m_legacy_top << 20) | 0x374);
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}
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}
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if (1)
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@ -223,19 +220,17 @@ WRITE32_MEMBER(ide_pci_device::address_base_w)
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// Bits 0 (primary) and 2 (secondary) control if the mapping is legacy or BAR
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switch (offset) {
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case 0: case 1:
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if ((pclass & 0x1) == 1)
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if (pclass & 0x1)
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pci_device::address_base_w(space, offset, data);
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break;
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case 2: case 3:
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if ((pclass & 0x4) == 1)
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if (pclass & 0x4)
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pci_device::address_base_w(space, offset, data);
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break;
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default:
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// Only the first 4 bars are controlled by pif
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pci_device::address_base_w(space, offset, data);
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// Not sure what to do for the bus master ide BAR in legacy mode
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// prog_if_w will disable register in legacy mode
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if ((pclass & 0x5) == 0)
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logerror("Mapping bar[%i] in legacy mode\n", offset);
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}
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logerror("Mapping bar[%i] = %08x\n", offset, data);
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}
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}
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@ -27,6 +27,10 @@ TODO:
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#define MCFG_IDE_PCI_IRQ_HANDLER(_devcb) \
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devcb = &ide_pci_device::set_irq_handler(*device, DEVCB_##_devcb);
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// This will set the top 12 bits for address decoding in legacy mode. Needed for seattle driver.
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#define MCFG_IDE_PCI_SET_LEGACY_TOP(_val) \
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downcast<ide_pci_device *>(device)->set_legacy_top(_val);
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class ide_pci_device : public pci_device {
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public:
|
||||
ide_pci_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
@ -40,7 +44,7 @@ public:
|
||||
DECLARE_WRITE32_MEMBER(ide2_write_cs1);
|
||||
void set_irq_info(const char *tag, const int irq_num);
|
||||
template<class _Object> static devcb_base &set_irq_handler(device_t &device, _Object object) { return downcast<ide_pci_device &>(device).m_irq_handler.set_callback(object); }
|
||||
|
||||
void set_legacy_top(int val) { m_legacy_top = val & 0xfff; };
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
@ -54,6 +58,8 @@ private:
|
||||
int m_irq_num;
|
||||
devcb_write_line m_irq_handler;
|
||||
uint32_t pci_bar[6];
|
||||
// Bits 31-20 for legacy mode hack
|
||||
uint32_t m_legacy_top;
|
||||
|
||||
uint32_t m_config_data[0x10];
|
||||
DECLARE_ADDRESS_MAP(chan1_data_command_map, 32);
|
||||
|
||||
@ -103,6 +103,12 @@ void pci_device::device_start()
|
||||
expansion_rom_size = 0;
|
||||
expansion_rom_base = 0;
|
||||
|
||||
for (int i = 0; i < ARRAY_LENGTH(bank_infos); i++) {
|
||||
save_item(NAME(bank_infos[i].adr), i);
|
||||
}
|
||||
save_item(NAME(command));
|
||||
save_item(NAME(command_mask));
|
||||
save_item(NAME(status));
|
||||
save_item(NAME(intr_line));
|
||||
save_item(NAME(intr_pin));
|
||||
}
|
||||
@ -836,6 +842,9 @@ void pci_host_device::device_start()
|
||||
io_window_start = io_window_end = io_offset = 0;
|
||||
|
||||
reset_all_mappings();
|
||||
|
||||
save_item(NAME(config_address));
|
||||
|
||||
}
|
||||
|
||||
void pci_host_device::device_reset()
|
||||
|
||||
@ -91,7 +91,6 @@ void pci9050_device::postload(void)
|
||||
remap_rom();
|
||||
for (int id = 0; id < 4; id++)
|
||||
remap_local(id);
|
||||
remap_cb();
|
||||
}
|
||||
|
||||
void pci9050_device::device_reset()
|
||||
|
||||
@ -62,9 +62,10 @@ void vrc4373_device::device_start()
|
||||
status = 0x0280;
|
||||
// Reserve 8M for ram
|
||||
m_ram.reserve(0x00800000 / 4);
|
||||
m_ram.resize(m_ram_size);
|
||||
// Reserve 32M for simm[0]
|
||||
m_simm[0].reserve(0x02000000 / 4);
|
||||
|
||||
m_simm[0].resize(m_simm0_size / 4);
|
||||
// ROM
|
||||
uint32_t romSize = m_romRegion->bytes();
|
||||
m_cpu_space->install_rom(0x1fc00000, 0x1fc00000 + romSize - 1, m_romRegion->base());
|
||||
@ -92,7 +93,13 @@ void vrc4373_device::device_start()
|
||||
save_item(NAME(m_pci_io_laddr));
|
||||
save_item(NAME(m_target1_laddr));
|
||||
save_item(NAME(m_target2_laddr));
|
||||
machine().save().register_postload(save_prepost_delegate(FUNC(vrc4373_device::map_cpu_space), this));
|
||||
machine().save().register_postload(save_prepost_delegate(FUNC(vrc4373_device::postload), this));
|
||||
}
|
||||
|
||||
void vrc4373_device::postload()
|
||||
{
|
||||
map_cpu_space();
|
||||
//remap_cb();
|
||||
}
|
||||
|
||||
void vrc4373_device::device_reset()
|
||||
|
||||
@ -77,6 +77,7 @@ public:
|
||||
virtual void reset_all_mappings() override;
|
||||
virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
|
||||
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
|
||||
void postload(void);
|
||||
|
||||
void set_cpu_tag(const char *tag);
|
||||
void set_ram_size(const int size) { m_ram_size = size; };
|
||||
|
||||
@ -928,7 +928,7 @@ DRIVER_INIT_MEMBER(atlantis_state,mwskins)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
GAME( 2000, mwskins, 0, mwskins, mwskins, atlantis_state, mwskins, ROT0, "Midway", "Skins Game (1.06)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
|
||||
GAME( 2000, mwskinsa, mwskins, mwskins, mwskins, atlantis_state, mwskins, ROT0, "Midway", "Skins Game (1.06, alt)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
|
||||
GAME( 2000, mwskinso, mwskins, mwskins, mwskins, atlantis_state, mwskins, ROT0, "Midway", "Skins Game (1.04)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
|
||||
GAME( 2000, mwskinst, mwskins, mwskins, mwskins, atlantis_state, mwskins, ROT0, "Midway", "Skins Game Tournament Edition", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
|
||||
GAME( 2000, mwskins, 0, mwskins, mwskins, atlantis_state, mwskins, ROT0, "Midway", "Skins Game (1.06)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND | MACHINE_SUPPORTS_SAVE )
|
||||
GAME( 2000, mwskinsa, mwskins, mwskins, mwskins, atlantis_state, mwskins, ROT0, "Midway", "Skins Game (1.06, alt)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND | MACHINE_SUPPORTS_SAVE)
|
||||
GAME( 2000, mwskinso, mwskins, mwskins, mwskins, atlantis_state, mwskins, ROT0, "Midway", "Skins Game (1.04)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND | MACHINE_SUPPORTS_SAVE)
|
||||
GAME( 2000, mwskinst, mwskins, mwskins, mwskins, atlantis_state, mwskins, ROT0, "Midway", "Skins Game Tournament Edition", MACHINE_NOT_WORKING | MACHINE_NO_SOUND | MACHINE_SUPPORTS_SAVE)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user