Core refactoring

- connect_late ==> connect
- register nets where they are created
This commit is contained in:
couriersud 2017-01-13 00:52:22 +01:00
parent 63e3b8c16c
commit ef8b7ccb6b
19 changed files with 79 additions and 78 deletions

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@ -850,7 +850,7 @@ public:
, m_feedback(*this, "FB") // clock part
, m_Q(*this, "Q")
{
connect_late(m_feedback, m_Q);
connect(m_feedback, m_Q);
m_inc = netlist::netlist_time::from_nsec(1);

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@ -114,10 +114,10 @@ NETLIB_OBJECT_DERIVED(QBJT_switch, QBJT)
//register_term("_B1", m_BC_dummy.m_P);
//register_term("_C1", m_BC_dummy.m_N);
connect_late(m_RB.m_N, m_RC.m_N);
connect(m_RB.m_N, m_RC.m_N);
connect_late(m_RB.m_P, m_BC_dummy.m_P);
connect_late(m_RC.m_P, m_BC_dummy.m_N);
connect(m_RB.m_P, m_BC_dummy.m_P);
connect(m_RC.m_P, m_BC_dummy.m_N);
}
NETLIB_RESETI();
@ -169,9 +169,9 @@ public:
//register_term("_E1", m_D_EC.m_P);
//register_term("_C1", m_D_EC.m_N);
connect_late(m_D_EB.m_P, m_D_EC.m_P);
connect_late(m_D_EB.m_N, m_D_CB.m_N);
connect_late(m_D_CB.m_P, m_D_EC.m_N);
connect(m_D_EB.m_P, m_D_EC.m_P);
connect(m_D_EB.m_N, m_D_CB.m_N);
connect(m_D_CB.m_P, m_D_EC.m_N);
}
protected:

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@ -76,8 +76,8 @@ public:
m_ON.m_otherterm = &m_IP;
m_ON1.m_otherterm = &m_IN;
connect_late(m_OP, m_OP1);
connect_late(m_ON, m_ON1);
connect(m_OP, m_OP1);
connect(m_ON, m_ON1);
m_gfac = NL_FCONST(1.0);
}
@ -208,8 +208,8 @@ public:
m_OP2.m_otherterm = &m_ON2;
m_ON2.m_otherterm = &m_OP2;
connect_late(m_OP2, m_OP1);
connect_late(m_ON2, m_ON1);
connect(m_OP2, m_OP1);
connect(m_ON2, m_ON1);
}
param_double_t m_RO;

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@ -51,9 +51,9 @@ NETLIB_OBJECT(OPAMP)
register_subalias("MINUS", "G1.IN");
register_subalias("OUT", "G1.OP");
connect_late("G1.ON", "VREF");
connect_late("RP1.2", "VREF");
connect_late("RP1.1", "G1.OP");
connect("G1.ON", "VREF");
connect("RP1.2", "VREF");
connect("RP1.1", "G1.OP");
}
else if (m_type == 3)
@ -70,21 +70,21 @@ NETLIB_OBJECT(OPAMP)
register_subalias("MINUS", "G1.IN");
register_subalias("OUT", "EBUF.OP");
connect_late("EBUF.ON", "VREF");
connect("EBUF.ON", "VREF");
connect_late("G1.ON", "VREF");
connect_late("RP1.2", "VREF");
connect_late("CP1.2", "VREF");
connect_late("EBUF.IN", "VREF");
connect("G1.ON", "VREF");
connect("RP1.2", "VREF");
connect("CP1.2", "VREF");
connect("EBUF.IN", "VREF");
connect_late("RP1.1", "G1.OP");
connect_late("CP1.1", "RP1.1");
connect("RP1.1", "G1.OP");
connect("CP1.1", "RP1.1");
connect_late("DP.K", "VH");
connect_late("VL", "DN.A");
connect_late("DP.A", "DN.K");
connect_late("DN.K", "RP1.1");
connect_late("EBUF.IP", "RP1.1");
connect("DP.K", "VH");
connect("VL", "DN.A");
connect("DP.A", "DN.K");
connect("DN.K", "RP1.1");
connect("EBUF.IP", "RP1.1");
}
else
netlist().log().fatal("Unknown opamp type: {1}", m_type);

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@ -56,7 +56,7 @@ NETLIB_OBJECT(switch2)
, m_R2(*this, "R2")
, m_POS(*this, "POS", 0)
{
connect_late(m_R1.m_N, m_R2.m_N);
connect(m_R1.m_N, m_R2.m_N);
register_subalias("1", m_R1.m_P);
register_subalias("2", m_R2.m_P);

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@ -216,7 +216,7 @@ NETLIB_OBJECT(POT)
register_subalias("2", m_R1.m_N);
register_subalias("3", m_R2.m_N);
connect_late(m_R2.m_P, m_R1.m_N);
connect(m_R2.m_P, m_R1.m_N);
}

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@ -42,11 +42,11 @@ namespace netlist
register_subalias("C", m_RN.m_R.m_N);
register_subalias("RC", m_RN.m_R.m_P);
connect_late(m_RP_Q, m_RP.m_I);
connect_late(m_RN_Q, m_RN.m_I);
connect(m_RP_Q, m_RP.m_I);
connect(m_RN_Q, m_RN.m_I);
connect_late(m_RN.m_R.m_P, m_RP.m_R.m_N);
connect_late(m_CV, m_RN.m_R.m_P);
connect(m_RN.m_R.m_P, m_RP.m_R.m_N);
connect(m_CV, m_RN.m_R.m_P);
m_RP.m_RON.setTo(m_RI());
m_RN.m_RON.setTo(m_RI());
@ -94,7 +94,7 @@ namespace netlist
register_subalias("6", m_2.m_RN.m_R.m_N);
register_subalias("7", m_2.m_RN.m_R.m_P);
register_subalias("8", m_1.m_RN.m_R.m_N);
connect_late(m_1.m_RN.m_R.m_N, m_2.m_RN.m_R.m_N);
connect(m_1.m_RN.m_R.m_N, m_2.m_RN.m_R.m_N);
register_subalias("9", m_2.m_A);
register_subalias("10", m_2.m_B);
@ -104,7 +104,7 @@ namespace netlist
register_subalias("14", m_1.m_RN.m_R.m_N);
register_subalias("15", m_1.m_RN.m_R.m_P);
register_subalias("16", m_1.m_RP.m_R.m_P);
connect_late(m_1.m_RP.m_R.m_P, m_2.m_RP.m_R.m_P);
connect(m_1.m_RP.m_R.m_P, m_2.m_RP.m_R.m_P);
}
NETLIB_RESETI();
NETLIB_UPDATEI();
@ -127,7 +127,7 @@ namespace netlist
register_subalias("6", m_1.m_Q);
register_subalias("7", m_1.m_QQ);
register_subalias("8", m_1.m_RN.m_R.m_N);
connect_late(m_1.m_RN.m_R.m_N, m_2.m_RN.m_R.m_N);
connect(m_1.m_RN.m_R.m_N, m_2.m_RN.m_R.m_N);
register_subalias("9", m_2.m_QQ);
register_subalias("10", m_2.m_Q);
@ -137,7 +137,7 @@ namespace netlist
register_subalias("14", m_2.m_RN.m_R.m_P); // RC2
register_subalias("15", m_2.m_RN.m_R.m_N); // C2
register_subalias("16", m_1.m_RP.m_R.m_P);
connect_late(m_1.m_RP.m_R.m_P, m_2.m_RP.m_R.m_P);
connect(m_1.m_RP.m_R.m_P, m_2.m_RP.m_R.m_P);
}
NETLIB_RESETI();
NETLIB_UPDATEI();
@ -161,7 +161,7 @@ namespace netlist
register_subalias("6", m_1.m_Q);
register_subalias("7", m_1.m_QQ);
register_subalias("8", m_1.m_RN.m_R.m_N);
connect_late(m_1.m_RN.m_R.m_N, m_2.m_RN.m_R.m_N);
connect(m_1.m_RN.m_R.m_N, m_2.m_RN.m_R.m_N);
register_subalias("9", m_2.m_QQ);
register_subalias("10", m_2.m_Q);
@ -171,7 +171,7 @@ namespace netlist
register_subalias("14", m_2.m_RN.m_R.m_P); // RC2
register_subalias("15", m_2.m_RN.m_R.m_N); // C2
register_subalias("16", m_1.m_RP.m_R.m_P);
connect_late(m_1.m_RP.m_R.m_P, m_2.m_RP.m_R.m_P);
connect(m_1.m_RP.m_R.m_P, m_2.m_RP.m_R.m_P);
}
NETLIB_RESETI();
NETLIB_UPDATEI();

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@ -51,8 +51,8 @@ namespace netlist
register_subalias("QC", C.m_Q);
register_subalias("QD", D.m_Q);
connect_late(C.m_I, B.m_Q);
connect_late(D.m_I, C.m_Q);
connect(C.m_I, B.m_Q);
connect(D.m_I, C.m_Q);
}
NETLIB_RESETI() { }

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@ -55,7 +55,7 @@ namespace netlist
, m_out(*this, "m_out", 0)
, m_inc(*this, "m_inc", netlist_time::zero())
{
connect_late(m_FB, m_Y);
connect(m_FB, m_Y);
}
NETLIB_RESETI()
@ -89,9 +89,9 @@ namespace netlist
{
register_subalias("GND", m_R_FC.m_N);
connect_late(m_FC, m_R_FC.m_P);
connect_late(m_RNG, m_R_RNG.m_P);
connect_late(m_R_FC.m_N, m_R_RNG.m_N);
connect(m_FC, m_R_FC.m_P);
connect(m_RNG, m_R_RNG.m_P);
connect(m_R_FC.m_N, m_R_RNG.m_N);
register_subalias("Y", m_clock.m_Y);
}
@ -133,7 +133,7 @@ namespace netlist
register_subalias("8", m_1.m_R_FC.m_N);
register_subalias("9", m_1.m_R_FC.m_N);
connect_late(m_1.m_R_FC.m_N, m_2.m_R_FC.m_N);
connect(m_1.m_R_FC.m_N, m_2.m_R_FC.m_N);
register_subalias("10", m_2.m_clock.m_Y);

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@ -31,12 +31,12 @@ namespace netlist
, m_shift(*this, "m_shift", 0)
, m_is_timestep(false)
{
connect_late(m_feedback, m_Q);
connect(m_feedback, m_Q);
/* output */
//register_term("_RV1", m_RV.m_P);
//register_term("_RV2", m_RV.m_N);
connect_late(m_RV.m_N, m_VDD);
connect(m_RV.m_N, m_VDD);
/* device */
register_subalias("3", m_RV.m_P);

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@ -35,9 +35,9 @@ namespace netlist
register_subalias("DISCH", m_RDIS.m_P); // Pin 7
register_subalias("VCC", m_R1.m_P); // Pin 8
connect_late(m_R1.m_N, m_R2.m_P);
connect_late(m_R2.m_N, m_R3.m_P);
connect_late(m_RDIS.m_N, m_R3.m_N);
connect(m_R1.m_N, m_R2.m_P);
connect(m_R2.m_N, m_R3.m_P);
connect(m_RDIS.m_N, m_R3.m_N);
}
NETLIB_UPDATEI();

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@ -171,7 +171,7 @@ namespace netlist
m_desc.push_back(*desc);
desc++;
}
startxx();
init();
}
template <class C>
@ -184,10 +184,10 @@ namespace netlist
, m_ttp(ttp)
{
m_desc = desc;
startxx();
init();
}
void startxx()
void init()
{
set_hint_deactivate(true);
@ -220,7 +220,7 @@ namespace netlist
const std::size_t idx = plib::container::indexof(inout, tmp);
if (idx != plib::container::npos)
{
connect_late(m_Q[i], m_I[idx]);
connect(m_Q[i], m_I[idx]);
// disable ignore for this inputs altogether.
// FIXME: This shouldn't be necessary
disabled_ignore |= (1<<idx);
@ -251,7 +251,7 @@ namespace netlist
for (std::size_t i = 0; i < m_NI; i++)
m_I[i].activate();
for (std::size_t i=0; i<m_NO;i++)
if (this->m_Q[i].net().num_cons()>0)
if (this->m_Q[i].has_net() && this->m_Q[i].net().num_cons()>0)
m_active++;
}

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@ -107,7 +107,7 @@ namespace netlist
register_subalias("Q", m_RV.m_P);
connect_late(m_RV.m_N, m_GNDHack);
connect(m_RV.m_N, m_GNDHack);
bool f = false;
for (int i = 0; i < 3; i++)
{

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@ -92,7 +92,7 @@ namespace netlist
{
m_inc = netlist_time::from_double(1.0 / (m_freq()*2.0));
connect_late(m_feedback, m_Q);
connect(m_feedback, m_Q);
}
NETLIB_UPDATEI();
//NETLIB_RESETI();
@ -123,7 +123,7 @@ namespace netlist
{
m_inc[0] = netlist_time::from_double(1.0 / (m_freq()*2.0));
connect_late(m_feedback, m_Q);
connect(m_feedback, m_Q);
{
netlist_time base = netlist_time::from_double(1.0 / (m_freq()*2.0));
plib::pstring_vector_t pat(m_pattern(),",");
@ -267,11 +267,11 @@ namespace netlist
{
register_subalias("I", m_RIN.m_P);
register_subalias("G", m_RIN.m_N);
connect_late(m_I, m_RIN.m_P);
connect(m_I, m_RIN.m_P);
register_subalias("_OP", m_ROUT.m_P);
register_subalias("Q", m_ROUT.m_N);
connect_late(m_Q, m_ROUT.m_P);
connect(m_Q, m_ROUT.m_P);
}
NETLIB_RESETI()

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@ -665,12 +665,12 @@ void device_t::register_subalias(const pstring &name, const pstring &aliased)
setup().register_alias_nofqn(alias, aliased_fqn);
}
void device_t::connect_late(detail::core_terminal_t &t1, detail::core_terminal_t &t2)
void device_t::connect(detail::core_terminal_t &t1, detail::core_terminal_t &t2)
{
setup().register_link_fqn(t1.name(), t2.name());
}
void device_t::connect_late(const pstring &t1, const pstring &t2)
void device_t::connect(const pstring &t1, const pstring &t2)
{
setup().register_link_fqn(name() + "." + t1, name() + "." + t2);
}
@ -722,10 +722,6 @@ detail::net_t::net_t(netlist_t &nl, const pstring &aname, core_terminal_t *mr)
, m_cur_Analog(*this, "m_cur_Analog", 0.0)
{
m_railterminal = mr;
if (mr != nullptr)
nl.m_nets.push_back(plib::owned_ptr<net_t>(this, false));
else
nl.m_nets.push_back(plib::owned_ptr<net_t>(this, true));
}
detail::net_t::~net_t()
@ -908,7 +904,7 @@ void detail::core_terminal_t::set_net(net_t *anet)
m_net = anet;
}
void detail::core_terminal_t::clear_net()
void detail::core_terminal_t::clear_net()
{
m_net = nullptr;
}
@ -970,6 +966,7 @@ logic_output_t::logic_output_t(core_device_t &dev, const pstring &aname)
, m_my_net(dev.netlist(), name() + ".net", this)
{
this->set_net(&m_my_net);
netlist().m_nets.push_back(plib::owned_ptr<logic_net_t>(&m_my_net, false));
set_logic_family(dev.logic_family());
netlist().setup().register_term(*this);
}
@ -980,7 +977,8 @@ logic_output_t::~logic_output_t()
void logic_output_t::initial(const netlist_sig_t val)
{
net().initial(val);
if (has_net())
net().initial(val);
}
// ----------------------------------------------------------------------------------------
@ -1005,6 +1003,7 @@ analog_output_t::analog_output_t(core_device_t &dev, const pstring &aname)
: analog_t(dev, aname, STATE_OUT)
, m_my_net(dev.netlist(), name() + ".net", this)
{
netlist().m_nets.push_back(plib::owned_ptr<analog_net_t>(&m_my_net, false));
this->set_net(&m_my_net);
net().m_cur_Analog = NL_FCONST(0.0);

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@ -1081,19 +1081,17 @@ namespace netlist
setup_t &setup();
#if 1
template<class C>
void register_sub(const pstring &name, std::unique_ptr<C> &dev)
{
dev.reset(new C(*this, name));
}
#endif
void register_subalias(const pstring &name, detail::core_terminal_t &term);
void register_subalias(const pstring &name, const pstring &aliased);
void connect_late(const pstring &t1, const pstring &t2);
void connect_late(detail::core_terminal_t &t1, detail::core_terminal_t &t2);
void connect(const pstring &t1, const pstring &t2);
void connect(detail::core_terminal_t &t1, detail::core_terminal_t &t2);
void connect_post_start(detail::core_terminal_t &t1, detail::core_terminal_t &t2);
protected:
@ -1246,7 +1244,7 @@ namespace netlist
plib::dynlib &lib() { return *m_lib; }
/* sole use is to manage lifetime of net objects */
std::vector<plib::owned_ptr<detail::net_t>> m_nets;
std::vector<plib::owned_ptr<detail::net_t>> m_nets;
protected:
void print_stats() const;
@ -1445,11 +1443,11 @@ namespace netlist
inline void analog_output_t::set_Q(const nl_double newQ) NL_NOEXCEPT
{
if (newQ != net().Q_Analog())
if (newQ != m_my_net.Q_Analog())
{
net().m_cur_Analog = newQ;
net().toggle_new_Q();
net().push_to_queue(NLTIME_FROM_NS(1));
m_my_net.m_cur_Analog = newQ;
m_my_net.toggle_new_Q();
m_my_net.push_to_queue(NLTIME_FROM_NS(1));
}
}

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@ -580,6 +580,7 @@ void setup_t::connect_terminals(detail::core_terminal_t &t1, detail::core_termin
log().debug("adding analog net ...\n");
// FIXME: Nets should have a unique name
auto anet = plib::palloc<analog_net_t>(netlist(),"net." + t1.name());
netlist().m_nets.push_back(plib::owned_ptr<analog_net_t>(anet, true));
t1.set_net(anet);
anet->add_terminal(t2);
anet->add_terminal(t1);
@ -756,8 +757,10 @@ void setup_t::resolve_inputs()
for (auto & t : netlist().get_device_list<devices::NETLIB_NAME(twoterm)>())
{
if (t->m_N.net().isRailNet() && t->m_P.net().isRailNet())
{
log().warning("Found device {1} connected only to railterminals {2}/{3}\n",
t->name(), t->m_N.net().name(), t->m_P.net().name());
}
}
}

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@ -61,6 +61,7 @@ public:
owned_ptr(SC *p, bool owned) noexcept
: m_ptr(p), m_is_owned(owned)
{ }
owned_ptr(const owned_ptr &r) = delete;
owned_ptr & operator =(owned_ptr &r) = delete;

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@ -66,7 +66,7 @@ NETLIB_OBJECT(solver)
{
// internal staff
connect_late(m_fb_step, m_Q_step);
connect(m_fb_step, m_Q_step);
}
virtual ~NETLIB_NAME(solver)();