mirror of
https://github.com/holub/mame
synced 2025-04-16 05:24:54 +03:00
r4000: timing improvements
* external clock is doubled internally * consume additional cycles for integer multiply/divide * streamline memory access
This commit is contained in:
Patrick Mackinlay
parent
ee62f40e1b
commit
efa3521d7a
@ -90,10 +90,11 @@ DEFINE_DEVICE_TYPE(R5000, r5000_device, "r5000", "MIPS R5000")
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u32 const r5000_device::s_fcc_masks[8] = { (1U << 23), (1U << 25), (1U << 26), (1U << 27), (1U << 28), (1U << 29), (1U << 30), (1U << 31) };
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u32 const r5000_device::s_fcc_shifts[8] = { 23, 25, 26, 27, 28, 29, 30, 31 };
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r4000_base_device::r4000_base_device(machine_config const &mconfig, device_type type, char const *tag, device_t *owner, u32 clock, u32 prid, u32 fcr, cache_size icache_size, cache_size dcache_size)
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r4000_base_device::r4000_base_device(machine_config const &mconfig, device_type type, char const *tag, device_t *owner, u32 clock, u32 prid, u32 fcr, cache_size icache_size, cache_size dcache_size, unsigned m32, unsigned m64, unsigned d32, unsigned d64)
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: cpu_device(mconfig, type, tag, owner, clock)
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, m_program_config_le("program", ENDIANNESS_LITTLE, 64, 32)
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, m_program_config_be("program", ENDIANNESS_BIG, 64, 32)
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, m_hilo_cycles{ m32, m64, d32, d64 }
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, m_r{}
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, m_cp0{}
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, m_f{}
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@ -193,6 +194,8 @@ void r4000_base_device::device_start()
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m_icache_mask_hi = (0x1000U << config_ic) - 1;
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m_icache_tag = std::make_unique<u32[]>(0x100U << config_ic);
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m_icache_data = std::make_unique<u32 []>((0x1000U << config_ic) >> 2);
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R4000_ENDIAN_LE_BE(accessors(m_le), accessors(m_be));
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}
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void r4000_base_device::device_reset()
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@ -205,6 +208,7 @@ void r4000_base_device::device_reset()
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else
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m_cp0[CP0_Status] = SR_BEV | SR_ERL;
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m_hilo_delay = 0;
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m_branch_state = NONE;
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m_pc = s64(s32(0xbfc00000));
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m_r[0] = 0;
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@ -294,6 +298,9 @@ void r4000_base_device::execute_run()
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m_r[0] = 0;
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});
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if (m_hilo_delay)
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m_hilo_delay--;
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// update pc and branch state
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switch (m_branch_state)
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{
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@ -428,12 +435,22 @@ void r4000_base_device::cpu_execute(u32 const op)
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break;
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case 0x10: // MFHI
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m_r[RDREG] = m_hi;
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if (m_hilo_delay)
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{
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m_icount -= m_hilo_delay;
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m_hilo_delay = 0;
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}
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break;
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case 0x11: // MTHI
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m_hi = m_r[RSREG];
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break;
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case 0x12: // MFLO
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m_r[RDREG] = m_lo;
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if (m_hilo_delay)
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{
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m_icount -= m_hilo_delay;
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m_hilo_delay = 0;
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}
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break;
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case 0x13: // MTLO
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m_lo = m_r[RSREG];
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@ -454,6 +471,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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m_lo = s64(s32(product));
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m_hi = s64(s32(product >> 32));
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m_hilo_delay = m_hilo_cycles[0];
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}
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break;
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case 0x19: // MULTU
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@ -462,6 +480,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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m_lo = s64(s32(product));
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m_hi = s64(s32(product >> 32));
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m_hilo_delay = m_hilo_cycles[0];
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}
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break;
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case 0x1a: // DIV
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@ -469,6 +488,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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{
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m_lo = s64(s32(m_r[RSREG]) / s32(m_r[RTREG]));
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m_hi = s64(s32(m_r[RSREG]) % s32(m_r[RTREG]));
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m_hilo_delay = m_hilo_cycles[2];
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}
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break;
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case 0x1b: // DIVU
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@ -476,19 +496,23 @@ void r4000_base_device::cpu_execute(u32 const op)
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{
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m_lo = s64(s32(u32(m_r[RSREG]) / u32(m_r[RTREG])));
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m_hi = s64(s32(u32(m_r[RSREG]) % u32(m_r[RTREG])));
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m_hilo_delay = m_hilo_cycles[2];
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}
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break;
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case 0x1c: // DMULT
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m_lo = mul_64x64(m_r[RSREG], m_r[RTREG], *reinterpret_cast<s64 *>(&m_hi));
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m_hilo_delay = m_hilo_cycles[1];
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break;
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case 0x1d: // DMULTU
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m_lo = mulu_64x64(m_r[RSREG], m_r[RTREG], m_hi);
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m_hilo_delay = m_hilo_cycles[1];
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break;
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case 0x1e: // DDIV
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if (m_r[RTREG])
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{
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m_lo = s64(m_r[RSREG]) / s64(m_r[RTREG]);
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m_hi = s64(m_r[RSREG]) % s64(m_r[RTREG]);
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m_hilo_delay = m_hilo_cycles[3];
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}
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break;
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case 0x1f: // DDIVU
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@ -496,6 +520,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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{
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m_lo = m_r[RSREG] / m_r[RTREG];
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m_hi = m_r[RSREG] % m_r[RTREG];
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m_hilo_delay = m_hilo_cycles[3];
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}
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break;
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case 0x20: // ADD
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@ -3704,6 +3729,21 @@ void r4000_base_device::address_error(int intention, u64 const address)
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}
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}
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template <typename T> void r4000_base_device::accessors(T &m)
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{
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space(AS_PROGRAM).cache(m);
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read_byte = [&m](offs_t offset) { return m.read_byte(offset); };
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read_word = [&m](offs_t offset) { return m.read_word(offset); };
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read_dword = [&m](offs_t offset) { return m.read_dword(offset); };
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read_qword = [&m](offs_t offset) { return m.read_qword(offset); };
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write_byte = [&m](offs_t offset, u8 data) { m.write_byte(offset, data); };
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write_word = [&m](offs_t offset, u16 data, u16 mem_mask) { m.write_word(offset, data, mem_mask); };
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write_dword = [&m](offs_t offset, u32 data, u32 mem_mask) { m.write_dword(offset, data, mem_mask); };
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write_qword = [&m](offs_t offset, u64 data, u64 mem_mask) { m.write_qword(offset, data, mem_mask); };
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}
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template <typename T, bool Aligned, typename U> std::enable_if_t<std::is_convertible<U, std::function<void(T)>>::value, bool> r4000_base_device::load(u64 address, U &&apply)
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{
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// alignment error
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@ -3748,10 +3788,10 @@ template <typename T, bool Aligned, typename U> std::enable_if_t<std::is_convert
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T value = 0;
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switch (sizeof(T))
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{
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case 1: value = T(space(0).read_byte(address)); break;
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case 2: value = T(space(0).read_word(address)); break;
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case 4: value = T(space(0).read_dword(address)); break;
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case 8: value = T(space(0).read_qword(address)); break;
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case 1: value = T(read_byte(address)); break;
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case 2: value = T(read_word(address)); break;
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case 4: value = T(read_dword(address)); break;
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case 8: value = T(read_qword(address)); break;
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}
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if (m_bus_error)
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@ -3805,8 +3845,8 @@ template <typename T, typename U> std::enable_if_t<std::is_convertible<U, std::f
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switch (sizeof(T))
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{
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case 4: apply(address, T(space(0).read_dword(address))); break;
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case 8: apply(address, T(space(0).read_qword(address))); break;
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case 4: apply(address, T(read_dword(address))); break;
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case 8: apply(address, T(read_qword(address))); break;
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}
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return true;
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@ -3854,10 +3894,10 @@ template <typename T, bool Aligned, typename U> std::enable_if_t<std::is_convert
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switch (sizeof(T))
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{
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case 1: space(0).write_byte(address, T(data)); break;
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case 2: space(0).write_word(address, T(data), mem_mask); break;
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case 4: space(0).write_dword(address, T(data), mem_mask); break;
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case 8: space(0).write_qword(address, T(data), mem_mask); break;
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case 1: write_byte(address, T(data)); break;
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case 2: write_word(address, T(data), mem_mask); break;
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case 4: write_dword(address, T(data), mem_mask); break;
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case 8: write_qword(address, T(data), mem_mask); break;
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}
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return true;
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@ -3893,7 +3933,7 @@ bool r4000_base_device::fetch(u64 address, std::function<void(u32)> &&apply)
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{
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if (t == UNCACHED)
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{
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const u32 insn = space(0).read_dword(address);
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const u32 insn = read_dword(address);
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if (m_bus_error)
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{
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@ -3922,7 +3962,7 @@ bool r4000_base_device::fetch(u64 address, std::function<void(u32)> &&apply)
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tag = ICACHE_V | (address >> 12);
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for (unsigned i = 0; i < m_icache_line_size; i += 8)
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{
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u64 const data = space(0).read_qword((address & m_icache_mask_lo) | i);
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u64 const data = read_qword((address & m_icache_mask_lo) | i);
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m_icache_data[(((cache_address & m_icache_mask_lo) | i) >> 2) + 0] = u32(data);
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m_icache_data[(((cache_address & m_icache_mask_lo) | i) >> 2) + 1] = data >> 32;
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@ -3936,7 +3976,7 @@ bool r4000_base_device::fetch(u64 address, std::function<void(u32)> &&apply)
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}
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else
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{
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const u32 insn = space(0).read_dword(address);
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const u32 insn = read_dword(address);
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if (m_bus_error)
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{
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@ -57,7 +57,7 @@ protected:
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CACHE_256K = 6,
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CACHE_512K = 7,
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};
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r4000_base_device(machine_config const &mconfig, device_type type, char const *tag, device_t *owner, u32 clock, u32 prid, u32 fcr, cache_size icache_size, cache_size dcache_size);
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r4000_base_device(machine_config const &mconfig, device_type type, char const *tag, device_t *owner, u32 clock, u32 prid, u32 fcr, cache_size icache_size, cache_size dcache_size, unsigned m32, unsigned m64, unsigned d32, unsigned d64);
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enum cp0_reg : int
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{
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@ -320,8 +320,10 @@ protected:
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virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
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// device_execute_interface overrides
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virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks * 2); }
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virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles + 1) / 2; }
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virtual u32 execute_min_cycles() const noexcept override { return 1; }
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virtual u32 execute_max_cycles() const noexcept override { return 40; }
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virtual u32 execute_max_cycles() const noexcept override { return *std::max_element(std::begin(m_hilo_cycles), std::end(m_hilo_cycles)); }
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virtual u32 execute_input_lines() const noexcept override { return 6; }
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virtual void execute_run() override;
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virtual void execute_set_input(int inputnum, int state) override;
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@ -370,6 +372,7 @@ protected:
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translate_result translate(int intention, u64 &address);
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void address_error(int intention, u64 const address);
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template <typename T> void accessors(T &m);
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template <typename T, bool Aligned = true, typename U> std::enable_if_t<std::is_convertible<U, std::function<void(T)>>::value, bool> load(u64 program_address, U &&apply);
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template <typename T, typename U> std::enable_if_t<std::is_convertible<U, std::function<void(u64, T)>>::value, bool> load_linked(u64 program_address, U &&apply);
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template <typename T, bool Aligned = true, typename U> std::enable_if_t<std::is_convertible<U, T>::value, bool> store(u64 program_address, U data, T mem_mask = ~T(0));
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@ -384,9 +387,26 @@ protected:
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address_space_config m_program_config_le;
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address_space_config m_program_config_be;
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// memory access helpers
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memory_access<64, 3, 0, ENDIANNESS_LITTLE>::cache m_le;
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memory_access<64, 3, 0, ENDIANNESS_BIG>::cache m_be;
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std::function<u8(offs_t offset)> read_byte;
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std::function<u16(offs_t offset)> read_word;
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std::function<u32(offs_t offset)> read_dword;
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std::function<u64(offs_t offset)> read_qword;
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std::function<void(offs_t offset, u8 data)> write_byte;
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std::function<void(offs_t offset, u16 data, u16 mem_mask)> write_word;
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std::function<void(offs_t offset, u32 data, u32 mem_mask)> write_dword;
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std::function<void(offs_t offset, u64 data, u64 mem_mask)> write_qword;
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// runtime state
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int m_icount;
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// integer multiple/divide state
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unsigned const m_hilo_cycles[4];
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unsigned m_hilo_delay;
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// cpu state
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u64 m_pc;
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u64 m_r[32];
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@ -447,7 +467,7 @@ class r4000_device : public r4000_base_device
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public:
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// NOTE: R4000 chips prior to 3.0 have an xtlb bug
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r4000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: r4000_base_device(mconfig, R4000, tag, owner, clock, 0x0430, 0x0500, CACHE_8K, CACHE_8K)
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: r4000_base_device(mconfig, R4000, tag, owner, clock, 0x0430, 0x0500, CACHE_8K, CACHE_8K, 10, 20, 69, 133)
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{
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// no secondary cache
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m_cp0[CP0_Config] |= CONFIG_SC;
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@ -458,7 +478,7 @@ class r4400_device : public r4000_base_device
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{
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public:
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r4400_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: r4000_base_device(mconfig, R4400, tag, owner, clock, 0x0440, 0x0500, CACHE_16K, CACHE_16K)
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: r4000_base_device(mconfig, R4400, tag, owner, clock, 0x0440, 0x0500, CACHE_16K, CACHE_16K, 10, 20, 69, 133)
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{
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// no secondary cache
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m_cp0[CP0_Config] |= CONFIG_SC;
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@ -469,7 +489,7 @@ class r4600_device : public r4000_base_device
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{
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public:
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r4600_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: r4000_base_device(mconfig, R4600, tag, owner, clock, 0x2020, 0x2020, CACHE_16K, CACHE_16K)
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: r4000_base_device(mconfig, R4600, tag, owner, clock, 0x2020, 0x2020, CACHE_16K, CACHE_16K, 10, 12, 42, 74)
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{
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// no secondary cache
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m_cp0[CP0_Config] |= CONFIG_SC;
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@ -480,7 +500,7 @@ class r5000_device : public r4000_base_device
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{
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public:
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r5000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: r4000_base_device(mconfig, R5000, tag, owner, clock, 0x2320, 0x2320, CACHE_32K, CACHE_32K)
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: r4000_base_device(mconfig, R5000, tag, owner, clock, 0x2320, 0x2320, CACHE_32K, CACHE_32K, 5, 9, 36, 68)
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{
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// no secondary cache
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m_cp0[CP0_Config] |= CONFIG_SC;
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@ -214,7 +214,7 @@ void indigo4k_state::indigo4k(machine_config &config)
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{
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indigo_base(config);
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R4000(config, m_maincpu, 50000000*2);
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R4000(config, m_maincpu, 50000000);
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//m_maincpu->set_icache_size(32768);
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//m_maincpu->set_dcache_size(32768);
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m_maincpu->set_addrmap(AS_PROGRAM, &indigo4k_state::mem_map);
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@ -407,7 +407,7 @@ void ip24_state::indy_5015(machine_config &config)
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{
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ip24(config);
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R5000(config, m_maincpu, 50000000*3);
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R5000(config, m_maincpu, 75'000'000);
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m_maincpu->set_addrmap(AS_PROGRAM, &ip24_state::ip24_map);
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}
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@ -415,7 +415,7 @@ void ip24_state::indy_4613(machine_config &config)
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{
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ip24(config);
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R4600(config, m_maincpu, 33333333*4);
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R4600(config, m_maincpu, 66'666'666);
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m_maincpu->set_addrmap(AS_PROGRAM, &ip24_state::ip24_map);
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}
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@ -423,7 +423,7 @@ void ip24_state::indy_4610(machine_config &config)
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{
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ip24(config);
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R4600(config, m_maincpu, 33333333*3);
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R4600(config, m_maincpu, 50'000'000);
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m_maincpu->set_addrmap(AS_PROGRAM, &ip24_state::ip24_map);
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}
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@ -436,7 +436,7 @@ void ip22_state::wd33c93_2(device_t *device)
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void ip22_state::indigo2_4415(machine_config &config)
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{
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R4400(config, m_maincpu, 50000000*3);
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R4400(config, m_maincpu, 75'000'000);
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m_maincpu->set_addrmap(AS_PROGRAM, &ip22_state::ip22_map);
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ip24_base(config);
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