mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
TMS340X0 updates
- tms34020: Upgrade data bus to 32 bits and add preliminary masking for 16-bit operations - tms34010, tms34020: Eliminate pure 8-bit read/write bus accesses (these are always read-modify-write, even if aligned) - btoads, midxunit: Use 8-bit handlers for NVRAM, reducing size to 8192 bytes - midwunit, midxunit: Eliminate dependencies on midtunit driver
This commit is contained in:
AJR
parent
0ca0f8e385
commit
efed2ea2c2
@ -484,13 +484,7 @@ uint32_t tms340x0_device::rfield_s_07(offs_t offset)
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uint32_t tms340x0_device::rfield_s_08(offs_t offset)
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{
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uint32_t ret;
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if (offset & 0x07)
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{
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RFIELDMAC(0xff,9);
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}
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else
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ret = TMS34010_RDMEM(offset);
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RFIELDMAC_8();
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return (int32_t)(int8_t)ret;
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}
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@ -205,40 +205,40 @@ int tms340x0_device::compute_pixblt_b_cycles(int left_partials, int right_partia
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/* Shift register handling */
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void tms340x0_device::memory_w(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t offset,uint16_t data)
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void tms340x0_device::memory_w(offs_t offset, uint16_t data)
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{
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//logerror("memory_w %08x %04x\n", offset << 3, data);
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if((offset << 3) == 0x02005010 && data == 0x0000) {
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machine().debug_break();
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// abort();
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}
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space.write_word(offset, data);
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TMS34010_WRMEM_WORD(offset, data);
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}
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uint16_t tms340x0_device::memory_r(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t offset)
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uint16_t tms340x0_device::memory_r(offs_t offset)
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{
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return space.read_word(offset);
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return TMS34010_RDMEM_WORD(offset);
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}
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void tms340x0_device::shiftreg_w(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t offset,uint16_t data)
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void tms340x0_device::shiftreg_w(offs_t offset, uint16_t data)
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{
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//logerror("shiftreg_w %08x %04x\n", offset << 3, data);
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if (!m_from_shiftreg_cb.isnull())
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m_from_shiftreg_cb(space, offset, &m_shiftreg[0]);
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m_from_shiftreg_cb(offset, &m_shiftreg[0]);
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else
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logerror("From ShiftReg function not set. PC = %08X\n", m_pc);
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}
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uint16_t tms340x0_device::shiftreg_r(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t offset)
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uint16_t tms340x0_device::shiftreg_r(offs_t offset)
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{
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if (!m_to_shiftreg_cb.isnull())
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m_to_shiftreg_cb(space, offset, &m_shiftreg[0]);
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m_to_shiftreg_cb(offset, &m_shiftreg[0]);
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else
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logerror("To ShiftReg function not set. PC = %08X\n", m_pc);
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return m_shiftreg[0];
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}
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uint16_t tms340x0_device::dummy_shiftreg_r(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t offset)
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uint16_t tms340x0_device::dummy_shiftreg_r(offs_t offset)
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{
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return m_shiftreg[0];
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}
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@ -1034,13 +1034,13 @@ void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear
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uint32_t srcword, dstword = 0;
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/* fetch the initial source word */
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srcword = (this->*word_read)(m_program, srcwordaddr++ << 4);
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srcword = (this->*word_read)(srcwordaddr++ << 4);
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readwrites++;
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/* fetch the initial dest word */
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if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY || (daddr & 0x0f) != 0)
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{
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dstword = (this->*word_read)(m_program, dstwordaddr << 4);
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dstword = (this->*word_read)(dstwordaddr << 4);
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readwrites++;
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}
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@ -1053,7 +1053,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear
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/* fetch more words if necessary */
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if (srcbit + BITS_PER_PIXEL > 16)
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{
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srcword |= (this->*word_read)(m_program, srcwordaddr++ << 4) << 16;
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srcword |= (this->*word_read)(srcwordaddr++ << 4) << 16;
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readwrites++;
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}
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@ -1070,7 +1070,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear
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if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY)
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if (dstbit + BITS_PER_PIXEL > 16)
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{
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dstword |= (this->*word_read)(m_program, (dstwordaddr + 1) << 4) << 16;
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dstword |= (this->*word_read)((dstwordaddr + 1) << 4) << 16;
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readwrites++;
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}
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@ -1085,7 +1085,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear
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dstbit += BITS_PER_PIXEL;
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if (dstbit > 16)
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{
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(this->*word_write)(m_program, dstwordaddr++ << 4, dstword);
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(this->*word_write)(dstwordaddr++ << 4, dstword);
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readwrites++;
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dstbit -= 16;
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dstword >>= 16;
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@ -1098,13 +1098,13 @@ void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear
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/* if we're right-partial, read and mask the remaining bits */
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if (dstbit != 16)
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{
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uint16_t origdst = (this->*word_read)(m_program, dstwordaddr << 4);
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uint16_t origdst = (this->*word_read)(dstwordaddr << 4);
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uint16_t mask = 0xffff << dstbit;
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dstword = (dstword & ~mask) | (origdst & mask);
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readwrites++;
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}
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(this->*word_write)(m_program, dstwordaddr++ << 4, dstword);
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(this->*word_write)(dstwordaddr++ << 4, dstword);
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readwrites++;
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}
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@ -1136,14 +1136,14 @@ void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear
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dwordaddr = daddr >> 4;
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/* fetch the initial source word */
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srcword = (this->*word_read)(m_program, swordaddr++ << 4);
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srcword = (this->*word_read)(swordaddr++ << 4);
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srcmask = PIXEL_MASK << (saddr & 15);
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/* handle the left partial word */
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if (left_partials != 0)
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{
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/* fetch the destination word */
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dstword = (this->*word_read)(m_program, dwordaddr << 4);
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dstword = (this->*word_read)(dwordaddr << 4);
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dstmask = PIXEL_MASK << (daddr & 15);
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/* loop over partials */
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@ -1152,7 +1152,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear
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/* fetch another word if necessary */
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if (srcmask == 0)
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{
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srcword = (this->*word_read)(m_program, swordaddr++ << 4);
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srcword = (this->*word_read)(swordaddr++ << 4);
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srcmask = PIXEL_MASK;
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}
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@ -1174,7 +1174,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear
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}
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/* write the result */
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(this->*word_write)(m_program, dwordaddr++ << 4, dstword);
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(this->*word_write)(dwordaddr++ << 4, dstword);
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}
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/* loop over full words */
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@ -1182,7 +1182,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear
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{
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/* fetch the destination word (if necessary) */
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if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY)
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dstword = (this->*word_read)(m_program, dwordaddr << 4);
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dstword = (this->*word_read)(dwordaddr << 4);
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else
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dstword = 0;
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dstmask = PIXEL_MASK;
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@ -1193,7 +1193,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear
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/* fetch another word if necessary */
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if (srcmask == 0)
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{
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srcword = (this->*word_read)(m_program, swordaddr++ << 4);
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srcword = (this->*word_read)(swordaddr++ << 4);
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srcmask = PIXEL_MASK;
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}
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@ -1215,14 +1215,14 @@ void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear
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}
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/* write the result */
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(this->*word_write)(m_program, dwordaddr++ << 4, dstword);
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(this->*word_write)(dwordaddr++ << 4, dstword);
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}
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/* handle the right partial word */
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if (right_partials != 0)
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{
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/* fetch the destination word */
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dstword = (this->*word_read)(m_program, dwordaddr << 4);
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dstword = (this->*word_read)(dwordaddr << 4);
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dstmask = PIXEL_MASK;
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/* loop over partials */
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@ -1232,7 +1232,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear
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if (srcmask == 0)
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{
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LOGGFX((" right fetch @ %08x\n", swordaddr));
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srcword = (this->*word_read)(m_program, swordaddr++ << 4);
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srcword = (this->*word_read)(swordaddr++ << 4);
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srcmask = PIXEL_MASK;
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}
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@ -1254,7 +1254,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear
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}
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/* write the result */
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(this->*word_write)(m_program, dwordaddr++ << 4, dstword);
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(this->*word_write)(dwordaddr++ << 4, dstword);
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}
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#endif
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@ -1405,14 +1405,14 @@ if ((daddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd d
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dwordaddr = (daddr + 15) >> 4;
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/* fetch the initial source word */
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srcword = (this->*word_read)(m_program, --swordaddr << 4);
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srcword = (this->*word_read)(--swordaddr << 4);
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srcmask = PIXEL_MASK << ((saddr - BITS_PER_PIXEL) & 15);
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/* handle the right partial word */
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if (right_partials != 0)
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{
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/* fetch the destination word */
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dstword = (this->*word_read)(m_program, --dwordaddr << 4);
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dstword = (this->*word_read)(--dwordaddr << 4);
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dstmask = PIXEL_MASK << ((daddr - BITS_PER_PIXEL) & 15);
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/* loop over partials */
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@ -1421,7 +1421,7 @@ if ((daddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd d
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/* fetch source pixel if necessary */
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if (srcmask == 0)
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{
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srcword = (this->*word_read)(m_program, --swordaddr << 4);
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srcword = (this->*word_read)(--swordaddr << 4);
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srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL);
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}
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@ -1448,7 +1448,7 @@ if ((daddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd d
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}
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/* write the result */
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(this->*word_write)(m_program, dwordaddr << 4, dstword);
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(this->*word_write)(dwordaddr << 4, dstword);
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}
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/* loop over full words */
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@ -1457,7 +1457,7 @@ if ((daddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd d
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/* fetch the destination word (if necessary) */
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dwordaddr--;
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if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY)
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dstword = (this->*word_read)(m_program, dwordaddr << 4);
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dstword = (this->*word_read)(dwordaddr << 4);
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else
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dstword = 0;
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dstmask = PIXEL_MASK << (16 - BITS_PER_PIXEL);
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@ -1468,7 +1468,7 @@ if ((daddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd d
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/* fetch source pixel if necessary */
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if (srcmask == 0)
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{
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srcword = (this->*word_read)(m_program, --swordaddr << 4);
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srcword = (this->*word_read)(--swordaddr << 4);
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srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL);
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}
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@ -1495,14 +1495,14 @@ if ((daddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd d
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}
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/* write the result */
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(this->*word_write)(m_program, dwordaddr << 4, dstword);
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(this->*word_write)(dwordaddr << 4, dstword);
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}
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/* handle the left partial word */
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if (left_partials != 0)
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{
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/* fetch the destination word */
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dstword = (this->*word_read)(m_program, --dwordaddr << 4);
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dstword = (this->*word_read)(--dwordaddr << 4);
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dstmask = PIXEL_MASK << (16 - BITS_PER_PIXEL);
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/* loop over partials */
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@ -1511,7 +1511,7 @@ if ((daddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd d
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/* fetch the source pixel if necessary */
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if (srcmask == 0)
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{
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srcword = (this->*word_read)(m_program, --swordaddr << 4);
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srcword = (this->*word_read)(--swordaddr << 4);
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srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL);
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}
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@ -1538,7 +1538,7 @@ if ((daddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd d
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}
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/* write the result */
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(this->*word_write)(m_program, dwordaddr << 4, dstword);
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(this->*word_write)(dwordaddr << 4, dstword);
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}
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/* update for next row */
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@ -1663,14 +1663,14 @@ void FUNCTION_NAME(tms340x0_device::pixblt_b)(int dst_is_linear)
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dwordaddr = daddr >> 4;
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/* fetch the initial source word */
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srcword = (this->*word_read)(m_program, swordaddr++ << 4);
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srcword = (this->*word_read)(swordaddr++ << 4);
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srcmask = 1 << (saddr & 15);
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/* handle the left partial word */
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if (left_partials != 0)
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{
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/* fetch the destination word */
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dstword = (this->*word_read)(m_program, dwordaddr << 4);
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dstword = (this->*word_read)(dwordaddr << 4);
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dstmask = PIXEL_MASK << (daddr & 15);
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/* loop over partials */
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@ -1687,7 +1687,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt_b)(int dst_is_linear)
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srcmask <<= 1;
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if (srcmask == 0)
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{
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srcword = (this->*word_read)(m_program, swordaddr++ << 4);
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srcword = (this->*word_read)(swordaddr++ << 4);
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srcmask = 0x0001;
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}
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@ -1696,7 +1696,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt_b)(int dst_is_linear)
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}
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/* write the result */
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(this->*word_write)(m_program, dwordaddr++ << 4, dstword);
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(this->*word_write)(dwordaddr++ << 4, dstword);
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}
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/* loop over full words */
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@ -1704,7 +1704,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt_b)(int dst_is_linear)
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{
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/* fetch the destination word (if necessary) */
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if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY)
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dstword = (this->*word_read)(m_program, dwordaddr << 4);
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dstword = (this->*word_read)(dwordaddr << 4);
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else
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dstword = 0;
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dstmask = PIXEL_MASK;
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@ -1723,7 +1723,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt_b)(int dst_is_linear)
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srcmask <<= 1;
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if (srcmask == 0)
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{
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srcword = (this->*word_read)(m_program, swordaddr++ << 4);
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srcword = (this->*word_read)(swordaddr++ << 4);
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srcmask = 0x0001;
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}
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@ -1732,14 +1732,14 @@ void FUNCTION_NAME(tms340x0_device::pixblt_b)(int dst_is_linear)
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}
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/* write the result */
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(this->*word_write)(m_program, dwordaddr++ << 4, dstword);
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(this->*word_write)(dwordaddr++ << 4, dstword);
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}
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/* handle the right partial word */
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if (right_partials != 0)
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{
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/* fetch the destination word */
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dstword = (this->*word_read)(m_program, dwordaddr << 4);
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dstword = (this->*word_read)(dwordaddr << 4);
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dstmask = PIXEL_MASK;
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/* loop over partials */
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@ -1756,7 +1756,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt_b)(int dst_is_linear)
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srcmask <<= 1;
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if (srcmask == 0)
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{
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srcword = (this->*word_read)(m_program, swordaddr++ << 4);
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srcword = (this->*word_read)(swordaddr++ << 4);
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srcmask = 0x0001;
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}
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@ -1765,7 +1765,7 @@ void FUNCTION_NAME(tms340x0_device::pixblt_b)(int dst_is_linear)
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}
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/* write the result */
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||||
(this->*word_write)(m_program, dwordaddr++ << 4, dstword);
|
||||
(this->*word_write)(dwordaddr++ << 4, dstword);
|
||||
}
|
||||
|
||||
/* update for next row */
|
||||
@ -1879,7 +1879,7 @@ void FUNCTION_NAME(tms340x0_device::fill)(int dst_is_linear)
|
||||
if (left_partials != 0)
|
||||
{
|
||||
/* fetch the destination word */
|
||||
dstword = (this->*word_read)(m_program, dwordaddr << 4);
|
||||
dstword = (this->*word_read)(dwordaddr << 4);
|
||||
dstmask = PIXEL_MASK << (daddr & 15);
|
||||
|
||||
/* loop over partials */
|
||||
@ -1896,7 +1896,7 @@ void FUNCTION_NAME(tms340x0_device::fill)(int dst_is_linear)
|
||||
}
|
||||
|
||||
/* write the result */
|
||||
(this->*word_write)(m_program, dwordaddr++ << 4, dstword);
|
||||
(this->*word_write)(dwordaddr++ << 4, dstword);
|
||||
}
|
||||
|
||||
/* loop over full words */
|
||||
@ -1904,7 +1904,7 @@ void FUNCTION_NAME(tms340x0_device::fill)(int dst_is_linear)
|
||||
{
|
||||
/* fetch the destination word (if necessary) */
|
||||
if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY)
|
||||
dstword = (this->*word_read)(m_program, dwordaddr << 4);
|
||||
dstword = (this->*word_read)(dwordaddr << 4);
|
||||
else
|
||||
dstword = 0;
|
||||
dstmask = PIXEL_MASK;
|
||||
@ -1923,14 +1923,14 @@ void FUNCTION_NAME(tms340x0_device::fill)(int dst_is_linear)
|
||||
}
|
||||
|
||||
/* write the result */
|
||||
(this->*word_write)(m_program, dwordaddr++ << 4, dstword);
|
||||
(this->*word_write)(dwordaddr++ << 4, dstword);
|
||||
}
|
||||
|
||||
/* handle the right partial word */
|
||||
if (right_partials != 0)
|
||||
{
|
||||
/* fetch the destination word */
|
||||
dstword = (this->*word_read)(m_program, dwordaddr << 4);
|
||||
dstword = (this->*word_read)(dwordaddr << 4);
|
||||
dstmask = PIXEL_MASK;
|
||||
|
||||
/* loop over partials */
|
||||
@ -1947,7 +1947,7 @@ void FUNCTION_NAME(tms340x0_device::fill)(int dst_is_linear)
|
||||
}
|
||||
|
||||
/* write the result */
|
||||
(this->*word_write)(m_program, dwordaddr++ << 4, dstword);
|
||||
(this->*word_write)(dwordaddr++ << 4, dstword);
|
||||
}
|
||||
|
||||
/* update for next row */
|
||||
|
||||
@ -21,24 +21,6 @@
|
||||
MEMORY I/O MACROS
|
||||
***************************************************************************/
|
||||
|
||||
#define TMS34010_RDMEM(A) ((unsigned)m_program.read_byte (A))
|
||||
#define TMS34010_RDMEM_WORD(A) ((unsigned)m_program.read_word (A))
|
||||
inline uint32_t tms340x0_device::TMS34010_RDMEM_DWORD(offs_t A)
|
||||
{
|
||||
uint32_t result = m_program.read_word(A);
|
||||
return result | (m_program.read_word(A+16)<<16);
|
||||
}
|
||||
|
||||
#define TMS34010_WRMEM(A,V) (m_program.write_byte(A,V))
|
||||
#define TMS34010_WRMEM_WORD(A,V) (m_program.write_word(A,V))
|
||||
inline void tms340x0_device::TMS34010_WRMEM_DWORD(offs_t A, uint32_t V)
|
||||
{
|
||||
m_program.write_word(A,V);
|
||||
m_program.write_word(A+16,V>>16);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* IO registers accessor */
|
||||
#define IOREG(reg) (m_IOregs[reg])
|
||||
#define SMART_IOREG(reg) (m_IOregs[m_is_34020 ? (int)REG020_##reg : (int)REG_##reg])
|
||||
@ -86,20 +68,16 @@ inline void tms340x0_device::TMS34010_WRMEM_DWORD(offs_t A, uint32_t V)
|
||||
}
|
||||
|
||||
#define WFIELDMAC_8() \
|
||||
if (offset & 0x07) \
|
||||
if (true) \
|
||||
{ \
|
||||
WFIELDMAC(0xff,9); \
|
||||
} \
|
||||
else \
|
||||
TMS34010_WRMEM(offset, data);
|
||||
}
|
||||
|
||||
#define RFIELDMAC_8() \
|
||||
if (offset & 0x07) \
|
||||
if (true) \
|
||||
{ \
|
||||
RFIELDMAC(0xff,9); \
|
||||
} \
|
||||
else \
|
||||
ret = TMS34010_RDMEM(offset);
|
||||
}
|
||||
|
||||
#define WFIELDMAC_32() \
|
||||
if (offset & 0x0f) \
|
||||
|
||||
@ -80,13 +80,13 @@ void tms340x0_device::unimpl(uint16_t op)
|
||||
{
|
||||
/* kludge for Super High Impact -- this doesn't seem to cause */
|
||||
/* an illegal opcode exception */
|
||||
if (m_cache.read_word(m_pc - 0x10) == 0x0007)
|
||||
if (space(AS_PROGRAM).read_word(m_pc - 0x10) == 0x0007)
|
||||
return;
|
||||
|
||||
/* 9 Ball Shootout calls to FFDF7468, expecting it */
|
||||
/* to execute the next instruction from FFDF7470 */
|
||||
/* but the instruction at FFDF7460 is an 0x0001 */
|
||||
if (m_cache.read_word(m_pc - 0x10) == 0x0001)
|
||||
if (space(AS_PROGRAM).read_word(m_pc - 0x10) == 0x0001)
|
||||
return;
|
||||
|
||||
PUSH(m_pc);
|
||||
@ -96,7 +96,7 @@ void tms340x0_device::unimpl(uint16_t op)
|
||||
COUNT_UNKNOWN_CYCLES(16);
|
||||
|
||||
/* extra check to prevent bad things */
|
||||
if (m_pc == 0 || s_opcode_table[m_cache.read_word(m_pc) >> 4] == &tms34010_device::unimpl)
|
||||
if (m_pc == 0 || s_opcode_table[space(AS_PROGRAM).read_word(m_pc) >> 4] == &tms34010_device::unimpl)
|
||||
{
|
||||
set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
|
||||
machine().debug_break();
|
||||
|
||||
@ -59,10 +59,10 @@ DEFINE_DEVICE_TYPE(TMS34020, tms34020_device, "tms34020", "Texas Instruments TMS
|
||||
GLOBAL VARIABLES
|
||||
***************************************************************************/
|
||||
|
||||
tms340x0_device::tms340x0_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor internal_regs_map)
|
||||
tms340x0_device::tms340x0_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor internal_regs_map, bool is_34020)
|
||||
: cpu_device(mconfig, type, tag, owner, clock)
|
||||
, device_video_interface(mconfig, *this)
|
||||
, m_program_config("program", ENDIANNESS_LITTLE, 16, 32, 3, internal_regs_map)
|
||||
, m_program_config("program", ENDIANNESS_LITTLE, is_34020 ? 32 : 16, 32, 3, internal_regs_map)
|
||||
, m_pc(0)
|
||||
, m_ppc(0)
|
||||
, m_st(0)
|
||||
@ -76,7 +76,7 @@ tms340x0_device::tms340x0_device(const machine_config &mconfig, device_type type
|
||||
, m_convmp(0)
|
||||
, m_gfxcycles(0)
|
||||
, m_pixelshift(0)
|
||||
, m_is_34020(0)
|
||||
, m_is_34020(is_34020)
|
||||
, m_reset_deferred(false)
|
||||
, m_halt_on_reset(false)
|
||||
, m_hblank_stable(0)
|
||||
@ -97,16 +97,14 @@ tms340x0_device::tms340x0_device(const machine_config &mconfig, device_type type
|
||||
|
||||
|
||||
tms34010_device::tms34010_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
|
||||
: tms340x0_device(mconfig, TMS34010, tag, owner, clock, address_map_constructor(FUNC(tms34010_device::internal_regs_map), this))
|
||||
: tms340x0_device(mconfig, TMS34010, tag, owner, clock, address_map_constructor(FUNC(tms34010_device::internal_regs_map), this), false)
|
||||
{
|
||||
m_is_34020 = 0;
|
||||
}
|
||||
|
||||
|
||||
tms34020_device::tms34020_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
|
||||
: tms340x0_device(mconfig, TMS34020, tag, owner, clock, address_map_constructor(FUNC(tms34020_device::internal_regs_map), this))
|
||||
: tms340x0_device(mconfig, TMS34020, tag, owner, clock, address_map_constructor(FUNC(tms34020_device::internal_regs_map), this), true)
|
||||
{
|
||||
m_is_34020 = 1;
|
||||
}
|
||||
|
||||
device_memory_interface::space_config_vector tms340x0_device::memory_space_config() const
|
||||
@ -230,38 +228,121 @@ inline void tms340x0_device::RESET_ST()
|
||||
}
|
||||
|
||||
/* shortcuts for reading opcodes */
|
||||
inline uint32_t tms340x0_device::ROPCODE()
|
||||
uint32_t tms34010_device::ROPCODE()
|
||||
{
|
||||
uint32_t pc = m_pc;
|
||||
m_pc += 2 << 3;
|
||||
return m_cache.read_word(pc);
|
||||
}
|
||||
|
||||
inline int16_t tms340x0_device::PARAM_WORD()
|
||||
uint32_t tms34020_device::ROPCODE()
|
||||
{
|
||||
uint32_t pc = m_pc;
|
||||
m_pc += 2 << 3;
|
||||
return m_cache.read_word(pc);
|
||||
}
|
||||
|
||||
inline int32_t tms340x0_device::PARAM_LONG()
|
||||
int16_t tms34010_device::PARAM_WORD()
|
||||
{
|
||||
uint32_t pc = m_pc;
|
||||
m_pc += 2 << 3;
|
||||
return m_cache.read_word(pc);
|
||||
}
|
||||
|
||||
int16_t tms34020_device::PARAM_WORD()
|
||||
{
|
||||
uint32_t pc = m_pc;
|
||||
m_pc += 2 << 3;
|
||||
return m_cache.read_word(pc);
|
||||
}
|
||||
|
||||
int32_t tms34010_device::PARAM_LONG()
|
||||
{
|
||||
uint32_t pc = m_pc;
|
||||
m_pc += 4 << 3;
|
||||
return (uint16_t)m_cache.read_word(pc) | (m_cache.read_word(pc + 16) << 16);
|
||||
}
|
||||
|
||||
inline int16_t tms340x0_device::PARAM_WORD_NO_INC()
|
||||
int32_t tms34020_device::PARAM_LONG()
|
||||
{
|
||||
uint32_t pc = m_pc;
|
||||
m_pc += 4 << 3;
|
||||
return m_cache.read_dword_unaligned(pc);
|
||||
}
|
||||
|
||||
int16_t tms34010_device::PARAM_WORD_NO_INC()
|
||||
{
|
||||
return m_cache.read_word(m_pc);
|
||||
}
|
||||
|
||||
inline int32_t tms340x0_device::PARAM_LONG_NO_INC()
|
||||
int16_t tms34020_device::PARAM_WORD_NO_INC()
|
||||
{
|
||||
return m_cache.read_word(m_pc);
|
||||
}
|
||||
|
||||
int32_t tms34010_device::PARAM_LONG_NO_INC()
|
||||
{
|
||||
uint32_t pc = m_pc;
|
||||
return (uint16_t)m_cache.read_word(pc) | (m_cache.read_word(pc + 16) << 16);
|
||||
}
|
||||
|
||||
int32_t tms34020_device::PARAM_LONG_NO_INC()
|
||||
{
|
||||
return m_cache.read_dword_unaligned(m_pc);
|
||||
}
|
||||
|
||||
uint32_t tms34010_device::TMS34010_RDMEM_WORD(offs_t A)
|
||||
{
|
||||
return m_program.read_word(A);
|
||||
}
|
||||
|
||||
uint32_t tms34020_device::TMS34010_RDMEM_WORD(offs_t A)
|
||||
{
|
||||
return m_program.read_word(A);
|
||||
}
|
||||
|
||||
uint32_t tms34010_device::TMS34010_RDMEM_DWORD(offs_t A)
|
||||
{
|
||||
uint32_t result = m_program.read_word(A);
|
||||
return result | (m_program.read_word(A+16)<<16);
|
||||
}
|
||||
|
||||
uint32_t tms34020_device::TMS34010_RDMEM_DWORD(offs_t A)
|
||||
{
|
||||
return m_program.read_dword_unaligned(A);
|
||||
}
|
||||
|
||||
void tms34010_device::TMS34010_WRMEM_WORD(offs_t A, uint32_t V)
|
||||
{
|
||||
m_program.write_word(A,V);
|
||||
}
|
||||
|
||||
void tms34020_device::TMS34010_WRMEM_WORD(offs_t A, uint32_t V)
|
||||
{
|
||||
if (BIT(A, 4))
|
||||
m_program.write_dword(A-16,(V<<16)|(V>>16),0xffff0000);
|
||||
else
|
||||
m_program.write_dword(A,V,0x0000ffff);
|
||||
}
|
||||
|
||||
void tms34010_device::TMS34010_WRMEM_DWORD(offs_t A, uint32_t V)
|
||||
{
|
||||
m_program.write_word(A,V);
|
||||
m_program.write_word(A+16,V>>16);
|
||||
}
|
||||
|
||||
void tms34020_device::TMS34010_WRMEM_DWORD(offs_t A, uint32_t V)
|
||||
{
|
||||
if (BIT(A, 4))
|
||||
{
|
||||
m_program.write_dword(A-16,(V<<16)|(V>>16),0xffff0000);
|
||||
m_program.write_dword(A+16,(V<<16)|(V>>16),0x0000ffff);
|
||||
}
|
||||
else
|
||||
m_program.write_dword(A,V);
|
||||
}
|
||||
|
||||
|
||||
/* read memory byte */
|
||||
inline uint32_t tms340x0_device::RBYTE(offs_t offset)
|
||||
{
|
||||
@ -331,7 +412,7 @@ uint32_t tms340x0_device::read_pixel_32(offs_t offset)
|
||||
uint32_t tms340x0_device::read_pixel_shiftreg(offs_t offset)
|
||||
{
|
||||
if (!m_to_shiftreg_cb.isnull())
|
||||
m_to_shiftreg_cb(m_program, offset, &m_shiftreg[0]);
|
||||
m_to_shiftreg_cb(offset, &m_shiftreg[0]);
|
||||
else
|
||||
fatalerror("To ShiftReg function not set. PC = %08X\n", m_pc);
|
||||
return m_shiftreg[0];
|
||||
@ -473,7 +554,7 @@ void tms340x0_device::write_pixel_r_t_32(offs_t offset, uint32_t data)
|
||||
void tms340x0_device::write_pixel_shiftreg(offs_t offset, uint32_t data)
|
||||
{
|
||||
if (!m_from_shiftreg_cb.isnull())
|
||||
m_from_shiftreg_cb(m_program, offset, &m_shiftreg[0]);
|
||||
m_from_shiftreg_cb(offset, &m_shiftreg[0]);
|
||||
else
|
||||
fatalerror("From ShiftReg function not set. PC = %08X\n", m_pc);
|
||||
}
|
||||
@ -640,9 +721,6 @@ void tms340x0_device::device_start()
|
||||
|
||||
m_external_host_access = false;
|
||||
|
||||
space(AS_PROGRAM).cache(m_cache);
|
||||
space(AS_PROGRAM).specific(m_program);
|
||||
|
||||
/* set up the state table */
|
||||
{
|
||||
state_add(TMS34010_PC, "PC", m_pc);
|
||||
@ -682,6 +760,22 @@ void tms340x0_device::device_start()
|
||||
set_icountptr(m_icount);
|
||||
}
|
||||
|
||||
void tms34010_device::device_start()
|
||||
{
|
||||
tms340x0_device::device_start();
|
||||
|
||||
space(AS_PROGRAM).cache(m_cache);
|
||||
space(AS_PROGRAM).specific(m_program);
|
||||
}
|
||||
|
||||
void tms34020_device::device_start()
|
||||
{
|
||||
tms340x0_device::device_start();
|
||||
|
||||
space(AS_PROGRAM).cache(m_cache);
|
||||
space(AS_PROGRAM).specific(m_program);
|
||||
}
|
||||
|
||||
void tms340x0_device::device_reset()
|
||||
{
|
||||
m_ppc = 0;
|
||||
|
||||
@ -105,8 +105,8 @@ enum
|
||||
|
||||
#define TMS340X0_SCANLINE_IND16_CB_MEMBER(_name) void _name(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms340x0_device::display_params *params)
|
||||
#define TMS340X0_SCANLINE_RGB32_CB_MEMBER(_name) void _name(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms340x0_device::display_params *params)
|
||||
#define TMS340X0_TO_SHIFTREG_CB_MEMBER(_name) void _name(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t address, uint16_t *shiftreg)
|
||||
#define TMS340X0_FROM_SHIFTREG_CB_MEMBER(_name) void _name(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t address, uint16_t *shiftreg)
|
||||
#define TMS340X0_TO_SHIFTREG_CB_MEMBER(_name) void _name(offs_t address, uint16_t *shiftreg)
|
||||
#define TMS340X0_FROM_SHIFTREG_CB_MEMBER(_name) void _name(offs_t address, uint16_t *shiftreg)
|
||||
|
||||
|
||||
class tms340x0_device : public cpu_device,
|
||||
@ -126,8 +126,8 @@ public:
|
||||
|
||||
typedef device_delegate<void (screen_device &screen, bitmap_ind16 &bitmap, int scanline, const display_params *params)> scanline_ind16_cb_delegate;
|
||||
typedef device_delegate<void (screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const display_params *params)> scanline_rgb32_cb_delegate;
|
||||
typedef device_delegate<void (memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t address, uint16_t *shiftreg)> shiftreg_in_cb_delegate;
|
||||
typedef device_delegate<void (memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t address, uint16_t *shiftreg)> shiftreg_out_cb_delegate;
|
||||
typedef device_delegate<void (offs_t address, uint16_t *shiftreg)> shiftreg_in_cb_delegate;
|
||||
typedef device_delegate<void (offs_t address, uint16_t *shiftreg)> shiftreg_out_cb_delegate;
|
||||
|
||||
void set_halt_on_reset(bool halt_on_reset) { m_halt_on_reset = halt_on_reset; }
|
||||
void set_pixel_clock(uint32_t pixclock) { m_pixclock = pixclock; }
|
||||
@ -252,7 +252,7 @@ protected:
|
||||
};
|
||||
|
||||
// construction/destruction
|
||||
tms340x0_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor internal_regs_map = address_map_constructor());
|
||||
tms340x0_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor internal_regs_map, bool is_34020);
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start() override;
|
||||
@ -281,8 +281,8 @@ protected:
|
||||
typedef uint32_t (tms340x0_device::*pixel_op_func)(uint32_t, uint32_t, uint32_t);
|
||||
typedef void (tms340x0_device::*pixblt_op_func)(int, int);
|
||||
typedef void (tms340x0_device::*pixblt_b_op_func)(int);
|
||||
typedef void (tms340x0_device::*word_write_func)(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t offset,uint16_t data);
|
||||
typedef uint16_t (tms340x0_device::*word_read_func)(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t offset);
|
||||
typedef void (tms340x0_device::*word_write_func)(offs_t offset, uint16_t data);
|
||||
typedef uint16_t (tms340x0_device::*word_read_func)(offs_t offset);
|
||||
|
||||
static const wfield_func s_wfield_functions[32];
|
||||
static const rfield_func s_rfield_functions[64];
|
||||
@ -312,14 +312,13 @@ protected:
|
||||
uint32_t m_convmp;
|
||||
int32_t m_gfxcycles;
|
||||
uint8_t m_pixelshift;
|
||||
uint8_t m_is_34020;
|
||||
const bool m_is_34020;
|
||||
bool m_reset_deferred;
|
||||
bool m_halt_on_reset; /* /HCS pin, which determines HALT state after reset */
|
||||
uint8_t m_hblank_stable;
|
||||
uint8_t m_external_host_access;
|
||||
uint8_t m_executing;
|
||||
memory_access<32, 1, 3, ENDIANNESS_LITTLE>::cache m_cache;
|
||||
memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific m_program;
|
||||
|
||||
uint32_t m_pixclock; /* the pixel clock (0 means don't adjust screen size) */
|
||||
int m_pixperclock; /* pixels per clock */
|
||||
emu_timer *m_scantimer;
|
||||
@ -354,15 +353,18 @@ protected:
|
||||
uint16_t m_IOregs[64];
|
||||
uint16_t m_shiftreg[(8 * 512 * sizeof(uint16_t))/2];
|
||||
|
||||
uint32_t TMS34010_RDMEM_DWORD(offs_t A);
|
||||
void TMS34010_WRMEM_DWORD(offs_t A, uint32_t V);
|
||||
|
||||
virtual uint32_t TMS34010_RDMEM_WORD(offs_t A) = 0;
|
||||
virtual uint32_t TMS34010_RDMEM_DWORD(offs_t A) = 0;
|
||||
virtual void TMS34010_WRMEM_WORD(offs_t A, uint32_t V) = 0;
|
||||
virtual void TMS34010_WRMEM_DWORD(offs_t A, uint32_t V) = 0;
|
||||
void SET_ST(uint32_t st);
|
||||
void RESET_ST();
|
||||
uint32_t ROPCODE();
|
||||
int16_t PARAM_WORD();
|
||||
int32_t PARAM_LONG();
|
||||
int16_t PARAM_WORD_NO_INC();
|
||||
int32_t PARAM_LONG_NO_INC();
|
||||
virtual uint32_t ROPCODE() = 0;
|
||||
virtual int16_t PARAM_WORD() = 0;
|
||||
virtual int32_t PARAM_LONG() = 0;
|
||||
virtual int16_t PARAM_WORD_NO_INC() = 0;
|
||||
virtual int32_t PARAM_LONG_NO_INC() = 0;
|
||||
uint32_t RBYTE(offs_t offset);
|
||||
void WBYTE(offs_t offset, uint32_t data);
|
||||
uint32_t RLONG(offs_t offset);
|
||||
@ -892,11 +894,11 @@ protected:
|
||||
int compute_fill_cycles(int left_partials, int right_partials, int full_words, int op_timing);
|
||||
int compute_pixblt_cycles(int left_partials, int right_partials, int full_words, int op_timing);
|
||||
int compute_pixblt_b_cycles(int left_partials, int right_partials, int full_words, int rows, int op_timing, int bpp);
|
||||
void memory_w(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t offset,uint16_t data);
|
||||
uint16_t memory_r(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t offset);
|
||||
void shiftreg_w(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t offset, uint16_t data);
|
||||
uint16_t shiftreg_r(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t offset);
|
||||
uint16_t dummy_shiftreg_r(memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific &space, offs_t offset);
|
||||
void memory_w(offs_t offset, uint16_t data);
|
||||
uint16_t memory_r(offs_t offset);
|
||||
void shiftreg_w(offs_t offset, uint16_t data);
|
||||
uint16_t shiftreg_r(offs_t offset);
|
||||
uint16_t dummy_shiftreg_r(offs_t offset);
|
||||
uint32_t pixel_op00(uint32_t dstpix, uint32_t mask, uint32_t srcpix);
|
||||
uint32_t pixel_op01(uint32_t dstpix, uint32_t mask, uint32_t srcpix);
|
||||
uint32_t pixel_op02(uint32_t dstpix, uint32_t mask, uint32_t srcpix);
|
||||
@ -1016,10 +1018,27 @@ public:
|
||||
virtual u16 io_register_r(offs_t offset) override;
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start() override;
|
||||
|
||||
virtual uint64_t execute_clocks_to_cycles(uint64_t clocks) const noexcept override { return (clocks + 8 - 1) / 8; }
|
||||
virtual uint64_t execute_cycles_to_clocks(uint64_t cycles) const noexcept override { return (cycles * 8); }
|
||||
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
|
||||
void internal_regs_map(address_map &map);
|
||||
|
||||
virtual uint32_t ROPCODE() override;
|
||||
virtual int16_t PARAM_WORD() override;
|
||||
virtual int32_t PARAM_LONG() override;
|
||||
virtual int16_t PARAM_WORD_NO_INC() override;
|
||||
virtual int32_t PARAM_LONG_NO_INC() override;
|
||||
virtual uint32_t TMS34010_RDMEM_WORD(offs_t A) override;
|
||||
virtual uint32_t TMS34010_RDMEM_DWORD(offs_t A) override;
|
||||
virtual void TMS34010_WRMEM_WORD(offs_t A, uint32_t V) override;
|
||||
virtual void TMS34010_WRMEM_DWORD(offs_t A, uint32_t V) override;
|
||||
|
||||
private:
|
||||
memory_access<32, 1, 3, ENDIANNESS_LITTLE>::cache m_cache;
|
||||
memory_access<32, 1, 3, ENDIANNESS_LITTLE>::specific m_program;
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(TMS34010, tms34010_device)
|
||||
@ -1034,10 +1053,27 @@ public:
|
||||
virtual u16 io_register_r(offs_t offset) override;
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start() override;
|
||||
|
||||
virtual uint64_t execute_clocks_to_cycles(uint64_t clocks) const noexcept override { return (clocks + 4 - 1) / 4; }
|
||||
virtual uint64_t execute_cycles_to_clocks(uint64_t cycles) const noexcept override { return (cycles * 4); }
|
||||
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
|
||||
void internal_regs_map(address_map &map);
|
||||
|
||||
virtual uint32_t ROPCODE() override;
|
||||
virtual int16_t PARAM_WORD() override;
|
||||
virtual int32_t PARAM_LONG() override;
|
||||
virtual int16_t PARAM_WORD_NO_INC() override;
|
||||
virtual int32_t PARAM_LONG_NO_INC() override;
|
||||
virtual uint32_t TMS34010_RDMEM_WORD(offs_t A) override;
|
||||
virtual uint32_t TMS34010_RDMEM_DWORD(offs_t A) override;
|
||||
virtual void TMS34010_WRMEM_WORD(offs_t A, uint32_t V) override;
|
||||
virtual void TMS34010_WRMEM_DWORD(offs_t A, uint32_t V) override;
|
||||
|
||||
private:
|
||||
memory_access<32, 2, 3, ENDIANNESS_LITTLE>::cache m_cache;
|
||||
memory_access<32, 2, 3, ENDIANNESS_LITTLE>::specific m_program;
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(TMS34020, tms34020_device)
|
||||
|
||||
@ -940,6 +940,11 @@ void memory_manager::allocate(device_memory_interface &memory)
|
||||
case 0x0000|0x100|16|(4-1): memory.allocate<address_space_specific<1, 1, -1, ENDIANNESS_LITTLE>>(*this, spacenum); break;
|
||||
case 0x1000|0x100|16|(4-1): memory.allocate<address_space_specific<1, 1, -1, ENDIANNESS_BIG >>(*this, spacenum); break;
|
||||
|
||||
case 0x0000|0x000|32|(4+3): memory.allocate<address_space_specific<0, 2, 3, ENDIANNESS_LITTLE>>(*this, spacenum); break;
|
||||
case 0x1000|0x000|32|(4+3): memory.allocate<address_space_specific<0, 2, 3, ENDIANNESS_BIG >>(*this, spacenum); break;
|
||||
case 0x0000|0x100|32|(4+3): memory.allocate<address_space_specific<1, 2, 3, ENDIANNESS_LITTLE>>(*this, spacenum); break;
|
||||
case 0x1000|0x100|32|(4+3): memory.allocate<address_space_specific<1, 2, 3, ENDIANNESS_BIG >>(*this, spacenum); break;
|
||||
|
||||
case 0x0000|0x000|32|(4-0): memory.allocate<address_space_specific<0, 2, 0, ENDIANNESS_LITTLE>>(*this, spacenum); break;
|
||||
case 0x1000|0x000|32|(4-0): memory.allocate<address_space_specific<0, 2, 0, ENDIANNESS_BIG >>(*this, spacenum); break;
|
||||
case 0x0000|0x100|32|(4-0): memory.allocate<address_space_specific<1, 2, 0, ENDIANNESS_LITTLE>>(*this, spacenum); break;
|
||||
|
||||
@ -180,6 +180,8 @@ template class handler_entry_read_delegate<1, 0, ENDIANNESS_LITTLE, read16_dele
|
||||
template class handler_entry_read_delegate<1, 0, ENDIANNESS_BIG, read16_delegate>;
|
||||
template class handler_entry_read_delegate<1, -1, ENDIANNESS_LITTLE, read16_delegate>;
|
||||
template class handler_entry_read_delegate<1, -1, ENDIANNESS_BIG, read16_delegate>;
|
||||
template class handler_entry_read_delegate<2, 3, ENDIANNESS_LITTLE, read32_delegate>;
|
||||
template class handler_entry_read_delegate<2, 3, ENDIANNESS_BIG, read32_delegate>;
|
||||
template class handler_entry_read_delegate<2, 0, ENDIANNESS_LITTLE, read32_delegate>;
|
||||
template class handler_entry_read_delegate<2, 0, ENDIANNESS_BIG, read32_delegate>;
|
||||
template class handler_entry_read_delegate<2, -1, ENDIANNESS_LITTLE, read32_delegate>;
|
||||
@ -205,6 +207,8 @@ template class handler_entry_read_delegate<1, 0, ENDIANNESS_LITTLE, read16m_del
|
||||
template class handler_entry_read_delegate<1, 0, ENDIANNESS_BIG, read16m_delegate>;
|
||||
template class handler_entry_read_delegate<1, -1, ENDIANNESS_LITTLE, read16m_delegate>;
|
||||
template class handler_entry_read_delegate<1, -1, ENDIANNESS_BIG, read16m_delegate>;
|
||||
template class handler_entry_read_delegate<2, 3, ENDIANNESS_LITTLE, read32m_delegate>;
|
||||
template class handler_entry_read_delegate<2, 3, ENDIANNESS_BIG, read32m_delegate>;
|
||||
template class handler_entry_read_delegate<2, 0, ENDIANNESS_LITTLE, read32m_delegate>;
|
||||
template class handler_entry_read_delegate<2, 0, ENDIANNESS_BIG, read32m_delegate>;
|
||||
template class handler_entry_read_delegate<2, -1, ENDIANNESS_LITTLE, read32m_delegate>;
|
||||
@ -230,6 +234,8 @@ template class handler_entry_read_delegate<1, 0, ENDIANNESS_LITTLE, read16s_del
|
||||
template class handler_entry_read_delegate<1, 0, ENDIANNESS_BIG, read16s_delegate>;
|
||||
template class handler_entry_read_delegate<1, -1, ENDIANNESS_LITTLE, read16s_delegate>;
|
||||
template class handler_entry_read_delegate<1, -1, ENDIANNESS_BIG, read16s_delegate>;
|
||||
template class handler_entry_read_delegate<2, 3, ENDIANNESS_LITTLE, read32s_delegate>;
|
||||
template class handler_entry_read_delegate<2, 3, ENDIANNESS_BIG, read32s_delegate>;
|
||||
template class handler_entry_read_delegate<2, 0, ENDIANNESS_LITTLE, read32s_delegate>;
|
||||
template class handler_entry_read_delegate<2, 0, ENDIANNESS_BIG, read32s_delegate>;
|
||||
template class handler_entry_read_delegate<2, -1, ENDIANNESS_LITTLE, read32s_delegate>;
|
||||
@ -255,6 +261,8 @@ template class handler_entry_read_delegate<1, 0, ENDIANNESS_LITTLE, read16sm_de
|
||||
template class handler_entry_read_delegate<1, 0, ENDIANNESS_BIG, read16sm_delegate>;
|
||||
template class handler_entry_read_delegate<1, -1, ENDIANNESS_LITTLE, read16sm_delegate>;
|
||||
template class handler_entry_read_delegate<1, -1, ENDIANNESS_BIG, read16sm_delegate>;
|
||||
template class handler_entry_read_delegate<2, 3, ENDIANNESS_LITTLE, read32sm_delegate>;
|
||||
template class handler_entry_read_delegate<2, 3, ENDIANNESS_BIG, read32sm_delegate>;
|
||||
template class handler_entry_read_delegate<2, 0, ENDIANNESS_LITTLE, read32sm_delegate>;
|
||||
template class handler_entry_read_delegate<2, 0, ENDIANNESS_BIG, read32sm_delegate>;
|
||||
template class handler_entry_read_delegate<2, -1, ENDIANNESS_LITTLE, read32sm_delegate>;
|
||||
@ -280,6 +288,8 @@ template class handler_entry_read_delegate<1, 0, ENDIANNESS_LITTLE, read16mo_de
|
||||
template class handler_entry_read_delegate<1, 0, ENDIANNESS_BIG, read16mo_delegate>;
|
||||
template class handler_entry_read_delegate<1, -1, ENDIANNESS_LITTLE, read16mo_delegate>;
|
||||
template class handler_entry_read_delegate<1, -1, ENDIANNESS_BIG, read16mo_delegate>;
|
||||
template class handler_entry_read_delegate<2, 3, ENDIANNESS_LITTLE, read32mo_delegate>;
|
||||
template class handler_entry_read_delegate<2, 3, ENDIANNESS_BIG, read32mo_delegate>;
|
||||
template class handler_entry_read_delegate<2, 0, ENDIANNESS_LITTLE, read32mo_delegate>;
|
||||
template class handler_entry_read_delegate<2, 0, ENDIANNESS_BIG, read32mo_delegate>;
|
||||
template class handler_entry_read_delegate<2, -1, ENDIANNESS_LITTLE, read32mo_delegate>;
|
||||
@ -305,6 +315,8 @@ template class handler_entry_read_delegate<1, 0, ENDIANNESS_LITTLE, read16smo_d
|
||||
template class handler_entry_read_delegate<1, 0, ENDIANNESS_BIG, read16smo_delegate>;
|
||||
template class handler_entry_read_delegate<1, -1, ENDIANNESS_LITTLE, read16smo_delegate>;
|
||||
template class handler_entry_read_delegate<1, -1, ENDIANNESS_BIG, read16smo_delegate>;
|
||||
template class handler_entry_read_delegate<2, 3, ENDIANNESS_LITTLE, read32smo_delegate>;
|
||||
template class handler_entry_read_delegate<2, 3, ENDIANNESS_BIG, read32smo_delegate>;
|
||||
template class handler_entry_read_delegate<2, 0, ENDIANNESS_LITTLE, read32smo_delegate>;
|
||||
template class handler_entry_read_delegate<2, 0, ENDIANNESS_BIG, read32smo_delegate>;
|
||||
template class handler_entry_read_delegate<2, -1, ENDIANNESS_LITTLE, read32smo_delegate>;
|
||||
@ -330,6 +342,8 @@ template class handler_entry_write_delegate<1, 0, ENDIANNESS_LITTLE, write16_de
|
||||
template class handler_entry_write_delegate<1, 0, ENDIANNESS_BIG, write16_delegate>;
|
||||
template class handler_entry_write_delegate<1, -1, ENDIANNESS_LITTLE, write16_delegate>;
|
||||
template class handler_entry_write_delegate<1, -1, ENDIANNESS_BIG, write16_delegate>;
|
||||
template class handler_entry_write_delegate<2, 3, ENDIANNESS_LITTLE, write32_delegate>;
|
||||
template class handler_entry_write_delegate<2, 3, ENDIANNESS_BIG, write32_delegate>;
|
||||
template class handler_entry_write_delegate<2, 0, ENDIANNESS_LITTLE, write32_delegate>;
|
||||
template class handler_entry_write_delegate<2, 0, ENDIANNESS_BIG, write32_delegate>;
|
||||
template class handler_entry_write_delegate<2, -1, ENDIANNESS_LITTLE, write32_delegate>;
|
||||
@ -355,6 +369,8 @@ template class handler_entry_write_delegate<1, 0, ENDIANNESS_LITTLE, write16m_d
|
||||
template class handler_entry_write_delegate<1, 0, ENDIANNESS_BIG, write16m_delegate>;
|
||||
template class handler_entry_write_delegate<1, -1, ENDIANNESS_LITTLE, write16m_delegate>;
|
||||
template class handler_entry_write_delegate<1, -1, ENDIANNESS_BIG, write16m_delegate>;
|
||||
template class handler_entry_write_delegate<2, 3, ENDIANNESS_LITTLE, write32m_delegate>;
|
||||
template class handler_entry_write_delegate<2, 3, ENDIANNESS_BIG, write32m_delegate>;
|
||||
template class handler_entry_write_delegate<2, 0, ENDIANNESS_LITTLE, write32m_delegate>;
|
||||
template class handler_entry_write_delegate<2, 0, ENDIANNESS_BIG, write32m_delegate>;
|
||||
template class handler_entry_write_delegate<2, -1, ENDIANNESS_LITTLE, write32m_delegate>;
|
||||
@ -380,6 +396,8 @@ template class handler_entry_write_delegate<1, 0, ENDIANNESS_LITTLE, write16s_d
|
||||
template class handler_entry_write_delegate<1, 0, ENDIANNESS_BIG, write16s_delegate>;
|
||||
template class handler_entry_write_delegate<1, -1, ENDIANNESS_LITTLE, write16s_delegate>;
|
||||
template class handler_entry_write_delegate<1, -1, ENDIANNESS_BIG, write16s_delegate>;
|
||||
template class handler_entry_write_delegate<2, 3, ENDIANNESS_LITTLE, write32s_delegate>;
|
||||
template class handler_entry_write_delegate<2, 3, ENDIANNESS_BIG, write32s_delegate>;
|
||||
template class handler_entry_write_delegate<2, 0, ENDIANNESS_LITTLE, write32s_delegate>;
|
||||
template class handler_entry_write_delegate<2, 0, ENDIANNESS_BIG, write32s_delegate>;
|
||||
template class handler_entry_write_delegate<2, -1, ENDIANNESS_LITTLE, write32s_delegate>;
|
||||
@ -405,6 +423,8 @@ template class handler_entry_write_delegate<1, 0, ENDIANNESS_LITTLE, write16sm_
|
||||
template class handler_entry_write_delegate<1, 0, ENDIANNESS_BIG, write16sm_delegate>;
|
||||
template class handler_entry_write_delegate<1, -1, ENDIANNESS_LITTLE, write16sm_delegate>;
|
||||
template class handler_entry_write_delegate<1, -1, ENDIANNESS_BIG, write16sm_delegate>;
|
||||
template class handler_entry_write_delegate<2, 3, ENDIANNESS_LITTLE, write32sm_delegate>;
|
||||
template class handler_entry_write_delegate<2, 3, ENDIANNESS_BIG, write32sm_delegate>;
|
||||
template class handler_entry_write_delegate<2, 0, ENDIANNESS_LITTLE, write32sm_delegate>;
|
||||
template class handler_entry_write_delegate<2, 0, ENDIANNESS_BIG, write32sm_delegate>;
|
||||
template class handler_entry_write_delegate<2, -1, ENDIANNESS_LITTLE, write32sm_delegate>;
|
||||
@ -430,6 +450,8 @@ template class handler_entry_write_delegate<1, 0, ENDIANNESS_LITTLE, write16mo_
|
||||
template class handler_entry_write_delegate<1, 0, ENDIANNESS_BIG, write16mo_delegate>;
|
||||
template class handler_entry_write_delegate<1, -1, ENDIANNESS_LITTLE, write16mo_delegate>;
|
||||
template class handler_entry_write_delegate<1, -1, ENDIANNESS_BIG, write16mo_delegate>;
|
||||
template class handler_entry_write_delegate<2, 3, ENDIANNESS_LITTLE, write32mo_delegate>;
|
||||
template class handler_entry_write_delegate<2, 3, ENDIANNESS_BIG, write32mo_delegate>;
|
||||
template class handler_entry_write_delegate<2, 0, ENDIANNESS_LITTLE, write32mo_delegate>;
|
||||
template class handler_entry_write_delegate<2, 0, ENDIANNESS_BIG, write32mo_delegate>;
|
||||
template class handler_entry_write_delegate<2, -1, ENDIANNESS_LITTLE, write32mo_delegate>;
|
||||
@ -455,6 +477,8 @@ template class handler_entry_write_delegate<1, 0, ENDIANNESS_LITTLE, write16smo
|
||||
template class handler_entry_write_delegate<1, 0, ENDIANNESS_BIG, write16smo_delegate>;
|
||||
template class handler_entry_write_delegate<1, -1, ENDIANNESS_LITTLE, write16smo_delegate>;
|
||||
template class handler_entry_write_delegate<1, -1, ENDIANNESS_BIG, write16smo_delegate>;
|
||||
template class handler_entry_write_delegate<2, 3, ENDIANNESS_LITTLE, write32smo_delegate>;
|
||||
template class handler_entry_write_delegate<2, 3, ENDIANNESS_BIG, write32smo_delegate>;
|
||||
template class handler_entry_write_delegate<2, 0, ENDIANNESS_LITTLE, write32smo_delegate>;
|
||||
template class handler_entry_write_delegate<2, 0, ENDIANNESS_BIG, write32smo_delegate>;
|
||||
template class handler_entry_write_delegate<2, -1, ENDIANNESS_LITTLE, write32smo_delegate>;
|
||||
@ -481,6 +505,8 @@ template class handler_entry_read_ioport<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_ioport<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_ioport<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_ioport<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_ioport<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_ioport<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_ioport<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_ioport<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_ioport<2, -1, ENDIANNESS_LITTLE>;
|
||||
@ -506,6 +532,8 @@ template class handler_entry_write_ioport<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_ioport<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_ioport<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_ioport<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_ioport<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_ioport<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_ioport<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_ioport<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_ioport<2, -1, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -90,6 +90,21 @@ template class handler_entry_read_dispatch< 7, 1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch< 8, 1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch< 8, 1, -1, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_read_dispatch< 2, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch< 2, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch< 3, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch< 3, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch< 4, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch< 4, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch< 5, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch< 5, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch< 6, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch< 6, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch< 7, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch< 7, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch< 8, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch< 8, 2, 3, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_read_dispatch< 2, 2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch< 2, 2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch< 3, 2, 0, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -89,6 +89,23 @@ template class handler_entry_read_dispatch<15, 1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<16, 1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<16, 1, -1, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_read_dispatch< 9, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch< 9, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<10, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<10, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<11, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<11, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<12, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<12, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<13, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<13, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<14, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<14, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<15, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<15, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<16, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<16, 2, 3, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_read_dispatch< 9, 2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch< 9, 2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<10, 2, 0, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -89,6 +89,23 @@ template class handler_entry_read_dispatch<23, 1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<24, 1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<24, 1, -1, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_read_dispatch<17, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<17, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<18, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<18, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<19, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<19, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<20, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<20, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<21, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<21, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<22, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<22, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<23, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<23, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<24, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<24, 2, 3, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_read_dispatch<17, 2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<17, 2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<18, 2, 0, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -90,6 +90,23 @@ template class handler_entry_read_dispatch<30, 1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<32, 1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<32, 1, -1, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_read_dispatch<25, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<25, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<26, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<26, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<27, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<27, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<28, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<28, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<29, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<29, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<31, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<31, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<30, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<30, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<32, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<32, 2, 3, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_read_dispatch<25, 2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_dispatch<25, 2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_dispatch<26, 2, 0, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -90,6 +90,21 @@ template class handler_entry_write_dispatch< 7, 1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch< 8, 1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch< 8, 1, -1, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_write_dispatch< 2, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch< 2, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch< 3, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch< 3, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch< 4, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch< 4, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch< 5, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch< 5, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch< 6, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch< 6, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch< 7, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch< 7, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch< 8, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch< 8, 2, 3, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_write_dispatch< 2, 2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch< 2, 2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch< 3, 2, 0, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -89,6 +89,23 @@ template class handler_entry_write_dispatch<15, 1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<16, 1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<16, 1, -1, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_write_dispatch< 9, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch< 9, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<10, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<10, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<11, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<11, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<12, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<12, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<13, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<13, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<14, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<14, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<15, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<15, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<16, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<16, 2, 3, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_write_dispatch< 9, 2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch< 9, 2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<10, 2, 0, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -89,6 +89,23 @@ template class handler_entry_write_dispatch<23, 1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<24, 1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<24, 1, -1, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_write_dispatch<17, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<17, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<18, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<18, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<19, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<19, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<20, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<20, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<21, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<21, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<22, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<22, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<23, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<23, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<24, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<24, 2, 3, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_write_dispatch<17, 2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<17, 2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<18, 2, 0, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -90,6 +90,23 @@ template class handler_entry_write_dispatch<30, 1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<32, 1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<32, 1, -1, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_write_dispatch<25, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<25, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<26, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<26, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<27, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<27, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<28, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<28, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<29, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<29, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<31, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<31, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<30, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<30, 2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<32, 2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<32, 2, 3, ENDIANNESS_BIG>;
|
||||
|
||||
template class handler_entry_write_dispatch<25, 2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_dispatch<25, 2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_dispatch<26, 2, 0, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -105,6 +105,8 @@ template class handler_entry_read_memory<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_memory<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_memory<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_memory<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_memory<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_memory<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_memory<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_memory<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_memory<2, -1, ENDIANNESS_LITTLE>;
|
||||
@ -130,6 +132,8 @@ template class handler_entry_write_memory<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_memory<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_memory<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_memory<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_memory<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_memory<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_memory<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_memory<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_memory<2, -1, ENDIANNESS_LITTLE>;
|
||||
@ -156,6 +160,8 @@ template class handler_entry_read_memory_bank<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_memory_bank<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_memory_bank<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_memory_bank<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_memory_bank<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_memory_bank<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_memory_bank<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_memory_bank<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_memory_bank<2, -1, ENDIANNESS_LITTLE>;
|
||||
@ -181,6 +187,8 @@ template class handler_entry_write_memory_bank<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_memory_bank<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_memory_bank<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_memory_bank<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_memory_bank<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_memory_bank<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_memory_bank<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_memory_bank<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_memory_bank<2, -1, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -60,6 +60,8 @@ template class handler_entry_read_passthrough<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_passthrough<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_passthrough<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_passthrough<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_passthrough<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_passthrough<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_passthrough<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_passthrough<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_passthrough<2, -1, ENDIANNESS_LITTLE>;
|
||||
@ -85,6 +87,8 @@ template class handler_entry_write_passthrough<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_passthrough<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_passthrough<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_passthrough<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_passthrough<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_passthrough<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_passthrough<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_passthrough<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_passthrough<2, -1, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -60,6 +60,8 @@ template class handler_entry_read_tap<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_tap<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_tap<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_tap<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_tap<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_tap<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_tap<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_tap<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_tap<2, -1, ENDIANNESS_LITTLE>;
|
||||
@ -85,6 +87,8 @@ template class handler_entry_write_tap<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_tap<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_tap<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_tap<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_tap<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_tap<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_tap<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_tap<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_tap<2, -1, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -248,6 +248,8 @@ template class handler_entry_read_units<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_units<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_units<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_units<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_units<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_units<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_units<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_units<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_units<2, -1, ENDIANNESS_LITTLE>;
|
||||
@ -273,6 +275,8 @@ template class handler_entry_write_units<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_units<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_units<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_units<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_units<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_units<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_units<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_units<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_units<2, -1, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -74,6 +74,8 @@ template class handler_entry_read_unmapped<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_unmapped<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_unmapped<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_unmapped<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_unmapped<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_unmapped<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_unmapped<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_unmapped<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_unmapped<2, -1, ENDIANNESS_LITTLE>;
|
||||
@ -99,6 +101,8 @@ template class handler_entry_write_unmapped<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_unmapped<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_unmapped<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_unmapped<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_unmapped<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_unmapped<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_unmapped<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_unmapped<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_unmapped<2, -1, ENDIANNESS_LITTLE>;
|
||||
@ -125,6 +129,8 @@ template class handler_entry_read_nop<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_nop<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_nop<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_nop<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_nop<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_nop<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_nop<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_read_nop<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_read_nop<2, -1, ENDIANNESS_LITTLE>;
|
||||
@ -150,6 +156,8 @@ template class handler_entry_write_nop<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_nop<1, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_nop<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_nop<1, -1, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_nop<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_nop<2, 3, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_nop<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class handler_entry_write_nop<2, 0, ENDIANNESS_BIG>;
|
||||
template class handler_entry_write_nop<2, -1, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -116,6 +116,8 @@ template class memory_units_descriptor<1, 0, ENDIANNESS_LITTLE>;
|
||||
template class memory_units_descriptor<1, 0, ENDIANNESS_BIG>;
|
||||
template class memory_units_descriptor<1, -1, ENDIANNESS_LITTLE>;
|
||||
template class memory_units_descriptor<1, -1, ENDIANNESS_BIG>;
|
||||
template class memory_units_descriptor<2, 3, ENDIANNESS_LITTLE>;
|
||||
template class memory_units_descriptor<2, 3, ENDIANNESS_BIG>;
|
||||
template class memory_units_descriptor<2, 0, ENDIANNESS_LITTLE>;
|
||||
template class memory_units_descriptor<2, 0, ENDIANNESS_BIG>;
|
||||
template class memory_units_descriptor<2, -1, ENDIANNESS_LITTLE>;
|
||||
|
||||
@ -359,7 +359,7 @@ private:
|
||||
required_device<tms34020_device> m_videocpu;
|
||||
required_device<ramdac_device> m_ramdac;
|
||||
|
||||
required_shared_ptr<uint16_t> m_vidram;
|
||||
required_shared_ptr<uint32_t> m_vidram;
|
||||
|
||||
TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
|
||||
TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
|
||||
@ -422,17 +422,19 @@ TMS340X0_FROM_SHIFTREG_CB_MEMBER(atronic_state::from_shiftreg)
|
||||
|
||||
TMS340X0_SCANLINE_RGB32_CB_MEMBER(atronic_state::scanline_update)
|
||||
{
|
||||
uint32_t fulladdr = ((params->rowaddr << 16) | params->coladdr) >> 4;
|
||||
uint16_t* bg0_base = &m_vidram[(fulladdr & 0xffc00)]; // this probably isn't screen ram, but some temp gfx are copied on startup
|
||||
uint32_t fulladdr = ((params->rowaddr << 16) | params->coladdr) >> 5;
|
||||
uint32_t* bg0_base = &m_vidram[(fulladdr & 0x7fe00)]; // this probably isn't screen ram, but some temp gfx are copied on startup
|
||||
uint32_t* dst = &bitmap.pix32(scanline);
|
||||
int coladdr = fulladdr & 0x3ff;
|
||||
int coladdr = fulladdr & 0x1ff;
|
||||
const pen_t *pens = m_palette->pens();
|
||||
|
||||
for (int x = params->heblnk; x < params->hsblnk; x += 2, coladdr++)
|
||||
for (int x = params->heblnk; x < params->hsblnk; x += 4, coladdr++)
|
||||
{
|
||||
uint16_t bg0pix = bg0_base[coladdr & 0x3ff];
|
||||
dst[x + 0] = pens[(bg0pix & 0x00ff)];
|
||||
dst[x + 1] = pens[(bg0pix & 0xff00) >> 8];
|
||||
uint32_t bg0pix = bg0_base[coladdr & 0x1ff];
|
||||
dst[x + 0] = pens[(bg0pix & 0x000000ff)];
|
||||
dst[x + 1] = pens[(bg0pix & 0x0000ff00) >> 8];
|
||||
dst[x + 2] = pens[(bg0pix & 0x00ff0000) >> 16];
|
||||
dst[x + 3] = pens[(bg0pix & 0xff000000) >> 24];
|
||||
}
|
||||
}
|
||||
|
||||
@ -440,9 +442,9 @@ void atronic_state::video_map(address_map &map)
|
||||
{
|
||||
map(0x00000000, 0x01ffffff).ram().share("vidram");
|
||||
|
||||
map(0xa0000010, 0xa000001f).w(m_ramdac, FUNC(ramdac_device::index_w)).umask16(0x00ff);
|
||||
map(0xa0000020, 0xa000002f).w(m_ramdac, FUNC(ramdac_device::pal_w)).umask16(0x00ff);
|
||||
map(0xa0000030, 0xa000003f).w(m_ramdac, FUNC(ramdac_device::mask_w)).umask16(0x00ff);
|
||||
map(0xa0000010, 0xa0000017).w(m_ramdac, FUNC(ramdac_device::index_w));
|
||||
map(0xa0000020, 0xa0000027).w(m_ramdac, FUNC(ramdac_device::pal_w));
|
||||
map(0xa0000030, 0xa0000037).w(m_ramdac, FUNC(ramdac_device::mask_w));
|
||||
|
||||
map(0xfc000000, 0xffffffff).rom().region("user1", 0);
|
||||
}
|
||||
@ -503,7 +505,7 @@ ROM_START( atronic )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "atronic u6.bin", 0x0000, 0x020000, CRC(9742b2d8) SHA1(9f5851c78f92055730b834de18f8dc7bd9b29a37) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", ROMREGION_ERASE00 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", ROMREGION_ERASE00 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION( 0x400000, "u18u21",ROMREGION_ERASE00 ) // sound
|
||||
ROM_REGION( 0x400000, "pals",ROMREGION_ERASE00 ) // pal (converted from JED)
|
||||
|
||||
@ -518,7 +520,7 @@ ROM_START( atronica )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "atronic u6 std.bin", 0x0000, 0x020000, CRC(9ef7ae79) SHA1(3ed0ea056b23cee8829421c2369ff869b370ee80) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", ROMREGION_ERASE00 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", ROMREGION_ERASE00 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION( 0x400000, "u18u21",ROMREGION_ERASE00 ) // sound
|
||||
ROM_REGION( 0x400000, "pals",ROMREGION_ERASE00 ) // pal (converted from JED)
|
||||
ROM_END
|
||||
@ -532,7 +534,7 @@ ROM_START( atlantca )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u6.1 atla01-a-zb-std-5-xx-xx-axx", 0x0000, 0x020000, CRC(5d09a4bf) SHA1(94aea5396a968ff659ac9e2f4879262c55eba2fe) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9.8 atla01-a-e-std-5", 0x000000, 0x100000, CRC(7f8210fa) SHA1(f71faee0d606c6aa06287f6ea31f41727e2a22d9) )
|
||||
ROM_LOAD32_BYTE( "u11.8 atla01-a-e-std-5", 0x000001, 0x100000, CRC(af648717) SHA1(8ab57dc9962ed47a8beb03dcfc686c57de326793) )
|
||||
ROM_LOAD32_BYTE( "u13.8 atla01-a-e-std-5", 0x000002, 0x100000, CRC(6e89bf2b) SHA1(0c3346a5da6c67bf2ef38cf657860dccb03a0461) )
|
||||
@ -560,7 +562,7 @@ ROM_START( atlantcaa )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u6.1 atla01-a-zb-std-5-xx-xx-axx", 0x0000, 0x020000, CRC(5d09a4bf) SHA1(94aea5396a968ff659ac9e2f4879262c55eba2fe) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9-80.bin", 0x000000, 0x100000, CRC(1c51f9e1) SHA1(9300c80409f28ba55b94b93a3359fac732262b27) )
|
||||
ROM_LOAD32_BYTE( "u11-80.bin", 0x000001, 0x100000, CRC(b2b1f41f) SHA1(7551c7acc5c6c26b672e4a42d847ec9af79b50fe) )
|
||||
ROM_LOAD32_BYTE( "u13-80.bin", 0x000002, 0x100000, CRC(515820fa) SHA1(2f5def7145b45f8cd63d5463880a548e58e2b2d3) )
|
||||
@ -589,7 +591,7 @@ ROM_START( baboshka )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u6-10.bin", 0x0000, 0x020000, CRC(8b0ccfd2) SHA1(abdc59ebddc9e4fc3aa5b723a746de1419f7d6e7) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9-80.bin", 0x000000, 0x100000, CRC(1a5d8a4f) SHA1(ff8160f000ecb032831ef4320b686fdd37c19bc9) )
|
||||
ROM_LOAD32_BYTE( "u11-80.bin", 0x000001, 0x100000, CRC(713e18c9) SHA1(eb14213101c3ee09601bf01000631c3a2509e876) )
|
||||
ROM_LOAD32_BYTE( "u13-80.bin", 0x000002, 0x100000, CRC(dfbc8c2f) SHA1(1ae2dcd572fa5fc31be5cdb7d6de2bced06ff94e) )
|
||||
@ -614,7 +616,7 @@ ROM_START( cfblue )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u6.bin", 0x0000, 0x020000, CRC(63690e7e) SHA1(9dcb3d64bae03556875185ead23d9b911773f5bd) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9.bin", 0x000000, 0x100000, CRC(d1c2ad08) SHA1(e53c7e91b2ab86e64f4ae753404aa86ae881becf) )
|
||||
ROM_LOAD32_BYTE( "u11.bin", 0x000001, 0x100000, CRC(42872aef) SHA1(54d7cf6a9f3d5d8b2b14fa381fd7b9db974525e1) )
|
||||
ROM_LOAD32_BYTE( "u13.bin", 0x000002, 0x100000, CRC(7da9415b) SHA1(aaa73465417dcf92838021b37cb412d52ccb4d85) )
|
||||
@ -639,7 +641,7 @@ ROM_START( cfbluea )
|
||||
ROM_LOAD( "u6-10.bin", 0x0000, 0x020000, CRC(0db0531d) SHA1(391e41b2dcd38669dcc24e938e9838feee972559) )
|
||||
ROM_LOAD( "u6low-10.bin", 0x0000, 0x020000, CRC(3cbad206) SHA1(d2a468d5bfd441b74ef85be088873d1f74d5c66e) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9-80.bin", 0x000000, 0x100000, CRC(37b3a499) SHA1(eb3252185596dd513d3cce95f3425241ca8513ab) )
|
||||
ROM_LOAD32_BYTE( "u11-80.bin", 0x000001, 0x100000, CRC(d98b2b1d) SHA1(414d300d113e9737d63efea09b358aeb8eeed7fc) )
|
||||
ROM_LOAD32_BYTE( "u13-80.bin", 0x000002, 0x100000, CRC(478bb4a5) SHA1(94304fe1477bfc66e8dcf2c2c91226754cb8c32a) )
|
||||
@ -664,7 +666,7 @@ ROM_START( cfgreen )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u6-10.bin", 0x0000, 0x020000, CRC(3cbad206) SHA1(d2a468d5bfd441b74ef85be088873d1f74d5c66e) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9-80.bin", 0x000000, 0x100000, CRC(19a47a1b) SHA1(ae9ad2027fddf96062833345a5e2b9e7101b3380) )
|
||||
ROM_LOAD32_BYTE( "u11-80.bin", 0x000001, 0x100000, CRC(7d805f07) SHA1(0bb27a702e45d3d660363ac75c0f52f07248d40a) )
|
||||
ROM_LOAD32_BYTE( "u13-80.bin", 0x000002, 0x100000, CRC(104110dc) SHA1(9322598a94e3c71f546da3b42f137a22fc78a894) )
|
||||
@ -689,7 +691,7 @@ ROM_START( chicken )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u6-10.bin", 0x0000, 0x020000, CRC(bac68023) SHA1(fdc5d540ceb4a2d44013dfd59b46103ec6745dea) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9-80.bin", 0x000000, 0x100000, CRC(1109b7d6) SHA1(c0f6f5d56ee95982688b595894a2985ef53629e7) )
|
||||
ROM_LOAD32_BYTE( "u11-80.bin", 0x000001, 0x100000, CRC(5a1449f6) SHA1(3903858239223c37615f12a8db6a8e873722e34c) )
|
||||
ROM_LOAD32_BYTE( "u13-80.bin", 0x000002, 0x100000, CRC(e1081c7a) SHA1(dd6390d64cda9af93093092361ca24b551d82549) )
|
||||
@ -714,7 +716,7 @@ ROM_START( aclown )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u6-10.bin", 0x0000, 0x020000, CRC(ab86b3d4) SHA1(b0d32887674f971a3ccd482775ec3f978a2ea0c1) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9-80.bin", 0x000000, 0x100000, CRC(8bcbb27f) SHA1(d953268213580af11a2cc0dbd8bf1652f97f3929) )
|
||||
ROM_LOAD32_BYTE( "u11-80.bin", 0x000001, 0x100000, CRC(73fb3169) SHA1(8bbe5d8b8898e2d3368506e7b66d05b8f8ac7d02) )
|
||||
ROM_LOAD32_BYTE( "u13-80.bin", 0x000002, 0x100000, CRC(47580998) SHA1(37a6e409618aa3fe7d24bd3580fa93269895b059) )
|
||||
@ -740,7 +742,7 @@ ROM_START( goldglen )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u6-10.bin", 0x0000, 0x020000, CRC(94409a39) SHA1(99af058e48147fc75a8c23e4f1a28484f3d5f625) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9-80.bin", 0x000000, 0x100000, CRC(01e69d2d) SHA1(a6e6974aec52931aeeb1f90d8f917ab85ebe843e) )
|
||||
ROM_LOAD32_BYTE( "u11-80.bin", 0x000001, 0x100000, CRC(6c39a180) SHA1(95f91ec10961d36c86dee5ce42fc7c8ab693e271) )
|
||||
ROM_LOAD32_BYTE( "u13-80.bin", 0x000002, 0x100000, CRC(e60a093f) SHA1(fa0af661f869f80e11097e101ec6100a75d1e63f) )
|
||||
@ -765,7 +767,7 @@ ROM_START( iccash )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u6-10.bin", 0x0000, 0x020000, CRC(5e7d8a05) SHA1(255355cf594c2818d358860e616b5b578a87e974) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9-80.bin", 0x000000, 0x100000, CRC(db77fe46) SHA1(2502c5c165a9720e5ff1196eaa17189281c3145c) )
|
||||
ROM_LOAD32_BYTE( "u11-80.bin", 0x000001, 0x100000, CRC(3a512c6c) SHA1(ba8592773d71e57b3dc6aaff7df1214a57429b10) )
|
||||
ROM_LOAD32_BYTE( "u13-80.bin", 0x000002, 0x100000, CRC(75fadda8) SHA1(5a968f10e582fbe74000f3de33dc1e2d07c3fec1) )
|
||||
@ -791,7 +793,7 @@ ROM_START( shpinxii )
|
||||
ROM_LOAD( "u6-10.bin", 0x0000, 0x020000, CRC(4d37999a) SHA1(678dc788cfe00ab2599df08941660324793d7f6c) )
|
||||
ROM_LOAD( "sphinx ii.bin", 0x0000, 0x020000, CRC(7fae09a6) SHA1(5c26798337d3691d81f853ee447cb7119fce7b14) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9-80.bin", 0x000000, 0x100000, CRC(c54e4e07) SHA1(1249494773dae044a7bb4381b084e3d2e14367d7) )
|
||||
ROM_LOAD32_BYTE( "u11-80.bin", 0x000001, 0x100000, CRC(5c1e82ab) SHA1(f22ba1dc6799388e855d8f3064b96d568619a75b) )
|
||||
ROM_LOAD32_BYTE( "u13-80.bin", 0x000002, 0x100000, CRC(fb49ae3e) SHA1(bf0cb5815639ebc3db3333249ab2ed81d3bdc684) )
|
||||
@ -819,7 +821,7 @@ ROM_START( beachpt )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u06_crp5bs1a.bin", 0x0000, 0x020000, CRC(0db0531d) SHA1(391e41b2dcd38669dcc24e938e9838feee972559) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u09_bep5a01d.bin", 0x000000, 0x100000, CRC(0f4614de) SHA1(2181c552e9a3669fda5e87d0c596d5534d24d4b3) )
|
||||
ROM_LOAD32_BYTE( "u11_bep5a01d.bin", 0x000001, 0x100000, CRC(4f8c6fee) SHA1(2b75fe948bddda899969ef4a7663a52dc7b0eb81) )
|
||||
ROM_LOAD32_BYTE( "u13_bep5a01d.bin", 0x000002, 0x100000, CRC(ca9a24e5) SHA1(67276f680f3aedf480c54c666f0db1110cd77aee) )
|
||||
@ -847,7 +849,7 @@ ROM_START( beetleup )
|
||||
ROM_LOAD( "u06_n5b0-a-05-b.648f.bin", 0x0000, 0x020000, CRC(2d2ff35f) SHA1(97759fbad4b6b30ca8f8ea74da74cfaa433a7fa2) )
|
||||
ROM_LOAD( "u06_n5b0-a-06-b.64 56.bin", 0x0000, 0x020000, CRC(7b4a6a97) SHA1(e3d54476730ca34a9f7214219cf991a220e15d5c) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u09_7b88.bin", 0x000000, 0x100000, CRC(8443972b) SHA1(5f2eea84ba18a83502f36eeaa52cff49a1631668) )
|
||||
ROM_LOAD32_BYTE( "u11_1957.bin", 0x000001, 0x100000, CRC(36c7e5c5) SHA1(2bad0bb6b363af6a37f5b11c7ca8b3b674df4072) )
|
||||
ROM_LOAD32_BYTE( "u13_b661.bin", 0x000002, 0x100000, CRC(0e74726c) SHA1(3103d801a622315877fc09d9c99290b54b266885) )
|
||||
@ -874,7 +876,7 @@ ROM_START( bigblue )
|
||||
ROM_LOAD( "big blue bags.bin", 0x0000, 0x020000, CRC(4ec3fc1c) SHA1(7a081d370c54a6ea333957958b1341560458e845) )
|
||||
ROM_LOAD( "bbbu01-c-za-std_-5-xx-xx-axx.1mu06.bin", 0x0000, 0x020000, CRC(09e6df0b) SHA1(85961160f95cb8d223f73483d6edad79fa37d729) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "bbbu01-a_-a-std_-5_.8gu09.bin", 0x000000, 0x100000, CRC(6f11b908) SHA1(663382bc295615afbc3a9a39c7089470b8b55926) )
|
||||
ROM_LOAD32_BYTE( "bbbu01-a_-a-std_-5_.8gu11.bin", 0x000001, 0x100000, CRC(4cddcb5a) SHA1(e23354ab36f814b22c39564111558d4935fe8d70) )
|
||||
ROM_LOAD32_BYTE( "bbbu01-a_-a-std_-5_.8gu13.bin", 0x000002, 0x100000, CRC(3a6dd649) SHA1(0f2b6cdf4f10ded99adc4fe0b47e4fada4aa6643) )
|
||||
@ -898,7 +900,7 @@ ROM_START( castaway )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u6.1 c5bo-a-03-a", 0x0000, 0x020000, CRC(3917302a) SHA1(39b0672c36554712825a0e310522933be4b46d84) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9.8 cw5_b-03-b", 0x000000, 0x100000, CRC(c49aaf25) SHA1(5518312046208b4f912e9dee2ff24653a9976c6f) )
|
||||
ROM_LOAD32_BYTE( "u11.8 cw5_b-03-b", 0x000001, 0x100000, CRC(24267b4b) SHA1(9103923dd1bba0b01f6020f7c357ac9b7bef4951) )
|
||||
ROM_LOAD32_BYTE( "u13.8 cw5_b-03-b", 0x000002, 0x100000, CRC(3e606516) SHA1(5edad0a3099700bfeedff5a143591a85b3c4f582) )
|
||||
@ -922,7 +924,7 @@ ROM_START( castawaya ) // bad dump? (roms all look incorrect size to me)
|
||||
ROM_REGION( 0x080000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u-6 m27c801.bin", 0x0000, 0x080000, CRC(86538b30) SHA1(6b8d732b59af2cc1a6524989f8cf12a4d4dac484) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
// seem to be half size, doesn't have the TMS vectors
|
||||
ROM_LOAD32_BYTE( "u-9 m27c801.bin", 0x000000, 0x080000, BAD_DUMP CRC(4a5efe38) SHA1(23e82eeadccdd0224858686b1d96bd5d184904cb) )
|
||||
ROM_LOAD32_BYTE( "u-11 m27c801.bin", 0x000001, 0x080000, BAD_DUMP CRC(099e27e2) SHA1(4419ac8090ccab673e61f4f73c837971e341e7e2) )
|
||||
@ -952,7 +954,7 @@ ROM_START( dncsprt )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "dasp01-d-za-std_-5-xx-xx-axx.1mu06", 0x0000, 0x020000, CRC(2d5f7976) SHA1(77de321ba2f46726a0c26aa498a4c3deb7f8c421) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "dasp01-a_-c-std_-5_.8gu09", 0x000000, 0x100000, CRC(e6941863) SHA1(c9fe08bd070c9fac7b8c9089a6ecbff581265b3a) )
|
||||
ROM_LOAD32_BYTE( "dasp01-a_-c-std_-5_.8gu11", 0x000001, 0x100000, CRC(400b82ab) SHA1(5af6daf65e50b0c5ad27c43b0f3d4d8d24f38102) )
|
||||
ROM_LOAD32_BYTE( "dasp01-a_-c-std_-5_.8gu13", 0x000002, 0x100000, CRC(b425a8f6) SHA1(82d8e0d8602a81c6d4cf528b73f3c84ab5dde11b) )
|
||||
@ -977,7 +979,7 @@ ROM_START( drmmake )
|
||||
ROM_LOAD( "u6-1001", 0x0000, 0x020000, CRC(7a00ad2a) SHA1(67d90b10b4f62922c4ed94bb8a0f77e474ee385d) )
|
||||
ROM_LOAD( "dream maker.bin", 0x0000, 0x020000, CRC(49c19eb3) SHA1(a55d4f9a0dd2b1db41fb28f475efa7e9f7c85be6) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9-801", 0x000000, 0x100000, CRC(e560eeff) SHA1(fe33927a91be7ecd2a283bb09b87f5f3d659cf09) )
|
||||
ROM_LOAD32_BYTE( "u11-801", 0x000001, 0x100000, CRC(693cec8e) SHA1(83d33603fa11aa4341a40b2ffc4862992307dcfc) )
|
||||
ROM_LOAD32_BYTE( "u13-801", 0x000002, 0x100000, CRC(8b78f6aa) SHA1(74804c44124b71f0f11446da342d0548130394f6) )
|
||||
@ -1004,7 +1006,7 @@ ROM_START( jumpjkpt )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "jujp01-a-za-std_-5_u06.bin", 0x0000, 0x020000, CRC(0f19b0c1) SHA1(c118215bcf502287277c34e6f389af70ab945674) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "jujp01-a_-b-std_-5_u09.bin", 0x000000, 0x100000, CRC(7d3cb293) SHA1(e9f102620f01309327678e115e206fd29dcffde6) )
|
||||
ROM_LOAD32_BYTE( "jujp01-a_-b-std_-5_u11.bin", 0x000001, 0x100000, CRC(d92c0c7e) SHA1(680032b81e76c74539ff56f8c5fc7d4d16fd4793) )
|
||||
ROM_LOAD32_BYTE( "jujp01-a_-b-std_-5_u13.bin", 0x000002, 0x100000, CRC(555ced70) SHA1(1ec115a2e2a1c171070775913a3eb831efc81dab) )
|
||||
@ -1030,7 +1032,7 @@ ROM_START( mushmagi )
|
||||
ROM_REGION( 0x080000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "mb-u06.bin", 0x0000, 0x080000, CRC(10e3f3f6) SHA1(458f5be7ee01e361b4c31c099fc721521fbe3864) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "gb-u09.bin", 0x000000, 0x100000, CRC(f2d82cee) SHA1(78a15f757bbbb1f4f0a5ab889a9807d886a543a8) )
|
||||
ROM_LOAD32_BYTE( "gb-u11.bin", 0x000001, 0x100000, CRC(3ead238a) SHA1(21956bd6b24e3281db70b6d28d97ee7bbd9ae75f) )
|
||||
ROM_LOAD32_BYTE( "gb-u13.bin", 0x000002, 0x100000, CRC(58c191e6) SHA1(b0f86f407958de2b8e0f5e61288f8b6c7a2c0c2f) )
|
||||
@ -1056,7 +1058,7 @@ ROM_START( splmastr )
|
||||
ROM_LOAD( "mb-u6 ebda.bin", 0x0000, 0x020000, CRC(7e73e9c7) SHA1(a8b00af9a3bf936e54391a96777ac78773b3cee0) )
|
||||
ROM_LOAD( "speel master.bin", 0x0000, 0x020000, CRC(04168ab7) SHA1(70a387599bf6629a9a8a6ff38ed0d40e92e54504) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "gb-u9 b408.bin", 0x000000, 0x100000, CRC(e7146c72) SHA1(21b143ae93a73dd59b652a0033ceaa9116575239) )
|
||||
ROM_LOAD32_BYTE( "gb-u11 abf6.bin", 0x000001, 0x100000, CRC(de54f849) SHA1(b628a69c8ad5f81543cd78c458dd9348226114a7) )
|
||||
ROM_LOAD32_BYTE( "gb-u13 6526.bin", 0x000002, 0x100000, CRC(e5744b4f) SHA1(8c36b087dc4fad6cd463abea5b1e7c0bd9c30074) )
|
||||
@ -1094,7 +1096,7 @@ ROM_START( tajmah )
|
||||
ROM_LOAD32_BYTE( "t5_d01d.u12", 0x600002, 0x080000, CRC(c2ca0b17) SHA1(cfd553f1943552620f6d324f767fd1f1957e8e25) )
|
||||
ROM_LOAD32_BYTE( "t5_d01d.u14", 0x600003, 0x080000, CRC(0d512057) SHA1(f5f43dad25940193516d467725ecbe1989cc9003) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) - is this an alt set, or a 2nd video board? */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) - is this an alt set, or a 2nd video board? */
|
||||
ROM_LOAD32_BYTE( "u9", 0x400000, 0x080000, CRC(157b9860) SHA1(6e04f035a945a63617e32b196fa0c1b6fd26b281) )
|
||||
ROM_LOAD32_BYTE( "u11", 0x400001, 0x080000, CRC(6aa2cecc) SHA1(7b1d6bb81fed7413f69e926e7cefe1ee171453b4) )
|
||||
ROM_LOAD32_BYTE( "u13", 0x400002, 0x080000, CRC(5c091b7a) SHA1(d1c758a6d155bbc7359f3f46a29bac44d96ec4b1) )
|
||||
@ -1127,7 +1129,7 @@ ROM_START( 3wishrd )
|
||||
ROM_LOAD( "three wishes.bin", 0x0000, 0x020000, CRC(37d85da7) SHA1(64db855e06dab5ea85c669bd72f1e8ee8856607a) )
|
||||
ROM_LOAD( "590a13a.1u6", 0x0000, 0x020000, CRC(3e674907) SHA1(ca933c416764ebf355d8e04f871f8421c9039078) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "tw5b01a.8u9", 0x000000, 0x100000, CRC(2410659a) SHA1(2bcd2539c0e3e7389c27c21e58d9199b9c7c742e) )
|
||||
ROM_LOAD32_BYTE( "tw5b01a.u11", 0x000001, 0x100000, CRC(44ca9ce1) SHA1(b1c6d83f749202c072c6ce99c0470a31cfab8986) )
|
||||
ROM_LOAD32_BYTE( "tw5b01a.u13", 0x000002, 0x100000, CRC(6c60097b) SHA1(f5ddb86b481b7b95d6ec151b37d662b583817813) )
|
||||
@ -1156,7 +1158,7 @@ ROM_START( atrwild )
|
||||
ROM_LOAD( "mb-u22-d.bin", 0x000, 0x117, CRC(dc097847) SHA1(305294284d0ffd578f9115b836ef1f9e906c1599) )
|
||||
ROM_LOAD( "mb-u32-b.bin", 0x000, 0x117, CRC(78a9310b) SHA1(deb84d96b0411b05c54fb2c998bed020a37d5005) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u8.bin", 0x600000, 0x080000, CRC(4acafd98) SHA1(d516c55ddce1470e4e19725b6d7dfd5f70ba1129) )
|
||||
ROM_LOAD32_BYTE( "u10.bin", 0x600001, 0x080000, CRC(804800be) SHA1(5fb2a5479c2a7073c2abd40e14a162fbf783eb70) )
|
||||
ROM_LOAD32_BYTE( "u12.bin", 0x600002, 0x080000, CRC(0845ff27) SHA1(5012569a79c9fcbee178a0cee45d25769a1cf9be) )
|
||||
@ -1177,7 +1179,7 @@ ROM_START( atricmon )
|
||||
ROM_LOAD( "mb-u32-d.bin", 0x000, 0x2e5, CRC(996854bc) SHA1(647d2f49b739f7ca55c0b85290b6a21256834fd8) )
|
||||
ROM_LOAD( "mb-u35-65994077_icm-s.bin", 0x000, 0x2e5, CRC(996854bc) SHA1(647d2f49b739f7ca55c0b85290b6a21256834fd8) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "gb-u9.bin", 0x000000, 0x100000, CRC(eff83f95) SHA1(743f2fb0dd84a83387919db70175aa62f5f6f858) )
|
||||
ROM_LOAD32_BYTE( "gb-u11.bin", 0x000001, 0x100000, CRC(3fc27ae9) SHA1(896da175c11b48fb28dbb0678849b8f167cf5f6e) )
|
||||
ROM_LOAD32_BYTE( "gb-u13.bin", 0x000002, 0x100000, CRC(6ad50f67) SHA1(b32781f06acc3e9929467d6d1212cf0dc757e5b3) )
|
||||
@ -1210,7 +1212,7 @@ ROM_START( atrbonpk )
|
||||
ROM_LOAD( "u6-b.bin", 0x000, 0x117, CRC(2750fb0a) SHA1(3814c4755a215073425a9d6bb048315498962c76) )
|
||||
ROM_LOAD( "u7-a.bin", 0x000, 0x117, CRC(adcb2789) SHA1(cc2ebd69abec73d66665faaec19b8706e539b34c) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_LOAD32_BYTE( "u9.bin", 0x400000, 0x080000, CRC(5b8450f1) SHA1(27fc771c3fb824cdb845237324984778fcd0a737) )
|
||||
ROM_LOAD32_BYTE( "u11.bin", 0x400001, 0x080000, CRC(c8c52bd1) SHA1(081b8b4c46f18d030329bf519a8ed50385f7c062) )
|
||||
ROM_LOAD32_BYTE( "u13.bin", 0x400002, 0x080000, CRC(23164a85) SHA1(e6de6aac28f1dac9ea908aaab9760b56ded1bb91) )
|
||||
@ -1231,7 +1233,7 @@ ROM_START( abigchs )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "bigc21-d-zf-std_-5-xx-xx-axx.1mu06", 0x0000, 0x020000, CRC(0eb376fb) SHA1(34e1f28e71503ffb0e1e922bd3ba17bad0d37d99) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
// not valid TMS code, looks like some x86 drive image split into ROMs?
|
||||
ROM_LOAD( "bigc01-a_-f-rus_-5_-g101.wigu09", 0x000000, 0x100000, CRC(c87e6bb4) SHA1(387e2498625ff718fccaa7701dd595ee787b9a83) )
|
||||
ROM_LOAD( "bigc01-a_-f-rus_-5_-g101.wigu11", 0x100000, 0x100000, CRC(c9e9fa7f) SHA1(1698215845f21cfde0274e880d89c66fb3226f04) )
|
||||
@ -1256,7 +1258,7 @@ ROM_START( bearnec )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u6_bene21-e-zg-std_-5-xx-xx-axx_0f78.bin", 0x0000, 0x020000, CRC(d956484f) SHA1(d2d659a4350d7204666234a511ebd4dd7a021d89) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
// not valid TMS code, looks like some x86 drive image split into ROMs?
|
||||
ROM_LOAD( "u09_a632.bin", 0x000000, 0x100000, CRC(a671b6e8) SHA1(86b97ba98fdd09575a371b5b7f7d42bf2916fe17) )
|
||||
ROM_LOAD( "u11_947b.bin", 0x100000, 0x100000, CRC(3dc60963) SHA1(d824cd4fbe4116744727180762fbf0ffe22e6398) )
|
||||
@ -1281,7 +1283,7 @@ ROM_START( goldcity )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "goci21-e-zf-std_-5-xx-xx-axx.1mu06", 0x0000, 0x020000, CRC(73ab9c41) SHA1(0888923bdaede83f264979c0757894f5cb2e0ec8) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
// not valid TMS code, looks like some x86 drive image split into ROMs?
|
||||
ROM_LOAD( "goci01-a_-c-rus_-5_-g101.wigu09", 0x000000, 0x100000, CRC(72c9b584) SHA1(1345e7ea34a819fbc01b9a64e9f9c1a2de927dda) )
|
||||
ROM_LOAD( "goci01-a_-c-rus_-5_-g101.wigu11", 0x100000, 0x100000, CRC(2ebe1d71) SHA1(1b540c3bb9b232f475c3fe2b56c55f473d8c09ee) )
|
||||
@ -1309,7 +1311,7 @@ ROM_START( santam )
|
||||
ROM_REGION( 0x020000, "u6", 0 ) // config?
|
||||
ROM_LOAD( "u06_1m_m27c1001-10f_da21h.bin", 0x0000, 0x020000, CRC(51c0a380) SHA1(861c8b4f825f4bc11dd02ac03dcc2cc7e8c65129) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* TMS34020APCM-40 code (34020) */
|
||||
// not valid TMS code, looks like some x86 drive image split into ROMs?
|
||||
ROM_LOAD( "gb_u09_8m_m27c801-100f1_9df6h.bin", 0x000000, 0x100000, CRC(470ccae5) SHA1(0521af7830cc59102edcc658df4d21a3d669d6db) )
|
||||
ROM_LOAD( "gb_u11_8m_m27c801-100f1_7621h.bin", 0x100000, 0x100000, CRC(8f9a1031) SHA1(1aca654b62e73f3005e627625bea2b4198c04a99) )
|
||||
|
||||
@ -28,11 +28,34 @@
|
||||
|
||||
void btoads_state::machine_start()
|
||||
{
|
||||
m_nvram_data = std::make_unique<uint8_t[]>(0x2000);
|
||||
subdevice<nvram_device>("nvram")->set_base(m_nvram_data.get(), 0x2000);
|
||||
|
||||
save_item(NAME(m_main_to_sound_data));
|
||||
save_item(NAME(m_main_to_sound_ready));
|
||||
save_item(NAME(m_sound_to_main_data));
|
||||
save_item(NAME(m_sound_to_main_ready));
|
||||
save_item(NAME(m_sound_int_state));
|
||||
save_pointer(NAME(m_nvram_data), 0x2000);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*************************************
|
||||
*
|
||||
* NVRAM
|
||||
*
|
||||
*************************************/
|
||||
|
||||
void btoads_state::nvram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_nvram_data[offset] = data;
|
||||
}
|
||||
|
||||
|
||||
uint8_t btoads_state::nvram_r(offs_t offset)
|
||||
{
|
||||
return m_nvram_data[offset];
|
||||
}
|
||||
|
||||
|
||||
@ -180,11 +203,11 @@ void btoads_state::main_map(address_map &map)
|
||||
map(0x20000180, 0x200001ff).w(FUNC(btoads_state::display_control_w));
|
||||
map(0x20000200, 0x2000027f).w(FUNC(btoads_state::scroll0_w));
|
||||
map(0x20000280, 0x200002ff).w(FUNC(btoads_state::scroll1_w));
|
||||
map(0x20000300, 0x2000037f).rw(FUNC(btoads_state::paletteram_r), FUNC(btoads_state::paletteram_w));
|
||||
map(0x20000300, 0x2000037f).rw(m_tlc34076, FUNC(tlc34076_device::read), FUNC(tlc34076_device::write)).umask32(0x000000ff);
|
||||
map(0x20000380, 0x200003ff).rw(FUNC(btoads_state::main_sound_r), FUNC(btoads_state::main_sound_w));
|
||||
map(0x20000400, 0x2000047f).w(FUNC(btoads_state::misc_control_w));
|
||||
map(0x40000000, 0x4000000f).nopw(); /* watchdog? */
|
||||
map(0x60000000, 0x6003ffff).ram().share("nvram");
|
||||
map(0x40000000, 0x4000001f).nopw(); /* watchdog? */
|
||||
map(0x60000000, 0x6003ffff).rw(FUNC(btoads_state::nvram_r), FUNC(btoads_state::nvram_w)).umask32(0x000000ff);
|
||||
map(0xa0000000, 0xa03fffff).rw(FUNC(btoads_state::vram_fg_display_r), FUNC(btoads_state::vram_fg_display_w)).share("vram_fg0");
|
||||
map(0xa4000000, 0xa43fffff).rw(FUNC(btoads_state::vram_fg_draw_r), FUNC(btoads_state::vram_fg_draw_w)).share("vram_fg1");
|
||||
map(0xa8000000, 0xa87fffff).ram().share("vram_fg_data");
|
||||
@ -228,46 +251,46 @@ void btoads_state::sound_io_map(address_map &map)
|
||||
|
||||
static INPUT_PORTS_START( btoads )
|
||||
PORT_START("P1")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
|
||||
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START1 )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
|
||||
PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_START1 )
|
||||
PORT_BIT( 0xffffff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
|
||||
PORT_START("P2")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2)
|
||||
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START2 )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2)
|
||||
PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_START2 )
|
||||
PORT_BIT( 0xffffff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
|
||||
PORT_START("P3")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_IMPULSE(2)
|
||||
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START3 )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_IMPULSE(2)
|
||||
PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_START3 )
|
||||
PORT_BIT( 0xffffff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
|
||||
PORT_START("UNK")
|
||||
PORT_BIT( 0xffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
PORT_BIT( 0xffffffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
|
||||
PORT_START("SPECIAL")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_MEMBER(btoads_state, sound_to_main_r)
|
||||
PORT_BIT( 0x00000001, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_MEMBER(btoads_state, sound_to_main_r)
|
||||
PORT_SERVICE_NO_TOGGLE( 0x0002, IP_ACTIVE_LOW )
|
||||
PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_MEMBER(btoads_state, main_to_sound_r)
|
||||
PORT_BIT( 0xff7c, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
PORT_BIT( 0x00000080, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_MEMBER(btoads_state, main_to_sound_r)
|
||||
PORT_BIT( 0xffffff7c, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
|
||||
PORT_START("SW1")
|
||||
PORT_DIPNAME( 0x0001, 0x0000, DEF_STR( Demo_Sounds )) PORT_DIPLOCATION("SW1:1")
|
||||
@ -292,7 +315,7 @@ static INPUT_PORTS_START( btoads )
|
||||
PORT_DIPSETTING( 0x0040, DEF_STR( Off ))
|
||||
PORT_DIPSETTING( 0x0000, DEF_STR( On ))
|
||||
PORT_DIPUNKNOWN_DIPLOC(0x0080, 0x0080, "SW1:8")
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0xffffff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
INPUT_PORTS_END
|
||||
|
||||
|
||||
@ -348,7 +371,7 @@ ROM_START( btoads )
|
||||
ROM_REGION( 0x10000, "audiocpu", 0 ) /* sound program, M27C256B rom */
|
||||
ROM_LOAD( "bt.u102", 0x0000, 0x8000, CRC(a90b911a) SHA1(6ec25161e68df1c9870d48cc2b1f85cd1a49aba9) )
|
||||
|
||||
ROM_REGION16_LE( 0x800000, "user1", 0 ) /* 34020 code, M27C322 roms */
|
||||
ROM_REGION32_LE( 0x800000, "user1", 0 ) /* 34020 code, M27C322 roms */
|
||||
ROM_LOAD32_WORD( "btc0-p0.u120", 0x000000, 0x400000, CRC(0dfd1e35) SHA1(733a0a4235bebd598c600f187ed2628f28cf9bd0) )
|
||||
ROM_LOAD32_WORD( "btc0-p1.u121", 0x000002, 0x400000, CRC(df7487e1) SHA1(67151b900767bb2653b5261a98c81ff8827222c3) )
|
||||
|
||||
|
||||
@ -525,8 +525,8 @@ void metalmx_state::adsp_data_map(address_map &map)
|
||||
|
||||
void metalmx_state::gsp_map(address_map &map)
|
||||
{
|
||||
map(0x88800000, 0x8880000f).ram(); /* ? */
|
||||
map(0x88c00000, 0x88c0000f).ram(); /* ? */
|
||||
map(0x88800000, 0x8880001f).ram(); /* ? */
|
||||
map(0x88c00000, 0x88c0001f).ram(); /* ? */
|
||||
map(0xff000000, 0xff7fffff).ram().share("gsp_dram");
|
||||
map(0xff800000, 0xffffffff).ram().share("gsp_vram");
|
||||
}
|
||||
|
||||
@ -94,7 +94,6 @@ Notes:
|
||||
|
||||
|
||||
#include "emu.h"
|
||||
#include "includes/midtunit.h"
|
||||
#include "includes/midwunit.h"
|
||||
#include "audio/dcs.h"
|
||||
|
||||
|
||||
@ -10,21 +10,6 @@
|
||||
Games supported:
|
||||
* Revolution X
|
||||
|
||||
Known bugs:
|
||||
* POST test ends with "CUSTOM CHIP U76 BAD" message,
|
||||
However, this is caused by failed blitter DMA test, it's buggy code:
|
||||
20D31460: MOVI 100000h,A14 ; control register value, set H-clip access
|
||||
20D31490: MOVE A14,@C08000E0h,1 ; 32bit write control reg
|
||||
20D314C0: MOVI 1FF0000h,A14 ; H-clip range value 0-511
|
||||
20D314F0: MOVE A14,@C08000C0h,1 ; 32bit write H-clip reg
|
||||
20D31520: MOVI 300000h,A14 ; control register value, set V-clip access
|
||||
20D31550: MOVE A14,@C08000E0h,0 ; 16bit(!!) write, upper word ignored in MAME, control reg still set to H-clip access
|
||||
20D31580: MOVI 1FF0000h,A14 ; V-clip range value 0-511
|
||||
20D315B0: MOVE A14,@C08000C0h,1 ; 32bit write, in MAME write goes to H-clip registers
|
||||
in result of not set V-clip range in MAME the whole DMA request is clipped.
|
||||
It is possible X-unit DMA registers block C08000xxh access is 32-bit only (/CAS0-3 lines ignored), so any write access always update whole 32bits.
|
||||
At the moment TMS34020 incorrectly emulated as 16bit wide data bus CPU, so we can't properly handle this issue.
|
||||
|
||||
***************************************************************************
|
||||
|
||||
Revolution X
|
||||
@ -131,7 +116,6 @@ ________________________________________________________________
|
||||
#include "cpu/adsp2100/adsp2100.h"
|
||||
#include "cpu/tms34010/tms34010.h"
|
||||
#include "machine/adc0844.h"
|
||||
#include "machine/nvram.h"
|
||||
|
||||
#include "screen.h"
|
||||
|
||||
@ -159,12 +143,11 @@ void midxunit_state::main_map(address_map &map)
|
||||
map(0x60c00060, 0x60c0007f).portr("DSW");
|
||||
map(0x60c00080, 0x60c000df).w(FUNC(midxunit_state::midxunit_io_w));
|
||||
map(0x60c000e0, 0x60c000ff).rw(FUNC(midxunit_state::midxunit_security_r), FUNC(midxunit_state::midxunit_security_w));
|
||||
map(0x80800000, 0x8080000f).r("adc", FUNC(adc0848_device::read)).umask16(0x00ff).w("adc", FUNC(adc0848_device::write)).umask16(0x00ff);
|
||||
map(0x80800010, 0x8080001f).noprw();
|
||||
map(0x80c00000, 0x80c000ff).rw(FUNC(midxunit_state::midxunit_uart_r), FUNC(midxunit_state::midxunit_uart_w));
|
||||
map(0xa0440000, 0xa047ffff).rw(FUNC(midxunit_state::midxunit_cmos_r), FUNC(midxunit_state::midxunit_cmos_w)).share("nvram");
|
||||
map(0x80800000, 0x80800007).rw("adc", FUNC(adc0848_device::read), FUNC(adc0848_device::write));
|
||||
map(0x80c00000, 0x80c000ff).rw(FUNC(midxunit_state::midxunit_uart_r), FUNC(midxunit_state::midxunit_uart_w)).umask32(0x000000ff);
|
||||
map(0xa0440000, 0xa047ffff).rw(FUNC(midxunit_state::midxunit_cmos_r), FUNC(midxunit_state::midxunit_cmos_w)).umask32(0x000000ff);
|
||||
map(0xa0800000, 0xa08fffff).rw(m_video, FUNC(midxunit_video_device::midxunit_paletteram_r), FUNC(midxunit_video_device::midxunit_paletteram_w)).share("palette");
|
||||
map(0xc0800000, 0xc08000ff).mirror(0x00400000).rw(m_video, FUNC(midxunit_video_device::midtunit_dma_r), FUNC(midxunit_video_device::midtunit_dma_w));
|
||||
map(0xc0800000, 0xc08000ff).mirror(0x00400000).rw(FUNC(midxunit_state::midxunit_dma_r), FUNC(midxunit_state::midxunit_dma_w));
|
||||
map(0xf8000000, 0xfeffffff).r(m_video, FUNC(midxunit_video_device::midwunit_gfxrom_r));
|
||||
map(0xff000000, 0xffffffff).rom().region("maincpu", 0);
|
||||
}
|
||||
@ -179,38 +162,39 @@ void midxunit_state::main_map(address_map &map)
|
||||
|
||||
static INPUT_PORTS_START( revx )
|
||||
PORT_START("IN0")
|
||||
PORT_BIT( 0x000f, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x00c0, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x0f00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0xc000, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x0000000f, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
|
||||
PORT_BIT( 0x000000c0, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x00000f00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x00001000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0x00002000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
|
||||
PORT_BIT( 0xffffc000, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
|
||||
PORT_START("IN1")
|
||||
PORT_BIT( 0x000f, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0xffc0, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x0000000f, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
|
||||
PORT_BIT( 0xffffffc0, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
|
||||
PORT_START("IN2")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
|
||||
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_START1 )
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_TILT ) /* Slam Switch */
|
||||
PORT_SERVICE_NO_TOGGLE(0x0010, IP_ACTIVE_LOW)
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_START2 )
|
||||
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_SERVICE1 )
|
||||
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_COIN3 )
|
||||
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_COIN4 )
|
||||
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START3 )
|
||||
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_VOLUME_DOWN )
|
||||
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_VOLUME_UP )
|
||||
PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_CUSTOM ) /* coin door */
|
||||
PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_BILL1 ) /* bill validator */
|
||||
PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_COIN1 )
|
||||
PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_COIN2 )
|
||||
PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_START1 )
|
||||
PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_TILT ) /* Slam Switch */
|
||||
PORT_SERVICE_NO_TOGGLE(0x00000010, IP_ACTIVE_LOW)
|
||||
PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_START2 )
|
||||
PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_SERVICE1 )
|
||||
PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_COIN3 )
|
||||
PORT_BIT( 0x00000100, IP_ACTIVE_LOW, IPT_COIN4 )
|
||||
PORT_BIT( 0x00000200, IP_ACTIVE_LOW, IPT_START3 )
|
||||
PORT_BIT( 0x00000400, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x00000800, IP_ACTIVE_LOW, IPT_VOLUME_DOWN )
|
||||
PORT_BIT( 0x00001000, IP_ACTIVE_LOW, IPT_VOLUME_UP )
|
||||
PORT_BIT( 0x00002000, IP_ACTIVE_LOW, IPT_CUSTOM ) /* coin door */
|
||||
PORT_BIT( 0x00004000, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x00008000, IP_ACTIVE_LOW, IPT_BILL1 ) /* bill validator */
|
||||
PORT_BIT( 0xffff0000, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
|
||||
PORT_START("DSW")
|
||||
PORT_DIPNAME( 0x0001, 0x0000, DEF_STR( Flip_Screen ))
|
||||
@ -255,6 +239,7 @@ static INPUT_PORTS_START( revx )
|
||||
PORT_DIPNAME( 0x8000, 0x8000, "Test Switch" )
|
||||
PORT_DIPSETTING( 0x8000, DEF_STR( Off ))
|
||||
PORT_DIPSETTING( 0x0000, DEF_STR( On ))
|
||||
PORT_BIT( 0xffff0000, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
|
||||
PORT_START("AN0")
|
||||
PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_CROSSHAIR(X, -1.0, 0.0, 0) PORT_SENSITIVITY(20) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(1)
|
||||
|
||||
@ -21,13 +21,13 @@ class btoads_state : public driver_device
|
||||
public:
|
||||
btoads_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_vram_fg0(*this, "vram_fg0", 16),
|
||||
m_vram_fg1(*this, "vram_fg1", 16),
|
||||
m_vram_fg_data(*this, "vram_fg_data"),
|
||||
m_vram_bg0(*this, "vram_bg0"),
|
||||
m_vram_bg1(*this, "vram_bg1"),
|
||||
m_sprite_scale(*this, "sprite_scale"),
|
||||
m_sprite_control(*this, "sprite_control"),
|
||||
m_vram_fg0(*this, "vram_fg0", 32),
|
||||
m_vram_fg1(*this, "vram_fg1", 32),
|
||||
m_vram_fg_data(*this, "vram_fg_data", 32),
|
||||
m_vram_bg0(*this, "vram_bg0", 32),
|
||||
m_vram_bg1(*this, "vram_bg1", 32),
|
||||
m_sprite_scale(*this, "sprite_scale", 32),
|
||||
m_sprite_control(*this, "sprite_control", 32),
|
||||
m_maincpu(*this, "maincpu"),
|
||||
m_audiocpu(*this, "audiocpu"),
|
||||
m_bsmt(*this, "bsmt"),
|
||||
@ -82,8 +82,11 @@ private:
|
||||
uint16_t m_sprite_dest_offs;
|
||||
uint16_t m_misc_control;
|
||||
int m_xcount;
|
||||
std::unique_ptr<uint8_t[]> m_nvram_data;
|
||||
|
||||
// in drivers/btoads
|
||||
void nvram_w(offs_t offset, uint8_t data);
|
||||
uint8_t nvram_r(offs_t offset);
|
||||
void main_sound_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t main_sound_r();
|
||||
void sound_data_w(uint8_t data);
|
||||
@ -99,8 +102,6 @@ private:
|
||||
void display_control_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void scroll0_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void scroll1_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void paletteram_w(offs_t offset, uint16_t data);
|
||||
uint16_t paletteram_r(offs_t offset);
|
||||
void vram_bg0_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void vram_bg1_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t vram_bg0_r(offs_t offset);
|
||||
|
||||
@ -10,13 +10,22 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "audio/dcs.h"
|
||||
#include "cpu/tms34010/tms34010.h"
|
||||
#include "machine/midwayic.h"
|
||||
#include "video/midtunit.h"
|
||||
#include "emupal.h"
|
||||
|
||||
class midwunit_state : public midtunit_state
|
||||
class midwunit_state : public driver_device
|
||||
{
|
||||
public:
|
||||
midwunit_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: midtunit_state(mconfig, type, tag)
|
||||
: driver_device(mconfig, type, tag)
|
||||
, m_maincpu(*this, "maincpu")
|
||||
, m_video(*this, "video")
|
||||
, m_dcs(*this, "dcs")
|
||||
, m_palette(*this, "palette")
|
||||
, m_gfxrom(*this, "gfxrom")
|
||||
, m_midway_serial_pic(*this, "serial_security_sim")
|
||||
, m_midway_serial_pic_emu(*this, "serial_security")
|
||||
, m_nvram(*this, "nvram")
|
||||
@ -53,12 +62,18 @@ private:
|
||||
uint16_t midwunit_sound_r();
|
||||
uint16_t midwunit_sound_state_r();
|
||||
void midwunit_sound_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void umk3_palette_hack_w(address_space &space, offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void umk3_palette_hack_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void wwfmania_io_0_w(uint16_t data);
|
||||
|
||||
void init_mk3_common();
|
||||
void main_map(address_map &map);
|
||||
|
||||
required_device<tms340x0_device> m_maincpu;
|
||||
required_device<midtunit_video_device> m_video;
|
||||
required_device<dcs_audio_device> m_dcs;
|
||||
required_device<palette_device> m_palette;
|
||||
required_memory_region m_gfxrom;
|
||||
|
||||
optional_device<midway_serial_pic_device> m_midway_serial_pic;
|
||||
optional_device<midway_serial_pic_emu_device> m_midway_serial_pic_emu;
|
||||
required_shared_ptr<uint16_t> m_nvram;
|
||||
|
||||
@ -10,15 +10,24 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "midtunit.h"
|
||||
#include "audio/dcs.h"
|
||||
#include "cpu/tms34010/tms34010.h"
|
||||
#include "machine/midwayic.h"
|
||||
#include "machine/nvram.h"
|
||||
#include "video/midtunit.h"
|
||||
#include "emupal.h"
|
||||
|
||||
|
||||
class midxunit_state : public midtunit_state
|
||||
class midxunit_state : public driver_device
|
||||
{
|
||||
public:
|
||||
midxunit_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: midtunit_state(mconfig, type, tag)
|
||||
: driver_device(mconfig, type, tag)
|
||||
, m_maincpu(*this, "maincpu")
|
||||
, m_video(*this, "video")
|
||||
, m_dcs(*this, "dcs")
|
||||
, m_palette(*this, "palette")
|
||||
, m_gfxrom(*this, "gfxrom")
|
||||
, m_nvram(*this, "nvram")
|
||||
, m_midway_serial_pic(*this, "serial_pic")
|
||||
, m_gun_recoil(*this, "Player%u_Gun_Recoil", 1U)
|
||||
@ -32,35 +41,40 @@ protected:
|
||||
virtual void machine_reset() override;
|
||||
|
||||
private:
|
||||
uint16_t midxunit_cmos_r(offs_t offset);
|
||||
void midxunit_cmos_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint8_t midxunit_cmos_r(offs_t offset);
|
||||
void midxunit_cmos_w(offs_t offset, uint8_t data);
|
||||
void midxunit_io_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void midxunit_unknown_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
DECLARE_WRITE_LINE_MEMBER(adc_int_w);
|
||||
uint16_t midxunit_status_r();
|
||||
uint16_t midxunit_uart_r(offs_t offset);
|
||||
void midxunit_uart_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint8_t midxunit_uart_r(offs_t offset);
|
||||
void midxunit_uart_w(offs_t offset, uint8_t data);
|
||||
uint16_t midxunit_security_r();
|
||||
void midxunit_security_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void midxunit_security_clock_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t midxunit_sound_r();
|
||||
uint16_t midxunit_sound_state_r();
|
||||
void midxunit_sound_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
DECLARE_WRITE_LINE_MEMBER(midxunit_dcs_output_full);
|
||||
uint32_t midxunit_dma_r(offs_t offset, uint32_t mem_mask = ~0);
|
||||
void midxunit_dma_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
|
||||
void main_map(address_map &map);
|
||||
|
||||
required_shared_ptr<uint16_t> m_nvram;
|
||||
required_device<tms340x0_device> m_maincpu;
|
||||
required_device<midtunit_video_device> m_video;
|
||||
required_device<dcs_audio_device> m_dcs;
|
||||
required_device<palette_device> m_palette;
|
||||
required_memory_region m_gfxrom;
|
||||
|
||||
required_device<nvram_device> m_nvram;
|
||||
required_device<midway_serial_pic_device> m_midway_serial_pic;
|
||||
output_finder<3> m_gun_recoil;
|
||||
output_finder<3> m_gun_led;
|
||||
|
||||
uint8_t m_cmos_write_enable;
|
||||
uint16_t m_iodata[8];
|
||||
uint8_t m_ioshuffle[16];
|
||||
uint8_t m_uart[8];
|
||||
uint8_t m_security_bits;
|
||||
bool m_adc_int;
|
||||
std::unique_ptr<uint8_t[]> m_nvram_data;
|
||||
};
|
||||
|
||||
#endif // MAME_INCLUDES_MIDXUNIT_H
|
||||
|
||||
@ -7,10 +7,6 @@
|
||||
**************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
#include "cpu/tms34010/tms34010.h"
|
||||
#include "cpu/m6809/m6809.h"
|
||||
#include "audio/dcs.h"
|
||||
#include "includes/midtunit.h"
|
||||
#include "includes/midwunit.h"
|
||||
|
||||
#define LOG_UNKNOWN (1 << 0)
|
||||
@ -165,7 +161,7 @@ void midwunit_state::machine_start()
|
||||
/********************** Mortal Kombat 3 **********************/
|
||||
|
||||
|
||||
void midwunit_state::umk3_palette_hack_w(address_space &space, offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void midwunit_state::umk3_palette_hack_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
/*
|
||||
UMK3 uses a circular buffer to hold pending palette changes; the buffer holds 17 entries
|
||||
@ -186,7 +182,7 @@ void midwunit_state::umk3_palette_hack_w(address_space &space, offs_t offset, ui
|
||||
without significantly impacting the rest of the system.
|
||||
*/
|
||||
COMBINE_DATA(&m_umk3_palette[offset]);
|
||||
space.device().execute().adjust_icount(-100);
|
||||
m_maincpu->adjust_icount(-100);
|
||||
/* printf("in=%04X%04X out=%04X%04X\n", m_umk3_palette[3], m_umk3_palette[2], m_umk3_palette[1], m_umk3_palette[0]); */
|
||||
}
|
||||
|
||||
@ -214,14 +210,14 @@ void midwunit_state::init_mk3r10()
|
||||
void midwunit_state::init_umk3()
|
||||
{
|
||||
init_mk3_common();
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0106a060, 0x0106a09f, write16_delegate(*this, FUNC(midwunit_state::umk3_palette_hack_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0106a060, 0x0106a09f, write16s_delegate(*this, FUNC(midwunit_state::umk3_palette_hack_w)));
|
||||
m_umk3_palette = m_mainram + (0x6a060>>4);
|
||||
}
|
||||
|
||||
void midwunit_state::init_umk3r11()
|
||||
{
|
||||
init_mk3_common();
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0106a060, 0x0106a09f, write16_delegate(*this, FUNC(midwunit_state::umk3_palette_hack_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0106a060, 0x0106a09f, write16s_delegate(*this, FUNC(midwunit_state::umk3_palette_hack_w)));
|
||||
m_umk3_palette = m_mainram + (0x6a060>>4);
|
||||
}
|
||||
|
||||
|
||||
@ -7,12 +7,7 @@
|
||||
**************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
#include "cpu/tms34010/tms34010.h"
|
||||
#include "cpu/m6809/m6809.h"
|
||||
#include "audio/dcs.h"
|
||||
#include "includes/midtunit.h"
|
||||
#include "includes/midxunit.h"
|
||||
#include "midwayic.h"
|
||||
|
||||
#define LOG_IO (1 << 0)
|
||||
#define LOG_UART (1 << 1)
|
||||
@ -29,14 +24,14 @@
|
||||
*
|
||||
*************************************/
|
||||
|
||||
uint16_t midxunit_state::midxunit_cmos_r(offs_t offset)
|
||||
uint8_t midxunit_state::midxunit_cmos_r(offs_t offset)
|
||||
{
|
||||
return m_nvram[offset];
|
||||
return m_nvram_data[offset];
|
||||
}
|
||||
|
||||
void midxunit_state::midxunit_cmos_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void midxunit_state::midxunit_cmos_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
COMBINE_DATA(m_nvram+offset);
|
||||
m_nvram_data[offset] = data;
|
||||
}
|
||||
|
||||
|
||||
@ -127,14 +122,9 @@ WRITE_LINE_MEMBER(midxunit_state::midxunit_dcs_output_full)
|
||||
}
|
||||
|
||||
|
||||
uint16_t midxunit_state::midxunit_uart_r(offs_t offset)
|
||||
uint8_t midxunit_state::midxunit_uart_r(offs_t offset)
|
||||
{
|
||||
int result = 0;
|
||||
|
||||
/* convert to a byte offset */
|
||||
if (offset & 1)
|
||||
return 0;
|
||||
offset /= 2;
|
||||
uint8_t result = 0;
|
||||
|
||||
/* switch off the offset */
|
||||
switch (offset)
|
||||
@ -152,7 +142,7 @@ uint16_t midxunit_state::midxunit_uart_r(offs_t offset)
|
||||
/* non-loopback case: bit 0 means data ready, bit 2 means ok to send */
|
||||
else
|
||||
{
|
||||
int temp = midxunit_sound_state_r();
|
||||
int temp = m_dcs->control_r();
|
||||
result |= (temp & 0x800) >> 9;
|
||||
result |= (~temp & 0x400) >> 10;
|
||||
machine().scheduler().synchronize();
|
||||
@ -167,7 +157,11 @@ uint16_t midxunit_state::midxunit_uart_r(offs_t offset)
|
||||
|
||||
/* non-loopback case: read from the DCS system */
|
||||
else
|
||||
result = midxunit_sound_r();
|
||||
{
|
||||
LOGMASKED(LOG_SOUND, "%08X:Sound read\n", m_maincpu->pc());
|
||||
|
||||
result = m_dcs->data_r();
|
||||
}
|
||||
break;
|
||||
|
||||
case 5: /* register 5 seems to be like 3, but with in/out swapped */
|
||||
@ -179,7 +173,7 @@ uint16_t midxunit_state::midxunit_uart_r(offs_t offset)
|
||||
/* non-loopback case: bit 0 means data ready, bit 2 means ok to send */
|
||||
else
|
||||
{
|
||||
int temp = midxunit_sound_state_r();
|
||||
int temp = m_dcs->control_r();
|
||||
result |= (temp & 0x800) >> 11;
|
||||
result |= (~temp & 0x400) >> 8;
|
||||
machine().scheduler().synchronize();
|
||||
@ -196,14 +190,8 @@ uint16_t midxunit_state::midxunit_uart_r(offs_t offset)
|
||||
}
|
||||
|
||||
|
||||
void midxunit_state::midxunit_uart_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void midxunit_state::midxunit_uart_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
/* convert to a byte offset, ignoring MSB writes */
|
||||
if ((offset & 1) || !ACCESSING_BITS_0_7)
|
||||
return;
|
||||
offset /= 2;
|
||||
data &= 0xff;
|
||||
|
||||
/* switch off the offset */
|
||||
switch (offset)
|
||||
{
|
||||
@ -215,7 +203,7 @@ void midxunit_state::midxunit_uart_w(offs_t offset, uint16_t data, uint16_t mem_
|
||||
|
||||
/* non-loopback case: send to the DCS system */
|
||||
else
|
||||
midxunit_sound_w(0, data, mem_mask);
|
||||
m_dcs->data_w(data);
|
||||
break;
|
||||
|
||||
case 5: /* register 5 write seems to reset things */
|
||||
@ -253,12 +241,15 @@ void midxunit_state::machine_start()
|
||||
m_gun_recoil.resolve();
|
||||
m_gun_led.resolve();
|
||||
|
||||
m_nvram_data = std::make_unique<uint8_t[]>(0x2000);
|
||||
m_nvram->set_base(m_nvram_data.get(), 0x2000);
|
||||
|
||||
save_item(NAME(m_cmos_write_enable));
|
||||
save_item(NAME(m_iodata));
|
||||
save_item(NAME(m_ioshuffle));
|
||||
save_item(NAME(m_uart));
|
||||
save_item(NAME(m_security_bits));
|
||||
save_item(NAME(m_adc_int));
|
||||
save_pointer(NAME(m_nvram_data), 0x2000);
|
||||
}
|
||||
|
||||
void midxunit_state::machine_reset()
|
||||
@ -269,10 +260,6 @@ void midxunit_state::machine_reset()
|
||||
|
||||
m_security_bits = 0;
|
||||
|
||||
/* reset I/O shuffling */
|
||||
for (int i = 0; i < 16; i++)
|
||||
m_ioshuffle[i] = i % 8;
|
||||
|
||||
m_dcs->set_io_callbacks(write_line_delegate(*this, FUNC(midxunit_state::midxunit_dcs_output_full)), write_line_delegate(*this));
|
||||
}
|
||||
|
||||
@ -314,37 +301,27 @@ void midxunit_state::midxunit_security_clock_w(offs_t offset, uint16_t data, uin
|
||||
|
||||
/*************************************
|
||||
*
|
||||
* Sound write handlers
|
||||
* DMA registers (inverted word select)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
uint16_t midxunit_state::midxunit_sound_r()
|
||||
uint32_t midxunit_state::midxunit_dma_r(offs_t offset, uint32_t mem_mask)
|
||||
{
|
||||
LOGMASKED(LOG_SOUND, "%08X:Sound read\n", m_maincpu->pc());
|
||||
uint32_t result = 0;
|
||||
|
||||
return m_dcs->data_r() & 0xff;
|
||||
if (ACCESSING_BITS_0_15)
|
||||
result |= uint32_t(m_video->midtunit_dma_r(offset * 2 + 1)) << 16;
|
||||
if (ACCESSING_BITS_16_31)
|
||||
result |= m_video->midtunit_dma_r(offset * 2);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
uint16_t midxunit_state::midxunit_sound_state_r()
|
||||
void midxunit_state::midxunit_dma_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
return m_dcs->control_r();
|
||||
}
|
||||
|
||||
|
||||
void midxunit_state::midxunit_sound_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
/* check for out-of-bounds accesses */
|
||||
if (offset)
|
||||
{
|
||||
LOGMASKED(LOG_SOUND | LOG_UNKNOWN, "%s: Unexpected write to sound (hi) = %04X\n", machine().describe_context(), data);
|
||||
return;
|
||||
}
|
||||
|
||||
/* call through based on the sound type */
|
||||
if (ACCESSING_BITS_0_7)
|
||||
{
|
||||
LOGMASKED(LOG_SOUND, "%s: Sound write = %04X\n", machine().describe_context(), data);
|
||||
m_dcs->data_w(data & 0xff);
|
||||
}
|
||||
if (ACCESSING_BITS_0_15)
|
||||
m_video->midtunit_dma_w(offset * 2 + 1, data >> 16);
|
||||
if (ACCESSING_BITS_16_31)
|
||||
m_video->midtunit_dma_w(offset * 2, data & 0xffff);
|
||||
}
|
||||
|
||||
@ -119,25 +119,6 @@ void btoads_state::scroll1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
|
||||
|
||||
|
||||
/*************************************
|
||||
*
|
||||
* Palette RAM
|
||||
*
|
||||
*************************************/
|
||||
|
||||
void btoads_state::paletteram_w(offs_t offset, uint16_t data)
|
||||
{
|
||||
m_tlc34076->write(offset/2, data);
|
||||
}
|
||||
|
||||
|
||||
uint16_t btoads_state::paletteram_r(offs_t offset)
|
||||
{
|
||||
return m_tlc34076->read(offset/2);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*************************************
|
||||
*
|
||||
* Background video RAM
|
||||
|
||||
Loading…
Reference in New Issue
Block a user