diff --git a/src/emu/cpu/hcd62121/hcd62121.c b/src/emu/cpu/hcd62121/hcd62121.c index d579f560fea..d8b610783bb 100644 --- a/src/emu/cpu/hcd62121/hcd62121.c +++ b/src/emu/cpu/hcd62121/hcd62121.c @@ -15,28 +15,6 @@ Martin Poupe's site can be found at http://martin.poupe.org/casio/ #include "hcd62121.h" -struct hcd62121_state -{ - UINT32 prev_pc; - UINT16 sp; - UINT16 ip; - UINT8 dsize; - UINT8 cseg; - UINT8 dseg; - UINT8 sseg; - UINT8 f; - UINT16 lar; - UINT8 reg[0x80]; - UINT8 temp1[0x10]; - UINT8 temp2[0x10]; - device_irq_acknowledge_callback irq_callback; - legacy_cpu_device *device; - address_space *program; - address_space *io; - int icount; -}; - - /* From the battery check routine at 20:e874 it looks like bit 3 of the flag register should be the Zero flag. */ #define _FLAG_Z 0x08 @@ -46,21 +24,26 @@ struct hcd62121_state #define _FLAG_ZH 0x10 -#define mem_readbyte(cs,A) ((UINT8)(cs)->program->read_byte(A)) -#define mem_writebyte(cs,A,V) ((cs)->program->write_byte(A,V)) -#define io_readbyte(cs,A) ((UINT8)(cs)->io->read_byte(A)) -#define io_writebyte(cs,A,V) ((cs)->io->write_byte(A,V)) +const device_type HCD62121 = &device_creator; -INLINE UINT8 read_op(hcd62121_state *cpustate) +hcd62121_cpu_device::hcd62121_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : cpu_device(mconfig, HCD62121, "Hitachi HCD62121", tag, owner, clock) + , m_program_config("program", ENDIANNESS_BIG, 8, 24, 0) + , m_io_config("io", ENDIANNESS_BIG, 8, 8, 0) { - UINT8 d = mem_readbyte(cpustate, ( cpustate->cseg << 16 ) | cpustate->ip ); - cpustate->ip++; +} + + +UINT8 hcd62121_cpu_device::read_op() +{ + UINT8 d = m_program->read_byte( ( m_cseg << 16 ) | m_ip ); + m_ip++; return d; } -INLINE UINT8 datasize( hcd62121_state *cpustate, UINT8 op ) +UINT8 hcd62121_cpu_device::datasize( UINT8 op ) { switch( op & 0x03 ) { @@ -69,67 +52,67 @@ INLINE UINT8 datasize( hcd62121_state *cpustate, UINT8 op ) case 1: return 2; case 2: - return ( cpustate->dsize >> 4 ) + 1; + return ( m_dsize >> 4 ) + 1; case 3: - return ( cpustate->dsize & 0x0f ) + 1; + return ( m_dsize & 0x0f ) + 1; } return 1; } -INLINE void read_reg( hcd62121_state *cpustate, int size, UINT8 op1 ) +void hcd62121_cpu_device::read_reg( int size, UINT8 op1 ) { int i; if ( op1 & 0x80 ) { for ( i = 0; i < size; i++ ) - cpustate->temp1[i] = cpustate->reg[ ( op1 - i ) & 0x7f ]; + m_temp1[i] = m_reg[ ( op1 - i ) & 0x7f ]; } else { for ( i = 0; i < size; i++ ) - cpustate->temp1[i] = cpustate->reg[ ( op1 + i ) & 0x7f ]; + m_temp1[i] = m_reg[ ( op1 + i ) & 0x7f ]; } } -INLINE void write_reg( hcd62121_state *cpustate, int size, UINT8 op1 ) +void hcd62121_cpu_device::write_reg( int size, UINT8 op1 ) { int i; if ( op1 & 0x80 ) { for ( i = 0; i < size; i++ ) - cpustate->reg[ ( op1 - i ) & 0x7f ] = cpustate->temp1[i]; + m_reg[ ( op1 - i ) & 0x7f ] = m_temp1[i]; } else { for ( i = 0; i < size; i++ ) - cpustate->reg[ ( op1 + i ) & 0x7f ] = cpustate->temp1[i]; + m_reg[ ( op1 + i ) & 0x7f ] = m_temp1[i]; } } -INLINE void read_regreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2, bool op_is_logical ) +void hcd62121_cpu_device::read_regreg( int size, UINT8 op1, UINT8 op2, bool op_is_logical ) { int i; for ( i = 0; i < size; i++ ) - cpustate->temp1[i] = cpustate->reg[ (op1 + i) & 0x7f]; + m_temp1[i] = m_reg[ (op1 + i) & 0x7f]; if ( op1 & 0x80 ) { /* Second operand is an immediate value */ - cpustate->temp2[0] = op2; + m_temp2[0] = op2; for ( i = 1; i < size; i++ ) - cpustate->temp2[i] = op_is_logical ? op2 : 0; + m_temp2[i] = op_is_logical ? op2 : 0; } else { /* Second operand is a register */ for ( i = 0; i < size; i++ ) - cpustate->temp2[i] = cpustate->reg[ (op2 + i) & 0x7f ]; + m_temp2[i] = m_reg[ (op2 + i) & 0x7f ]; } if ( ! ( op1 & 0x80 ) && ! ( op2 & 0x80 ) ) @@ -137,15 +120,15 @@ INLINE void read_regreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op /* We need to swap parameters */ for ( i = 0; i < size; i++ ) { - UINT8 v = cpustate->temp1[i]; - cpustate->temp1[i] = cpustate->temp2[i]; - cpustate->temp2[i] = v; + UINT8 v = m_temp1[i]; + m_temp1[i] = m_temp2[i]; + m_temp2[i] = v; } } } -INLINE void write_regreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 ) +void hcd62121_cpu_device::write_regreg( int size, UINT8 op1, UINT8 op2 ) { int i; @@ -153,41 +136,41 @@ INLINE void write_regreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 o { /* store in reg1 */ for ( i = 0; i < size; i++ ) - cpustate->reg[ (op1 + i) & 0x7f] = cpustate->temp1[i]; + m_reg[ (op1 + i) & 0x7f] = m_temp1[i]; } else { /* store in reg2 */ for ( i = 0; i < size; i++ ) - cpustate->reg[ (op2 + i) & 0x7f] = cpustate->temp1[i]; + m_reg[ (op2 + i) & 0x7f] = m_temp1[i]; } } -INLINE void read_iregreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 ) +void hcd62121_cpu_device::read_iregreg( int size, UINT8 op1, UINT8 op2 ) { int i; UINT16 ad; - ad = cpustate->reg[ ( 0x40 | op1 ) & 0x7f ] | ( cpustate->reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 ); + ad = m_reg[ ( 0x40 | op1 ) & 0x7f ] | ( m_reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 ); for ( i = 0; i < size; i++ ) { - cpustate->temp1[i] = mem_readbyte( cpustate, ( cpustate->dseg << 16 ) | ad ); + m_temp1[i] = m_program->read_byte( ( m_dseg << 16 ) | ad ); ad += ( op1 & 0x40 ) ? -1 : 1; } - cpustate->lar = ad; + m_lar = ad; if ( op1 & 0x80 ) { - cpustate->temp2[0] = op2; + m_temp2[0] = op2; for ( i = 1; i < size; i++ ) - cpustate->temp2[i] = 0; + m_temp2[i] = 0; } else { for ( i = 0; i < size; i++ ) - cpustate->temp2[i] = cpustate->reg[ (op2 + i) & 0x7f ]; + m_temp2[i] = m_reg[ (op2 + i) & 0x7f ]; } if ( ! ( op1 & 0x80 ) && ! ( op2 & 0x80 ) ) @@ -195,40 +178,40 @@ INLINE void read_iregreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 o /* We need to swap parameters */ for ( i = 0; i < size; i++ ) { - UINT8 v = cpustate->temp1[i]; - cpustate->temp1[i] = cpustate->temp2[i]; - cpustate->temp2[i] = v; + UINT8 v = m_temp1[i]; + m_temp1[i] = m_temp2[i]; + m_temp2[i] = v; } } } -INLINE void write_iregreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 ) +void hcd62121_cpu_device::write_iregreg( int size, UINT8 op1, UINT8 op2 ) { int i; if ( ( op1 & 0x80 ) || ( op2 & 0x80 ) ) { /* store in (reg1) */ - UINT16 ad = cpustate->reg[ ( 0x40 | op1 ) & 0x7f ] | ( cpustate->reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 ); + UINT16 ad = m_reg[ ( 0x40 | op1 ) & 0x7f ] | ( m_reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 ); for ( i = 0; i < size; i++ ) { - mem_writebyte( cpustate, ( cpustate->dseg << 16 ) | ad, cpustate->temp1[i] ); + m_program->write_byte( ( m_dseg << 16 ) | ad, m_temp1[i] ); ad += ( op1 & 0x40 ) ? -1 : 1; } - cpustate->lar = ad; + m_lar = ad; } else { /* store in reg2 */ for ( i = 0; i < size; i++ ) - cpustate->reg[ (op2 + i) & 0x7f] = cpustate->temp1[i]; + m_reg[ (op2 + i) & 0x7f] = m_temp1[i]; } } -INLINE void write_iregreg2( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 ) +void hcd62121_cpu_device::write_iregreg2( int size, UINT8 op1, UINT8 op2 ) { int i; @@ -236,64 +219,64 @@ INLINE void write_iregreg2( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 { /* store in reg2 */ for ( i = 0; i < size; i++ ) - cpustate->reg[ (op2 + i) & 0x7f] = cpustate->temp2[i]; + m_reg[ (op2 + i) & 0x7f] = m_temp2[i]; } else { /* store in (reg1) */ - UINT16 ad = cpustate->reg[ ( 0x40 | op1 ) & 0x7f ] | ( cpustate->reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 ); + UINT16 ad = m_reg[ ( 0x40 | op1 ) & 0x7f ] | ( m_reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 ); for ( i = 0; i < size; i++ ) { - mem_writebyte( cpustate, ( cpustate->dseg << 16 ) | ad, cpustate->temp2[i] ); + m_program->write_byte( ( m_dseg << 16 ) | ad, m_temp2[i] ); ad += ( op1 & 0x40 ) ? -1 : 1; } - cpustate->lar = ad; + m_lar = ad; } } -INLINE int check_cond( hcd62121_state *cpustate, UINT8 op ) +int hcd62121_cpu_device::check_cond( UINT8 op ) { switch ( op & 0x07 ) { case 0x00: /* ZH set */ - if ( cpustate->f & _FLAG_ZH ) + if ( m_f & _FLAG_ZH ) return 1; break; case 0x01: /* ZL set */ - if ( cpustate->f & _FLAG_ZL ) + if ( m_f & _FLAG_ZL ) return 1; break; case 0x02: /* C set */ - if ( cpustate->f & _FLAG_C ) + if ( m_f & _FLAG_C ) return 1; break; case 0x03: /* Z set */ - if ( cpustate->f & _FLAG_Z ) + if ( m_f & _FLAG_Z ) return 1; break; case 0x04: /* Z or C set */ - if ( cpustate->f & ( _FLAG_Z | _FLAG_C ) ) + if ( m_f & ( _FLAG_Z | _FLAG_C ) ) return 1; break; case 0x05: /* CL set */ - if ( cpustate->f & _FLAG_CL ) + if ( m_f & _FLAG_CL ) return 1; break; case 0x06: /* C clear */ - if ( ! ( cpustate->f & _FLAG_C ) ) + if ( ! ( m_f & _FLAG_C ) ) return 1; break; case 0x07: /* Z clear */ - if ( ! ( cpustate->f & _FLAG_Z ) ) + if ( ! ( m_f & _FLAG_Z ) ) return 1; break; } @@ -302,208 +285,238 @@ INLINE int check_cond( hcd62121_state *cpustate, UINT8 op ) } -INLINE hcd62121_state *get_safe_token(device_t *device) +void hcd62121_cpu_device::device_start() { - assert(device != NULL); - assert(device->type() == HCD62121); - return (hcd62121_state *)downcast(device)->token(); +// m_irq_callback = irqcallback; + m_program = &space(AS_PROGRAM); + m_io = &space(AS_IO); + + save_item( NAME(m_prev_pc) ); + save_item( NAME(m_sp) ); + save_item( NAME(m_ip) ); + save_item( NAME(m_dsize) ); + save_item( NAME(m_cseg) ); + save_item( NAME(m_dseg) ); + save_item( NAME(m_sseg) ); + save_item( NAME(m_f) ); + save_item( NAME(m_lar) ); + save_item( NAME(m_reg) ); + save_item( NAME(m_temp1) ); + save_item( NAME(m_temp2) ); + + // Register state for debugger + state_add( STATE_GENPC, "curpc", m_ip ).callimport().callexport().formatstr("%8s"); + state_add( STATE_GENFLAGS, "GENFLAGS", m_f ).callimport().callexport().formatstr("%12s").noshow(); + + state_add( HCD62121_IP, "IP", m_ip ).callimport().callexport().formatstr("%04X"); + state_add( HCD62121_SP, "SP", m_sp ).callimport().callexport().formatstr("%04X"); + state_add( HCD62121_LAR, "LAR", m_lar ).callimport().callexport().formatstr("%04X"); + state_add( HCD62121_CS, "CS", m_cseg ).callimport().callexport().formatstr("%02X"); + state_add( HCD62121_DS, "DS", m_dseg ).callimport().callexport().formatstr("%02X"); + state_add( HCD62121_SS, "SS", m_sseg ).callimport().callexport().formatstr("%02X"); + state_add( HCD62121_DSIZE, "DSIZE", m_dsize ).callimport().callexport().formatstr("%02X"); + state_add( HCD62121_F, "F", m_f ).callimport().callexport().formatstr("%02X"); + + state_add( HCD62121_R00, "R00", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R04, "R04", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R08, "R08", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R0C, "R0C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R10, "R10", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R14, "R14", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R18, "R18", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R1C, "R1C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R20, "R20", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R24, "R24", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R28, "R28", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R2C, "R2C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R30, "R30", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R34, "R34", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R38, "R38", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R3C, "R3C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R40, "R40", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R44, "R44", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R48, "R48", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R4C, "R4C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R50, "R50", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R54, "R54", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R58, "R58", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R5C, "R5C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R60, "R60", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R64, "R64", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R68, "R68", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R6C, "R6C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R70, "R70", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R74, "R74", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R78, "R78", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + state_add( HCD62121_R7C, "R7C", m_reg[0x00] ).callimport().callexport().formatstr("%8s"); + + m_icountptr = &m_icount; } -static CPU_INIT( hcd62121 ) +void hcd62121_cpu_device::state_string_export(const device_state_entry &entry, astring &string) { - hcd62121_state *cpustate = get_safe_token(device); - - cpustate->irq_callback = irqcallback; - cpustate->device = device; - cpustate->program = &device->space(AS_PROGRAM); - cpustate->io = &device->space(AS_IO); -} - - -static CPU_RESET( hcd62121 ) -{ - hcd62121_state *cpustate = get_safe_token(device); - - cpustate->sp = 0x0000; - cpustate->ip = 0x0000; - cpustate->cseg = 0; - cpustate->dseg = 0; - cpustate->sseg = 0; - cpustate->lar = 0; - cpustate->f = 0; - cpustate->dsize = 0; - - for( int i = 0; i < 0x80; i++ ) + switch (entry.index()) { - cpustate->reg[i] = 0; + case STATE_GENPC: + string.printf("%06X", ( m_cseg << 16 ) | m_ip); + break; + + case STATE_GENFLAGS: + string.printf("%s-%s-%s-%c-%c", + m_f & _FLAG_ZH ? "ZH":"__", + m_f & _FLAG_CL ? "CL":"__", + m_f & _FLAG_ZL ? "ZL":"__", + m_f & _FLAG_C ? 'C':'_', + m_f & _FLAG_Z ? 'Z':'_' + ); + + break; + + case HCD62121_R00: + string.printf("%02X%02X%02X%02X", m_reg[0x00], m_reg[0x01], m_reg[0x02], m_reg[0x03]); + break; + case HCD62121_R04: + string.printf("%02X%02X%02X%02X", m_reg[0x04], m_reg[0x05], m_reg[0x06], m_reg[0x07]); + break; + case HCD62121_R08: + string.printf("%02X%02X%02X%02X", m_reg[0x08], m_reg[0x09], m_reg[0x0A], m_reg[0x0B]); + break; + case HCD62121_R0C: + string.printf("%02X%02X%02X%02X", m_reg[0x0C], m_reg[0x0D], m_reg[0x0E], m_reg[0x0F]); + break; + case HCD62121_R10: + string.printf("%02X%02X%02X%02X", m_reg[0x10], m_reg[0x11], m_reg[0x12], m_reg[0x13]); + break; + case HCD62121_R14: + string.printf("%02X%02X%02X%02X", m_reg[0x14], m_reg[0x15], m_reg[0x16], m_reg[0x17]); + break; + case HCD62121_R18: + string.printf("%02X%02X%02X%02X", m_reg[0x18], m_reg[0x19], m_reg[0x1A], m_reg[0x1B]); + break; + case HCD62121_R1C: + string.printf("%02X%02X%02X%02X", m_reg[0x1C], m_reg[0x1D], m_reg[0x1E], m_reg[0x1F]); + break; + case HCD62121_R20: + string.printf("%02X%02X%02X%02X", m_reg[0x20], m_reg[0x21], m_reg[0x22], m_reg[0x23]); + break; + case HCD62121_R24: + string.printf("%02X%02X%02X%02X", m_reg[0x24], m_reg[0x25], m_reg[0x26], m_reg[0x27]); + break; + case HCD62121_R28: + string.printf("%02X%02X%02X%02X", m_reg[0x28], m_reg[0x29], m_reg[0x2A], m_reg[0x2B]); + break; + case HCD62121_R2C: + string.printf("%02X%02X%02X%02X", m_reg[0x2C], m_reg[0x2D], m_reg[0x2E], m_reg[0x2F]); + break; + case HCD62121_R30: + string.printf("%02X%02X%02X%02X", m_reg[0x30], m_reg[0x31], m_reg[0x32], m_reg[0x33]); + break; + case HCD62121_R34: + string.printf("%02X%02X%02X%02X", m_reg[0x34], m_reg[0x35], m_reg[0x36], m_reg[0x37]); + break; + case HCD62121_R38: + string.printf("%02X%02X%02X%02X", m_reg[0x38], m_reg[0x39], m_reg[0x3A], m_reg[0x3B]); + break; + case HCD62121_R3C: + string.printf("%02X%02X%02X%02X", m_reg[0x3C], m_reg[0x3D], m_reg[0x3E], m_reg[0x3F]); + break; + case HCD62121_R40: + string.printf("%02X%02X%02X%02X", m_reg[0x40], m_reg[0x41], m_reg[0x42], m_reg[0x43]); + break; + case HCD62121_R44: + string.printf("%02X%02X%02X%02X", m_reg[0x44], m_reg[0x45], m_reg[0x46], m_reg[0x47]); + break; + case HCD62121_R48: + string.printf("%02X%02X%02X%02X", m_reg[0x48], m_reg[0x49], m_reg[0x4A], m_reg[0x4B]); + break; + case HCD62121_R4C: + string.printf("%02X%02X%02X%02X", m_reg[0x4C], m_reg[0x4D], m_reg[0x4E], m_reg[0x4F]); + break; + case HCD62121_R50: + string.printf("%02X%02X%02X%02X", m_reg[0x50], m_reg[0x51], m_reg[0x52], m_reg[0x53]); + break; + case HCD62121_R54: + string.printf("%02X%02X%02X%02X", m_reg[0x54], m_reg[0x55], m_reg[0x56], m_reg[0x57]); + break; + case HCD62121_R58: + string.printf("%02X%02X%02X%02X", m_reg[0x58], m_reg[0x59], m_reg[0x5A], m_reg[0x5B]); + break; + case HCD62121_R5C: + string.printf("%02X%02X%02X%02X", m_reg[0x5C], m_reg[0x5D], m_reg[0x5E], m_reg[0x5F]); + break; + case HCD62121_R60: + string.printf("%02X%02X%02X%02X", m_reg[0x60], m_reg[0x61], m_reg[0x62], m_reg[0x63]); + break; + case HCD62121_R64: + string.printf("%02X%02X%02X%02X", m_reg[0x64], m_reg[0x65], m_reg[0x66], m_reg[0x67]); + break; + case HCD62121_R68: + string.printf("%02X%02X%02X%02X", m_reg[0x68], m_reg[0x69], m_reg[0x6A], m_reg[0x6B]); + break; + case HCD62121_R6C: + string.printf("%02X%02X%02X%02X", m_reg[0x6C], m_reg[0x6D], m_reg[0x6E], m_reg[0x6F]); + break; + case HCD62121_R70: + string.printf("%02X%02X%02X%02X", m_reg[0x70], m_reg[0x71], m_reg[0x72], m_reg[0x73]); + break; + case HCD62121_R74: + string.printf("%02X%02X%02X%02X", m_reg[0x74], m_reg[0x75], m_reg[0x76], m_reg[0x77]); + break; + case HCD62121_R78: + string.printf("%02X%02X%02X%02X", m_reg[0x78], m_reg[0x79], m_reg[0x7A], m_reg[0x7B]); + break; + case HCD62121_R7C: + string.printf("%02X%02X%02X%02X", m_reg[0x7C], m_reg[0x7D], m_reg[0x7E], m_reg[0x7F]); + break; } } -static CPU_EXECUTE( hcd62121 ) +void hcd62121_cpu_device::device_reset() { - hcd62121_state *cpustate = get_safe_token(device); + m_sp = 0x0000; + m_ip = 0x0000; + m_cseg = 0; + m_dseg = 0; + m_sseg = 0; + m_lar = 0; + m_f = 0; + m_dsize = 0; + for( int i = 0; i < 0x80; i++ ) + { + m_reg[i] = 0; + } +} + + +void hcd62121_cpu_device::execute_run() +{ do { - UINT32 pc = ( cpustate->cseg << 16 ) | cpustate->ip; + UINT32 pc = ( m_cseg << 16 ) | m_ip; UINT8 op; - debugger_instruction_hook(device, pc); - cpustate->prev_pc = pc; + debugger_instruction_hook(this, pc); + m_prev_pc = pc; - op = read_op( cpustate ); + op = read_op(); - cpustate->icount -= 4; + m_icount -= 4; switch ( op ) { #include "hcd62121_ops.h" }; - } while (cpustate->icount > 0); + } while (m_icount > 0); } -static CPU_SET_INFO( hcd62121 ) +offs_t hcd62121_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { - hcd62121_state *cpustate = get_safe_token(device); - - switch (state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + 0: - case CPUINFO_INT_INPUT_STATE + 1: - break; - - case CPUINFO_INT_SP: cpustate->sp = info->i; break; - case CPUINFO_INT_PC: cpustate->ip = info->i; break; - - case CPUINFO_INT_REGISTER + HCD62121_IP: cpustate->ip = info->i; break; - case CPUINFO_INT_REGISTER + HCD62121_SP: cpustate->sp = info->i; break; - case CPUINFO_INT_REGISTER + HCD62121_LAR: cpustate->lar = info->i; break; - case CPUINFO_INT_REGISTER + HCD62121_CS: cpustate->cseg = info->i; break; - case CPUINFO_INT_REGISTER + HCD62121_DS: cpustate->dseg = info->i; break; - case CPUINFO_INT_REGISTER + HCD62121_SS: cpustate->sseg = info->i; break; - case CPUINFO_INT_REGISTER + HCD62121_DSIZE: cpustate->dsize = info->i; break; -// case CPUINFO_INT_REGISTER + HCD62121_R00: break; -// case CPUINFO_INT_REGISTER + HCD62121_R02: break; - } + extern CPU_DISASSEMBLE( hcd62121 ); + return CPU_DISASSEMBLE_NAME(hcd62121)(this, buffer, pc, oprom, opram, options); } - -CPU_GET_INFO( hcd62121 ) -{ - hcd62121_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hcd62121_state); break; - case CPUINFO_INT_INPUT_LINES: info->i = 2; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 18; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 4; /* right? */ break; - case CPUINFO_INT_MAX_CYCLES: info->i = 48; /* right? */ break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_SP: info->i = cpustate->sp; break; - case CPUINFO_INT_PC: info->i = ( cpustate->cseg << 16 ) | cpustate->ip; break; - case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->prev_pc; break; - - case CPUINFO_INT_INPUT_STATE + 0: - case CPUINFO_INT_INPUT_STATE + 1: - /* TODO */ break; - - case CPUINFO_INT_REGISTER + HCD62121_IP: info->i = cpustate->ip; break; - case CPUINFO_INT_REGISTER + HCD62121_SP: info->i = cpustate->sp; break; - case CPUINFO_INT_REGISTER + HCD62121_LAR: info->i = cpustate->lar; break; - case CPUINFO_INT_REGISTER + HCD62121_CS: info->i = cpustate->cseg; break; - case CPUINFO_INT_REGISTER + HCD62121_DS: info->i = cpustate->dseg; break; - case CPUINFO_INT_REGISTER + HCD62121_SS: info->i = cpustate->sseg; break; - case CPUINFO_INT_REGISTER + HCD62121_DSIZE: info->i = cpustate->dsize; break; - case CPUINFO_INT_REGISTER + HCD62121_R00: info->i = ( cpustate->reg[0x00] << 24 ) | ( cpustate->reg[0x01] << 16 ) | ( cpustate->reg[0x02] << 8 ) | cpustate->reg[0x03]; break; -// case CPUINFO_INT_REGISTER + HCD62121_R02: info->i = cpustate->; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(hcd62121); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(hcd62121); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(hcd62121); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(hcd62121); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(hcd62121); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "HCD62121"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Hitachi HCD62121"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "0.1"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright The MESS Team."); break; - - case CPUINFO_STR_FLAGS: - sprintf(info->s, "%s-%s-%s-%c-%c", - cpustate->f & _FLAG_ZH ? "ZH":"__", - cpustate->f & _FLAG_CL ? "CL":"__", - cpustate->f & _FLAG_ZL ? "ZL":"__", - cpustate->f & _FLAG_C ? 'C':'_', - cpustate->f & _FLAG_Z ? 'Z':'_' - ); - break; - - case CPUINFO_STR_REGISTER + HCD62121_IP: sprintf(info->s, "IP:%04X", cpustate->ip); break; - case CPUINFO_STR_REGISTER + HCD62121_SP: sprintf(info->s, "SP:%04X", cpustate->sp); break; - case CPUINFO_STR_REGISTER + HCD62121_LAR: sprintf(info->s, "LAR:%04X", cpustate->lar); break; - case CPUINFO_STR_REGISTER + HCD62121_CS: sprintf(info->s, "CS:%02X", cpustate->cseg); break; - case CPUINFO_STR_REGISTER + HCD62121_DS: sprintf(info->s, "DS:%02X", cpustate->dseg); break; - case CPUINFO_STR_REGISTER + HCD62121_SS: sprintf(info->s, "SS:%02X", cpustate->sseg); break; - case CPUINFO_STR_REGISTER + HCD62121_DSIZE: sprintf(info->s, "DSIZE:%02X", cpustate->dsize); break; - case CPUINFO_STR_REGISTER + HCD62121_R00: sprintf(info->s, "R00:%02X%02X%02X%02X", cpustate->reg[0x00], cpustate->reg[0x01], cpustate->reg[0x02], cpustate->reg[0x03]); break; - case CPUINFO_STR_REGISTER + HCD62121_R04: sprintf(info->s, "R04:%02X%02X%02X%02X", cpustate->reg[0x04], cpustate->reg[0x05], cpustate->reg[0x06], cpustate->reg[0x07]); break; - case CPUINFO_STR_REGISTER + HCD62121_R08: sprintf(info->s, "R08:%02X%02X%02X%02X", cpustate->reg[0x08], cpustate->reg[0x09], cpustate->reg[0x0a], cpustate->reg[0x0b]); break; - case CPUINFO_STR_REGISTER + HCD62121_R0C: sprintf(info->s, "R0C:%02X%02X%02X%02X", cpustate->reg[0x0c], cpustate->reg[0x0d], cpustate->reg[0x0e], cpustate->reg[0x0f]); break; - case CPUINFO_STR_REGISTER + HCD62121_R10: sprintf(info->s, "R10:%02X%02X%02X%02X", cpustate->reg[0x10], cpustate->reg[0x11], cpustate->reg[0x12], cpustate->reg[0x13]); break; - case CPUINFO_STR_REGISTER + HCD62121_R14: sprintf(info->s, "R14:%02X%02X%02X%02X", cpustate->reg[0x14], cpustate->reg[0x15], cpustate->reg[0x16], cpustate->reg[0x17]); break; - case CPUINFO_STR_REGISTER + HCD62121_R18: sprintf(info->s, "R18:%02X%02X%02X%02X", cpustate->reg[0x18], cpustate->reg[0x19], cpustate->reg[0x1a], cpustate->reg[0x1b]); break; - case CPUINFO_STR_REGISTER + HCD62121_R1C: sprintf(info->s, "R1C:%02X%02X%02X%02X", cpustate->reg[0x1c], cpustate->reg[0x1d], cpustate->reg[0x1e], cpustate->reg[0x1f]); break; - case CPUINFO_STR_REGISTER + HCD62121_R20: sprintf(info->s, "R20:%02X%02X%02X%02X", cpustate->reg[0x20], cpustate->reg[0x21], cpustate->reg[0x22], cpustate->reg[0x23]); break; - case CPUINFO_STR_REGISTER + HCD62121_R24: sprintf(info->s, "R24:%02X%02X%02X%02X", cpustate->reg[0x24], cpustate->reg[0x25], cpustate->reg[0x26], cpustate->reg[0x27]); break; - case CPUINFO_STR_REGISTER + HCD62121_R28: sprintf(info->s, "R28:%02X%02X%02X%02X", cpustate->reg[0x28], cpustate->reg[0x29], cpustate->reg[0x2a], cpustate->reg[0x2b]); break; - case CPUINFO_STR_REGISTER + HCD62121_R2C: sprintf(info->s, "R2C:%02X%02X%02X%02X", cpustate->reg[0x2c], cpustate->reg[0x2d], cpustate->reg[0x2e], cpustate->reg[0x2f]); break; - case CPUINFO_STR_REGISTER + HCD62121_R30: sprintf(info->s, "R30:%02X%02X%02X%02X", cpustate->reg[0x30], cpustate->reg[0x31], cpustate->reg[0x32], cpustate->reg[0x33]); break; - case CPUINFO_STR_REGISTER + HCD62121_R34: sprintf(info->s, "R34:%02X%02X%02X%02X", cpustate->reg[0x34], cpustate->reg[0x35], cpustate->reg[0x36], cpustate->reg[0x37]); break; - case CPUINFO_STR_REGISTER + HCD62121_R38: sprintf(info->s, "R38:%02X%02X%02X%02X", cpustate->reg[0x38], cpustate->reg[0x39], cpustate->reg[0x3a], cpustate->reg[0x3b]); break; - case CPUINFO_STR_REGISTER + HCD62121_R3C: sprintf(info->s, "R3C:%02X%02X%02X%02X", cpustate->reg[0x3c], cpustate->reg[0x3d], cpustate->reg[0x3e], cpustate->reg[0x3f]); break; - case CPUINFO_STR_REGISTER + HCD62121_R40: sprintf(info->s, "R40:%02X%02X%02X%02X", cpustate->reg[0x40], cpustate->reg[0x41], cpustate->reg[0x42], cpustate->reg[0x43]); break; - case CPUINFO_STR_REGISTER + HCD62121_R44: sprintf(info->s, "R44:%02X%02X%02X%02X", cpustate->reg[0x44], cpustate->reg[0x45], cpustate->reg[0x46], cpustate->reg[0x47]); break; - case CPUINFO_STR_REGISTER + HCD62121_R48: sprintf(info->s, "R48:%02X%02X%02X%02X", cpustate->reg[0x48], cpustate->reg[0x49], cpustate->reg[0x4a], cpustate->reg[0x4b]); break; - case CPUINFO_STR_REGISTER + HCD62121_R4C: sprintf(info->s, "R4C:%02X%02X%02X%02X", cpustate->reg[0x4c], cpustate->reg[0x4d], cpustate->reg[0x4e], cpustate->reg[0x4f]); break; - case CPUINFO_STR_REGISTER + HCD62121_R50: sprintf(info->s, "R50:%02X%02X%02X%02X", cpustate->reg[0x50], cpustate->reg[0x51], cpustate->reg[0x52], cpustate->reg[0x53]); break; - case CPUINFO_STR_REGISTER + HCD62121_R54: sprintf(info->s, "R54:%02X%02X%02X%02X", cpustate->reg[0x54], cpustate->reg[0x55], cpustate->reg[0x56], cpustate->reg[0x57]); break; - case CPUINFO_STR_REGISTER + HCD62121_R58: sprintf(info->s, "R58:%02X%02X%02X%02X", cpustate->reg[0x58], cpustate->reg[0x59], cpustate->reg[0x5a], cpustate->reg[0x5b]); break; - case CPUINFO_STR_REGISTER + HCD62121_R5C: sprintf(info->s, "R5C:%02X%02X%02X%02X", cpustate->reg[0x5c], cpustate->reg[0x5d], cpustate->reg[0x5e], cpustate->reg[0x5f]); break; - case CPUINFO_STR_REGISTER + HCD62121_R60: sprintf(info->s, "R60:%02X%02X%02X%02X", cpustate->reg[0x60], cpustate->reg[0x61], cpustate->reg[0x62], cpustate->reg[0x63]); break; - case CPUINFO_STR_REGISTER + HCD62121_R64: sprintf(info->s, "R64:%02X%02X%02X%02X", cpustate->reg[0x64], cpustate->reg[0x65], cpustate->reg[0x66], cpustate->reg[0x67]); break; - case CPUINFO_STR_REGISTER + HCD62121_R68: sprintf(info->s, "R68:%02X%02X%02X%02X", cpustate->reg[0x68], cpustate->reg[0x69], cpustate->reg[0x6a], cpustate->reg[0x6b]); break; - case CPUINFO_STR_REGISTER + HCD62121_R6C: sprintf(info->s, "R6C:%02X%02X%02X%02X", cpustate->reg[0x6c], cpustate->reg[0x6d], cpustate->reg[0x6e], cpustate->reg[0x6f]); break; - case CPUINFO_STR_REGISTER + HCD62121_R70: sprintf(info->s, "R70:%02X%02X%02X%02X", cpustate->reg[0x70], cpustate->reg[0x71], cpustate->reg[0x72], cpustate->reg[0x73]); break; - case CPUINFO_STR_REGISTER + HCD62121_R74: sprintf(info->s, "R74:%02X%02X%02X%02X", cpustate->reg[0x74], cpustate->reg[0x75], cpustate->reg[0x76], cpustate->reg[0x77]); break; - case CPUINFO_STR_REGISTER + HCD62121_R78: sprintf(info->s, "R78:%02X%02X%02X%02X", cpustate->reg[0x78], cpustate->reg[0x79], cpustate->reg[0x7a], cpustate->reg[0x7b]); break; - case CPUINFO_STR_REGISTER + HCD62121_R7C: sprintf(info->s, "R7C:%02X%02X%02X%02X", cpustate->reg[0x7c], cpustate->reg[0x7d], cpustate->reg[0x7e], cpustate->reg[0x7f]); break; - } -} - -DEFINE_LEGACY_CPU_DEVICE(HCD62121, hcd62121); diff --git a/src/emu/cpu/hcd62121/hcd62121.h b/src/emu/cpu/hcd62121/hcd62121.h index 43189d20622..3f49120e275 100644 --- a/src/emu/cpu/hcd62121/hcd62121.h +++ b/src/emu/cpu/hcd62121/hcd62121.h @@ -31,9 +31,68 @@ enum }; -DECLARE_LEGACY_CPU_DEVICE(HCD62121, hcd62121); +class hcd62121_cpu_device : public cpu_device +{ +public: + // construction/destruction + hcd62121_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 4; } + virtual UINT32 execute_max_cycles() const { return 48; } + virtual UINT32 execute_input_lines() const { return 2; } + virtual void execute_run(); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); } + + // device_state_interface overrides + void state_string_export(const device_state_entry &entry, astring &string); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 1; } + virtual UINT32 disasm_max_opcode_bytes() const { return 18; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + + UINT8 read_op(); + UINT8 datasize( UINT8 op ); + void read_reg( int size, UINT8 op1 ); + void write_reg( int size, UINT8 op1 ); + void read_regreg( int size, UINT8 op1, UINT8 op2, bool op_is_logical ); + void write_regreg( int size, UINT8 op1, UINT8 op2 ); + void read_iregreg( int size, UINT8 op1, UINT8 op2 ); + void write_iregreg( int size, UINT8 op1, UINT8 op2 ); + void write_iregreg2( int size, UINT8 op1, UINT8 op2 ); + int check_cond( UINT8 op ); + + address_space_config m_program_config; + address_space_config m_io_config; + + UINT32 m_prev_pc; + UINT16 m_sp; + UINT16 m_ip; + UINT8 m_dsize; + UINT8 m_cseg; + UINT8 m_dseg; + UINT8 m_sseg; + UINT8 m_f; + UINT16 m_lar; + UINT8 m_reg[0x80]; + UINT8 m_temp1[0x10]; + UINT8 m_temp2[0x10]; + + address_space *m_program; + address_space *m_io; + int m_icount; +}; -extern CPU_DISASSEMBLE( hcd62121 ); +extern const device_type HCD62121; + #endif /* __HCD62121_H__ */ diff --git a/src/emu/cpu/hcd62121/hcd62121_ops.h b/src/emu/cpu/hcd62121/hcd62121_ops.h index d4ded8f29f2..dedfeefd50a 100644 --- a/src/emu/cpu/hcd62121/hcd62121_ops.h +++ b/src/emu/cpu/hcd62121/hcd62121_ops.h @@ -6,14 +6,14 @@ \ for ( i = 0; i < size; i++ ) \ { \ - if ( ( cpustate->temp1[i] & cpustate->temp2[i] ) != cpustate->temp2[i] ) \ + if ( ( m_temp1[i] & m_temp2[i] ) != m_temp2[i] ) \ mskres = 0; \ } \ \ if ( mskres ) \ - cpustate->f &= ~_FLAG_Z; \ + m_f &= ~_FLAG_Z; \ else \ - cpustate->f |= _FLAG_Z; \ + m_f |= _FLAG_Z; \ } #define HCD62121_IMSK \ @@ -24,21 +24,21 @@ \ for ( i = 0; i < size; i++ ) \ { \ - if ( ( cpustate->temp1[i] & ~cpustate->temp2[i] ) != ~cpustate->temp2[i] ) \ + if ( ( m_temp1[i] & ~m_temp2[i] ) != ~m_temp2[i] ) \ mskres = 0; \ - if ( cpustate->temp1[i] | cpustate->temp2[i] ) \ + if ( m_temp1[i] | m_temp2[i] ) \ set_zero = 1; \ } \ \ if ( set_zero ) \ - cpustate->f |= _FLAG_Z; \ + m_f |= _FLAG_Z; \ else \ - cpustate->f &= ~_FLAG_Z; \ + m_f &= ~_FLAG_Z; \ \ if ( mskres ) \ - cpustate->f &= ~_FLAG_C; \ + m_f &= ~_FLAG_C; \ else \ - cpustate->f |= _FLAG_C; \ + m_f |= _FLAG_C; \ } @@ -49,25 +49,25 @@ \ for ( i = 0; i < size; i++ ) \ { \ - cpustate->temp1[i] = cpustate->temp1[i] & cpustate->temp2[i]; \ - if ( cpustate->temp1[i] ) \ + m_temp1[i] = m_temp1[i] & m_temp2[i]; \ + if ( m_temp1[i] ) \ is_zero = 0; \ } \ \ if ( is_zero ) \ - cpustate->f |= _FLAG_Z; \ + m_f |= _FLAG_Z; \ else \ - cpustate->f &= ~_FLAG_Z; \ + m_f &= ~_FLAG_Z; \ \ - if ( cpustate->temp1[0] & 0x0f ) \ - cpustate->f &= ~_FLAG_ZL; \ + if ( m_temp1[0] & 0x0f ) \ + m_f &= ~_FLAG_ZL; \ else \ - cpustate->f |= _FLAG_ZL; \ + m_f |= _FLAG_ZL; \ \ - if ( cpustate->temp1[0] & 0xf0 ) \ - cpustate->f &= ~_FLAG_ZH; \ + if ( m_temp1[0] & 0xf0 ) \ + m_f &= ~_FLAG_ZH; \ else \ - cpustate->f |= _FLAG_ZH; \ + m_f |= _FLAG_ZH; \ } #define HCD62121_OR \ @@ -77,25 +77,25 @@ \ for ( i = 0; i < size; i++ ) \ { \ - cpustate->temp1[i] = cpustate->temp1[i] | cpustate->temp2[i]; \ - if ( cpustate->temp1[i] ) \ + m_temp1[i] = m_temp1[i] | m_temp2[i]; \ + if ( m_temp1[i] ) \ is_zero = 0; \ } \ \ if ( is_zero ) \ - cpustate->f |= _FLAG_Z; \ + m_f |= _FLAG_Z; \ else \ - cpustate->f &= ~_FLAG_Z; \ + m_f &= ~_FLAG_Z; \ \ - if ( cpustate->temp1[0] & 0x0f ) \ - cpustate->f &= ~_FLAG_ZL; \ + if ( m_temp1[0] & 0x0f ) \ + m_f &= ~_FLAG_ZL; \ else \ - cpustate->f |= _FLAG_ZL; \ + m_f |= _FLAG_ZL; \ \ - if ( cpustate->temp1[0] & 0xf0 ) \ - cpustate->f &= ~_FLAG_ZH; \ + if ( m_temp1[0] & 0xf0 ) \ + m_f &= ~_FLAG_ZH; \ else \ - cpustate->f |= _FLAG_ZH; \ + m_f |= _FLAG_ZH; \ } #define HCD62121_XOR \ @@ -105,25 +105,25 @@ \ for ( i = 0; i < size; i++ ) \ { \ - cpustate->temp1[i] = cpustate->temp1[i] ^ cpustate->temp2[i]; \ - if ( cpustate->temp1[i] ) \ + m_temp1[i] = m_temp1[i] ^ m_temp2[i]; \ + if ( m_temp1[i] ) \ is_zero = 0; \ } \ \ if ( is_zero ) \ - cpustate->f |= _FLAG_Z; \ + m_f |= _FLAG_Z; \ else \ - cpustate->f &= ~_FLAG_Z; \ + m_f &= ~_FLAG_Z; \ \ - if ( cpustate->temp1[0] & 0x0f ) \ - cpustate->f &= ~_FLAG_ZL; \ + if ( m_temp1[0] & 0x0f ) \ + m_f &= ~_FLAG_ZL; \ else \ - cpustate->f |= _FLAG_ZL; \ + m_f |= _FLAG_ZL; \ \ - if ( cpustate->temp1[0] & 0xf0 ) \ - cpustate->f &= ~_FLAG_ZH; \ + if ( m_temp1[0] & 0xf0 ) \ + m_f &= ~_FLAG_ZH; \ else \ - cpustate->f |= _FLAG_ZH; \ + m_f |= _FLAG_ZH; \ } #define HCD62121_ADD \ @@ -131,41 +131,41 @@ int i; \ UINT8 is_zero = 1, carry = 0; \ \ - if ( ( cpustate->temp1[0] & 0x0f ) + ( cpustate->temp2[0] & 0x0f ) > 15 ) \ - cpustate->f |= _FLAG_CL; \ + if ( ( m_temp1[0] & 0x0f ) + ( m_temp2[0] & 0x0f ) > 15 ) \ + m_f |= _FLAG_CL; \ else \ - cpustate->f &= ~_FLAG_CL; \ + m_f &= ~_FLAG_CL; \ \ for ( i = 0; i < size; i++ ) \ { \ - UINT16 res = cpustate->temp1[i] + cpustate->temp2[i] + carry; \ + UINT16 res = m_temp1[i] + m_temp2[i] + carry; \ \ - cpustate->temp1[i] = res & 0xff; \ - if ( cpustate->temp1[i] ) \ + m_temp1[i] = res & 0xff; \ + if ( m_temp1[i] ) \ is_zero = 0; \ \ carry = ( res & 0xff00 ) ? 1 : 0; \ } \ \ if ( is_zero ) \ - cpustate->f |= _FLAG_Z; \ + m_f |= _FLAG_Z; \ else \ - cpustate->f &= ~_FLAG_Z; \ + m_f &= ~_FLAG_Z; \ \ if ( carry ) \ - cpustate->f |= _FLAG_C; \ + m_f |= _FLAG_C; \ else \ - cpustate->f &= ~_FLAG_C; \ + m_f &= ~_FLAG_C; \ \ - if ( cpustate->temp1[0] & 0x0f ) \ - cpustate->f &= ~_FLAG_ZL; \ + if ( m_temp1[0] & 0x0f ) \ + m_f &= ~_FLAG_ZL; \ else \ - cpustate->f |= _FLAG_ZL; \ + m_f |= _FLAG_ZL; \ \ - if ( cpustate->temp1[0] & 0xf0 ) \ - cpustate->f &= ~_FLAG_ZH; \ + if ( m_temp1[0] & 0xf0 ) \ + m_f &= ~_FLAG_ZH; \ else \ - cpustate->f |= _FLAG_ZH; \ + m_f |= _FLAG_ZH; \ } /* BCD ADD */ @@ -174,51 +174,51 @@ int i; \ UINT8 is_zero = 1, carry = 0; \ \ - if ( ( cpustate->temp1[0] & 0x0f ) + ( cpustate->temp2[0] & 0x0f ) > 9 ) \ - cpustate->f |= _FLAG_CL; \ + if ( ( m_temp1[0] & 0x0f ) + ( m_temp2[0] & 0x0f ) > 9 ) \ + m_f |= _FLAG_CL; \ else \ - cpustate->f &= ~_FLAG_CL; \ + m_f &= ~_FLAG_CL; \ \ for ( i = 0; i < size; i++ ) \ { \ - UINT16 res = ( cpustate->temp1[i] & 0x0f ) + ( cpustate->temp2[i] & 0x0f ) + carry; \ + UINT16 res = ( m_temp1[i] & 0x0f ) + ( m_temp2[i] & 0x0f ) + carry; \ \ carry = 0; \ if ( res > 9 ) \ { \ res += 6; \ } \ - res += ( cpustate->temp1[i] & 0xf0 ) + ( cpustate->temp2[i] & 0xf0 ); \ + res += ( m_temp1[i] & 0xf0 ) + ( m_temp2[i] & 0xf0 ); \ if ( res > 0x9f ) \ { \ res += 0x60; \ } \ - cpustate->temp1[i] = res & 0xff; \ - if ( cpustate->temp1[i] ) \ + m_temp1[i] = res & 0xff; \ + if ( m_temp1[i] ) \ is_zero = 0; \ \ carry = ( res & 0xff00 ) ? 1 : 0; \ } \ \ if ( is_zero ) \ - cpustate->f |= _FLAG_Z; \ + m_f |= _FLAG_Z; \ else \ - cpustate->f &= ~_FLAG_Z; \ + m_f &= ~_FLAG_Z; \ \ if ( carry ) \ - cpustate->f |= _FLAG_C; \ + m_f |= _FLAG_C; \ else \ - cpustate->f &= ~_FLAG_C; \ + m_f &= ~_FLAG_C; \ \ - if ( cpustate->temp1[0] & 0x0f ) \ - cpustate->f &= ~_FLAG_ZL; \ + if ( m_temp1[0] & 0x0f ) \ + m_f &= ~_FLAG_ZL; \ else \ - cpustate->f |= _FLAG_ZL; \ + m_f |= _FLAG_ZL; \ \ - if ( cpustate->temp1[0] & 0xf0 ) \ - cpustate->f &= ~_FLAG_ZH; \ + if ( m_temp1[0] & 0xf0 ) \ + m_f &= ~_FLAG_ZH; \ else \ - cpustate->f |= _FLAG_ZH; \ + m_f |= _FLAG_ZH; \ } #define HCD62121_SUB \ @@ -226,59 +226,59 @@ int i; \ UINT8 is_zero = 1, carry = 0; \ \ - if ( ( cpustate->temp1[0] & 0x0f ) < ( cpustate->temp2[0] & 0x0f ) ) \ - cpustate->f |= _FLAG_CL; \ + if ( ( m_temp1[0] & 0x0f ) < ( m_temp2[0] & 0x0f ) ) \ + m_f |= _FLAG_CL; \ else \ - cpustate->f &= ~_FLAG_CL; \ + m_f &= ~_FLAG_CL; \ \ for ( i = 0; i < size; i++ ) \ { \ - UINT16 res = cpustate->temp1[i] - cpustate->temp2[i] - carry; \ + UINT16 res = m_temp1[i] - m_temp2[i] - carry; \ \ - cpustate->temp1[i] = res & 0xff; \ - if ( cpustate->temp1[i] ) \ + m_temp1[i] = res & 0xff; \ + if ( m_temp1[i] ) \ is_zero = 0; \ \ carry = ( res & 0xff00 ) ? 1 : 0; \ } \ \ if ( is_zero ) \ - cpustate->f |= _FLAG_Z; \ + m_f |= _FLAG_Z; \ else \ - cpustate->f &= ~_FLAG_Z; \ + m_f &= ~_FLAG_Z; \ \ if ( carry ) \ - cpustate->f |= _FLAG_C; \ + m_f |= _FLAG_C; \ else \ - cpustate->f &= ~_FLAG_C; \ + m_f &= ~_FLAG_C; \ \ - if ( cpustate->temp1[0] & 0x0f ) \ - cpustate->f &= ~_FLAG_ZL; \ + if ( m_temp1[0] & 0x0f ) \ + m_f &= ~_FLAG_ZL; \ else \ - cpustate->f |= _FLAG_ZL; \ + m_f |= _FLAG_ZL; \ \ - if ( cpustate->temp1[0] & 0xf0 ) \ - cpustate->f &= ~_FLAG_ZH; \ + if ( m_temp1[0] & 0xf0 ) \ + m_f &= ~_FLAG_ZH; \ else \ - cpustate->f |= _FLAG_ZH; \ + m_f |= _FLAG_ZH; \ } #define HCD62121_PUSHW(source) \ { \ UINT16 address = source; \ - mem_writebyte( cpustate, ( cpustate->sseg << 16 ) | cpustate->sp, ( address ) & 0xff ); \ - cpustate->sp--; \ - mem_writebyte( cpustate, ( cpustate->sseg << 16 ) | cpustate->sp, ( address ) >> 8 ); \ - cpustate->sp--; \ + m_program->write_byte( ( m_sseg << 16 ) | m_sp, ( address ) & 0xff ); \ + m_sp--; \ + m_program->write_byte( ( m_sseg << 16 ) | m_sp, ( address ) >> 8 ); \ + m_sp--; \ } #define HCD62121_POPW(dest) \ { \ UINT16 res; \ - cpustate->sp++; \ - res = mem_readbyte( cpustate, ( cpustate->sseg << 16 ) | cpustate->sp ) << 8; \ - cpustate->sp++; \ - res |= mem_readbyte( cpustate, ( cpustate->sseg << 16 ) | cpustate->sp ); \ + m_sp++; \ + res = m_program->read_byte( ( m_sseg << 16 ) | m_sp ) << 8; \ + m_sp++; \ + res |= m_program->read_byte( ( m_sseg << 16 ) | m_sp ); \ dest = res; \ } @@ -287,11 +287,11 @@ case 0x05: /* mskw r1,r2 */ case 0x06: /* mskq r1,r2 */ case 0x07: /* mskt r1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_regreg( cpustate, size, reg1, reg2, false ); + read_regreg( size, reg1, reg2, false ); HCD62121_MSK; } @@ -304,28 +304,28 @@ case 0x0B: /* sht r1,4 */ /* Shift is a nibble shift! */ { int i; - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); UINT8 d1 = 0, d2 = 0; - read_reg( cpustate, size, reg1 ); + read_reg( size, reg1 ); for ( i = 0; i < size; i++ ) { if ( reg1 & 0x80 ) { - d1 = ( cpustate->temp1[i] & 0x0f ) << 4; - cpustate->temp1[i] = ( cpustate->temp1[i] >> 4 ) | d2; + d1 = ( m_temp1[i] & 0x0f ) << 4; + m_temp1[i] = ( m_temp1[i] >> 4 ) | d2; } else { - d1 = ( cpustate->temp1[i] & 0xf0 ) >> 4; - cpustate->temp1[i] = ( cpustate->temp1[i] << 4 ) | d2; + d1 = ( m_temp1[i] & 0xf0 ) >> 4; + m_temp1[i] = ( m_temp1[i] << 4 ) | d2; } d2 = d1; } - write_reg( cpustate, size, reg1 ); + write_reg( size, reg1 ); } break; @@ -334,11 +334,11 @@ case 0x0D: /* testw r1,r2 */ case 0x0E: /* testq r1,r2 */ case 0x0F: /* testt r1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_regreg( cpustate, size, reg1, reg2, false ); + read_regreg( size, reg1, reg2, false ); HCD62121_AND; } @@ -349,15 +349,15 @@ case 0x11: /* xorw r1,r2 */ case 0x12: /* xorq r1,r2 */ case 0x13: /* xort r1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_regreg( cpustate, size, reg1, reg2, false ); + read_regreg( size, reg1, reg2, false ); HCD62121_XOR; - write_regreg( cpustate, size, reg1, reg2 ); + write_regreg( size, reg1, reg2 ); } break; @@ -366,11 +366,11 @@ case 0x15: /* cmpw r1,r2 */ case 0x16: /* cmpq r1,r2 */ case 0x17: /* cmpt r1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_regreg( cpustate, size, reg1, reg2, false ); + read_regreg( size, reg1, reg2, false ); HCD62121_SUB; } @@ -382,16 +382,16 @@ case 0x1A: /* movq r1,r2 */ case 0x1B: /* movt r1,r2 */ { int i; - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_regreg( cpustate, size, reg1, reg2, false ); + read_regreg( size, reg1, reg2, false ); for ( i = 0; i < size; i++ ) - cpustate->temp1[i] = cpustate->temp2[i]; + m_temp1[i] = m_temp2[i]; - write_regreg( cpustate, size, reg1, reg2 ); + write_regreg( size, reg1, reg2 ); } break; @@ -400,11 +400,11 @@ case 0x1D: /* imskw r1,r2 */ case 0x1E: /* imskq r1,r2 */ case 0x1F: /* imskt r1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_regreg( cpustate, size, reg1, reg2, false ); + read_regreg( size, reg1, reg2, false ); HCD62121_IMSK; } @@ -417,20 +417,20 @@ case 0x23: /* shrt r1 */ /* Shift is a single shift! */ { int i; - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); UINT8 d1 = 0, d2 = 0; - read_reg( cpustate, size, reg1 ); + read_reg( size, reg1 ); for ( i = 0; i < size; i++ ) { - d1 = ( cpustate->temp1[i] & 0x01 ) << 7; - cpustate->temp1[i] = ( cpustate->temp1[i] >> 1 ) | d2; + d1 = ( m_temp1[i] & 0x01 ) << 7; + m_temp1[i] = ( m_temp1[i] >> 1 ) | d2; d2 = d1; } - write_reg( cpustate, size, reg1 ); + write_reg( size, reg1 ); } break; @@ -439,15 +439,15 @@ case 0x25: /* orw r1,r2 */ case 0x26: /* orq r1,r2 */ case 0x27: /* ort r1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_regreg( cpustate, size, reg1, reg2, false ); + read_regreg( size, reg1, reg2, false ); HCD62121_OR; - write_regreg( cpustate, size, reg1, reg2 ); + write_regreg( size, reg1, reg2 ); } break; @@ -458,20 +458,20 @@ case 0x2B: /* shlt r1 */ /* Shift is a single shift! */ { int i; - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); UINT8 d1 = 0, d2 = 0; - read_reg( cpustate, size, reg1 ); + read_reg( size, reg1 ); for ( i = 0; i < size; i++ ) { - d1 = ( cpustate->temp1[i] & 0x80 ) >> 7; - cpustate->temp1[i] = ( cpustate->temp1[i] << 1 ) | d2; + d1 = ( m_temp1[i] & 0x80 ) >> 7; + m_temp1[i] = ( m_temp1[i] << 1 ) | d2; d2 = d1; } - write_reg( cpustate, size, reg1 ); + write_reg( size, reg1 ); } break; @@ -480,15 +480,15 @@ case 0x2D: /* andw r1,r2 */ case 0x2E: /* andq r1,r2 */ case 0x2F: /* andt r1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_regreg( cpustate, size, reg1, reg2, true ); + read_regreg( size, reg1, reg2, true ); HCD62121_AND; - write_regreg( cpustate, size, reg1, reg2 ); + write_regreg( size, reg1, reg2 ); } break; @@ -497,15 +497,15 @@ case 0x35: /* subw r1,r2 */ case 0x36: /* subq r1,r2 */ case 0x37: /* subt r1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_regreg( cpustate, size, reg1, reg2, false ); + read_regreg( size, reg1, reg2, false ); HCD62121_SUB; - write_regreg( cpustate, size, reg1, reg2 ); + write_regreg( size, reg1, reg2 ); } break; @@ -514,15 +514,15 @@ case 0x39: /* adbw r1,r2 */ case 0x3A: /* adbq r1,r2 */ case 0x3B: /* adbt r1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_regreg( cpustate, size, reg1, reg2, false ); + read_regreg( size, reg1, reg2, false ); HCD62121_ADDB; - write_regreg( cpustate, size, reg1, reg2 ); + write_regreg( size, reg1, reg2 ); } break; @@ -531,15 +531,15 @@ case 0x3D: /* addw r1,r2 */ case 0x3E: /* addq r1,r2 */ case 0x3F: /* addt r1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_regreg( cpustate, size, reg1, reg2, false ); + read_regreg( size, reg1, reg2, false ); HCD62121_ADD; - write_regreg( cpustate, size, reg1, reg2 ); + write_regreg( size, reg1, reg2 ); } break; @@ -548,11 +548,11 @@ case 0x4D: /* testw ir1,r2 */ case 0x4E: /* testq ir1,r2 */ case 0x4F: /* testt ir1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_iregreg( cpustate, size, reg1, reg2 ); + read_iregreg( size, reg1, reg2 ); HCD62121_AND; } @@ -563,11 +563,11 @@ case 0x55: /* cmpw ir1,r2 */ case 0x56: /* cmpq ir1,r2 */ case 0x57: /* cmpt ir1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_iregreg( cpustate, size, reg1, reg2 ); + read_iregreg( size, reg1, reg2 ); HCD62121_SUB; } @@ -579,16 +579,16 @@ case 0x5A: /* movq ir1,r2 */ case 0x5B: /* movt ir1,r2 */ { int i; - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_iregreg( cpustate, size, reg1, reg2 ); + read_iregreg( size, reg1, reg2 ); for ( i = 0; i < size; i++ ) - cpustate->temp1[i] = cpustate->temp2[i]; + m_temp1[i] = m_temp2[i]; - write_iregreg( cpustate, size, reg1, reg2 ); + write_iregreg( size, reg1, reg2 ); } break; @@ -597,15 +597,15 @@ case 0x65: /* orb ir1,r2 */ case 0x66: /* orb ir1,r2 */ case 0x67: /* orb ir1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_iregreg( cpustate, size, reg1, reg2 ); + read_iregreg( size, reg1, reg2 ); HCD62121_OR; - write_iregreg( cpustate, size, reg1, reg2 ); + write_iregreg( size, reg1, reg2 ); } break; @@ -614,15 +614,15 @@ case 0x6D: /* andw ir1,r2 */ case 0x6E: /* andq ir1,r2 */ case 0x6F: /* andt ir1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_iregreg( cpustate, size, reg1, reg2 ); + read_iregreg( size, reg1, reg2 ); HCD62121_AND; - write_iregreg( cpustate, size, reg1, reg2 ); + write_iregreg( size, reg1, reg2 ); } break; @@ -631,48 +631,48 @@ case 0x7D: /* addw ir1,r2 */ case 0x7E: /* addq ir1,r2 */ case 0x7F: /* addt ir1,r2 */ { - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_iregreg( cpustate, size, reg1, reg2 ); + read_iregreg( size, reg1, reg2 ); HCD62121_ADD; - write_iregreg( cpustate, size, reg1, reg2 ); + write_iregreg( size, reg1, reg2 ); } break; case 0x88: /* jump _a16 */ - cpustate->ip = ( read_op( cpustate ) << 8 ) | read_op( cpustate ); + m_ip = ( read_op() << 8 ) | read_op(); break; case 0x89: /* jumpf cs:a16 */ { - UINT8 cs = read_op( cpustate ); - UINT8 a1 = read_op( cpustate ); - UINT8 a2 = read_op( cpustate ); + UINT8 cs = read_op(); + UINT8 a1 = read_op(); + UINT8 a2 = read_op(); - cpustate->cseg = cs; - cpustate->ip = ( a1 << 8 ) | a2; + m_cseg = cs; + m_ip = ( a1 << 8 ) | a2; } break; case 0x8A: /* call a16 */ { - UINT8 a1 = read_op( cpustate ); - UINT8 a2 = read_op( cpustate ); + UINT8 a1 = read_op(); + UINT8 a2 = read_op(); - HCD62121_PUSHW( cpustate->ip ); + HCD62121_PUSHW( m_ip ); - cpustate->ip = ( a1 << 8 ) | a2; + m_ip = ( a1 << 8 ) | a2; } break; case 0x8C: /* unk_8C */ case 0x8D: /* unk_8D */ case 0x8E: /* unk_8E */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op ); + logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); break; case 0x90: /* retzh */ @@ -683,26 +683,26 @@ case 0x94: /* retzc */ case 0x95: /* retcl */ case 0x96: /* retnc */ case 0x97: /* retnz */ - if ( check_cond( cpustate, op ) ) - HCD62121_POPW( cpustate->ip ); + if ( check_cond( op ) ) + HCD62121_POPW( m_ip ); break; case 0x98: /* jump (r1) */ { - UINT8 reg1 = read_op( cpustate ); - UINT16 ad = cpustate->reg[ ( reg1 | 0x40 ) & 0x7f ] << 8; + UINT8 reg1 = read_op(); + UINT16 ad = m_reg[ ( reg1 | 0x40 ) & 0x7f ] << 8; if ( reg1 & 0x40 ) - ad |= cpustate->reg[ ( ( reg1 - 1 ) | 0x40 ) & 0x7f ]; + ad |= m_reg[ ( ( reg1 - 1 ) | 0x40 ) & 0x7f ]; else - ad |= cpustate->reg[ ( ( reg1 + 1 ) | 0x40 ) & 0x7f ]; + ad |= m_reg[ ( ( reg1 + 1 ) | 0x40 ) & 0x7f ]; - cpustate->ip = ad; + m_ip = ad; } break; case 0x9F: /* ret */ - HCD62121_POPW( cpustate->ip ); + HCD62121_POPW( m_ip ); break; case 0xA0: /* jmpzh a16 */ @@ -714,11 +714,11 @@ case 0xA5: /* jmpcl a16 */ case 0xA6: /* jmpnc a16 */ case 0xA7: /* jmpnz a16 */ { - UINT8 a1 = read_op( cpustate ); - UINT8 a2 = read_op( cpustate ); + UINT8 a1 = read_op(); + UINT8 a2 = read_op(); - if ( check_cond( cpustate, op ) ) - cpustate->ip = ( a1 << 8 ) | a2; + if ( check_cond( op ) ) + m_ip = ( a1 << 8 ) | a2; } break; @@ -731,64 +731,64 @@ case 0xAD: /* callcl a16 */ case 0xAE: /* callnc a16 */ case 0xAF: /* callnz a16 */ { - UINT8 a1 = read_op( cpustate ); - UINT8 a2 = read_op( cpustate ); + UINT8 a1 = read_op(); + UINT8 a2 = read_op(); - if ( check_cond( cpustate, op ) ) + if ( check_cond( op ) ) { - HCD62121_PUSHW( cpustate->ip ); + HCD62121_PUSHW( m_ip ); - cpustate->ip = ( a1 << 8 ) | a2; + m_ip = ( a1 << 8 ) | a2; } } break; case 0xB1: /* unk_B1 reg/i8 */ case 0xB3: /* unk_B3 reg/i8 */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op ); - read_op( cpustate ); + logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); + read_op(); break; case 0xB4: /* out koh,reg */ - io_writebyte( cpustate, HCD62121_KOH, cpustate->reg[ read_op( cpustate ) & 0x7f ] ); + m_io->write_byte( HCD62121_KOH, m_reg[ read_op() & 0x7f ] ); break; case 0xB5: /* out koh,i8 */ - io_writebyte( cpustate, HCD62121_KOH, read_op( cpustate ) ); + m_io->write_byte( HCD62121_KOH, read_op() ); break; case 0xB6: /* out kol,reg */ - io_writebyte( cpustate, HCD62121_KOL, cpustate->reg[ read_op( cpustate ) & 0x7f ] ); + m_io->write_byte( HCD62121_KOL, m_reg[ read_op() & 0x7f ] ); break; case 0xB7: /* out kol,i8 */ - io_writebyte( cpustate, HCD62121_KOL, read_op( cpustate ) ); + m_io->write_byte( HCD62121_KOL, read_op() ); break; case 0xB9: /* unk_B9 reg/i8 */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op ); - read_op( cpustate ); + logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); + read_op(); break; case 0xBB: /* jmpcl? a16 */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op ); + logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); { - UINT8 a1 = read_op( cpustate ); - UINT8 a2 = read_op( cpustate ); + UINT8 a1 = read_op(); + UINT8 a2 = read_op(); - if ( cpustate->f & _FLAG_CL ) - cpustate->ip = ( a1 << 8 ) | a2; + if ( m_f & _FLAG_CL ) + m_ip = ( a1 << 8 ) | a2; } break; case 0xBF: /* jmpncl? a16 */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op ); + logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); { - UINT8 a1 = read_op( cpustate ); - UINT8 a2 = read_op( cpustate ); + UINT8 a1 = read_op(); + UINT8 a2 = read_op(); - if ( ! ( cpustate->f & _FLAG_CL ) ) - cpustate->ip = ( a1 << 8 ) | a2; + if ( ! ( m_f & _FLAG_CL ) ) + m_ip = ( a1 << 8 ) | a2; } break; @@ -798,12 +798,12 @@ case 0xC2: /* movw reg,i64 */ case 0xC3: /* movw reg,i80 */ { int i; - int size = datasize( cpustate, op ); - UINT8 reg = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg = read_op(); for( i = 0; i < size; i++ ) { - cpustate->reg[(reg + i) & 0x7f] = read_op( cpustate ); + m_reg[(reg + i) & 0x7f] = read_op(); } } break; @@ -814,9 +814,9 @@ case 0xC6: /* movq (lar),r1 / r1,(lar) */ case 0xC7: /* movt (lar),r1 / r1,(lar) */ { int i; - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); int pre_inc = 0; int post_inc = 1; @@ -845,9 +845,9 @@ case 0xC7: /* movt (lar),r1 / r1,(lar) */ /* (lar) <- r1 */ for ( i = 0; i < size; i++ ) { - cpustate->lar += pre_inc; - mem_writebyte( cpustate, ( cpustate->dseg << 16 ) | cpustate->lar, cpustate->reg[ ( reg2 + i ) & 0x7f ] ); - cpustate->lar += post_inc; + m_lar += pre_inc; + m_program->write_byte( ( m_dseg << 16 ) | m_lar, m_reg[ ( reg2 + i ) & 0x7f ] ); + m_lar += post_inc; } } else @@ -855,9 +855,9 @@ case 0xC7: /* movt (lar),r1 / r1,(lar) */ /* r1 <- (lar) */ for ( i = 0; i < size; i++ ) { - cpustate->lar += pre_inc; - cpustate->reg[ ( reg2 + i ) & 0x7f ] = mem_readbyte( cpustate, ( cpustate->dseg << 16 ) | cpustate->lar ); - cpustate->lar += post_inc; + m_lar += pre_inc; + m_reg[ ( reg2 + i ) & 0x7f ] = m_program->read_byte( ( m_dseg << 16 ) | m_lar ); + m_lar += post_inc; } } } @@ -869,100 +869,100 @@ case 0xCE: /* swapq ir1,r2 */ case 0xCF: /* swapt ir1,r2? */ { int i; - int size = datasize( cpustate, op ); - UINT8 reg1 = read_op( cpustate ); - UINT8 reg2 = read_op( cpustate ); + int size = datasize( op ); + UINT8 reg1 = read_op(); + UINT8 reg2 = read_op(); - read_iregreg( cpustate, size, reg1, reg2 ); + read_iregreg( size, reg1, reg2 ); for ( i = 0; i < size; i++ ) { - UINT8 d = cpustate->temp1[i]; - cpustate->temp1[i] = cpustate->temp2[i]; - cpustate->temp2[i] = d; + UINT8 d = m_temp1[i]; + m_temp1[i] = m_temp2[i]; + m_temp2[i] = d; } - write_iregreg( cpustate, size, reg1, reg2 ); - write_iregreg2( cpustate, size, reg1, reg2 ); + write_iregreg( size, reg1, reg2 ); + write_iregreg2( size, reg1, reg2 ); } break; case 0xD0: /* movb cs,reg */ - cpustate->cseg = cpustate->reg[ read_op( cpustate ) & 0x7f ]; + m_cseg = m_reg[ read_op() & 0x7f ]; break; case 0xD1: /* movb cs,i8 */ - cpustate->cseg = read_op( cpustate ); + m_cseg = read_op(); break; case 0xD2: /* movb dsize,reg */ - cpustate->dsize = cpustate->reg[ read_op( cpustate ) & 0x7f ]; + m_dsize = m_reg[ read_op() & 0x7f ]; break; case 0xD3: /* movb dsize,i8 */ - cpustate->dsize = read_op( cpustate ); + m_dsize = read_op(); break; case 0xD4: /* movb ss,reg */ - cpustate->sseg = cpustate->reg[ read_op( cpustate ) & 0x7f ]; + m_sseg = m_reg[ read_op() & 0x7f ]; break; case 0xD5: /* movb ss,i8 */ - cpustate->sseg = read_op( cpustate ); + m_sseg = read_op(); break; case 0xD6: /* movw sp,reg */ { - UINT8 reg1 = read_op( cpustate ); + UINT8 reg1 = read_op(); - cpustate->sp = cpustate->reg[ reg1 & 0x7f ] | ( cpustate->reg[ ( reg1 + 1 ) & 0x7f ] << 8 ); + m_sp = m_reg[ reg1 & 0x7f ] | ( m_reg[ ( reg1 + 1 ) & 0x7f ] << 8 ); } break; case 0xD7: /* movw sp,i16 */ - cpustate->sp = read_op( cpustate) << 8; - cpustate->sp |= read_op( cpustate ); + m_sp = read_op() << 8; + m_sp |= read_op(); break; case 0xD8: /* movb f,reg */ - cpustate->f = cpustate->reg[ read_op( cpustate ) & 0x7f ]; + m_f = m_reg[ read_op() & 0x7f ]; break; case 0xD9: /* movb f,i8 */ - cpustate->f = read_op( cpustate ); + m_f = read_op(); break; case 0xDC: /* movb ds,reg */ - cpustate->dseg = cpustate->reg[ read_op( cpustate ) & 0x7f ]; + m_dseg = m_reg[ read_op() & 0x7f ]; break; case 0xDD: /* movb ds,i8 */ - cpustate->dseg = read_op( cpustate ); + m_dseg = read_op(); break; case 0xDE: /* movw lar,reg */ { - UINT8 reg1 = read_op( cpustate ); + UINT8 reg1 = read_op(); - cpustate->lar = cpustate->reg[ reg1 & 0x7f ] | ( cpustate->reg[ ( reg1 + 1 ) & 0x7f ] << 8 ); + m_lar = m_reg[ reg1 & 0x7f ] | ( m_reg[ ( reg1 + 1 ) & 0x7f ] << 8 ); } break; case 0xE0: /* in0 reg */ { - UINT8 reg1 = read_op( cpustate ); + UINT8 reg1 = read_op(); - cpustate->reg[ reg1 & 0x7f ] = io_readbyte( cpustate, HCD62121_IN0 ); + m_reg[ reg1 & 0x7f ] = m_io->read_byte( HCD62121_IN0 ); } break; case 0xE1: /* unk_E1 reg/i8 (in?) */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op ); - read_op( cpustate ); + logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); + read_op(); break; case 0xE2: /* in kb, reg */ - cpustate->reg[ read_op( cpustate ) & 0x7f ] = io_readbyte( cpustate, HCD62121_KI ); + m_reg[ read_op() & 0x7f ] = m_io->read_byte( HCD62121_KI ); break; case 0xE3: /* unk_e3 reg/i8 (in?) */ @@ -970,30 +970,30 @@ case 0xE4: /* unk_e4 reg/i8 (in?) */ case 0xE5: /* unk_e5 reg/i8 (in?) */ case 0xE6: /* unk_e6 reg/i8 (in?) */ case 0xE7: /* unk_e7 reg/i8 (in?) */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op ); - read_op( cpustate ); + logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); + read_op(); break; case 0xE8: /* movw r1,lar */ { - UINT8 reg1 = read_op( cpustate ); + UINT8 reg1 = read_op(); - cpustate->reg[ reg1 & 0x7f ] = cpustate->lar & 0xff; - cpustate->reg[ ( reg1 + 1 ) & 0x7f ] = cpustate->lar >> 8; + m_reg[ reg1 & 0x7f ] = m_lar & 0xff; + m_reg[ ( reg1 + 1 ) & 0x7f ] = m_lar >> 8; } break; case 0xEB: /* movw reg,ss */ { - UINT8 reg1 = read_op( cpustate ); + UINT8 reg1 = read_op(); - cpustate->reg[ reg1 & 0x7f ] = cpustate->sp & 0xff; - cpustate->reg[ ( reg1 + 1 ) & 0x7f ] = cpustate->sp >> 8; + m_reg[ reg1 & 0x7f ] = m_sp & 0xff; + m_reg[ ( reg1 + 1 ) & 0x7f ] = m_sp >> 8; } break; case 0xEF: /* movb reg,ss */ - cpustate->reg[ read_op( cpustate ) & 0x7f ] = cpustate->sseg; + m_reg[ read_op() & 0x7f ] = m_sseg; break; case 0xF0: /* unk_F0 reg/i8 (out?) */ @@ -1004,19 +1004,19 @@ case 0xF4: /* unk_F4 reg/i8 (out?) */ case 0xF5: /* unk_F5 reg/i8 (out?) */ case 0xF6: /* unk_F6 reg/i8 (out?) */ case 0xF7: /* unk_F7 reg/i8 (out?) */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op ); - read_op( cpustate ); + logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); + read_op(); break; case 0xFC: /* unk_FC */ case 0xFD: /* unk_FD */ case 0xFE: /* unk_FE */ - logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op ); + logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); break; case 0xFF: /* nop */ break; default: - /*logerror*/fatalerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op ); + /*logerror*/fatalerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op ); break;