From f0849513d03058e1e06bba39f598488bb0e9482b Mon Sep 17 00:00:00 2001 From: Aaron Giles Date: Mon, 8 Dec 2008 05:07:54 +0000 Subject: [PATCH] From: Atari Ace [mailto:atari_ace@verizon.net] Sent: Sunday, December 07, 2008 1:48 PM To: submit@mamedev.org Cc: atariace@hotmail.com Subject: [patch] Pointerify sharc core Hi mamedev, The attached patch pointerifies the sharc core. If this has already been done, no great loss, it only took about an hour and a half to do this. ~aa --- src/emu/cpu/sharc/compute.c | 498 +++++------ src/emu/cpu/sharc/sharc.c | 1147 ++++++++++++------------ src/emu/cpu/sharc/sharc.h | 6 +- src/emu/cpu/sharc/sharcdma.c | 166 ++-- src/emu/cpu/sharc/sharcmem.c | 96 +- src/emu/cpu/sharc/sharcops.c | 1602 +++++++++++++++++----------------- src/emu/cpu/sharc/sharcops.h | 2 +- src/mame/drivers/model2.c | 54 +- src/mame/drivers/zr107.c | 8 +- src/mame/machine/konppc.c | 36 +- src/mame/video/gticlub.c | 28 +- 11 files changed, 1791 insertions(+), 1852 deletions(-) diff --git a/src/emu/cpu/sharc/compute.c b/src/emu/cpu/sharc/compute.c index e286a4bf046..d2fa09a167c 100644 --- a/src/emu/cpu/sharc/compute.c +++ b/src/emu/cpu/sharc/compute.c @@ -2,27 +2,27 @@ #include -#define CLEAR_ALU_FLAGS() (sharc.astat &= ~(AZ|AN|AV|AC|AS|AI)) +#define CLEAR_ALU_FLAGS() (cpustate->astat &= ~(AZ|AN|AV|AC|AS|AI)) -#define SET_FLAG_AZ(r) { sharc.astat |= (((r) == 0) ? AZ : 0); } -#define SET_FLAG_AN(r) { sharc.astat |= (((r) & 0x80000000) ? AN : 0); } -#define SET_FLAG_AC_ADD(r,a,b) { sharc.astat |= (((UINT32)r < (UINT32)a) ? AC : 0); } -#define SET_FLAG_AV_ADD(r,a,b) { sharc.astat |= (((~((a) ^ (b)) & ((a) ^ (r))) & 0x80000000) ? AV : 0); } -#define SET_FLAG_AC_SUB(r,a,b) { sharc.astat |= ((!((UINT32)a < (UINT32)b)) ? AC : 0); } -#define SET_FLAG_AV_SUB(r,a,b) { sharc.astat |= ((( ((a) ^ (b)) & ((a) ^ (r))) & 0x80000000) ? AV : 0); } +#define SET_FLAG_AZ(r) { cpustate->astat |= (((r) == 0) ? AZ : 0); } +#define SET_FLAG_AN(r) { cpustate->astat |= (((r) & 0x80000000) ? AN : 0); } +#define SET_FLAG_AC_ADD(r,a,b) { cpustate->astat |= (((UINT32)r < (UINT32)a) ? AC : 0); } +#define SET_FLAG_AV_ADD(r,a,b) { cpustate->astat |= (((~((a) ^ (b)) & ((a) ^ (r))) & 0x80000000) ? AV : 0); } +#define SET_FLAG_AC_SUB(r,a,b) { cpustate->astat |= ((!((UINT32)a < (UINT32)b)) ? AC : 0); } +#define SET_FLAG_AV_SUB(r,a,b) { cpustate->astat |= ((( ((a) ^ (b)) & ((a) ^ (r))) & 0x80000000) ? AV : 0); } #define IS_FLOAT_ZERO(r) ((((r) & 0x7fffffff) == 0)) #define IS_FLOAT_DENORMAL(r) ((((r) & 0x7f800000) == 0) && (((r) & 0x7fffff) != 0)) #define IS_FLOAT_NAN(r) ((((r) & 0x7f800000) == 0x7f800000) && (((r) & 0x7fffff) != 0)) #define IS_FLOAT_INFINITY(r) (((r) & 0x7fffffff) == 0x7f800000) -#define CLEAR_MULTIPLIER_FLAGS() (sharc.astat &= ~(MN|MV|MU|MI)) +#define CLEAR_MULTIPLIER_FLAGS() (cpustate->astat &= ~(MN|MV|MU|MI)) -#define SET_FLAG_MN(r) { sharc.astat |= (((r) & 0x80000000) ? MN : 0); } -#define SET_FLAG_MV(r) { sharc.astat |= ((((UINT32)((r) >> 32) != 0) && ((UINT32)((r) >> 32) != 0xffffffff)) ? MV : 0); } +#define SET_FLAG_MN(r) { cpustate->astat |= (((r) & 0x80000000) ? MN : 0); } +#define SET_FLAG_MV(r) { cpustate->astat |= ((((UINT32)((r) >> 32) != 0) && ((UINT32)((r) >> 32) != 0xffffffff)) ? MV : 0); } /* TODO: MU needs 80-bit result */ -#define SET_FLAG_MU(r) { sharc.astat |= ((((UINT32)((r) >> 32) == 0) && ((UINT32)(r)) != 0) ? MU : 0); } +#define SET_FLAG_MU(r) { cpustate->astat |= ((((UINT32)((r) >> 32) == 0) && ((UINT32)(r)) != 0) ? MU : 0); } #define FLOAT_SIGN 0x80000000 @@ -109,11 +109,11 @@ static const UINT32 rsqrts_mantissa_lookup[128] = /* Integer ALU operations */ /* Rn = Rx + Ry */ -INLINE void compute_add(int rn, int rx, int ry) +INLINE void compute_add(SHARC_REGS *cpustate, int rn, int rx, int ry) { UINT32 r = REG(rx) + REG(ry); - if (sharc.mode1 & MODE1_ALUSAT) + if (cpustate->mode1 & MODE1_ALUSAT) fatalerror("SHARC: compute_add: ALU saturation not implemented !"); CLEAR_ALU_FLAGS(); @@ -123,15 +123,15 @@ INLINE void compute_add(int rn, int rx, int ry) SET_FLAG_AC_ADD(r, REG(rx), REG(ry)); REG(rn) = r; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rn = Rx - Ry */ -INLINE void compute_sub(int rn, int rx, int ry) +INLINE void compute_sub(SHARC_REGS *cpustate, int rn, int rx, int ry) { UINT32 r = REG(rx) - REG(ry); - if (sharc.mode1 & MODE1_ALUSAT) + if (cpustate->mode1 & MODE1_ALUSAT) fatalerror("SHARC: compute_sub: ALU saturation not implemented !"); CLEAR_ALU_FLAGS(); @@ -141,16 +141,16 @@ INLINE void compute_sub(int rn, int rx, int ry) SET_FLAG_AC_SUB(r, REG(rx), REG(ry)); REG(rn) = r; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rn = Rx + Ry + CI */ -INLINE void compute_add_ci(int rn, int rx, int ry) +INLINE void compute_add_ci(SHARC_REGS *cpustate, int rn, int rx, int ry) { - int c = (sharc.astat & AC) ? 1 : 0; + int c = (cpustate->astat & AC) ? 1 : 0; UINT32 r = REG(rx) + REG(ry) + c; - if (sharc.mode1 & MODE1_ALUSAT) + if (cpustate->mode1 & MODE1_ALUSAT) fatalerror("SHARC: compute_add_ci: ALU saturation not implemented !"); CLEAR_ALU_FLAGS(); @@ -160,16 +160,16 @@ INLINE void compute_add_ci(int rn, int rx, int ry) SET_FLAG_AC_ADD(r, REG(rx), REG(ry)+c); REG(rn) = r; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rn = Rx - Ry + CI - 1 */ -INLINE void compute_sub_ci(int rn, int rx, int ry) +INLINE void compute_sub_ci(SHARC_REGS *cpustate, int rn, int rx, int ry) { - int c = (sharc.astat & AC) ? 1 : 0; + int c = (cpustate->astat & AC) ? 1 : 0; UINT32 r = REG(rx) - REG(ry) + c - 1; - if (sharc.mode1 & MODE1_ALUSAT) + if (cpustate->mode1 & MODE1_ALUSAT) fatalerror("SHARC: compute_sub_ci: ALU saturation not implemented !"); CLEAR_ALU_FLAGS(); @@ -179,11 +179,11 @@ INLINE void compute_sub_ci(int rn, int rx, int ry) SET_FLAG_AC_SUB(r, REG(rx), REG(ry)+c-1); REG(rn) = r; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rn = Rx AND Ry */ -INLINE void compute_and(int rn, int rx, int ry) +INLINE void compute_and(SHARC_REGS *cpustate, int rn, int rx, int ry) { UINT32 r = REG(rx) & REG(ry); @@ -192,50 +192,50 @@ INLINE void compute_and(int rn, int rx, int ry) SET_FLAG_AZ(r); REG(rn) = r; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* COMP(Rx, Ry) */ -INLINE void compute_comp(int rx, int ry) +INLINE void compute_comp(SHARC_REGS *cpustate, int rx, int ry) { UINT32 comp_accum; CLEAR_ALU_FLAGS(); if( REG(rx) == REG(ry) ) - sharc.astat |= AZ; + cpustate->astat |= AZ; if( (INT32)REG(rx) < (INT32)REG(ry) ) - sharc.astat |= AN; + cpustate->astat |= AN; // Update ASTAT compare accumulation register - comp_accum = (sharc.astat >> 24) & 0xff; + comp_accum = (cpustate->astat >> 24) & 0xff; comp_accum >>= 1; - if ((sharc.astat & (AZ|AN)) == 0) + if ((cpustate->astat & (AZ|AN)) == 0) { comp_accum |= 0x80; } - sharc.astat &= 0xffffff; - sharc.astat |= comp_accum << 24; + cpustate->astat &= 0xffffff; + cpustate->astat |= comp_accum << 24; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rn = PASS Rx */ -INLINE void compute_pass(int rn, int rx) +INLINE void compute_pass(SHARC_REGS *cpustate, int rn, int rx) { CLEAR_ALU_FLAGS(); /* TODO: floating-point extension field is set to 0 */ REG(rn) = REG(rx); if (REG(rn) == 0) - sharc.astat |= AZ; + cpustate->astat |= AZ; if (REG(rn) & 0x80000000) - sharc.astat |= AN; + cpustate->astat |= AN; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rn = Rx XOR Ry */ -INLINE void compute_xor(int rn, int rx, int ry) +INLINE void compute_xor(SHARC_REGS *cpustate, int rn, int rx, int ry) { UINT32 r = REG(rx) ^ REG(ry); CLEAR_ALU_FLAGS(); @@ -243,11 +243,11 @@ INLINE void compute_xor(int rn, int rx, int ry) SET_FLAG_AZ(r); REG(rn) = r; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rn = Rx OR Ry */ -INLINE void compute_or(int rn, int rx, int ry) +INLINE void compute_or(SHARC_REGS *cpustate, int rn, int rx, int ry) { UINT32 r = REG(rx) | REG(ry); CLEAR_ALU_FLAGS(); @@ -255,11 +255,11 @@ INLINE void compute_or(int rn, int rx, int ry) SET_FLAG_AZ(r); REG(rn) = r; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rn = Rx + 1 */ -INLINE void compute_inc(int rn, int rx) +INLINE void compute_inc(SHARC_REGS *cpustate, int rn, int rx) { UINT32 r = REG(rx) + 1; @@ -271,11 +271,11 @@ INLINE void compute_inc(int rn, int rx) REG(rn) = r; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rn = Rx - 1 */ -INLINE void compute_dec(int rn, int rx) +INLINE void compute_dec(SHARC_REGS *cpustate, int rn, int rx) { UINT32 r = REG(rx) - 1; @@ -287,11 +287,11 @@ INLINE void compute_dec(int rn, int rx) REG(rn) = r; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rn = MIN(Rx, Ry) */ -INLINE void compute_min(int rn, int rx, int ry) +INLINE void compute_min(SHARC_REGS *cpustate, int rn, int rx, int ry) { UINT32 r = MIN((INT32)REG(rx), (INT32)REG(ry)); @@ -301,11 +301,11 @@ INLINE void compute_min(int rn, int rx, int ry) REG(rn) = r; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rn = MAX(Rx, Ry) */ -INLINE void compute_max(int rn, int rx, int ry) +INLINE void compute_max(SHARC_REGS *cpustate, int rn, int rx, int ry) { UINT32 r = MAX((INT32)REG(rx), (INT32)REG(ry)); @@ -315,11 +315,11 @@ INLINE void compute_max(int rn, int rx, int ry) REG(rn) = r; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rn = -Rx */ -INLINE void compute_neg(int rn, int rx) +INLINE void compute_neg(SHARC_REGS *cpustate, int rn, int rx) { UINT32 r = -(INT32)(REG(rx)); @@ -331,11 +331,11 @@ INLINE void compute_neg(int rn, int rx) REG(rn) = r; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rn = NOT Rx */ -INLINE void compute_not(int rn, int rx) +INLINE void compute_not(SHARC_REGS *cpustate, int rn, int rx) { UINT32 r = ~REG(rx); @@ -345,13 +345,13 @@ INLINE void compute_not(int rn, int rx) REG(rn) = r; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /*****************************************************************************/ /* Floating-point ALU operations */ -INLINE UINT32 SCALB(SHARC_REG rx, int ry) +INLINE UINT32 SCALB(SHARC_REGS *cpustate, SHARC_REG rx, int ry) { UINT32 mantissa = rx.r & FLOAT_MANTISSA; UINT32 sign = rx.r & FLOAT_SIGN; @@ -362,13 +362,13 @@ INLINE UINT32 SCALB(SHARC_REG rx, int ry) if (exponent > 127) { // overflow - sharc.astat |= AV; + cpustate->astat |= AV; return sign | FLOAT_INFINITY; } else if (exponent < -126) { // denormal - sharc.astat |= AZ; + cpustate->astat |= AZ; return sign; } else @@ -378,7 +378,7 @@ INLINE UINT32 SCALB(SHARC_REG rx, int ry) } /* Fn = FLOAT Rx */ -INLINE void compute_float(int rn, int rx) +INLINE void compute_float(SHARC_REGS *cpustate, int rn, int rx) { // verified FREG(rn) = (float)(INT32)REG(rx); @@ -387,22 +387,22 @@ INLINE void compute_float(int rn, int rx) // AN SET_FLAG_AN(REG(rn)); // AZ - sharc.astat |= (IS_FLOAT_DENORMAL(REG(rn)) || IS_FLOAT_ZERO(REG(rn))) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_DENORMAL(REG(rn)) || IS_FLOAT_ZERO(REG(rn))) ? AZ : 0; // AUS - sharc.stky |= (IS_FLOAT_DENORMAL(REG(rn))) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(REG(rn))) ? AUS : 0; /* TODO: AV flag */ - sharc.astat |= AF; + cpustate->astat |= AF; } /* Rn = FIX Fx */ -INLINE void compute_fix(int rn, int rx) +INLINE void compute_fix(SHARC_REGS *cpustate, int rn, int rx) { INT32 alu_i; SHARC_REG r_alu; r_alu.f = FREG(rx); - if (sharc.mode1 & MODE1_TRUNCATE) + if (cpustate->mode1 & MODE1_TRUNCATE) { alu_i = (INT32)(r_alu.f); } @@ -416,23 +416,23 @@ INLINE void compute_fix(int rn, int rx) // AZ SET_FLAG_AZ(alu_i); // AU - sharc.stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; /* TODO: AV flag */ REG(rn) = alu_i; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Rn = FIX Fx BY Ry */ -INLINE void compute_fix_scaled(int rn, int rx, int ry) +INLINE void compute_fix_scaled(SHARC_REGS *cpustate, int rn, int rx, int ry) { INT32 alu_i; SHARC_REG r_alu; - r_alu.r = SCALB(sharc.r[rx], ry); - if (sharc.mode1 & MODE1_TRUNCATE) + r_alu.r = SCALB(cpustate, cpustate->r[rx], ry); + if (cpustate->mode1 & MODE1_TRUNCATE) { alu_i = (INT32)(r_alu.f); } @@ -446,17 +446,17 @@ INLINE void compute_fix_scaled(int rn, int rx, int ry) // AZ SET_FLAG_AZ(alu_i); // AU - sharc.stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; /* TODO: AV flag */ REG(rn) = alu_i; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fn = FLOAT Rx BY Ry */ -INLINE void compute_float_scaled(int rn, int rx, int ry) +INLINE void compute_float_scaled(SHARC_REGS *cpustate, int rn, int rx, int ry) { SHARC_REG x; x.f = (float)(INT32)(REG(rx)); @@ -464,20 +464,20 @@ INLINE void compute_float_scaled(int rn, int rx, int ry) // verified CLEAR_ALU_FLAGS(); - REG(rn) = SCALB(x, ry); + REG(rn) = SCALB(cpustate, x, ry); // AN SET_FLAG_AN(REG(rn)); // AZ - sharc.astat |= (IS_FLOAT_DENORMAL(REG(rn)) || IS_FLOAT_ZERO(REG(rn))) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_DENORMAL(REG(rn)) || IS_FLOAT_ZERO(REG(rn))) ? AZ : 0; // AU - sharc.stky |= (IS_FLOAT_DENORMAL(REG(rn))) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(REG(rn))) ? AUS : 0; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Rn = LOGB Fx */ -INLINE void compute_logb(int rn, int rx) +INLINE void compute_logb(SHARC_REGS *cpustate, int rn, int rx) { // verified UINT32 r = REG(rx); @@ -488,20 +488,20 @@ INLINE void compute_logb(int rn, int rx) { REG(rn) = FLOAT_INFINITY; - sharc.astat |= AV; + cpustate->astat |= AV; } else if (IS_FLOAT_ZERO(REG(rx))) { REG(rn) = FLOAT_SIGN | FLOAT_INFINITY; - sharc.astat |= AV; + cpustate->astat |= AV; } else if (IS_FLOAT_NAN(REG(rx))) { REG(rn) = 0xffffffff; - sharc.astat |= AI; - sharc.stky |= AIS; + cpustate->astat |= AI; + cpustate->stky |= AIS; } else { @@ -515,11 +515,11 @@ INLINE void compute_logb(int rn, int rx) REG(rn) = exponent; } - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fn = SCALB Fx BY Fy */ -INLINE void compute_scalb(int rn, int rx, int ry) +INLINE void compute_scalb(SHARC_REGS *cpustate, int rn, int rx, int ry) { // verified SHARC_REG r; @@ -527,192 +527,192 @@ INLINE void compute_scalb(int rn, int rx, int ry) if (IS_FLOAT_NAN(REG(rx))) { - sharc.astat |= AI; - sharc.stky |= AIS; + cpustate->astat |= AI; + cpustate->stky |= AIS; REG(rn) = 0xffffffff; } else { - r.r = SCALB(sharc.r[rx], ry); + r.r = SCALB(cpustate, cpustate->r[rx], ry); // AN SET_FLAG_AN(r.r); // AZ - sharc.astat |= IS_FLOAT_ZERO(r.r) ? AZ : 0; + cpustate->astat |= IS_FLOAT_ZERO(r.r) ? AZ : 0; // AUS - sharc.stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; FREG(rn) = r.f; } - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fn = Fx + Fy */ -INLINE void compute_fadd(int rn, int rx, int ry) +INLINE void compute_fadd(SHARC_REGS *cpustate, int rn, int rx, int ry) { SHARC_REG r; r.f = FREG(rx) + FREG(ry); CLEAR_ALU_FLAGS(); // AN - sharc.astat |= (r.f < 0.0f) ? AN : 0; + cpustate->astat |= (r.f < 0.0f) ? AN : 0; // AZ - sharc.astat |= (IS_FLOAT_DENORMAL(r.r) || IS_FLOAT_ZERO(r.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_DENORMAL(r.r) || IS_FLOAT_ZERO(r.r)) ? AZ : 0; // AUS - sharc.stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; /* TODO: AV flag */ // AIS - if (sharc.astat & AI) sharc.stky |= AIS; + if (cpustate->astat & AI) cpustate->stky |= AIS; FREG(rn) = r.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fn = Fx - Fy */ -INLINE void compute_fsub(int rn, int rx, int ry) +INLINE void compute_fsub(SHARC_REGS *cpustate, int rn, int rx, int ry) { SHARC_REG r; r.f = FREG(rx) - FREG(ry); CLEAR_ALU_FLAGS(); // AN - sharc.astat |= (r.f < 0.0f) ? AN : 0; + cpustate->astat |= (r.f < 0.0f) ? AN : 0; // AZ - sharc.astat |= (IS_FLOAT_DENORMAL(r.r) || IS_FLOAT_ZERO(r.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_DENORMAL(r.r) || IS_FLOAT_ZERO(r.r)) ? AZ : 0; // AUS - sharc.stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; /* TODO: AV flag */ // AIS - if (sharc.astat & AI) sharc.stky |= AIS; + if (cpustate->astat & AI) cpustate->stky |= AIS; FREG(rn) = r.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fn = -Fx */ -INLINE void compute_fneg(int rn, int rx) +INLINE void compute_fneg(SHARC_REGS *cpustate, int rn, int rx) { SHARC_REG r; r.f = -FREG(rx); CLEAR_ALU_FLAGS(); // AZ - sharc.astat |= (IS_FLOAT_ZERO(r.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_ZERO(r.r)) ? AZ : 0; // AN - sharc.astat |= (r.f < 0.0f) ? AN : 0; + cpustate->astat |= (r.f < 0.0f) ? AN : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; // AIS - if (sharc.astat & AI) sharc.stky |= AIS; + if (cpustate->astat & AI) cpustate->stky |= AIS; FREG(rn) = r.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* COMP(Fx, Fy) */ -INLINE void compute_fcomp(int rx, int ry) +INLINE void compute_fcomp(SHARC_REGS *cpustate, int rx, int ry) { UINT32 comp_accum; CLEAR_ALU_FLAGS(); // AZ if( FREG(rx) == FREG(ry) ) - sharc.astat |= AZ; + cpustate->astat |= AZ; // AN if( FREG(rx) < FREG(ry) ) - sharc.astat |= AN; + cpustate->astat |= AN; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; // AIS - if (sharc.astat & AI) sharc.stky |= AIS; + if (cpustate->astat & AI) cpustate->stky |= AIS; // Update ASTAT compare accumulation register - comp_accum = (sharc.astat >> 24) & 0xff; + comp_accum = (cpustate->astat >> 24) & 0xff; comp_accum >>= 1; - if ((sharc.astat & (AZ|AN)) == 0) + if ((cpustate->astat & (AZ|AN)) == 0) { comp_accum |= 0x80; } - sharc.astat &= 0xffffff; - sharc.astat |= comp_accum << 24; - sharc.astat |= AF; + cpustate->astat &= 0xffffff; + cpustate->astat |= comp_accum << 24; + cpustate->astat |= AF; } /* Fn = ABS(Fx + Fy) */ -INLINE void compute_fabs_plus(int rn, int rx, int ry) +INLINE void compute_fabs_plus(SHARC_REGS *cpustate, int rn, int rx, int ry) { SHARC_REG r; r.f = fabs(FREG(rx) + FREG(ry)); CLEAR_ALU_FLAGS(); // AZ - sharc.astat |= (IS_FLOAT_DENORMAL(r.r) || IS_FLOAT_ZERO(r.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_DENORMAL(r.r) || IS_FLOAT_ZERO(r.r)) ? AZ : 0; // AUS - sharc.stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; /* TODO: AV flag */ // AIS - if (sharc.astat & AI) sharc.stky |= AIS; + if (cpustate->astat & AI) cpustate->stky |= AIS; FREG(rn) = r.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fn = MAX(Fx, Fy) */ -INLINE void compute_fmax(int rn, int rx, int ry) +INLINE void compute_fmax(SHARC_REGS *cpustate, int rn, int rx, int ry) { SHARC_REG r_alu; r_alu.f = MAX(FREG(rx), FREG(ry)); CLEAR_ALU_FLAGS(); - sharc.astat |= (r_alu.f < 0.0f) ? AN : 0; + cpustate->astat |= (r_alu.f < 0.0f) ? AN : 0; // AZ - sharc.astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; // AU - sharc.stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; /* TODO: AV flag */ FREG(rn) = r_alu.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fn = MIN(Fx, Fy) */ -INLINE void compute_fmin(int rn, int rx, int ry) +INLINE void compute_fmin(SHARC_REGS *cpustate, int rn, int rx, int ry) { SHARC_REG r_alu; r_alu.f = MIN(FREG(rx), FREG(ry)); CLEAR_ALU_FLAGS(); - sharc.astat |= (r_alu.f < 0.0f) ? AN : 0; + cpustate->astat |= (r_alu.f < 0.0f) ? AN : 0; // AZ - sharc.astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; // AU - sharc.stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; /* TODO: AV flag */ FREG(rn) = r_alu.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fn = CLIP Fx BY Fy */ -INLINE void compute_fclip(int rn, int rx, int ry) +INLINE void compute_fclip(SHARC_REGS *cpustate, int rn, int rx, int ry) { SHARC_REG r_alu; @@ -736,18 +736,18 @@ INLINE void compute_fclip(int rn, int rx, int ry) CLEAR_ALU_FLAGS(); SET_FLAG_AN(r_alu.r); // AZ - sharc.astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; // AU - sharc.stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; FREG(rn) = r_alu.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fn = RECIPS Fx */ -INLINE void compute_recips(int rn, int rx) +INLINE void compute_recips(SHARC_REGS *cpustate, int rn, int rx) { // verified UINT32 r; @@ -760,17 +760,17 @@ INLINE void compute_recips(int rn, int rx) r = 0xffffffff; // AI - sharc.astat |= AI; + cpustate->astat |= AI; // AIS - sharc.stky |= AIS; + cpustate->stky |= AIS; } else if (IS_FLOAT_ZERO(REG(rx))) { // +- Zero r = (REG(rx) & FLOAT_SIGN) | FLOAT_INFINITY; - sharc.astat |= AZ; + cpustate->astat |= AZ; } else { @@ -795,23 +795,23 @@ INLINE void compute_recips(int rn, int rx) SET_FLAG_AN(REG(rx)); // AZ & AV - sharc.astat |= (IS_FLOAT_ZERO(r)) ? AZ : 0; - sharc.astat |= (IS_FLOAT_ZERO(REG(rx))) ? AV : 0; + cpustate->astat |= (IS_FLOAT_ZERO(r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_ZERO(REG(rx))) ? AV : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; // AIS - if (sharc.astat & AI) sharc.stky |= AIS; + if (cpustate->astat & AI) cpustate->stky |= AIS; } // AF - sharc.astat |= AF; + cpustate->astat |= AF; REG(rn) = r; } /* Fn = RSQRTS Fx */ -INLINE void compute_rsqrts(int rn, int rx) +INLINE void compute_rsqrts(SHARC_REGS *cpustate, int rn, int rx) { // verified UINT32 r; @@ -842,62 +842,62 @@ INLINE void compute_rsqrts(int rn, int rx) CLEAR_ALU_FLAGS(); // AN - sharc.astat |= (REG(rx) == 0x80000000) ? AN : 0; + cpustate->astat |= (REG(rx) == 0x80000000) ? AN : 0; // AZ & AV - sharc.astat |= (IS_FLOAT_ZERO(r)) ? AZ : 0; - sharc.astat |= (IS_FLOAT_ZERO(REG(rx))) ? AV : 0; + cpustate->astat |= (IS_FLOAT_ZERO(r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_ZERO(REG(rx))) ? AV : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx)) || (REG(rx) & 0x80000000)) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || (REG(rx) & 0x80000000)) ? AI : 0; // AIS - if (sharc.astat & AI) sharc.stky |= AIS; + if (cpustate->astat & AI) cpustate->stky |= AIS; // AF - sharc.astat |= AF; + cpustate->astat |= AF; REG(rn) = r; } /* Fn = PASS Fx */ -INLINE void compute_fpass(int rn, int rx) +INLINE void compute_fpass(SHARC_REGS *cpustate, int rn, int rx) { SHARC_REG r; r.f = FREG(rx); CLEAR_ALU_FLAGS(); // AN - sharc.astat |= (r.f < 0.0f) ? AN : 0; + cpustate->astat |= (r.f < 0.0f) ? AN : 0; // AZ - sharc.astat |= (IS_FLOAT_ZERO(r.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_ZERO(r.r)) ? AZ : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; FREG(rn) = r.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fn = ABS Fx */ -INLINE void compute_fabs(int rn, int rx) +INLINE void compute_fabs(SHARC_REGS *cpustate, int rn, int rx) { SHARC_REG r; r.f = fabs(FREG(rx)); CLEAR_ALU_FLAGS(); // AN - sharc.astat |= (r.f < 0.0f) ? AN : 0; + cpustate->astat |= (r.f < 0.0f) ? AN : 0; // AZ - sharc.astat |= (IS_FLOAT_ZERO(r.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_ZERO(r.r)) ? AZ : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; FREG(rn) = r.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /*****************************************************************************/ /* Multiplier opcodes */ /* Rn = (unsigned)Rx * (unsigned)Ry, integer, no rounding */ -INLINE void compute_mul_uuin(int rn, int rx, int ry) +INLINE void compute_mul_uuin(SHARC_REGS *cpustate, int rn, int rx, int ry) { UINT64 r = (UINT64)(UINT32)REG(rx) * (UINT64)(UINT32)REG(ry); @@ -910,7 +910,7 @@ INLINE void compute_mul_uuin(int rn, int rx, int ry) } /* Rn = (signed)Rx * (signed)Ry, integer, no rounding */ -INLINE void compute_mul_ssin(int rn, int rx, int ry) +INLINE void compute_mul_ssin(SHARC_REGS *cpustate, int rn, int rx, int ry) { UINT64 r = (INT64)(INT32)REG(rx) * (INT64)(INT32)REG(ry); @@ -923,9 +923,9 @@ INLINE void compute_mul_ssin(int rn, int rx, int ry) } /* MRF + (signed)Rx * (signed)Ry, integer, no rounding */ -INLINE UINT32 compute_mrf_plus_mul_ssin(int rx, int ry) +INLINE UINT32 compute_mrf_plus_mul_ssin(SHARC_REGS *cpustate, int rx, int ry) { - UINT64 r = sharc.mrf + ((INT64)(INT32)REG(rx) * (INT64)(INT32)REG(ry)); + UINT64 r = cpustate->mrf + ((INT64)(INT32)REG(rx) * (INT64)(INT32)REG(ry)); CLEAR_MULTIPLIER_FLAGS(); SET_FLAG_MN((UINT32)r); @@ -936,9 +936,9 @@ INLINE UINT32 compute_mrf_plus_mul_ssin(int rx, int ry) } /* MRB + (signed)Rx * (signed)Ry, integer, no rounding */ -INLINE UINT32 compute_mrb_plus_mul_ssin(int rx, int ry) +INLINE UINT32 compute_mrb_plus_mul_ssin(SHARC_REGS *cpustate, int rx, int ry) { - INT64 r = sharc.mrb + ((INT64)(INT32)REG(rx) * (INT64)(INT32)REG(ry)); + INT64 r = cpustate->mrb + ((INT64)(INT32)REG(rx) * (INT64)(INT32)REG(ry)); CLEAR_MULTIPLIER_FLAGS(); SET_FLAG_MN((UINT32)r); @@ -949,7 +949,7 @@ INLINE UINT32 compute_mrb_plus_mul_ssin(int rx, int ry) } /* Fn = Fx * Fy */ -INLINE void compute_fmul(int rn, int rx, int ry) +INLINE void compute_fmul(SHARC_REGS *cpustate, int rn, int rx, int ry) { FREG(rn) = FREG(rx) * FREG(ry); @@ -965,15 +965,15 @@ INLINE void compute_fmul(int rn, int rx, int ry) /* multi function opcodes */ /* integer*/ -INLINE void compute_multi_mr_to_reg(int ai, int rk) +INLINE void compute_multi_mr_to_reg(SHARC_REGS *cpustate, int ai, int rk) { switch(ai) { - case 0: SET_UREG(rk, (UINT32)(sharc.mrf)); break; - case 1: SET_UREG(rk, (UINT32)(sharc.mrf >> 32)); break; + case 0: SET_UREG(cpustate, rk, (UINT32)(cpustate->mrf)); break; + case 1: SET_UREG(cpustate, rk, (UINT32)(cpustate->mrf >> 32)); break; case 2: fatalerror("SHARC: tried to load MR2F"); break; - case 4: SET_UREG(rk, (UINT32)(sharc.mrb)); break; - case 5: SET_UREG(rk, (UINT32)(sharc.mrb >> 32)); break; + case 4: SET_UREG(cpustate, rk, (UINT32)(cpustate->mrb)); break; + case 5: SET_UREG(cpustate, rk, (UINT32)(cpustate->mrb >> 32)); break; case 6: fatalerror("SHARC: tried to load MR2B"); break; default: fatalerror("SHARC: unknown ai %d in mr_to_reg", ai); } @@ -981,15 +981,15 @@ INLINE void compute_multi_mr_to_reg(int ai, int rk) CLEAR_MULTIPLIER_FLAGS(); } -INLINE void compute_multi_reg_to_mr(int ai, int rk) +INLINE void compute_multi_reg_to_mr(SHARC_REGS *cpustate, int ai, int rk) { switch(ai) { - case 0: sharc.mrf &= ~0xffffffff; sharc.mrf |= GET_UREG(rk); break; - case 1: sharc.mrf &= 0xffffffff; sharc.mrf |= (UINT64)(GET_UREG(rk)) << 32; break; + case 0: cpustate->mrf &= ~0xffffffff; cpustate->mrf |= GET_UREG(cpustate, rk); break; + case 1: cpustate->mrf &= 0xffffffff; cpustate->mrf |= (UINT64)(GET_UREG(cpustate, rk)) << 32; break; case 2: fatalerror("SHARC: tried to write MR2F"); break; - case 4: sharc.mrb &= ~0xffffffff; sharc.mrb |= GET_UREG(rk); break; - case 5: sharc.mrb &= 0xffffffff; sharc.mrb |= (UINT64)(GET_UREG(rk)) << 32; break; + case 4: cpustate->mrb &= ~0xffffffff; cpustate->mrb |= GET_UREG(cpustate, rk); break; + case 5: cpustate->mrb &= 0xffffffff; cpustate->mrb |= (UINT64)(GET_UREG(cpustate, rk)) << 32; break; case 6: fatalerror("SHARC: tried to write MR2B"); break; default: fatalerror("SHARC: unknown ai %d in reg_to_mr", ai); } @@ -998,7 +998,7 @@ INLINE void compute_multi_reg_to_mr(int ai, int rk) } /* Ra = Rx + Ry, Rs = Rx - Ry */ -INLINE void compute_dual_add_sub(int ra, int rs, int rx, int ry) +INLINE void compute_dual_add_sub(SHARC_REGS *cpustate, int ra, int rs, int rx, int ry) { UINT32 r_add = REG(rx) + REG(ry); UINT32 r_sub = REG(rx) - REG(ry); @@ -1006,31 +1006,31 @@ INLINE void compute_dual_add_sub(int ra, int rs, int rx, int ry) CLEAR_ALU_FLAGS(); if (r_add == 0 || r_sub == 0) { - sharc.astat |= AZ; + cpustate->astat |= AZ; } if (r_add & 0x80000000 || r_sub & 0x80000000) { - sharc.astat |= AN; + cpustate->astat |= AN; } if (((~(REG(rx) ^ REG(ry)) & (REG(rx) ^ r_add)) & 0x80000000) || (( (REG(rx) ^ REG(ry)) & (REG(rx) ^ r_sub)) & 0x80000000)) { - sharc.astat |= AV; + cpustate->astat |= AV; } if (((UINT32)r_add < (UINT32)REG(rx)) || (!((UINT32)r_sub < (UINT32)REG(rx)))) { - sharc.astat |= AC; + cpustate->astat |= AC; } REG(ra) = r_add; REG(rs) = r_sub; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rm = (signed)Rxm * (signed)Rym, fractional, rounding, Ra = Rxa + Rya */ -INLINE void compute_mul_ssfr_add(int rm, int rxm, int rym, int ra, int rxa, int rya) +INLINE void compute_mul_ssfr_add(SHARC_REGS *cpustate, int rm, int rxm, int rym, int ra, int rxa, int rya) { UINT32 r_mul = (UINT32)(((INT64)(REG(rxm)) * (INT64)(REG(rym))) >> 31); UINT32 r_add = REG(rxa) + REG(rya); @@ -1051,11 +1051,11 @@ INLINE void compute_mul_ssfr_add(int rm, int rxm, int rym, int ra, int rxa, int REG(rm) = r_mul; REG(ra) = r_add; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* Rm = (signed)Rxm * (signed)Rym, fractional, rounding, Ra = Rxa - Rya */ -INLINE void compute_mul_ssfr_sub(int rm, int rxm, int rym, int ra, int rxa, int rya) +INLINE void compute_mul_ssfr_sub(SHARC_REGS *cpustate, int rm, int rxm, int rym, int ra, int rxa, int rya) { UINT32 r_mul = (UINT32)(((INT64)(REG(rxm)) * (INT64)(REG(rym))) >> 31); UINT32 r_sub = REG(rxa) - REG(rya); @@ -1076,14 +1076,14 @@ INLINE void compute_mul_ssfr_sub(int rm, int rxm, int rym, int ra, int rxa, int REG(rm) = r_mul; REG(ra) = r_sub; - sharc.astat &= ~AF; + cpustate->astat &= ~AF; } /* floating-point */ /* Fa = Fx + Fy, Fs = Fx - Fy */ -INLINE void compute_dual_fadd_fsub(int ra, int rs, int rx, int ry) +INLINE void compute_dual_fadd_fsub(SHARC_REGS *cpustate, int ra, int rs, int rx, int ry) { SHARC_REG r_add, r_sub; r_add.f = FREG(rx) + FREG(ry); @@ -1091,26 +1091,26 @@ INLINE void compute_dual_fadd_fsub(int ra, int rs, int rx, int ry) CLEAR_ALU_FLAGS(); // AN - sharc.astat |= ((r_add.f < 0.0f) || (r_sub.f < 0.0f)) ? AN : 0; + cpustate->astat |= ((r_add.f < 0.0f) || (r_sub.f < 0.0f)) ? AN : 0; // AZ - sharc.astat |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_ZERO(r_add.r) || + cpustate->astat |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_ZERO(r_add.r) || IS_FLOAT_DENORMAL(r_sub.r) || IS_FLOAT_ZERO(r_sub.r)) ? AZ : 0; // AUS - sharc.stky |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_DENORMAL(r_sub.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_DENORMAL(r_sub.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; /* TODO: AV flag */ // AIS - if (sharc.astat & AI) sharc.stky |= AIS; + if (cpustate->astat & AI) cpustate->stky |= AIS; FREG(ra) = r_add.f; FREG(rs) = r_sub.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fm = Fxm * Fym, Fa = Fxa + Fya */ -INLINE void compute_fmul_fadd(int fm, int fxm, int fym, int fa, int fxa, int fya) +INLINE void compute_fmul_fadd(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fxa, int fya) { SHARC_REG r_mul, r_add; r_mul.f = FREG(fxm) * FREG(fym); @@ -1123,25 +1123,25 @@ INLINE void compute_fmul_fadd(int fm, int fxm, int fym, int fa, int fxa, int fya /* TODO: MI flag */ CLEAR_ALU_FLAGS(); - sharc.astat |= (r_add.f < 0.0f) ? AN : 0; + cpustate->astat |= (r_add.f < 0.0f) ? AN : 0; // AZ - sharc.astat |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_ZERO(r_add.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_ZERO(r_add.r)) ? AZ : 0; // AU - sharc.stky |= (IS_FLOAT_DENORMAL(r_add.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r_add.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; /* TODO: AV flag */ // AIS - if (sharc.astat & AI) sharc.stky |= AIS; + if (cpustate->astat & AI) cpustate->stky |= AIS; FREG(fm) = r_mul.f; FREG(fa) = r_add.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fm = Fxm * Fym, Fa = Fxa - Fya */ -INLINE void compute_fmul_fsub(int fm, int fxm, int fym, int fa, int fxa, int fya) +INLINE void compute_fmul_fsub(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fxa, int fya) { SHARC_REG r_mul, r_sub; r_mul.f = FREG(fxm) * FREG(fym); @@ -1154,25 +1154,25 @@ INLINE void compute_fmul_fsub(int fm, int fxm, int fym, int fa, int fxa, int fya /* TODO: MI flag */ CLEAR_ALU_FLAGS(); - sharc.astat |= (r_sub.f < 0.0f) ? AN : 0; + cpustate->astat |= (r_sub.f < 0.0f) ? AN : 0; // AZ - sharc.astat |= (IS_FLOAT_DENORMAL(r_sub.r) || IS_FLOAT_ZERO(r_sub.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_DENORMAL(r_sub.r) || IS_FLOAT_ZERO(r_sub.r)) ? AZ : 0; // AU - sharc.stky |= (IS_FLOAT_DENORMAL(r_sub.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r_sub.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; /* TODO: AV flag */ // AIS - if (sharc.astat & AI) sharc.stky |= AIS; + if (cpustate->astat & AI) cpustate->stky |= AIS; FREG(fm) = r_mul.f; FREG(fa) = r_sub.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fm = Fxm * Fym, Fa = FLOAT Fxa BY Fya */ -INLINE void compute_fmul_float_scaled(int fm, int fxm, int fym, int fa, int fxa, int fya) +INLINE void compute_fmul_float_scaled(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fxa, int fya) { SHARC_REG x; SHARC_REG r_mul, r_alu; @@ -1180,7 +1180,7 @@ INLINE void compute_fmul_float_scaled(int fm, int fxm, int fym, int fa, int fxa, x.f = (float)(INT32)REG(fxa); - r_alu.r = SCALB(x, fya); + r_alu.r = SCALB(cpustate, x, fya); CLEAR_MULTIPLIER_FLAGS(); SET_FLAG_MN(r_mul.r); @@ -1189,28 +1189,28 @@ INLINE void compute_fmul_float_scaled(int fm, int fxm, int fym, int fa, int fxa, /* TODO: MI flag */ CLEAR_ALU_FLAGS(); - sharc.astat |= (r_alu.f < 0.0f) ? AN : 0; + cpustate->astat |= (r_alu.f < 0.0f) ? AN : 0; // AZ - sharc.astat |= (IS_FLOAT_DENORMAL(r_alu.r) || IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_DENORMAL(r_alu.r) || IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; // AU - sharc.stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; /* TODO: set AV if overflowed */ FREG(fm) = r_mul.f; FREG(fa) = r_alu.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fm = Fxm * Fym, Fa = FIX Fxa BY Fya */ -INLINE void compute_fmul_fix_scaled(int fm, int fxm, int fym, int fa, int fxa, int fya) +INLINE void compute_fmul_fix_scaled(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fxa, int fya) { INT32 alu_i; SHARC_REG r_mul, r_alu; r_mul.f = FREG(fxm) * FREG(fym); - r_alu.r = SCALB(sharc.r[fxa], fya); + r_alu.r = SCALB(cpustate, cpustate->r[fxa], fya); - if (sharc.mode1 & MODE1_TRUNCATE) + if (cpustate->mode1 & MODE1_TRUNCATE) { alu_i = (INT32)(r_alu.f); } @@ -1230,19 +1230,19 @@ INLINE void compute_fmul_fix_scaled(int fm, int fxm, int fym, int fa, int fxa, i // AZ SET_FLAG_AZ(alu_i); // AU - sharc.stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(fxa))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(fxa))) ? AI : 0; /* TODO: AV flag */ FREG(fm) = r_mul.f; REG(fa) = alu_i; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fm = Fxm * Fym, Fa = MAX(Fxa, Fya) */ -INLINE void compute_fmul_fmax(int fm, int fxm, int fym, int fa, int fxa, int fya) +INLINE void compute_fmul_fmax(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fxa, int fya) { SHARC_REG r_mul, r_alu; r_mul.f = FREG(fxm) * FREG(fym); @@ -1256,23 +1256,23 @@ INLINE void compute_fmul_fmax(int fm, int fxm, int fym, int fa, int fxa, int fya /* TODO: MI flag */ CLEAR_ALU_FLAGS(); - sharc.astat |= (r_alu.f < 0.0f) ? AN : 0; + cpustate->astat |= (r_alu.f < 0.0f) ? AN : 0; // AZ - sharc.astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; // AU - sharc.stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; /* TODO: AV flag */ FREG(fm) = r_mul.f; FREG(fa) = r_alu.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fm = Fxm * Fym, Fa = MIN(Fxa, Fya) */ -INLINE void compute_fmul_fmin(int fm, int fxm, int fym, int fa, int fxa, int fya) +INLINE void compute_fmul_fmin(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fxa, int fya) { SHARC_REG r_mul, r_alu; r_mul.f = FREG(fxm) * FREG(fym); @@ -1286,24 +1286,24 @@ INLINE void compute_fmul_fmin(int fm, int fxm, int fym, int fa, int fxa, int fya /* TODO: MI flag */ CLEAR_ALU_FLAGS(); - sharc.astat |= (r_alu.f < 0.0f) ? AN : 0; + cpustate->astat |= (r_alu.f < 0.0f) ? AN : 0; // AZ - sharc.astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; + cpustate->astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; // AU - sharc.stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; /* TODO: AV flag */ FREG(fm) = r_mul.f; FREG(fa) = r_alu.f; - sharc.astat |= AF; + cpustate->astat |= AF; } /* Fm = Fxm * Fym, Fa = Fxa + Fya, Fs = Fxa - Fya */ -INLINE void compute_fmul_dual_fadd_fsub(int fm, int fxm, int fym, int fa, int fs, int fxa, int fya) +INLINE void compute_fmul_dual_fadd_fsub(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fs, int fxa, int fya) { SHARC_REG r_mul, r_add, r_sub; r_mul.f = FREG(fxm) * FREG(fym); @@ -1318,21 +1318,21 @@ INLINE void compute_fmul_dual_fadd_fsub(int fm, int fxm, int fym, int fa, int fs CLEAR_ALU_FLAGS(); // AN - sharc.astat |= ((r_add.r < 0.0f) || (r_sub.r < 0.0f)) ? AN : 0; + cpustate->astat |= ((r_add.r < 0.0f) || (r_sub.r < 0.0f)) ? AN : 0; // AZ - sharc.astat |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_ZERO(r_add.r) || + cpustate->astat |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_ZERO(r_add.r) || IS_FLOAT_DENORMAL(r_sub.r) || IS_FLOAT_ZERO(r_sub.r)) ? AZ : 0; // AUS - sharc.stky |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_DENORMAL(r_sub.r)) ? AUS : 0; + cpustate->stky |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_DENORMAL(r_sub.r)) ? AUS : 0; // AI - sharc.astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; + cpustate->astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; /* TODO: AV flag */ // AIS - if (sharc.astat & AI) sharc.stky |= AIS; + if (cpustate->astat & AI) cpustate->stky |= AIS; FREG(fm) = r_mul.f; FREG(fa) = r_add.f; FREG(fs) = r_sub.f; - sharc.astat |= AF; + cpustate->astat |= AF; } diff --git a/src/emu/cpu/sharc/sharc.c b/src/emu/cpu/sharc/sharc.c index ed83452740f..629d93df575 100644 --- a/src/emu/cpu/sharc/sharc.c +++ b/src/emu/cpu/sharc/sharc.c @@ -6,11 +6,6 @@ #include "sharc.h" #include "debugger.h" -static CPU_DISASSEMBLE( sharc ); - -static void sharc_dma_exec(int channel); -static void check_interrupts(void); - enum { SHARC_PC=1, SHARC_PCSTK, SHARC_MODE1, SHARC_MODE2, @@ -68,7 +63,8 @@ typedef struct UINT32 ext_count; } DMA_REGS; -typedef struct +typedef struct _SHARC_REGS SHARC_REGS; +struct _SHARC_REGS { UINT32 pc; SHARC_REG r[16]; @@ -129,7 +125,8 @@ typedef struct const device_config *device; const address_space *program; const address_space *data; - void (*opcode_handler)(void); + void (*opcode_handler)(SHARC_REGS *cpustate); + int icount; UINT64 opcode; UINT64 fetch_opcode; UINT64 decode_opcode; @@ -170,61 +167,63 @@ typedef struct UINT32 astat_old; UINT32 astat_old_old; UINT32 astat_old_old_old; -} SHARC_REGS; +}; -static SHARC_REGS sharc; -static int sharc_icount; +static CPU_DISASSEMBLE( sharc ); -static void (* sharc_op[512])(void); +static void sharc_dma_exec(SHARC_REGS *cpustate, int channel); +static void check_interrupts(SHARC_REGS *cpustate); + +static void (* sharc_op[512])(SHARC_REGS *cpustate); -#define ROPCODE(pc) ((UINT64)(sharc.internal_ram[((pc-0x20000) * 3) + 0]) << 32) | \ - ((UINT64)(sharc.internal_ram[((pc-0x20000) * 3) + 1]) << 16) | \ - ((UINT64)(sharc.internal_ram[((pc-0x20000) * 3) + 2]) << 0) +#define ROPCODE(pc) ((UINT64)(cpustate->internal_ram[((pc-0x20000) * 3) + 0]) << 32) | \ + ((UINT64)(cpustate->internal_ram[((pc-0x20000) * 3) + 1]) << 16) | \ + ((UINT64)(cpustate->internal_ram[((pc-0x20000) * 3) + 2]) << 0) -INLINE void CHANGE_PC(UINT32 newpc) +INLINE void CHANGE_PC(SHARC_REGS *cpustate, UINT32 newpc) { - sharc.pc = newpc; - sharc.daddr = newpc; - sharc.faddr = newpc+1; - sharc.nfaddr = newpc+2; + cpustate->pc = newpc; + cpustate->daddr = newpc; + cpustate->faddr = newpc+1; + cpustate->nfaddr = newpc+2; // next instruction to be executed - sharc.decode_opcode = ROPCODE(sharc.daddr); + cpustate->decode_opcode = ROPCODE(cpustate->daddr); // next instruction to be decoded - sharc.fetch_opcode = ROPCODE(sharc.faddr); + cpustate->fetch_opcode = ROPCODE(cpustate->faddr); } -INLINE void CHANGE_PC_DELAYED(UINT32 newpc) +INLINE void CHANGE_PC_DELAYED(SHARC_REGS *cpustate, UINT32 newpc) { - sharc.nfaddr = newpc; + cpustate->nfaddr = newpc; - sharc.delay_slot1 = sharc.pc; - sharc.delay_slot2 = sharc.daddr; + cpustate->delay_slot1 = cpustate->pc; + cpustate->delay_slot2 = cpustate->daddr; } -static void add_iop_write_latency_effect(int iop_reg, UINT32 data, int latency) +static void add_iop_write_latency_effect(SHARC_REGS *cpustate, int iop_reg, UINT32 data, int latency) { - sharc.iop_latency_cycles = latency+1; - sharc.iop_latency_reg = iop_reg; - sharc.iop_latency_data = data; + cpustate->iop_latency_cycles = latency+1; + cpustate->iop_latency_reg = iop_reg; + cpustate->iop_latency_data = data; } -static void iop_write_latency_effect(void) +static void iop_write_latency_effect(SHARC_REGS *cpustate) { - UINT32 data = sharc.iop_latency_data; + UINT32 data = cpustate->iop_latency_data; - switch (sharc.iop_latency_reg) + switch (cpustate->iop_latency_reg) { case 0x1c: { if (data & 0x1) { - sharc_dma_exec(6); + sharc_dma_exec(cpustate, 6); } break; } @@ -233,19 +232,19 @@ static void iop_write_latency_effect(void) { if (data & 0x1) { - sharc_dma_exec(7); + sharc_dma_exec(cpustate, 7); } break; } - default: fatalerror("SHARC: iop_write_latency_effect: unknown IOP register %02X", sharc.iop_latency_reg); + default: fatalerror("SHARC: iop_write_latency_effect: unknown IOP register %02X", cpustate->iop_latency_reg); } } /* IOP registers */ -static UINT32 sharc_iop_r(UINT32 address) +static UINT32 sharc_iop_r(SHARC_REGS *cpustate, UINT32 address) { switch (address) { @@ -254,18 +253,18 @@ static UINT32 sharc_iop_r(UINT32 address) case 0x37: // DMA status { UINT32 r = 0; - if (sharc.dmaop_cycles > 0) + if (cpustate->dmaop_cycles > 0) { - r |= 1 << sharc.dmaop_channel; + r |= 1 << cpustate->dmaop_channel; } return r; } - default: fatalerror("sharc_iop_r: Unimplemented IOP reg %02X at %08X", address, sharc.pc); + default: fatalerror("sharc_iop_r: Unimplemented IOP reg %02X at %08X", address, cpustate->pc); } return 0; } -static void sharc_iop_w(UINT32 address, UINT32 data) +static void sharc_iop_w(SHARC_REGS *cpustate, UINT32 address, UINT32 data) { switch (address) { @@ -284,40 +283,40 @@ static void sharc_iop_w(UINT32 address, UINT32 data) // DMA 6 case 0x1c: { - sharc.dma[6].control = data; - add_iop_write_latency_effect(0x1c, data, 1); + cpustate->dma[6].control = data; + add_iop_write_latency_effect(cpustate, 0x1c, data, 1); break; } case 0x20: break; - case 0x40: sharc.dma[6].int_index = data; return; - case 0x41: sharc.dma[6].int_modifier = data; return; - case 0x42: sharc.dma[6].int_count = data; return; - case 0x43: sharc.dma[6].chain_ptr = data; return; - case 0x44: sharc.dma[6].gen_purpose = data; return; - case 0x45: sharc.dma[6].ext_index = data; return; - case 0x46: sharc.dma[6].ext_modifier = data; return; - case 0x47: sharc.dma[6].ext_count = data; return; + case 0x40: cpustate->dma[6].int_index = data; return; + case 0x41: cpustate->dma[6].int_modifier = data; return; + case 0x42: cpustate->dma[6].int_count = data; return; + case 0x43: cpustate->dma[6].chain_ptr = data; return; + case 0x44: cpustate->dma[6].gen_purpose = data; return; + case 0x45: cpustate->dma[6].ext_index = data; return; + case 0x46: cpustate->dma[6].ext_modifier = data; return; + case 0x47: cpustate->dma[6].ext_count = data; return; // DMA 7 case 0x1d: { - sharc.dma[7].control = data; - add_iop_write_latency_effect(0x1d, data, 30); + cpustate->dma[7].control = data; + add_iop_write_latency_effect(cpustate, 0x1d, data, 30); break; } - case 0x48: sharc.dma[7].int_index = data; return; - case 0x49: sharc.dma[7].int_modifier = data; return; - case 0x4a: sharc.dma[7].int_count = data; return; - case 0x4b: sharc.dma[7].chain_ptr = data; return; - case 0x4c: sharc.dma[7].gen_purpose = data; return; - case 0x4d: sharc.dma[7].ext_index = data; return; - case 0x4e: sharc.dma[7].ext_modifier = data; return; - case 0x4f: sharc.dma[7].ext_count = data; return; + case 0x48: cpustate->dma[7].int_index = data; return; + case 0x49: cpustate->dma[7].int_modifier = data; return; + case 0x4a: cpustate->dma[7].int_count = data; return; + case 0x4b: cpustate->dma[7].chain_ptr = data; return; + case 0x4c: cpustate->dma[7].gen_purpose = data; return; + case 0x4d: cpustate->dma[7].ext_index = data; return; + case 0x4e: cpustate->dma[7].ext_modifier = data; return; + case 0x4f: cpustate->dma[7].ext_count = data; return; - default: fatalerror("sharc_iop_w: Unimplemented IOP reg %02X, %08X at %08X", address, data, sharc.pc); + default: fatalerror("sharc_iop_w: Unimplemented IOP reg %02X, %08X at %08X", address, data, cpustate->pc); } } @@ -362,46 +361,48 @@ static void build_opcode_table(void) /*****************************************************************************/ -void sharc_external_iop_write(UINT32 address, UINT32 data) +void sharc_external_iop_write(const device_config *device, UINT32 address, UINT32 data) { + SHARC_REGS *cpustate = device->token; if (address == 0x1c) { if (data != 0) { - sharc.dma[6].control = data; + cpustate->dma[6].control = data; } } else { mame_printf_debug("SHARC IOP write %08X, %08X\n", address, data); - sharc_iop_w(address, data); + sharc_iop_w(cpustate, address, data); } } -void sharc_external_dma_write(UINT32 address, UINT64 data) +void sharc_external_dma_write(const device_config *device, UINT32 address, UINT64 data) { - switch ((sharc.dma[6].control >> 6) & 0x3) + SHARC_REGS *cpustate = device->token; + switch ((cpustate->dma[6].control >> 6) & 0x3) { case 2: // 16/48 packing { int shift = address % 3; - UINT64 r = pm_read48(sharc.dma[6].int_index); + UINT64 r = pm_read48(cpustate, cpustate->dma[6].int_index); r &= ~((UINT64)(0xffff) << (shift*16)); r |= (data & 0xffff) << (shift*16); - pm_write48(sharc.dma[6].int_index, r); + pm_write48(cpustate, cpustate->dma[6].int_index, r); if (shift == 2) { - sharc.dma[6].int_index += sharc.dma[6].int_modifier; + cpustate->dma[6].int_index += cpustate->dma[6].int_modifier; } break; } default: { - fatalerror("sharc_external_dma_write: unimplemented packing mode %d\n", (sharc.dma[6].control >> 6) & 0x3); + fatalerror("sharc_external_dma_write: unimplemented packing mode %d\n", (cpustate->dma[6].control >> 6) & 0x3); } } } @@ -422,158 +423,160 @@ static CPU_DISASSEMBLE( sharc ) static CPU_INIT( sharc ) { + SHARC_REGS *cpustate = device->token; const sharc_config *cfg = device->static_config; int saveindex; - sharc.boot_mode = cfg->boot_mode; + cpustate->boot_mode = cfg->boot_mode; - sharc.irq_callback = irqcallback; - sharc.device = device; - sharc.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); - sharc.data = memory_find_address_space(device, ADDRESS_SPACE_DATA); + cpustate->irq_callback = irqcallback; + cpustate->device = device; + cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); + cpustate->data = memory_find_address_space(device, ADDRESS_SPACE_DATA); build_opcode_table(); - sharc.internal_ram = auto_malloc(2 * 0x10000 * sizeof(UINT16)); // 2x 128KB - sharc.internal_ram_block0 = &sharc.internal_ram[0]; - sharc.internal_ram_block1 = &sharc.internal_ram[0x20000/2]; + cpustate->internal_ram = auto_malloc(2 * 0x10000 * sizeof(UINT16)); // 2x 128KB + cpustate->internal_ram_block0 = &cpustate->internal_ram[0]; + cpustate->internal_ram_block1 = &cpustate->internal_ram[0x20000/2]; - state_save_register_device_item(device, 0, sharc.pc); - state_save_register_device_item_pointer(device, 0, (&sharc.r[0].r), ARRAY_LENGTH(sharc.r)); - state_save_register_device_item_pointer(device, 0, (&sharc.reg_alt[0].r), ARRAY_LENGTH(sharc.reg_alt)); - state_save_register_device_item(device, 0, sharc.mrf); - state_save_register_device_item(device, 0, sharc.mrb); + state_save_register_device_item(device, 0, cpustate->pc); + state_save_register_device_item_pointer(device, 0, (&cpustate->r[0].r), ARRAY_LENGTH(cpustate->r)); + state_save_register_device_item_pointer(device, 0, (&cpustate->reg_alt[0].r), ARRAY_LENGTH(cpustate->reg_alt)); + state_save_register_device_item(device, 0, cpustate->mrf); + state_save_register_device_item(device, 0, cpustate->mrb); - state_save_register_device_item_array(device, 0, sharc.pcstack); - state_save_register_device_item_array(device, 0, sharc.lcstack); - state_save_register_device_item_array(device, 0, sharc.lastack); - state_save_register_device_item(device, 0, sharc.lstkp); + state_save_register_device_item_array(device, 0, cpustate->pcstack); + state_save_register_device_item_array(device, 0, cpustate->lcstack); + state_save_register_device_item_array(device, 0, cpustate->lastack); + state_save_register_device_item(device, 0, cpustate->lstkp); - state_save_register_device_item(device, 0, sharc.faddr); - state_save_register_device_item(device, 0, sharc.daddr); - state_save_register_device_item(device, 0, sharc.pcstk); - state_save_register_device_item(device, 0, sharc.pcstkp); - state_save_register_device_item(device, 0, sharc.laddr); - state_save_register_device_item(device, 0, sharc.curlcntr); - state_save_register_device_item(device, 0, sharc.lcntr); + state_save_register_device_item(device, 0, cpustate->faddr); + state_save_register_device_item(device, 0, cpustate->daddr); + state_save_register_device_item(device, 0, cpustate->pcstk); + state_save_register_device_item(device, 0, cpustate->pcstkp); + state_save_register_device_item(device, 0, cpustate->laddr); + state_save_register_device_item(device, 0, cpustate->curlcntr); + state_save_register_device_item(device, 0, cpustate->lcntr); - state_save_register_device_item_array(device, 0, sharc.dag1.i); - state_save_register_device_item_array(device, 0, sharc.dag1.m); - state_save_register_device_item_array(device, 0, sharc.dag1.b); - state_save_register_device_item_array(device, 0, sharc.dag1.l); - state_save_register_device_item_array(device, 0, sharc.dag2.i); - state_save_register_device_item_array(device, 0, sharc.dag2.m); - state_save_register_device_item_array(device, 0, sharc.dag2.b); - state_save_register_device_item_array(device, 0, sharc.dag2.l); - state_save_register_device_item_array(device, 0, sharc.dag1_alt.i); - state_save_register_device_item_array(device, 0, sharc.dag1_alt.m); - state_save_register_device_item_array(device, 0, sharc.dag1_alt.b); - state_save_register_device_item_array(device, 0, sharc.dag1_alt.l); - state_save_register_device_item_array(device, 0, sharc.dag2_alt.i); - state_save_register_device_item_array(device, 0, sharc.dag2_alt.m); - state_save_register_device_item_array(device, 0, sharc.dag2_alt.b); - state_save_register_device_item_array(device, 0, sharc.dag2_alt.l); + state_save_register_device_item_array(device, 0, cpustate->dag1.i); + state_save_register_device_item_array(device, 0, cpustate->dag1.m); + state_save_register_device_item_array(device, 0, cpustate->dag1.b); + state_save_register_device_item_array(device, 0, cpustate->dag1.l); + state_save_register_device_item_array(device, 0, cpustate->dag2.i); + state_save_register_device_item_array(device, 0, cpustate->dag2.m); + state_save_register_device_item_array(device, 0, cpustate->dag2.b); + state_save_register_device_item_array(device, 0, cpustate->dag2.l); + state_save_register_device_item_array(device, 0, cpustate->dag1_alt.i); + state_save_register_device_item_array(device, 0, cpustate->dag1_alt.m); + state_save_register_device_item_array(device, 0, cpustate->dag1_alt.b); + state_save_register_device_item_array(device, 0, cpustate->dag1_alt.l); + state_save_register_device_item_array(device, 0, cpustate->dag2_alt.i); + state_save_register_device_item_array(device, 0, cpustate->dag2_alt.m); + state_save_register_device_item_array(device, 0, cpustate->dag2_alt.b); + state_save_register_device_item_array(device, 0, cpustate->dag2_alt.l); - for (saveindex = 0; saveindex < ARRAY_LENGTH(sharc.dma); saveindex++) + for (saveindex = 0; saveindex < ARRAY_LENGTH(cpustate->dma); saveindex++) { - state_save_register_device_item(device, saveindex, sharc.dma[saveindex].control); - state_save_register_device_item(device, saveindex, sharc.dma[saveindex].int_index); - state_save_register_device_item(device, saveindex, sharc.dma[saveindex].int_modifier); - state_save_register_device_item(device, saveindex, sharc.dma[saveindex].int_count); - state_save_register_device_item(device, saveindex, sharc.dma[saveindex].chain_ptr); - state_save_register_device_item(device, saveindex, sharc.dma[saveindex].gen_purpose); - state_save_register_device_item(device, saveindex, sharc.dma[saveindex].ext_index); - state_save_register_device_item(device, saveindex, sharc.dma[saveindex].ext_modifier); - state_save_register_device_item(device, saveindex, sharc.dma[saveindex].ext_count); + state_save_register_device_item(device, saveindex, cpustate->dma[saveindex].control); + state_save_register_device_item(device, saveindex, cpustate->dma[saveindex].int_index); + state_save_register_device_item(device, saveindex, cpustate->dma[saveindex].int_modifier); + state_save_register_device_item(device, saveindex, cpustate->dma[saveindex].int_count); + state_save_register_device_item(device, saveindex, cpustate->dma[saveindex].chain_ptr); + state_save_register_device_item(device, saveindex, cpustate->dma[saveindex].gen_purpose); + state_save_register_device_item(device, saveindex, cpustate->dma[saveindex].ext_index); + state_save_register_device_item(device, saveindex, cpustate->dma[saveindex].ext_modifier); + state_save_register_device_item(device, saveindex, cpustate->dma[saveindex].ext_count); } - state_save_register_device_item(device, 0, sharc.mode1); - state_save_register_device_item(device, 0, sharc.mode2); - state_save_register_device_item(device, 0, sharc.astat); - state_save_register_device_item(device, 0, sharc.stky); - state_save_register_device_item(device, 0, sharc.irptl); - state_save_register_device_item(device, 0, sharc.imask); - state_save_register_device_item(device, 0, sharc.imaskp); - state_save_register_device_item(device, 0, sharc.ustat1); - state_save_register_device_item(device, 0, sharc.ustat2); + state_save_register_device_item(device, 0, cpustate->mode1); + state_save_register_device_item(device, 0, cpustate->mode2); + state_save_register_device_item(device, 0, cpustate->astat); + state_save_register_device_item(device, 0, cpustate->stky); + state_save_register_device_item(device, 0, cpustate->irptl); + state_save_register_device_item(device, 0, cpustate->imask); + state_save_register_device_item(device, 0, cpustate->imaskp); + state_save_register_device_item(device, 0, cpustate->ustat1); + state_save_register_device_item(device, 0, cpustate->ustat2); - state_save_register_device_item_array(device, 0, sharc.flag); + state_save_register_device_item_array(device, 0, cpustate->flag); - state_save_register_device_item(device, 0, sharc.syscon); - state_save_register_device_item(device, 0, sharc.sysstat); + state_save_register_device_item(device, 0, cpustate->syscon); + state_save_register_device_item(device, 0, cpustate->sysstat); - for (saveindex = 0; saveindex < ARRAY_LENGTH(sharc.status_stack); saveindex++) + for (saveindex = 0; saveindex < ARRAY_LENGTH(cpustate->status_stack); saveindex++) { - state_save_register_device_item(device, saveindex, sharc.status_stack[saveindex].mode1); - state_save_register_device_item(device, saveindex, sharc.status_stack[saveindex].astat); + state_save_register_device_item(device, saveindex, cpustate->status_stack[saveindex].mode1); + state_save_register_device_item(device, saveindex, cpustate->status_stack[saveindex].astat); } - state_save_register_device_item(device, 0, sharc.status_stkp); + state_save_register_device_item(device, 0, cpustate->status_stkp); - state_save_register_device_item(device, 0, sharc.px); + state_save_register_device_item(device, 0, cpustate->px); - state_save_register_device_item_pointer(device, 0, sharc.internal_ram, 2 * 0x10000); + state_save_register_device_item_pointer(device, 0, cpustate->internal_ram, 2 * 0x10000); - state_save_register_device_item(device, 0, sharc.opcode); - state_save_register_device_item(device, 0, sharc.fetch_opcode); - state_save_register_device_item(device, 0, sharc.decode_opcode); + state_save_register_device_item(device, 0, cpustate->opcode); + state_save_register_device_item(device, 0, cpustate->fetch_opcode); + state_save_register_device_item(device, 0, cpustate->decode_opcode); - state_save_register_device_item(device, 0, sharc.nfaddr); + state_save_register_device_item(device, 0, cpustate->nfaddr); - state_save_register_device_item(device, 0, sharc.idle); - state_save_register_device_item(device, 0, sharc.irq_active); - state_save_register_device_item(device, 0, sharc.active_irq_num); + state_save_register_device_item(device, 0, cpustate->idle); + state_save_register_device_item(device, 0, cpustate->irq_active); + state_save_register_device_item(device, 0, cpustate->active_irq_num); - state_save_register_device_item(device, 0, sharc.dmaop_src); - state_save_register_device_item(device, 0, sharc.dmaop_dst); - state_save_register_device_item(device, 0, sharc.dmaop_chain_ptr); - state_save_register_device_item(device, 0, sharc.dmaop_src_modifier); - state_save_register_device_item(device, 0, sharc.dmaop_dst_modifier); - state_save_register_device_item(device, 0, sharc.dmaop_src_count); - state_save_register_device_item(device, 0, sharc.dmaop_dst_count); - state_save_register_device_item(device, 0, sharc.dmaop_pmode); - state_save_register_device_item(device, 0, sharc.dmaop_cycles); - state_save_register_device_item(device, 0, sharc.dmaop_channel); - state_save_register_device_item(device, 0, sharc.dmaop_chained_direction); + state_save_register_device_item(device, 0, cpustate->dmaop_src); + state_save_register_device_item(device, 0, cpustate->dmaop_dst); + state_save_register_device_item(device, 0, cpustate->dmaop_chain_ptr); + state_save_register_device_item(device, 0, cpustate->dmaop_src_modifier); + state_save_register_device_item(device, 0, cpustate->dmaop_dst_modifier); + state_save_register_device_item(device, 0, cpustate->dmaop_src_count); + state_save_register_device_item(device, 0, cpustate->dmaop_dst_count); + state_save_register_device_item(device, 0, cpustate->dmaop_pmode); + state_save_register_device_item(device, 0, cpustate->dmaop_cycles); + state_save_register_device_item(device, 0, cpustate->dmaop_channel); + state_save_register_device_item(device, 0, cpustate->dmaop_chained_direction); - state_save_register_device_item(device, 0, sharc.interrupt_active); + state_save_register_device_item(device, 0, cpustate->interrupt_active); - state_save_register_device_item(device, 0, sharc.iop_latency_cycles); - state_save_register_device_item(device, 0, sharc.iop_latency_reg); - state_save_register_device_item(device, 0, sharc.iop_latency_data); + state_save_register_device_item(device, 0, cpustate->iop_latency_cycles); + state_save_register_device_item(device, 0, cpustate->iop_latency_reg); + state_save_register_device_item(device, 0, cpustate->iop_latency_data); - state_save_register_device_item(device, 0, sharc.delay_slot1); - state_save_register_device_item(device, 0, sharc.delay_slot2); + state_save_register_device_item(device, 0, cpustate->delay_slot1); + state_save_register_device_item(device, 0, cpustate->delay_slot2); - state_save_register_device_item(device, 0, sharc.systemreg_latency_cycles); - state_save_register_device_item(device, 0, sharc.systemreg_latency_reg); - state_save_register_device_item(device, 0, sharc.systemreg_latency_data); - state_save_register_device_item(device, 0, sharc.systemreg_previous_data); + state_save_register_device_item(device, 0, cpustate->systemreg_latency_cycles); + state_save_register_device_item(device, 0, cpustate->systemreg_latency_reg); + state_save_register_device_item(device, 0, cpustate->systemreg_latency_data); + state_save_register_device_item(device, 0, cpustate->systemreg_previous_data); - state_save_register_device_item(device, 0, sharc.astat_old); - state_save_register_device_item(device, 0, sharc.astat_old_old); - state_save_register_device_item(device, 0, sharc.astat_old_old_old); + state_save_register_device_item(device, 0, cpustate->astat_old); + state_save_register_device_item(device, 0, cpustate->astat_old_old); + state_save_register_device_item(device, 0, cpustate->astat_old_old_old); } static CPU_RESET( sharc ) { - memset(sharc.internal_ram, 0, 2 * 0x10000 * sizeof(UINT16)); + SHARC_REGS *cpustate = device->token; + memset(cpustate->internal_ram, 0, 2 * 0x10000 * sizeof(UINT16)); - switch(sharc.boot_mode) + switch(cpustate->boot_mode) { case BOOT_MODE_EPROM: { - sharc.dma[6].int_index = 0x20000; - sharc.dma[6].int_modifier = 1; - sharc.dma[6].int_count = 0x100; - sharc.dma[6].ext_index = 0x400000; - sharc.dma[6].ext_modifier = 1; - sharc.dma[6].ext_count = 0x600; - sharc.dma[6].control = 0x2a1; + cpustate->dma[6].int_index = 0x20000; + cpustate->dma[6].int_modifier = 1; + cpustate->dma[6].int_count = 0x100; + cpustate->dma[6].ext_index = 0x400000; + cpustate->dma[6].ext_modifier = 1; + cpustate->dma[6].ext_count = 0x600; + cpustate->dma[6].control = 0x2a1; - sharc_dma_exec(6); - dma_op(sharc.dmaop_src, sharc.dmaop_dst, sharc.dmaop_src_modifier, sharc.dmaop_dst_modifier, - sharc.dmaop_src_count, sharc.dmaop_dst_count, sharc.dmaop_pmode); - sharc.dmaop_cycles = 0; + sharc_dma_exec(cpustate, 6); + dma_op(cpustate, cpustate->dmaop_src, cpustate->dmaop_dst, cpustate->dmaop_src_modifier, cpustate->dmaop_dst_modifier, + cpustate->dmaop_src_count, cpustate->dmaop_dst_count, cpustate->dmaop_pmode); + cpustate->dmaop_cycles = 0; break; } @@ -582,18 +585,18 @@ static CPU_RESET( sharc ) break; default: - fatalerror("SHARC: Unimplemented boot mode %d", sharc.boot_mode); + fatalerror("SHARC: Unimplemented boot mode %d", cpustate->boot_mode); } - sharc.pc = 0x20004; - sharc.daddr = sharc.pc + 1; - sharc.faddr = sharc.daddr + 1; - sharc.nfaddr = sharc.faddr+1; + cpustate->pc = 0x20004; + cpustate->daddr = cpustate->pc + 1; + cpustate->faddr = cpustate->daddr + 1; + cpustate->nfaddr = cpustate->faddr+1; - sharc.idle = 0; - sharc.stky = 0x5400000; + cpustate->idle = 0; + cpustate->stky = 0x5400000; - sharc.interrupt_active = 0; + cpustate->interrupt_active = 0; } static CPU_EXIT( sharc ) @@ -603,38 +606,29 @@ static CPU_EXIT( sharc ) static CPU_GET_CONTEXT( sharc ) { - /* copy the context */ - if (dst) - { - *(SHARC_REGS *)dst = sharc; - } } static CPU_SET_CONTEXT( sharc ) { - /* copy the context */ - if (src) - { - sharc = *(SHARC_REGS *)src; - } } -static void sharc_set_irq_line(int irqline, int state) +static void sharc_set_irq_line(SHARC_REGS *cpustate, int irqline, int state) { if (state) { - sharc.irq_active |= 1 << (8-irqline); + cpustate->irq_active |= 1 << (8-irqline); } } -void sharc_set_flag_input(int flag_num, int state) +void sharc_set_flag_input(const device_config *device, int flag_num, int state) { + SHARC_REGS *cpustate = device->token; if (flag_num >= 0 && flag_num < 4) { // Check if flag is set to input in MODE2 (bit == 0) - if ((sharc.mode2 & (1 << (flag_num+15))) == 0) + if ((cpustate->mode2 & (1 << (flag_num+15))) == 0) { - sharc.flag[flag_num] = state ? 1 : 0; + cpustate->flag[flag_num] = state ? 1 : 0; } else { @@ -643,221 +637,222 @@ void sharc_set_flag_input(int flag_num, int state) } } -static void check_interrupts(void) +static void check_interrupts(SHARC_REGS *cpustate) { int i; - if ((sharc.imask & sharc.irq_active) && (sharc.mode1 & MODE1_IRPTEN) && !sharc.interrupt_active && - sharc.pc != sharc.delay_slot1 && sharc.pc != sharc.delay_slot2) + if ((cpustate->imask & cpustate->irq_active) && (cpustate->mode1 & MODE1_IRPTEN) && !cpustate->interrupt_active && + cpustate->pc != cpustate->delay_slot1 && cpustate->pc != cpustate->delay_slot2) { int which = 0; for (i=0; i < 32; i++) { - if (sharc.irq_active & (1 << i)) + if (cpustate->irq_active & (1 << i)) { break; } which++; } - if (sharc.idle) + if (cpustate->idle) { - PUSH_PC(sharc.pc+1); + PUSH_PC(cpustate, cpustate->pc+1); } else { - PUSH_PC(sharc.daddr); + PUSH_PC(cpustate, cpustate->daddr); } - sharc.irptl |= 1 << which; + cpustate->irptl |= 1 << which; if (which >= 6 && which <= 8) { - PUSH_STATUS_STACK(); + PUSH_STATUS_STACK(cpustate); } - CHANGE_PC(0x20000 + (which * 0x4)); + CHANGE_PC(cpustate, 0x20000 + (which * 0x4)); /* TODO: alter IMASKP */ - sharc.active_irq_num = which; - sharc.irq_active &= ~(1 << which); + cpustate->active_irq_num = which; + cpustate->irq_active &= ~(1 << which); - sharc.interrupt_active = 1; + cpustate->interrupt_active = 1; } } static CPU_EXECUTE( sharc ) { - sharc_icount = cycles; + SHARC_REGS *cpustate = device->token; + cpustate->icount = cycles; - if (sharc.idle && sharc.irq_active == 0) + if (cpustate->idle && cpustate->irq_active == 0) { // handle pending DMA transfers - if (sharc.dmaop_cycles > 0) + if (cpustate->dmaop_cycles > 0) { - sharc.dmaop_cycles -= cycles; - if (sharc.dmaop_cycles <= 0) + cpustate->dmaop_cycles -= cycles; + if (cpustate->dmaop_cycles <= 0) { - sharc.dmaop_cycles = 0; - dma_op(sharc.dmaop_src, sharc.dmaop_dst, sharc.dmaop_src_modifier, sharc.dmaop_dst_modifier, sharc.dmaop_src_count, sharc.dmaop_dst_count, sharc.dmaop_pmode); - if (sharc.dmaop_chain_ptr != 0) + cpustate->dmaop_cycles = 0; + dma_op(cpustate, cpustate->dmaop_src, cpustate->dmaop_dst, cpustate->dmaop_src_modifier, cpustate->dmaop_dst_modifier, cpustate->dmaop_src_count, cpustate->dmaop_dst_count, cpustate->dmaop_pmode); + if (cpustate->dmaop_chain_ptr != 0) { - schedule_chained_dma_op(sharc.dmaop_channel, sharc.dmaop_chain_ptr, sharc.dmaop_chained_direction); + schedule_chained_dma_op(cpustate, cpustate->dmaop_channel, cpustate->dmaop_chain_ptr, cpustate->dmaop_chained_direction); } } } - sharc_icount = 0; - debugger_instruction_hook(device, sharc.daddr); + cpustate->icount = 0; + debugger_instruction_hook(device, cpustate->daddr); return cycles; } - if (sharc.irq_active != 0) + if (cpustate->irq_active != 0) { - check_interrupts(); - sharc.idle = 0; + check_interrupts(cpustate); + cpustate->idle = 0; } // fill the initial pipeline // next executed instruction - sharc.opcode = ROPCODE(sharc.daddr); - sharc.opcode_handler = sharc_op[(sharc.opcode >> 39) & 0x1ff]; + cpustate->opcode = ROPCODE(cpustate->daddr); + cpustate->opcode_handler = sharc_op[(cpustate->opcode >> 39) & 0x1ff]; // next decoded instruction - sharc.fetch_opcode = ROPCODE(sharc.faddr); + cpustate->fetch_opcode = ROPCODE(cpustate->faddr); - while (sharc_icount > 0 && !sharc.idle) + while (cpustate->icount > 0 && !cpustate->idle) { - sharc.pc = sharc.daddr; - sharc.daddr = sharc.faddr; - sharc.faddr = sharc.nfaddr; - sharc.nfaddr++; + cpustate->pc = cpustate->daddr; + cpustate->daddr = cpustate->faddr; + cpustate->faddr = cpustate->nfaddr; + cpustate->nfaddr++; - sharc.astat_old_old_old = sharc.astat_old_old; - sharc.astat_old_old = sharc.astat_old; - sharc.astat_old = sharc.astat; + cpustate->astat_old_old_old = cpustate->astat_old_old; + cpustate->astat_old_old = cpustate->astat_old; + cpustate->astat_old = cpustate->astat; - sharc.decode_opcode = sharc.fetch_opcode; + cpustate->decode_opcode = cpustate->fetch_opcode; // fetch next instruction - sharc.fetch_opcode = ROPCODE(sharc.faddr); + cpustate->fetch_opcode = ROPCODE(cpustate->faddr); - debugger_instruction_hook(device, sharc.pc); + debugger_instruction_hook(device, cpustate->pc); // handle looping - if (sharc.pc == (sharc.laddr & 0xffffff)) + if (cpustate->pc == (cpustate->laddr & 0xffffff)) { - switch (sharc.laddr >> 30) + switch (cpustate->laddr >> 30) { case 0: // arithmetic condition-based { - int condition = (sharc.laddr >> 24) & 0x1f; + int condition = (cpustate->laddr >> 24) & 0x1f; { - UINT32 looptop = TOP_PC(); - if (sharc.pc - looptop > 2) + UINT32 looptop = TOP_PC(cpustate); + if (cpustate->pc - looptop > 2) { - sharc.astat = sharc.astat_old_old_old; + cpustate->astat = cpustate->astat_old_old_old; } } - if (DO_CONDITION_CODE(condition)) + if (DO_CONDITION_CODE(cpustate, condition)) { - POP_LOOP(); - POP_PC(); + POP_LOOP(cpustate); + POP_PC(cpustate); } else { - CHANGE_PC(TOP_PC()); + CHANGE_PC(cpustate, TOP_PC(cpustate)); } - sharc.astat = sharc.astat_old; + cpustate->astat = cpustate->astat_old; break; } case 1: // counter-based, length 1 { - //fatalerror("SHARC: counter-based loop, length 1 at %08X", sharc.pc); + //fatalerror("SHARC: counter-based loop, length 1 at %08X", cpustate->pc); //break; } case 2: // counter-based, length 2 { - //fatalerror("SHARC: counter-based loop, length 2 at %08X", sharc.pc); + //fatalerror("SHARC: counter-based loop, length 2 at %08X", cpustate->pc); //break; } case 3: // counter-based, length >2 { - --sharc.lcstack[sharc.lstkp]; - --sharc.curlcntr; - if (sharc.curlcntr == 0) + --cpustate->lcstack[cpustate->lstkp]; + --cpustate->curlcntr; + if (cpustate->curlcntr == 0) { - POP_LOOP(); - POP_PC(); + POP_LOOP(cpustate); + POP_PC(cpustate); } else { - CHANGE_PC(TOP_PC()); + CHANGE_PC(cpustate, TOP_PC(cpustate)); } } } } // execute current instruction - sharc.opcode_handler(); + cpustate->opcode_handler(cpustate); // decode next instruction - sharc.opcode = sharc.decode_opcode; - sharc.opcode_handler = sharc_op[(sharc.opcode >> 39) & 0x1ff]; + cpustate->opcode = cpustate->decode_opcode; + cpustate->opcode_handler = sharc_op[(cpustate->opcode >> 39) & 0x1ff]; // System register latency effect - if (sharc.systemreg_latency_cycles > 0) + if (cpustate->systemreg_latency_cycles > 0) { - --sharc.systemreg_latency_cycles; - if (sharc.systemreg_latency_cycles <= 0) + --cpustate->systemreg_latency_cycles; + if (cpustate->systemreg_latency_cycles <= 0) { - systemreg_write_latency_effect(); + systemreg_write_latency_effect(cpustate); } } // IOP register latency effect - if (sharc.iop_latency_cycles > 0) + if (cpustate->iop_latency_cycles > 0) { - --sharc.iop_latency_cycles; - if (sharc.iop_latency_cycles <= 0) + --cpustate->iop_latency_cycles; + if (cpustate->iop_latency_cycles <= 0) { - iop_write_latency_effect(); + iop_write_latency_effect(cpustate); } } // DMA transfer - if (sharc.dmaop_cycles > 0) + if (cpustate->dmaop_cycles > 0) { - --sharc.dmaop_cycles; - if (sharc.dmaop_cycles <= 0) + --cpustate->dmaop_cycles; + if (cpustate->dmaop_cycles <= 0) { - sharc.irptl |= (1 << (sharc.dmaop_channel+10)); + cpustate->irptl |= (1 << (cpustate->dmaop_channel+10)); /* DMA interrupt */ - if (sharc.imask & (1 << (sharc.dmaop_channel+10))) + if (cpustate->imask & (1 << (cpustate->dmaop_channel+10))) { - sharc.irq_active |= 1 << (sharc.dmaop_channel+10); + cpustate->irq_active |= 1 << (cpustate->dmaop_channel+10); } - dma_op(sharc.dmaop_src, sharc.dmaop_dst, sharc.dmaop_src_modifier, sharc.dmaop_dst_modifier, sharc.dmaop_src_count, sharc.dmaop_dst_count, sharc.dmaop_pmode); - if (sharc.dmaop_chain_ptr != 0) + dma_op(cpustate, cpustate->dmaop_src, cpustate->dmaop_dst, cpustate->dmaop_src_modifier, cpustate->dmaop_dst_modifier, cpustate->dmaop_src_count, cpustate->dmaop_dst_count, cpustate->dmaop_pmode); + if (cpustate->dmaop_chain_ptr != 0) { - schedule_chained_dma_op(sharc.dmaop_channel, sharc.dmaop_chain_ptr, sharc.dmaop_chained_direction); + schedule_chained_dma_op(cpustate, cpustate->dmaop_channel, cpustate->dmaop_chain_ptr, cpustate->dmaop_chained_direction); } } } - --sharc_icount; + --cpustate->icount; }; - return cycles - sharc_icount; + return cycles - cpustate->icount; } /************************************************************************** @@ -866,97 +861,99 @@ static CPU_EXECUTE( sharc ) static CPU_SET_INFO( sharc ) { + SHARC_REGS *cpustate = device->token; + switch (state) { case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + SHARC_PC: sharc.pc = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_FADDR: sharc.faddr = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_DADDR: sharc.daddr = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_PC: cpustate->pc = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_FADDR: cpustate->faddr = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_DADDR: cpustate->daddr = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R0: sharc.r[0].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R1: sharc.r[1].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R2: sharc.r[2].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R3: sharc.r[3].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R4: sharc.r[4].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R5: sharc.r[5].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R6: sharc.r[6].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R7: sharc.r[7].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R8: sharc.r[8].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R9: sharc.r[9].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R10: sharc.r[10].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R11: sharc.r[11].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R12: sharc.r[12].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R13: sharc.r[13].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R14: sharc.r[14].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R15: sharc.r[15].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R0: cpustate->r[0].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R1: cpustate->r[1].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R2: cpustate->r[2].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R3: cpustate->r[3].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R4: cpustate->r[4].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R5: cpustate->r[5].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R6: cpustate->r[6].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R7: cpustate->r[7].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R8: cpustate->r[8].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R9: cpustate->r[9].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R10: cpustate->r[10].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R11: cpustate->r[11].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R12: cpustate->r[12].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R13: cpustate->r[13].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R14: cpustate->r[14].r = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_R15: cpustate->r[15].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I0: sharc.dag1.i[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I1: sharc.dag1.i[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I2: sharc.dag1.i[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I3: sharc.dag1.i[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I4: sharc.dag1.i[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I5: sharc.dag1.i[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I6: sharc.dag1.i[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I7: sharc.dag1.i[7] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I8: sharc.dag2.i[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I9: sharc.dag2.i[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I10: sharc.dag2.i[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I11: sharc.dag2.i[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I12: sharc.dag2.i[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I13: sharc.dag2.i[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I14: sharc.dag2.i[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I15: sharc.dag2.i[7] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I0: cpustate->dag1.i[0] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I1: cpustate->dag1.i[1] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I2: cpustate->dag1.i[2] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I3: cpustate->dag1.i[3] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I4: cpustate->dag1.i[4] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I5: cpustate->dag1.i[5] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I6: cpustate->dag1.i[6] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I7: cpustate->dag1.i[7] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I8: cpustate->dag2.i[0] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I9: cpustate->dag2.i[1] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I10: cpustate->dag2.i[2] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I11: cpustate->dag2.i[3] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I12: cpustate->dag2.i[4] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I13: cpustate->dag2.i[5] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I14: cpustate->dag2.i[6] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_I15: cpustate->dag2.i[7] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M0: sharc.dag1.m[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M1: sharc.dag1.m[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M2: sharc.dag1.m[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M3: sharc.dag1.m[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M4: sharc.dag1.m[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M5: sharc.dag1.m[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M6: sharc.dag1.m[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M7: sharc.dag1.m[7] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M8: sharc.dag2.m[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M9: sharc.dag2.m[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M10: sharc.dag2.m[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M11: sharc.dag2.m[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M12: sharc.dag2.m[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M13: sharc.dag2.m[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M14: sharc.dag2.m[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M15: sharc.dag2.m[7] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M0: cpustate->dag1.m[0] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M1: cpustate->dag1.m[1] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M2: cpustate->dag1.m[2] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M3: cpustate->dag1.m[3] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M4: cpustate->dag1.m[4] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M5: cpustate->dag1.m[5] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M6: cpustate->dag1.m[6] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M7: cpustate->dag1.m[7] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M8: cpustate->dag2.m[0] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M9: cpustate->dag2.m[1] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M10: cpustate->dag2.m[2] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M11: cpustate->dag2.m[3] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M12: cpustate->dag2.m[4] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M13: cpustate->dag2.m[5] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M14: cpustate->dag2.m[6] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_M15: cpustate->dag2.m[7] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L0: sharc.dag1.l[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L1: sharc.dag1.l[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L2: sharc.dag1.l[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L3: sharc.dag1.l[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L4: sharc.dag1.l[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L5: sharc.dag1.l[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L6: sharc.dag1.l[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L7: sharc.dag1.l[7] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L8: sharc.dag2.l[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L9: sharc.dag2.l[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L10: sharc.dag2.l[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L11: sharc.dag2.l[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L12: sharc.dag2.l[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L13: sharc.dag2.l[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L14: sharc.dag2.l[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L15: sharc.dag2.m[7] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L0: cpustate->dag1.l[0] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L1: cpustate->dag1.l[1] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L2: cpustate->dag1.l[2] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L3: cpustate->dag1.l[3] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L4: cpustate->dag1.l[4] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L5: cpustate->dag1.l[5] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L6: cpustate->dag1.l[6] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L7: cpustate->dag1.l[7] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L8: cpustate->dag2.l[0] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L9: cpustate->dag2.l[1] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L10: cpustate->dag2.l[2] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L11: cpustate->dag2.l[3] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L12: cpustate->dag2.l[4] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L13: cpustate->dag2.l[5] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L14: cpustate->dag2.l[6] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_L15: cpustate->dag2.m[7] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B0: sharc.dag1.b[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B1: sharc.dag1.b[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B2: sharc.dag1.b[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B3: sharc.dag1.b[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B4: sharc.dag1.b[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B5: sharc.dag1.b[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B6: sharc.dag1.b[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B7: sharc.dag1.b[7] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B8: sharc.dag2.b[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B9: sharc.dag2.b[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B10: sharc.dag2.b[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B11: sharc.dag2.b[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B12: sharc.dag2.b[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B13: sharc.dag2.b[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B14: sharc.dag2.b[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B15: sharc.dag2.b[7] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B0: cpustate->dag1.b[0] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B1: cpustate->dag1.b[1] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B2: cpustate->dag1.b[2] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B3: cpustate->dag1.b[3] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B4: cpustate->dag1.b[4] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B5: cpustate->dag1.b[5] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B6: cpustate->dag1.b[6] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B7: cpustate->dag1.b[7] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B8: cpustate->dag2.b[0] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B9: cpustate->dag2.b[1] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B10: cpustate->dag2.b[2] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B11: cpustate->dag2.b[3] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B12: cpustate->dag2.b[4] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B13: cpustate->dag2.b[5] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B14: cpustate->dag2.b[6] = info->i; break; + case CPUINFO_INT_REGISTER + SHARC_B15: cpustate->dag2.b[7] = info->i; break; } } @@ -965,12 +962,12 @@ static CPU_SET_INFO( adsp21062 ) { if (state >= CPUINFO_INT_INPUT_STATE && state <= CPUINFO_INT_INPUT_STATE + 2) { - sharc_set_irq_line(state-CPUINFO_INT_INPUT_STATE, info->i); + sharc_set_irq_line(device->token, state-CPUINFO_INT_INPUT_STATE, info->i); return; } else if (state >= CPUINFO_INT_INPUT_STATE + SHARC_INPUT_FLAG0 && state <= CPUINFO_INT_INPUT_STATE + SHARC_INPUT_FLAG3) { - sharc_set_flag_input(state-(CPUINFO_INT_INPUT_STATE + SHARC_INPUT_FLAG0), info->i); + sharc_set_flag_input(device, state-(CPUINFO_INT_INPUT_STATE + SHARC_INPUT_FLAG0), info->i); return; } switch(state) @@ -983,6 +980,7 @@ static CPU_SET_INFO( adsp21062 ) static CPU_READ( sharc ) { + SHARC_REGS *cpustate = device->token; if (space == ADDRESS_SPACE_PROGRAM) { int address = offset >> 3; @@ -994,12 +992,12 @@ static CPU_READ( sharc ) case 1: { int frac = offset & 7; - *value = (pm_read48(offset >> 3) >> ((frac^7) * 8)) & 0xff; + *value = (pm_read48(cpustate, offset >> 3) >> ((frac^7) * 8)) & 0xff; break; } case 8: { - *value = pm_read48(offset >> 3); + *value = pm_read48(cpustate, offset >> 3); break; } } @@ -1019,18 +1017,18 @@ static CPU_READ( sharc ) case 1: { int frac = offset & 3; - *value = (dm_read32(offset >> 2) >> ((frac^3) * 8)) & 0xff; + *value = (dm_read32(cpustate, offset >> 2) >> ((frac^3) * 8)) & 0xff; break; } case 2: { int frac = (offset >> 1) & 1; - *value = (dm_read32(offset >> 2) >> ((frac^1) * 16)) & 0xffff; + *value = (dm_read32(cpustate, offset >> 2) >> ((frac^1) * 16)) & 0xffff; break; } case 4: { - *value = dm_read32(offset >> 2); + *value = dm_read32(cpustate, offset >> 2); break; } } @@ -1045,22 +1043,23 @@ static CPU_READ( sharc ) static CPU_READOP( sharc ) { + SHARC_REGS *cpustate = device->token; UINT64 mask = (size < 8) ? (((UINT64)1 << (8 * size)) - 1) : ~(UINT64)0; int shift = 8 * (offset & 7); offset >>= 3; if (offset >= 0x20000 && offset < 0x28000) { - UINT64 op = ((UINT64)(sharc.internal_ram_block0[((offset-0x20000) * 3) + 0]) << 32) | - ((UINT64)(sharc.internal_ram_block0[((offset-0x20000) * 3) + 1]) << 16) | - ((UINT64)(sharc.internal_ram_block0[((offset-0x20000) * 3) + 2]) << 0); + UINT64 op = ((UINT64)(cpustate->internal_ram_block0[((offset-0x20000) * 3) + 0]) << 32) | + ((UINT64)(cpustate->internal_ram_block0[((offset-0x20000) * 3) + 1]) << 16) | + ((UINT64)(cpustate->internal_ram_block0[((offset-0x20000) * 3) + 2]) << 0); *value = (op >> shift) & mask; } else if (offset >= 0x28000 && offset < 0x30000) { - UINT64 op = ((UINT64)(sharc.internal_ram_block1[((offset-0x28000) * 3) + 0]) << 32) | - ((UINT64)(sharc.internal_ram_block1[((offset-0x28000) * 3) + 1]) << 16) | - ((UINT64)(sharc.internal_ram_block1[((offset-0x28000) * 3) + 2]) << 0); + UINT64 op = ((UINT64)(cpustate->internal_ram_block1[((offset-0x28000) * 3) + 0]) << 32) | + ((UINT64)(cpustate->internal_ram_block1[((offset-0x28000) * 3) + 1]) << 16) | + ((UINT64)(cpustate->internal_ram_block1[((offset-0x28000) * 3) + 2]) << 0); *value = (op >> shift) & mask; } @@ -1074,10 +1073,12 @@ ADDRESS_MAP_END static CPU_GET_INFO( sharc ) { + SHARC_REGS *cpustate = (device != NULL) ? device->token : NULL; + switch(state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(sharc); break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(SHARC_REGS); break; case CPUINFO_INT_INPUT_LINES: info->i = 32; break; case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; @@ -1103,105 +1104,105 @@ static CPU_GET_INFO( sharc ) case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + SHARC_PC: info->i = sharc.pc; break; - case CPUINFO_INT_REGISTER + SHARC_PCSTK: info->i = sharc.pcstk; break; - case CPUINFO_INT_REGISTER + SHARC_PCSTKP: info->i = sharc.pcstkp; break; - case CPUINFO_INT_REGISTER + SHARC_LSTKP: info->i = sharc.lstkp; break; - case CPUINFO_INT_REGISTER + SHARC_FADDR: info->i = sharc.faddr; break; - case CPUINFO_INT_REGISTER + SHARC_DADDR: info->i = sharc.daddr; break; - case CPUINFO_INT_REGISTER + SHARC_MODE1: info->i = sharc.mode1; break; - case CPUINFO_INT_REGISTER + SHARC_MODE2: info->i = sharc.mode2; break; - case CPUINFO_INT_REGISTER + SHARC_ASTAT: info->i = sharc.astat; break; - case CPUINFO_INT_REGISTER + SHARC_IRPTL: info->i = sharc.irptl; break; - case CPUINFO_INT_REGISTER + SHARC_IMASK: info->i = sharc.imask; break; - case CPUINFO_INT_REGISTER + SHARC_USTAT1: info->i = sharc.ustat1; break; - case CPUINFO_INT_REGISTER + SHARC_USTAT2: info->i = sharc.ustat2; break; - case CPUINFO_INT_REGISTER + SHARC_STSTKP: info->i = sharc.status_stkp; break; + case CPUINFO_INT_REGISTER + SHARC_PC: info->i = cpustate->pc; break; + case CPUINFO_INT_REGISTER + SHARC_PCSTK: info->i = cpustate->pcstk; break; + case CPUINFO_INT_REGISTER + SHARC_PCSTKP: info->i = cpustate->pcstkp; break; + case CPUINFO_INT_REGISTER + SHARC_LSTKP: info->i = cpustate->lstkp; break; + case CPUINFO_INT_REGISTER + SHARC_FADDR: info->i = cpustate->faddr; break; + case CPUINFO_INT_REGISTER + SHARC_DADDR: info->i = cpustate->daddr; break; + case CPUINFO_INT_REGISTER + SHARC_MODE1: info->i = cpustate->mode1; break; + case CPUINFO_INT_REGISTER + SHARC_MODE2: info->i = cpustate->mode2; break; + case CPUINFO_INT_REGISTER + SHARC_ASTAT: info->i = cpustate->astat; break; + case CPUINFO_INT_REGISTER + SHARC_IRPTL: info->i = cpustate->irptl; break; + case CPUINFO_INT_REGISTER + SHARC_IMASK: info->i = cpustate->imask; break; + case CPUINFO_INT_REGISTER + SHARC_USTAT1: info->i = cpustate->ustat1; break; + case CPUINFO_INT_REGISTER + SHARC_USTAT2: info->i = cpustate->ustat2; break; + case CPUINFO_INT_REGISTER + SHARC_STSTKP: info->i = cpustate->status_stkp; break; - case CPUINFO_INT_REGISTER + SHARC_R0: info->i = sharc.r[0].r; break; - case CPUINFO_INT_REGISTER + SHARC_R1: info->i = sharc.r[1].r; break; - case CPUINFO_INT_REGISTER + SHARC_R2: info->i = sharc.r[2].r; break; - case CPUINFO_INT_REGISTER + SHARC_R3: info->i = sharc.r[3].r; break; - case CPUINFO_INT_REGISTER + SHARC_R4: info->i = sharc.r[4].r; break; - case CPUINFO_INT_REGISTER + SHARC_R5: info->i = sharc.r[5].r; break; - case CPUINFO_INT_REGISTER + SHARC_R6: info->i = sharc.r[6].r; break; - case CPUINFO_INT_REGISTER + SHARC_R7: info->i = sharc.r[7].r; break; - case CPUINFO_INT_REGISTER + SHARC_R8: info->i = sharc.r[8].r; break; - case CPUINFO_INT_REGISTER + SHARC_R9: info->i = sharc.r[9].r; break; - case CPUINFO_INT_REGISTER + SHARC_R10: info->i = sharc.r[10].r; break; - case CPUINFO_INT_REGISTER + SHARC_R11: info->i = sharc.r[11].r; break; - case CPUINFO_INT_REGISTER + SHARC_R12: info->i = sharc.r[12].r; break; - case CPUINFO_INT_REGISTER + SHARC_R13: info->i = sharc.r[13].r; break; - case CPUINFO_INT_REGISTER + SHARC_R14: info->i = sharc.r[14].r; break; - case CPUINFO_INT_REGISTER + SHARC_R15: info->i = sharc.r[15].r; break; + case CPUINFO_INT_REGISTER + SHARC_R0: info->i = cpustate->r[0].r; break; + case CPUINFO_INT_REGISTER + SHARC_R1: info->i = cpustate->r[1].r; break; + case CPUINFO_INT_REGISTER + SHARC_R2: info->i = cpustate->r[2].r; break; + case CPUINFO_INT_REGISTER + SHARC_R3: info->i = cpustate->r[3].r; break; + case CPUINFO_INT_REGISTER + SHARC_R4: info->i = cpustate->r[4].r; break; + case CPUINFO_INT_REGISTER + SHARC_R5: info->i = cpustate->r[5].r; break; + case CPUINFO_INT_REGISTER + SHARC_R6: info->i = cpustate->r[6].r; break; + case CPUINFO_INT_REGISTER + SHARC_R7: info->i = cpustate->r[7].r; break; + case CPUINFO_INT_REGISTER + SHARC_R8: info->i = cpustate->r[8].r; break; + case CPUINFO_INT_REGISTER + SHARC_R9: info->i = cpustate->r[9].r; break; + case CPUINFO_INT_REGISTER + SHARC_R10: info->i = cpustate->r[10].r; break; + case CPUINFO_INT_REGISTER + SHARC_R11: info->i = cpustate->r[11].r; break; + case CPUINFO_INT_REGISTER + SHARC_R12: info->i = cpustate->r[12].r; break; + case CPUINFO_INT_REGISTER + SHARC_R13: info->i = cpustate->r[13].r; break; + case CPUINFO_INT_REGISTER + SHARC_R14: info->i = cpustate->r[14].r; break; + case CPUINFO_INT_REGISTER + SHARC_R15: info->i = cpustate->r[15].r; break; - case CPUINFO_INT_REGISTER + SHARC_I0: info->i = sharc.dag1.i[0]; break; - case CPUINFO_INT_REGISTER + SHARC_I1: info->i = sharc.dag1.i[1]; break; - case CPUINFO_INT_REGISTER + SHARC_I2: info->i = sharc.dag1.i[2]; break; - case CPUINFO_INT_REGISTER + SHARC_I3: info->i = sharc.dag1.i[3]; break; - case CPUINFO_INT_REGISTER + SHARC_I4: info->i = sharc.dag1.i[4]; break; - case CPUINFO_INT_REGISTER + SHARC_I5: info->i = sharc.dag1.i[5]; break; - case CPUINFO_INT_REGISTER + SHARC_I6: info->i = sharc.dag1.i[6]; break; - case CPUINFO_INT_REGISTER + SHARC_I7: info->i = sharc.dag1.i[7]; break; - case CPUINFO_INT_REGISTER + SHARC_I8: info->i = sharc.dag2.i[0]; break; - case CPUINFO_INT_REGISTER + SHARC_I9: info->i = sharc.dag2.i[1]; break; - case CPUINFO_INT_REGISTER + SHARC_I10: info->i = sharc.dag2.i[2]; break; - case CPUINFO_INT_REGISTER + SHARC_I11: info->i = sharc.dag2.i[3]; break; - case CPUINFO_INT_REGISTER + SHARC_I12: info->i = sharc.dag2.i[4]; break; - case CPUINFO_INT_REGISTER + SHARC_I13: info->i = sharc.dag2.i[5]; break; - case CPUINFO_INT_REGISTER + SHARC_I14: info->i = sharc.dag2.i[6]; break; - case CPUINFO_INT_REGISTER + SHARC_I15: info->i = sharc.dag2.i[7]; break; + case CPUINFO_INT_REGISTER + SHARC_I0: info->i = cpustate->dag1.i[0]; break; + case CPUINFO_INT_REGISTER + SHARC_I1: info->i = cpustate->dag1.i[1]; break; + case CPUINFO_INT_REGISTER + SHARC_I2: info->i = cpustate->dag1.i[2]; break; + case CPUINFO_INT_REGISTER + SHARC_I3: info->i = cpustate->dag1.i[3]; break; + case CPUINFO_INT_REGISTER + SHARC_I4: info->i = cpustate->dag1.i[4]; break; + case CPUINFO_INT_REGISTER + SHARC_I5: info->i = cpustate->dag1.i[5]; break; + case CPUINFO_INT_REGISTER + SHARC_I6: info->i = cpustate->dag1.i[6]; break; + case CPUINFO_INT_REGISTER + SHARC_I7: info->i = cpustate->dag1.i[7]; break; + case CPUINFO_INT_REGISTER + SHARC_I8: info->i = cpustate->dag2.i[0]; break; + case CPUINFO_INT_REGISTER + SHARC_I9: info->i = cpustate->dag2.i[1]; break; + case CPUINFO_INT_REGISTER + SHARC_I10: info->i = cpustate->dag2.i[2]; break; + case CPUINFO_INT_REGISTER + SHARC_I11: info->i = cpustate->dag2.i[3]; break; + case CPUINFO_INT_REGISTER + SHARC_I12: info->i = cpustate->dag2.i[4]; break; + case CPUINFO_INT_REGISTER + SHARC_I13: info->i = cpustate->dag2.i[5]; break; + case CPUINFO_INT_REGISTER + SHARC_I14: info->i = cpustate->dag2.i[6]; break; + case CPUINFO_INT_REGISTER + SHARC_I15: info->i = cpustate->dag2.i[7]; break; - case CPUINFO_INT_REGISTER + SHARC_M0: info->i = sharc.dag1.m[0]; break; - case CPUINFO_INT_REGISTER + SHARC_M1: info->i = sharc.dag1.m[1]; break; - case CPUINFO_INT_REGISTER + SHARC_M2: info->i = sharc.dag1.m[2]; break; - case CPUINFO_INT_REGISTER + SHARC_M3: info->i = sharc.dag1.m[3]; break; - case CPUINFO_INT_REGISTER + SHARC_M4: info->i = sharc.dag1.m[4]; break; - case CPUINFO_INT_REGISTER + SHARC_M5: info->i = sharc.dag1.m[5]; break; - case CPUINFO_INT_REGISTER + SHARC_M6: info->i = sharc.dag1.m[6]; break; - case CPUINFO_INT_REGISTER + SHARC_M7: info->i = sharc.dag1.m[7]; break; - case CPUINFO_INT_REGISTER + SHARC_M8: info->i = sharc.dag2.m[0]; break; - case CPUINFO_INT_REGISTER + SHARC_M9: info->i = sharc.dag2.m[1]; break; - case CPUINFO_INT_REGISTER + SHARC_M10: info->i = sharc.dag2.m[2]; break; - case CPUINFO_INT_REGISTER + SHARC_M11: info->i = sharc.dag2.m[3]; break; - case CPUINFO_INT_REGISTER + SHARC_M12: info->i = sharc.dag2.m[4]; break; - case CPUINFO_INT_REGISTER + SHARC_M13: info->i = sharc.dag2.m[5]; break; - case CPUINFO_INT_REGISTER + SHARC_M14: info->i = sharc.dag2.m[6]; break; - case CPUINFO_INT_REGISTER + SHARC_M15: info->i = sharc.dag2.m[7]; break; + case CPUINFO_INT_REGISTER + SHARC_M0: info->i = cpustate->dag1.m[0]; break; + case CPUINFO_INT_REGISTER + SHARC_M1: info->i = cpustate->dag1.m[1]; break; + case CPUINFO_INT_REGISTER + SHARC_M2: info->i = cpustate->dag1.m[2]; break; + case CPUINFO_INT_REGISTER + SHARC_M3: info->i = cpustate->dag1.m[3]; break; + case CPUINFO_INT_REGISTER + SHARC_M4: info->i = cpustate->dag1.m[4]; break; + case CPUINFO_INT_REGISTER + SHARC_M5: info->i = cpustate->dag1.m[5]; break; + case CPUINFO_INT_REGISTER + SHARC_M6: info->i = cpustate->dag1.m[6]; break; + case CPUINFO_INT_REGISTER + SHARC_M7: info->i = cpustate->dag1.m[7]; break; + case CPUINFO_INT_REGISTER + SHARC_M8: info->i = cpustate->dag2.m[0]; break; + case CPUINFO_INT_REGISTER + SHARC_M9: info->i = cpustate->dag2.m[1]; break; + case CPUINFO_INT_REGISTER + SHARC_M10: info->i = cpustate->dag2.m[2]; break; + case CPUINFO_INT_REGISTER + SHARC_M11: info->i = cpustate->dag2.m[3]; break; + case CPUINFO_INT_REGISTER + SHARC_M12: info->i = cpustate->dag2.m[4]; break; + case CPUINFO_INT_REGISTER + SHARC_M13: info->i = cpustate->dag2.m[5]; break; + case CPUINFO_INT_REGISTER + SHARC_M14: info->i = cpustate->dag2.m[6]; break; + case CPUINFO_INT_REGISTER + SHARC_M15: info->i = cpustate->dag2.m[7]; break; - case CPUINFO_INT_REGISTER + SHARC_L0: info->i = sharc.dag1.l[0]; break; - case CPUINFO_INT_REGISTER + SHARC_L1: info->i = sharc.dag1.l[1]; break; - case CPUINFO_INT_REGISTER + SHARC_L2: info->i = sharc.dag1.l[2]; break; - case CPUINFO_INT_REGISTER + SHARC_L3: info->i = sharc.dag1.l[3]; break; - case CPUINFO_INT_REGISTER + SHARC_L4: info->i = sharc.dag1.l[4]; break; - case CPUINFO_INT_REGISTER + SHARC_L5: info->i = sharc.dag1.l[5]; break; - case CPUINFO_INT_REGISTER + SHARC_L6: info->i = sharc.dag1.l[6]; break; - case CPUINFO_INT_REGISTER + SHARC_L7: info->i = sharc.dag1.l[7]; break; - case CPUINFO_INT_REGISTER + SHARC_L8: info->i = sharc.dag2.l[0]; break; - case CPUINFO_INT_REGISTER + SHARC_L9: info->i = sharc.dag2.l[1]; break; - case CPUINFO_INT_REGISTER + SHARC_L10: info->i = sharc.dag2.l[2]; break; - case CPUINFO_INT_REGISTER + SHARC_L11: info->i = sharc.dag2.l[3]; break; - case CPUINFO_INT_REGISTER + SHARC_L12: info->i = sharc.dag2.l[4]; break; - case CPUINFO_INT_REGISTER + SHARC_L13: info->i = sharc.dag2.l[5]; break; - case CPUINFO_INT_REGISTER + SHARC_L14: info->i = sharc.dag2.l[6]; break; - case CPUINFO_INT_REGISTER + SHARC_L15: info->i = sharc.dag2.l[7]; break; + case CPUINFO_INT_REGISTER + SHARC_L0: info->i = cpustate->dag1.l[0]; break; + case CPUINFO_INT_REGISTER + SHARC_L1: info->i = cpustate->dag1.l[1]; break; + case CPUINFO_INT_REGISTER + SHARC_L2: info->i = cpustate->dag1.l[2]; break; + case CPUINFO_INT_REGISTER + SHARC_L3: info->i = cpustate->dag1.l[3]; break; + case CPUINFO_INT_REGISTER + SHARC_L4: info->i = cpustate->dag1.l[4]; break; + case CPUINFO_INT_REGISTER + SHARC_L5: info->i = cpustate->dag1.l[5]; break; + case CPUINFO_INT_REGISTER + SHARC_L6: info->i = cpustate->dag1.l[6]; break; + case CPUINFO_INT_REGISTER + SHARC_L7: info->i = cpustate->dag1.l[7]; break; + case CPUINFO_INT_REGISTER + SHARC_L8: info->i = cpustate->dag2.l[0]; break; + case CPUINFO_INT_REGISTER + SHARC_L9: info->i = cpustate->dag2.l[1]; break; + case CPUINFO_INT_REGISTER + SHARC_L10: info->i = cpustate->dag2.l[2]; break; + case CPUINFO_INT_REGISTER + SHARC_L11: info->i = cpustate->dag2.l[3]; break; + case CPUINFO_INT_REGISTER + SHARC_L12: info->i = cpustate->dag2.l[4]; break; + case CPUINFO_INT_REGISTER + SHARC_L13: info->i = cpustate->dag2.l[5]; break; + case CPUINFO_INT_REGISTER + SHARC_L14: info->i = cpustate->dag2.l[6]; break; + case CPUINFO_INT_REGISTER + SHARC_L15: info->i = cpustate->dag2.l[7]; break; - case CPUINFO_INT_REGISTER + SHARC_B0: info->i = sharc.dag1.b[0]; break; - case CPUINFO_INT_REGISTER + SHARC_B1: info->i = sharc.dag1.b[1]; break; - case CPUINFO_INT_REGISTER + SHARC_B2: info->i = sharc.dag1.b[2]; break; - case CPUINFO_INT_REGISTER + SHARC_B3: info->i = sharc.dag1.b[3]; break; - case CPUINFO_INT_REGISTER + SHARC_B4: info->i = sharc.dag1.b[4]; break; - case CPUINFO_INT_REGISTER + SHARC_B5: info->i = sharc.dag1.b[5]; break; - case CPUINFO_INT_REGISTER + SHARC_B6: info->i = sharc.dag1.b[6]; break; - case CPUINFO_INT_REGISTER + SHARC_B7: info->i = sharc.dag1.b[7]; break; - case CPUINFO_INT_REGISTER + SHARC_B8: info->i = sharc.dag2.b[0]; break; - case CPUINFO_INT_REGISTER + SHARC_B9: info->i = sharc.dag2.b[1]; break; - case CPUINFO_INT_REGISTER + SHARC_B10: info->i = sharc.dag2.b[2]; break; - case CPUINFO_INT_REGISTER + SHARC_B11: info->i = sharc.dag2.b[3]; break; - case CPUINFO_INT_REGISTER + SHARC_B12: info->i = sharc.dag2.b[4]; break; - case CPUINFO_INT_REGISTER + SHARC_B13: info->i = sharc.dag2.b[5]; break; - case CPUINFO_INT_REGISTER + SHARC_B14: info->i = sharc.dag2.b[6]; break; - case CPUINFO_INT_REGISTER + SHARC_B15: info->i = sharc.dag2.b[7]; break; + case CPUINFO_INT_REGISTER + SHARC_B0: info->i = cpustate->dag1.b[0]; break; + case CPUINFO_INT_REGISTER + SHARC_B1: info->i = cpustate->dag1.b[1]; break; + case CPUINFO_INT_REGISTER + SHARC_B2: info->i = cpustate->dag1.b[2]; break; + case CPUINFO_INT_REGISTER + SHARC_B3: info->i = cpustate->dag1.b[3]; break; + case CPUINFO_INT_REGISTER + SHARC_B4: info->i = cpustate->dag1.b[4]; break; + case CPUINFO_INT_REGISTER + SHARC_B5: info->i = cpustate->dag1.b[5]; break; + case CPUINFO_INT_REGISTER + SHARC_B6: info->i = cpustate->dag1.b[6]; break; + case CPUINFO_INT_REGISTER + SHARC_B7: info->i = cpustate->dag1.b[7]; break; + case CPUINFO_INT_REGISTER + SHARC_B8: info->i = cpustate->dag2.b[0]; break; + case CPUINFO_INT_REGISTER + SHARC_B9: info->i = cpustate->dag2.b[1]; break; + case CPUINFO_INT_REGISTER + SHARC_B10: info->i = cpustate->dag2.b[2]; break; + case CPUINFO_INT_REGISTER + SHARC_B11: info->i = cpustate->dag2.b[3]; break; + case CPUINFO_INT_REGISTER + SHARC_B12: info->i = cpustate->dag2.b[4]; break; + case CPUINFO_INT_REGISTER + SHARC_B13: info->i = cpustate->dag2.b[5]; break; + case CPUINFO_INT_REGISTER + SHARC_B14: info->i = cpustate->dag2.b[6]; break; + case CPUINFO_INT_REGISTER + SHARC_B15: info->i = cpustate->dag2.b[7]; break; /* --- the following bits of info are returned as pointers to data or functions --- */ case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(sharc); break; @@ -1212,7 +1213,7 @@ static CPU_GET_INFO( sharc ) case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(sharc);break; case CPUINFO_PTR_BURN: info->burn = NULL; break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(sharc); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &sharc_icount; break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; case CPUINFO_PTR_READ: info->read = CPU_READ_NAME(sharc); break; case CPUINFO_PTR_READOP: info->readop = CPU_READOP_NAME(sharc); break; case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map64 = ADDRESS_MAP_NAME(internal_pgm); break; @@ -1225,105 +1226,105 @@ static CPU_GET_INFO( sharc ) case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break; - case CPUINFO_STR_REGISTER + SHARC_PC: sprintf(info->s, "PC: %08X", sharc.pc); break; - case CPUINFO_STR_REGISTER + SHARC_PCSTK: sprintf(info->s, "PCSTK: %08X", sharc.pcstk); break; - case CPUINFO_STR_REGISTER + SHARC_PCSTKP: sprintf(info->s, "PCSTKP: %08X", sharc.pcstkp); break; - case CPUINFO_STR_REGISTER + SHARC_LSTKP: sprintf(info->s, "LSTKP: %08X", sharc.lstkp); break; - case CPUINFO_STR_REGISTER + SHARC_FADDR: sprintf(info->s, "FADDR: %08X", sharc.faddr); break; - case CPUINFO_STR_REGISTER + SHARC_DADDR: sprintf(info->s, "DADDR: %08X", sharc.daddr); break; - case CPUINFO_STR_REGISTER + SHARC_MODE1: sprintf(info->s, "MODE1: %08X", sharc.mode1); break; - case CPUINFO_STR_REGISTER + SHARC_MODE2: sprintf(info->s, "MODE2: %08X", sharc.mode2); break; - case CPUINFO_STR_REGISTER + SHARC_ASTAT: sprintf(info->s, "ASTAT: %08X", sharc.astat); break; - case CPUINFO_STR_REGISTER + SHARC_IRPTL: sprintf(info->s, "IRPTL: %08X", sharc.irptl); break; - case CPUINFO_STR_REGISTER + SHARC_IMASK: sprintf(info->s, "IMASK: %08X", sharc.imask); break; - case CPUINFO_STR_REGISTER + SHARC_USTAT1: sprintf(info->s, "USTAT1: %08X", sharc.ustat1); break; - case CPUINFO_STR_REGISTER + SHARC_USTAT2: sprintf(info->s, "USTAT2: %08X", sharc.ustat2); break; - case CPUINFO_STR_REGISTER + SHARC_STSTKP: sprintf(info->s, "STSTKP: %08X", sharc.status_stkp); break; + case CPUINFO_STR_REGISTER + SHARC_PC: sprintf(info->s, "PC: %08X", cpustate->pc); break; + case CPUINFO_STR_REGISTER + SHARC_PCSTK: sprintf(info->s, "PCSTK: %08X", cpustate->pcstk); break; + case CPUINFO_STR_REGISTER + SHARC_PCSTKP: sprintf(info->s, "PCSTKP: %08X", cpustate->pcstkp); break; + case CPUINFO_STR_REGISTER + SHARC_LSTKP: sprintf(info->s, "LSTKP: %08X", cpustate->lstkp); break; + case CPUINFO_STR_REGISTER + SHARC_FADDR: sprintf(info->s, "FADDR: %08X", cpustate->faddr); break; + case CPUINFO_STR_REGISTER + SHARC_DADDR: sprintf(info->s, "DADDR: %08X", cpustate->daddr); break; + case CPUINFO_STR_REGISTER + SHARC_MODE1: sprintf(info->s, "MODE1: %08X", cpustate->mode1); break; + case CPUINFO_STR_REGISTER + SHARC_MODE2: sprintf(info->s, "MODE2: %08X", cpustate->mode2); break; + case CPUINFO_STR_REGISTER + SHARC_ASTAT: sprintf(info->s, "ASTAT: %08X", cpustate->astat); break; + case CPUINFO_STR_REGISTER + SHARC_IRPTL: sprintf(info->s, "IRPTL: %08X", cpustate->irptl); break; + case CPUINFO_STR_REGISTER + SHARC_IMASK: sprintf(info->s, "IMASK: %08X", cpustate->imask); break; + case CPUINFO_STR_REGISTER + SHARC_USTAT1: sprintf(info->s, "USTAT1: %08X", cpustate->ustat1); break; + case CPUINFO_STR_REGISTER + SHARC_USTAT2: sprintf(info->s, "USTAT2: %08X", cpustate->ustat2); break; + case CPUINFO_STR_REGISTER + SHARC_STSTKP: sprintf(info->s, "STSTKP: %08X", cpustate->status_stkp); break; - case CPUINFO_STR_REGISTER + SHARC_R0: sprintf(info->s, "R0: %08X", (UINT32)sharc.r[0].r); break; - case CPUINFO_STR_REGISTER + SHARC_R1: sprintf(info->s, "R1: %08X", (UINT32)sharc.r[1].r); break; - case CPUINFO_STR_REGISTER + SHARC_R2: sprintf(info->s, "R2: %08X", (UINT32)sharc.r[2].r); break; - case CPUINFO_STR_REGISTER + SHARC_R3: sprintf(info->s, "R3: %08X", (UINT32)sharc.r[3].r); break; - case CPUINFO_STR_REGISTER + SHARC_R4: sprintf(info->s, "R4: %08X", (UINT32)sharc.r[4].r); break; - case CPUINFO_STR_REGISTER + SHARC_R5: sprintf(info->s, "R5: %08X", (UINT32)sharc.r[5].r); break; - case CPUINFO_STR_REGISTER + SHARC_R6: sprintf(info->s, "R6: %08X", (UINT32)sharc.r[6].r); break; - case CPUINFO_STR_REGISTER + SHARC_R7: sprintf(info->s, "R7: %08X", (UINT32)sharc.r[7].r); break; - case CPUINFO_STR_REGISTER + SHARC_R8: sprintf(info->s, "R8: %08X", (UINT32)sharc.r[8].r); break; - case CPUINFO_STR_REGISTER + SHARC_R9: sprintf(info->s, "R9: %08X", (UINT32)sharc.r[9].r); break; - case CPUINFO_STR_REGISTER + SHARC_R10: sprintf(info->s, "R10: %08X", (UINT32)sharc.r[10].r); break; - case CPUINFO_STR_REGISTER + SHARC_R11: sprintf(info->s, "R11: %08X", (UINT32)sharc.r[11].r); break; - case CPUINFO_STR_REGISTER + SHARC_R12: sprintf(info->s, "R12: %08X", (UINT32)sharc.r[12].r); break; - case CPUINFO_STR_REGISTER + SHARC_R13: sprintf(info->s, "R13: %08X", (UINT32)sharc.r[13].r); break; - case CPUINFO_STR_REGISTER + SHARC_R14: sprintf(info->s, "R14: %08X", (UINT32)sharc.r[14].r); break; - case CPUINFO_STR_REGISTER + SHARC_R15: sprintf(info->s, "R15: %08X", (UINT32)sharc.r[15].r); break; + case CPUINFO_STR_REGISTER + SHARC_R0: sprintf(info->s, "R0: %08X", (UINT32)cpustate->r[0].r); break; + case CPUINFO_STR_REGISTER + SHARC_R1: sprintf(info->s, "R1: %08X", (UINT32)cpustate->r[1].r); break; + case CPUINFO_STR_REGISTER + SHARC_R2: sprintf(info->s, "R2: %08X", (UINT32)cpustate->r[2].r); break; + case CPUINFO_STR_REGISTER + SHARC_R3: sprintf(info->s, "R3: %08X", (UINT32)cpustate->r[3].r); break; + case CPUINFO_STR_REGISTER + SHARC_R4: sprintf(info->s, "R4: %08X", (UINT32)cpustate->r[4].r); break; + case CPUINFO_STR_REGISTER + SHARC_R5: sprintf(info->s, "R5: %08X", (UINT32)cpustate->r[5].r); break; + case CPUINFO_STR_REGISTER + SHARC_R6: sprintf(info->s, "R6: %08X", (UINT32)cpustate->r[6].r); break; + case CPUINFO_STR_REGISTER + SHARC_R7: sprintf(info->s, "R7: %08X", (UINT32)cpustate->r[7].r); break; + case CPUINFO_STR_REGISTER + SHARC_R8: sprintf(info->s, "R8: %08X", (UINT32)cpustate->r[8].r); break; + case CPUINFO_STR_REGISTER + SHARC_R9: sprintf(info->s, "R9: %08X", (UINT32)cpustate->r[9].r); break; + case CPUINFO_STR_REGISTER + SHARC_R10: sprintf(info->s, "R10: %08X", (UINT32)cpustate->r[10].r); break; + case CPUINFO_STR_REGISTER + SHARC_R11: sprintf(info->s, "R11: %08X", (UINT32)cpustate->r[11].r); break; + case CPUINFO_STR_REGISTER + SHARC_R12: sprintf(info->s, "R12: %08X", (UINT32)cpustate->r[12].r); break; + case CPUINFO_STR_REGISTER + SHARC_R13: sprintf(info->s, "R13: %08X", (UINT32)cpustate->r[13].r); break; + case CPUINFO_STR_REGISTER + SHARC_R14: sprintf(info->s, "R14: %08X", (UINT32)cpustate->r[14].r); break; + case CPUINFO_STR_REGISTER + SHARC_R15: sprintf(info->s, "R15: %08X", (UINT32)cpustate->r[15].r); break; - case CPUINFO_STR_REGISTER + SHARC_I0: sprintf(info->s, "I0: %08X", (UINT32)sharc.dag1.i[0]); break; - case CPUINFO_STR_REGISTER + SHARC_I1: sprintf(info->s, "I1: %08X", (UINT32)sharc.dag1.i[1]); break; - case CPUINFO_STR_REGISTER + SHARC_I2: sprintf(info->s, "I2: %08X", (UINT32)sharc.dag1.i[2]); break; - case CPUINFO_STR_REGISTER + SHARC_I3: sprintf(info->s, "I3: %08X", (UINT32)sharc.dag1.i[3]); break; - case CPUINFO_STR_REGISTER + SHARC_I4: sprintf(info->s, "I4: %08X", (UINT32)sharc.dag1.i[4]); break; - case CPUINFO_STR_REGISTER + SHARC_I5: sprintf(info->s, "I5: %08X", (UINT32)sharc.dag1.i[5]); break; - case CPUINFO_STR_REGISTER + SHARC_I6: sprintf(info->s, "I6: %08X", (UINT32)sharc.dag1.i[6]); break; - case CPUINFO_STR_REGISTER + SHARC_I7: sprintf(info->s, "I7: %08X", (UINT32)sharc.dag1.i[7]); break; - case CPUINFO_STR_REGISTER + SHARC_I8: sprintf(info->s, "I8: %08X", (UINT32)sharc.dag2.i[0]); break; - case CPUINFO_STR_REGISTER + SHARC_I9: sprintf(info->s, "I9: %08X", (UINT32)sharc.dag2.i[1]); break; - case CPUINFO_STR_REGISTER + SHARC_I10: sprintf(info->s, "I10: %08X", (UINT32)sharc.dag2.i[2]); break; - case CPUINFO_STR_REGISTER + SHARC_I11: sprintf(info->s, "I11: %08X", (UINT32)sharc.dag2.i[3]); break; - case CPUINFO_STR_REGISTER + SHARC_I12: sprintf(info->s, "I12: %08X", (UINT32)sharc.dag2.i[4]); break; - case CPUINFO_STR_REGISTER + SHARC_I13: sprintf(info->s, "I13: %08X", (UINT32)sharc.dag2.i[5]); break; - case CPUINFO_STR_REGISTER + SHARC_I14: sprintf(info->s, "I14: %08X", (UINT32)sharc.dag2.i[6]); break; - case CPUINFO_STR_REGISTER + SHARC_I15: sprintf(info->s, "I15: %08X", (UINT32)sharc.dag2.i[7]); break; + case CPUINFO_STR_REGISTER + SHARC_I0: sprintf(info->s, "I0: %08X", (UINT32)cpustate->dag1.i[0]); break; + case CPUINFO_STR_REGISTER + SHARC_I1: sprintf(info->s, "I1: %08X", (UINT32)cpustate->dag1.i[1]); break; + case CPUINFO_STR_REGISTER + SHARC_I2: sprintf(info->s, "I2: %08X", (UINT32)cpustate->dag1.i[2]); break; + case CPUINFO_STR_REGISTER + SHARC_I3: sprintf(info->s, "I3: %08X", (UINT32)cpustate->dag1.i[3]); break; + case CPUINFO_STR_REGISTER + SHARC_I4: sprintf(info->s, "I4: %08X", (UINT32)cpustate->dag1.i[4]); break; + case CPUINFO_STR_REGISTER + SHARC_I5: sprintf(info->s, "I5: %08X", (UINT32)cpustate->dag1.i[5]); break; + case CPUINFO_STR_REGISTER + SHARC_I6: sprintf(info->s, "I6: %08X", (UINT32)cpustate->dag1.i[6]); break; + case CPUINFO_STR_REGISTER + SHARC_I7: sprintf(info->s, "I7: %08X", (UINT32)cpustate->dag1.i[7]); break; + case CPUINFO_STR_REGISTER + SHARC_I8: sprintf(info->s, "I8: %08X", (UINT32)cpustate->dag2.i[0]); break; + case CPUINFO_STR_REGISTER + SHARC_I9: sprintf(info->s, "I9: %08X", (UINT32)cpustate->dag2.i[1]); break; + case CPUINFO_STR_REGISTER + SHARC_I10: sprintf(info->s, "I10: %08X", (UINT32)cpustate->dag2.i[2]); break; + case CPUINFO_STR_REGISTER + SHARC_I11: sprintf(info->s, "I11: %08X", (UINT32)cpustate->dag2.i[3]); break; + case CPUINFO_STR_REGISTER + SHARC_I12: sprintf(info->s, "I12: %08X", (UINT32)cpustate->dag2.i[4]); break; + case CPUINFO_STR_REGISTER + SHARC_I13: sprintf(info->s, "I13: %08X", (UINT32)cpustate->dag2.i[5]); break; + case CPUINFO_STR_REGISTER + SHARC_I14: sprintf(info->s, "I14: %08X", (UINT32)cpustate->dag2.i[6]); break; + case CPUINFO_STR_REGISTER + SHARC_I15: sprintf(info->s, "I15: %08X", (UINT32)cpustate->dag2.i[7]); break; - case CPUINFO_STR_REGISTER + SHARC_M0: sprintf(info->s, "M0: %08X", (UINT32)sharc.dag1.m[0]); break; - case CPUINFO_STR_REGISTER + SHARC_M1: sprintf(info->s, "M1: %08X", (UINT32)sharc.dag1.m[1]); break; - case CPUINFO_STR_REGISTER + SHARC_M2: sprintf(info->s, "M2: %08X", (UINT32)sharc.dag1.m[2]); break; - case CPUINFO_STR_REGISTER + SHARC_M3: sprintf(info->s, "M3: %08X", (UINT32)sharc.dag1.m[3]); break; - case CPUINFO_STR_REGISTER + SHARC_M4: sprintf(info->s, "M4: %08X", (UINT32)sharc.dag1.m[4]); break; - case CPUINFO_STR_REGISTER + SHARC_M5: sprintf(info->s, "M5: %08X", (UINT32)sharc.dag1.m[5]); break; - case CPUINFO_STR_REGISTER + SHARC_M6: sprintf(info->s, "M6: %08X", (UINT32)sharc.dag1.m[6]); break; - case CPUINFO_STR_REGISTER + SHARC_M7: sprintf(info->s, "M7: %08X", (UINT32)sharc.dag1.m[7]); break; - case CPUINFO_STR_REGISTER + SHARC_M8: sprintf(info->s, "M8: %08X", (UINT32)sharc.dag2.m[0]); break; - case CPUINFO_STR_REGISTER + SHARC_M9: sprintf(info->s, "M9: %08X", (UINT32)sharc.dag2.m[1]); break; - case CPUINFO_STR_REGISTER + SHARC_M10: sprintf(info->s, "M10: %08X", (UINT32)sharc.dag2.m[2]); break; - case CPUINFO_STR_REGISTER + SHARC_M11: sprintf(info->s, "M11: %08X", (UINT32)sharc.dag2.m[3]); break; - case CPUINFO_STR_REGISTER + SHARC_M12: sprintf(info->s, "M12: %08X", (UINT32)sharc.dag2.m[4]); break; - case CPUINFO_STR_REGISTER + SHARC_M13: sprintf(info->s, "M13: %08X", (UINT32)sharc.dag2.m[5]); break; - case CPUINFO_STR_REGISTER + SHARC_M14: sprintf(info->s, "M14: %08X", (UINT32)sharc.dag2.m[6]); break; - case CPUINFO_STR_REGISTER + SHARC_M15: sprintf(info->s, "M15: %08X", (UINT32)sharc.dag2.m[7]); break; + case CPUINFO_STR_REGISTER + SHARC_M0: sprintf(info->s, "M0: %08X", (UINT32)cpustate->dag1.m[0]); break; + case CPUINFO_STR_REGISTER + SHARC_M1: sprintf(info->s, "M1: %08X", (UINT32)cpustate->dag1.m[1]); break; + case CPUINFO_STR_REGISTER + SHARC_M2: sprintf(info->s, "M2: %08X", (UINT32)cpustate->dag1.m[2]); break; + case CPUINFO_STR_REGISTER + SHARC_M3: sprintf(info->s, "M3: %08X", (UINT32)cpustate->dag1.m[3]); break; + case CPUINFO_STR_REGISTER + SHARC_M4: sprintf(info->s, "M4: %08X", (UINT32)cpustate->dag1.m[4]); break; + case CPUINFO_STR_REGISTER + SHARC_M5: sprintf(info->s, "M5: %08X", (UINT32)cpustate->dag1.m[5]); break; + case CPUINFO_STR_REGISTER + SHARC_M6: sprintf(info->s, "M6: %08X", (UINT32)cpustate->dag1.m[6]); break; + case CPUINFO_STR_REGISTER + SHARC_M7: sprintf(info->s, "M7: %08X", (UINT32)cpustate->dag1.m[7]); break; + case CPUINFO_STR_REGISTER + SHARC_M8: sprintf(info->s, "M8: %08X", (UINT32)cpustate->dag2.m[0]); break; + case CPUINFO_STR_REGISTER + SHARC_M9: sprintf(info->s, "M9: %08X", (UINT32)cpustate->dag2.m[1]); break; + case CPUINFO_STR_REGISTER + SHARC_M10: sprintf(info->s, "M10: %08X", (UINT32)cpustate->dag2.m[2]); break; + case CPUINFO_STR_REGISTER + SHARC_M11: sprintf(info->s, "M11: %08X", (UINT32)cpustate->dag2.m[3]); break; + case CPUINFO_STR_REGISTER + SHARC_M12: sprintf(info->s, "M12: %08X", (UINT32)cpustate->dag2.m[4]); break; + case CPUINFO_STR_REGISTER + SHARC_M13: sprintf(info->s, "M13: %08X", (UINT32)cpustate->dag2.m[5]); break; + case CPUINFO_STR_REGISTER + SHARC_M14: sprintf(info->s, "M14: %08X", (UINT32)cpustate->dag2.m[6]); break; + case CPUINFO_STR_REGISTER + SHARC_M15: sprintf(info->s, "M15: %08X", (UINT32)cpustate->dag2.m[7]); break; - case CPUINFO_STR_REGISTER + SHARC_L0: sprintf(info->s, "L0: %08X", (UINT32)sharc.dag1.l[0]); break; - case CPUINFO_STR_REGISTER + SHARC_L1: sprintf(info->s, "L1: %08X", (UINT32)sharc.dag1.l[1]); break; - case CPUINFO_STR_REGISTER + SHARC_L2: sprintf(info->s, "L2: %08X", (UINT32)sharc.dag1.l[2]); break; - case CPUINFO_STR_REGISTER + SHARC_L3: sprintf(info->s, "L3: %08X", (UINT32)sharc.dag1.l[3]); break; - case CPUINFO_STR_REGISTER + SHARC_L4: sprintf(info->s, "L4: %08X", (UINT32)sharc.dag1.l[4]); break; - case CPUINFO_STR_REGISTER + SHARC_L5: sprintf(info->s, "L5: %08X", (UINT32)sharc.dag1.l[5]); break; - case CPUINFO_STR_REGISTER + SHARC_L6: sprintf(info->s, "L6: %08X", (UINT32)sharc.dag1.l[6]); break; - case CPUINFO_STR_REGISTER + SHARC_L7: sprintf(info->s, "L7: %08X", (UINT32)sharc.dag1.l[7]); break; - case CPUINFO_STR_REGISTER + SHARC_L8: sprintf(info->s, "L8: %08X", (UINT32)sharc.dag2.l[0]); break; - case CPUINFO_STR_REGISTER + SHARC_L9: sprintf(info->s, "L9: %08X", (UINT32)sharc.dag2.l[1]); break; - case CPUINFO_STR_REGISTER + SHARC_L10: sprintf(info->s, "L10: %08X", (UINT32)sharc.dag2.l[2]); break; - case CPUINFO_STR_REGISTER + SHARC_L11: sprintf(info->s, "L11: %08X", (UINT32)sharc.dag2.l[3]); break; - case CPUINFO_STR_REGISTER + SHARC_L12: sprintf(info->s, "L12: %08X", (UINT32)sharc.dag2.l[4]); break; - case CPUINFO_STR_REGISTER + SHARC_L13: sprintf(info->s, "L13: %08X", (UINT32)sharc.dag2.l[5]); break; - case CPUINFO_STR_REGISTER + SHARC_L14: sprintf(info->s, "L14: %08X", (UINT32)sharc.dag2.l[6]); break; - case CPUINFO_STR_REGISTER + SHARC_L15: sprintf(info->s, "L15: %08X", (UINT32)sharc.dag2.l[7]); break; + case CPUINFO_STR_REGISTER + SHARC_L0: sprintf(info->s, "L0: %08X", (UINT32)cpustate->dag1.l[0]); break; + case CPUINFO_STR_REGISTER + SHARC_L1: sprintf(info->s, "L1: %08X", (UINT32)cpustate->dag1.l[1]); break; + case CPUINFO_STR_REGISTER + SHARC_L2: sprintf(info->s, "L2: %08X", (UINT32)cpustate->dag1.l[2]); break; + case CPUINFO_STR_REGISTER + SHARC_L3: sprintf(info->s, "L3: %08X", (UINT32)cpustate->dag1.l[3]); break; + case CPUINFO_STR_REGISTER + SHARC_L4: sprintf(info->s, "L4: %08X", (UINT32)cpustate->dag1.l[4]); break; + case CPUINFO_STR_REGISTER + SHARC_L5: sprintf(info->s, "L5: %08X", (UINT32)cpustate->dag1.l[5]); break; + case CPUINFO_STR_REGISTER + SHARC_L6: sprintf(info->s, "L6: %08X", (UINT32)cpustate->dag1.l[6]); break; + case CPUINFO_STR_REGISTER + SHARC_L7: sprintf(info->s, "L7: %08X", (UINT32)cpustate->dag1.l[7]); break; + case CPUINFO_STR_REGISTER + SHARC_L8: sprintf(info->s, "L8: %08X", (UINT32)cpustate->dag2.l[0]); break; + case CPUINFO_STR_REGISTER + SHARC_L9: sprintf(info->s, "L9: %08X", (UINT32)cpustate->dag2.l[1]); break; + case CPUINFO_STR_REGISTER + SHARC_L10: sprintf(info->s, "L10: %08X", (UINT32)cpustate->dag2.l[2]); break; + case CPUINFO_STR_REGISTER + SHARC_L11: sprintf(info->s, "L11: %08X", (UINT32)cpustate->dag2.l[3]); break; + case CPUINFO_STR_REGISTER + SHARC_L12: sprintf(info->s, "L12: %08X", (UINT32)cpustate->dag2.l[4]); break; + case CPUINFO_STR_REGISTER + SHARC_L13: sprintf(info->s, "L13: %08X", (UINT32)cpustate->dag2.l[5]); break; + case CPUINFO_STR_REGISTER + SHARC_L14: sprintf(info->s, "L14: %08X", (UINT32)cpustate->dag2.l[6]); break; + case CPUINFO_STR_REGISTER + SHARC_L15: sprintf(info->s, "L15: %08X", (UINT32)cpustate->dag2.l[7]); break; - case CPUINFO_STR_REGISTER + SHARC_B0: sprintf(info->s, "B0: %08X", (UINT32)sharc.dag1.b[0]); break; - case CPUINFO_STR_REGISTER + SHARC_B1: sprintf(info->s, "B1: %08X", (UINT32)sharc.dag1.b[1]); break; - case CPUINFO_STR_REGISTER + SHARC_B2: sprintf(info->s, "B2: %08X", (UINT32)sharc.dag1.b[2]); break; - case CPUINFO_STR_REGISTER + SHARC_B3: sprintf(info->s, "B3: %08X", (UINT32)sharc.dag1.b[3]); break; - case CPUINFO_STR_REGISTER + SHARC_B4: sprintf(info->s, "B4: %08X", (UINT32)sharc.dag1.b[4]); break; - case CPUINFO_STR_REGISTER + SHARC_B5: sprintf(info->s, "B5: %08X", (UINT32)sharc.dag1.b[5]); break; - case CPUINFO_STR_REGISTER + SHARC_B6: sprintf(info->s, "B6: %08X", (UINT32)sharc.dag1.b[6]); break; - case CPUINFO_STR_REGISTER + SHARC_B7: sprintf(info->s, "B7: %08X", (UINT32)sharc.dag1.b[7]); break; - case CPUINFO_STR_REGISTER + SHARC_B8: sprintf(info->s, "B8: %08X", (UINT32)sharc.dag2.b[0]); break; - case CPUINFO_STR_REGISTER + SHARC_B9: sprintf(info->s, "B9: %08X", (UINT32)sharc.dag2.b[1]); break; - case CPUINFO_STR_REGISTER + SHARC_B10: sprintf(info->s, "B10: %08X", (UINT32)sharc.dag2.b[2]); break; - case CPUINFO_STR_REGISTER + SHARC_B11: sprintf(info->s, "B11: %08X", (UINT32)sharc.dag2.b[3]); break; - case CPUINFO_STR_REGISTER + SHARC_B12: sprintf(info->s, "B12: %08X", (UINT32)sharc.dag2.b[4]); break; - case CPUINFO_STR_REGISTER + SHARC_B13: sprintf(info->s, "B13: %08X", (UINT32)sharc.dag2.b[5]); break; - case CPUINFO_STR_REGISTER + SHARC_B14: sprintf(info->s, "B14: %08X", (UINT32)sharc.dag2.b[6]); break; - case CPUINFO_STR_REGISTER + SHARC_B15: sprintf(info->s, "B15: %08X", (UINT32)sharc.dag2.b[7]); break; + case CPUINFO_STR_REGISTER + SHARC_B0: sprintf(info->s, "B0: %08X", (UINT32)cpustate->dag1.b[0]); break; + case CPUINFO_STR_REGISTER + SHARC_B1: sprintf(info->s, "B1: %08X", (UINT32)cpustate->dag1.b[1]); break; + case CPUINFO_STR_REGISTER + SHARC_B2: sprintf(info->s, "B2: %08X", (UINT32)cpustate->dag1.b[2]); break; + case CPUINFO_STR_REGISTER + SHARC_B3: sprintf(info->s, "B3: %08X", (UINT32)cpustate->dag1.b[3]); break; + case CPUINFO_STR_REGISTER + SHARC_B4: sprintf(info->s, "B4: %08X", (UINT32)cpustate->dag1.b[4]); break; + case CPUINFO_STR_REGISTER + SHARC_B5: sprintf(info->s, "B5: %08X", (UINT32)cpustate->dag1.b[5]); break; + case CPUINFO_STR_REGISTER + SHARC_B6: sprintf(info->s, "B6: %08X", (UINT32)cpustate->dag1.b[6]); break; + case CPUINFO_STR_REGISTER + SHARC_B7: sprintf(info->s, "B7: %08X", (UINT32)cpustate->dag1.b[7]); break; + case CPUINFO_STR_REGISTER + SHARC_B8: sprintf(info->s, "B8: %08X", (UINT32)cpustate->dag2.b[0]); break; + case CPUINFO_STR_REGISTER + SHARC_B9: sprintf(info->s, "B9: %08X", (UINT32)cpustate->dag2.b[1]); break; + case CPUINFO_STR_REGISTER + SHARC_B10: sprintf(info->s, "B10: %08X", (UINT32)cpustate->dag2.b[2]); break; + case CPUINFO_STR_REGISTER + SHARC_B11: sprintf(info->s, "B11: %08X", (UINT32)cpustate->dag2.b[3]); break; + case CPUINFO_STR_REGISTER + SHARC_B12: sprintf(info->s, "B12: %08X", (UINT32)cpustate->dag2.b[4]); break; + case CPUINFO_STR_REGISTER + SHARC_B13: sprintf(info->s, "B13: %08X", (UINT32)cpustate->dag2.b[5]); break; + case CPUINFO_STR_REGISTER + SHARC_B14: sprintf(info->s, "B14: %08X", (UINT32)cpustate->dag2.b[6]); break; + case CPUINFO_STR_REGISTER + SHARC_B15: sprintf(info->s, "B15: %08X", (UINT32)cpustate->dag2.b[7]); break; } } diff --git a/src/emu/cpu/sharc/sharc.h b/src/emu/cpu/sharc/sharc.h index 9e9a2f6081f..ef31e58ba5c 100644 --- a/src/emu/cpu/sharc/sharc.h +++ b/src/emu/cpu/sharc/sharc.h @@ -22,10 +22,10 @@ typedef struct { SHARC_BOOT_MODE boot_mode; } sharc_config; -extern void sharc_set_flag_input(int flag_num, int state); +extern void sharc_set_flag_input(const device_config *device, int flag_num, int state); -extern void sharc_external_iop_write(UINT32 address, UINT32 data); -extern void sharc_external_dma_write(UINT32 address, UINT64 data); +extern void sharc_external_iop_write(const device_config *device, UINT32 address, UINT32 data); +extern void sharc_external_dma_write(const device_config *device, UINT32 address, UINT64 data); #if (HAS_ADSP21062) CPU_GET_INFO( adsp21062 ); diff --git a/src/emu/cpu/sharc/sharcdma.c b/src/emu/cpu/sharc/sharcdma.c index 720bd9538c0..8506a567c3d 100644 --- a/src/emu/cpu/sharc/sharcdma.c +++ b/src/emu/cpu/sharc/sharcdma.c @@ -6,70 +6,70 @@ #define DMA_PMODE_32_48 3 #define DMA_PMODE_8_48 4 -static void schedule_chained_dma_op(int channel, UINT32 dma_chain_ptr, int chained_direction) +static void schedule_chained_dma_op(SHARC_REGS *cpustate, int channel, UINT32 dma_chain_ptr, int chained_direction) { UINT32 op_ptr = 0x20000 + dma_chain_ptr; - UINT32 int_index = dm_read32(op_ptr - 0); - UINT32 int_modifier = dm_read32(op_ptr - 1); - UINT32 int_count = dm_read32(op_ptr - 2); - UINT32 chain_ptr = dm_read32(op_ptr - 3); - //UINT32 gen_purpose = dm_read32(op_ptr - 4); - UINT32 ext_index = dm_read32(op_ptr - 5); - UINT32 ext_modifier = dm_read32(op_ptr - 6); - UINT32 ext_count = dm_read32(op_ptr - 7); + UINT32 int_index = dm_read32(cpustate, op_ptr - 0); + UINT32 int_modifier = dm_read32(cpustate, op_ptr - 1); + UINT32 int_count = dm_read32(cpustate, op_ptr - 2); + UINT32 chain_ptr = dm_read32(cpustate, op_ptr - 3); + //UINT32 gen_purpose = dm_read32(cpustate, op_ptr - 4); + UINT32 ext_index = dm_read32(cpustate, op_ptr - 5); + UINT32 ext_modifier = dm_read32(cpustate, op_ptr - 6); + UINT32 ext_count = dm_read32(cpustate, op_ptr - 7); - if (sharc.dmaop_cycles > 0) + if (cpustate->dmaop_cycles > 0) { - fatalerror("schedule_chained_dma_op: DMA operation already scheduled at %08X!", sharc.pc); + fatalerror("schedule_chained_dma_op: DMA operation already scheduled at %08X!", cpustate->pc); } if (chained_direction) // Transmit to external { - sharc.dmaop_dst = ext_index; - sharc.dmaop_dst_modifier = ext_modifier; - sharc.dmaop_dst_count = ext_count; - sharc.dmaop_src = int_index; - sharc.dmaop_src_modifier = int_modifier; - sharc.dmaop_src_count = int_count; + cpustate->dmaop_dst = ext_index; + cpustate->dmaop_dst_modifier = ext_modifier; + cpustate->dmaop_dst_count = ext_count; + cpustate->dmaop_src = int_index; + cpustate->dmaop_src_modifier = int_modifier; + cpustate->dmaop_src_count = int_count; } else // Receive from external { - sharc.dmaop_src = ext_index; - sharc.dmaop_src_modifier = ext_modifier; - sharc.dmaop_src_count = ext_count; - sharc.dmaop_dst = int_index; - sharc.dmaop_dst_modifier = int_modifier; - sharc.dmaop_dst_count = int_count; + cpustate->dmaop_src = ext_index; + cpustate->dmaop_src_modifier = ext_modifier; + cpustate->dmaop_src_count = ext_count; + cpustate->dmaop_dst = int_index; + cpustate->dmaop_dst_modifier = int_modifier; + cpustate->dmaop_dst_count = int_count; } - sharc.dmaop_pmode = 0; - sharc.dmaop_channel = channel; - sharc.dmaop_cycles = sharc.dmaop_src_count / 4; - sharc.dmaop_chain_ptr = chain_ptr; - sharc.dmaop_chained_direction = chained_direction; + cpustate->dmaop_pmode = 0; + cpustate->dmaop_channel = channel; + cpustate->dmaop_cycles = cpustate->dmaop_src_count / 4; + cpustate->dmaop_chain_ptr = chain_ptr; + cpustate->dmaop_chained_direction = chained_direction; } -static void schedule_dma_op(int channel, UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode) +static void schedule_dma_op(SHARC_REGS *cpustate, int channel, UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode) { - if (sharc.dmaop_cycles > 0) + if (cpustate->dmaop_cycles > 0) { - fatalerror("schedule_dma_op: DMA operation already scheduled at %08X!", sharc.pc); + fatalerror("schedule_dma_op: DMA operation already scheduled at %08X!", cpustate->pc); } - sharc.dmaop_channel = channel; - sharc.dmaop_src = src; - sharc.dmaop_dst = dst; - sharc.dmaop_src_modifier = src_modifier; - sharc.dmaop_dst_modifier = dst_modifier; - sharc.dmaop_src_count = src_count; - sharc.dmaop_dst_count = dst_count; - sharc.dmaop_pmode = pmode; - sharc.dmaop_chain_ptr = 0; - sharc.dmaop_cycles = src_count / 4; + cpustate->dmaop_channel = channel; + cpustate->dmaop_src = src; + cpustate->dmaop_dst = dst; + cpustate->dmaop_src_modifier = src_modifier; + cpustate->dmaop_dst_modifier = dst_modifier; + cpustate->dmaop_src_count = src_count; + cpustate->dmaop_dst_count = dst_count; + cpustate->dmaop_pmode = pmode; + cpustate->dmaop_chain_ptr = 0; + cpustate->dmaop_cycles = src_count / 4; } -static void dma_op(UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode) +static void dma_op(SHARC_REGS *cpustate, UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode) { int i; //printf("dma_op: %08X, %08X, %08X, %08X, %08X, %08X, %d\n", src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode); @@ -80,8 +80,8 @@ static void dma_op(UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, i { for (i=0; i < src_count; i++) { - UINT32 data = dm_read32(src); - dm_write32(dst, data); + UINT32 data = dm_read32(cpustate, src); + dm_write32(cpustate, dst, data); src += src_modifier; dst += dst_modifier; } @@ -92,9 +92,9 @@ static void dma_op(UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, i int length = src_count/2; for (i=0; i < length; i++) { - UINT32 data = ((dm_read32(src+0) & 0xffff) << 16) | (dm_read32(src+1) & 0xffff); + UINT32 data = ((dm_read32(cpustate, src+0) & 0xffff) << 16) | (dm_read32(cpustate, src+1) & 0xffff); - dm_write32(dst, data); + dm_write32(cpustate, dst, data); src += src_modifier * 2; dst += dst_modifier; } @@ -105,14 +105,14 @@ static void dma_op(UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, i int length = src_count/6; for (i=0; i < length; i++) { - UINT64 data = ((UINT64)(dm_read32(src+0) & 0xff) << 0) | - ((UINT64)(dm_read32(src+1) & 0xff) << 8) | - ((UINT64)(dm_read32(src+2) & 0xff) << 16) | - ((UINT64)(dm_read32(src+3) & 0xff) << 24) | - ((UINT64)(dm_read32(src+4) & 0xff) << 32) | - ((UINT64)(dm_read32(src+5) & 0xff) << 40); + UINT64 data = ((UINT64)(dm_read32(cpustate, src+0) & 0xff) << 0) | + ((UINT64)(dm_read32(cpustate, src+1) & 0xff) << 8) | + ((UINT64)(dm_read32(cpustate, src+2) & 0xff) << 16) | + ((UINT64)(dm_read32(cpustate, src+3) & 0xff) << 24) | + ((UINT64)(dm_read32(cpustate, src+4) & 0xff) << 32) | + ((UINT64)(dm_read32(cpustate, src+5) & 0xff) << 40); - pm_write48(dst, data); + pm_write48(cpustate, dst, data); src += src_modifier * 6; dst += dst_modifier; } @@ -124,35 +124,35 @@ static void dma_op(UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, i } } - if (sharc.dmaop_channel == 6) + if (cpustate->dmaop_channel == 6) { - sharc.irptl |= (1 << (sharc.dmaop_channel+10)); + cpustate->irptl |= (1 << (cpustate->dmaop_channel+10)); /* DMA interrupt */ - if (sharc.imask & (1 << (sharc.dmaop_channel+10))) + if (cpustate->imask & (1 << (cpustate->dmaop_channel+10))) { - sharc.irq_active |= 1 << (sharc.dmaop_channel+10); + cpustate->irq_active |= 1 << (cpustate->dmaop_channel+10); } } } -static void sharc_dma_exec(int channel) +static void sharc_dma_exec(SHARC_REGS *cpustate, int channel) { UINT32 src, dst; UINT32 src_count, dst_count; UINT32 src_modifier, dst_modifier; int chen, tran, dtype, pmode, mswf, master, ishake, intio, ext, flsh; - chen = (sharc.dma[channel].control >> 1) & 0x1; - tran = (sharc.dma[channel].control >> 2) & 0x1; - dtype = (sharc.dma[channel].control >> 5) & 0x1; - pmode = (sharc.dma[channel].control >> 6) & 0x3; - mswf = (sharc.dma[channel].control >> 8) & 0x1; - master = (sharc.dma[channel].control >> 9) & 0x1; - ishake = (sharc.dma[channel].control >> 10) & 0x1; - intio = (sharc.dma[channel].control >> 11) & 0x1; - ext = (sharc.dma[channel].control >> 12) & 0x1; - flsh = (sharc.dma[channel].control >> 13) & 0x1; + chen = (cpustate->dma[channel].control >> 1) & 0x1; + tran = (cpustate->dma[channel].control >> 2) & 0x1; + dtype = (cpustate->dma[channel].control >> 5) & 0x1; + pmode = (cpustate->dma[channel].control >> 6) & 0x3; + mswf = (cpustate->dma[channel].control >> 8) & 0x1; + master = (cpustate->dma[channel].control >> 9) & 0x1; + ishake = (cpustate->dma[channel].control >> 10) & 0x1; + intio = (cpustate->dma[channel].control >> 11) & 0x1; + ext = (cpustate->dma[channel].control >> 12) & 0x1; + flsh = (cpustate->dma[channel].control >> 13) & 0x1; if (ishake) fatalerror("SHARC: dma_exec: handshake not supported"); @@ -163,29 +163,29 @@ static void sharc_dma_exec(int channel) if (chen) // Chained DMA { - UINT32 dma_chain_ptr = sharc.dma[channel].chain_ptr & 0x1ffff; + UINT32 dma_chain_ptr = cpustate->dma[channel].chain_ptr & 0x1ffff; - schedule_chained_dma_op(channel, dma_chain_ptr, tran); + schedule_chained_dma_op(cpustate, channel, dma_chain_ptr, tran); } else { if (tran) // Transmit to external { - dst = sharc.dma[channel].ext_index; - dst_modifier = sharc.dma[channel].ext_modifier; - dst_count = sharc.dma[channel].ext_count; - src = sharc.dma[channel].int_index; - src_modifier = sharc.dma[channel].int_modifier; - src_count = sharc.dma[channel].int_count; + dst = cpustate->dma[channel].ext_index; + dst_modifier = cpustate->dma[channel].ext_modifier; + dst_count = cpustate->dma[channel].ext_count; + src = cpustate->dma[channel].int_index; + src_modifier = cpustate->dma[channel].int_modifier; + src_count = cpustate->dma[channel].int_count; } else // Receive from external { - src = sharc.dma[channel].ext_index; - src_modifier = sharc.dma[channel].ext_modifier; - src_count = sharc.dma[channel].ext_count; - dst = sharc.dma[channel].int_index; - dst_modifier = sharc.dma[channel].int_modifier; - dst_count = sharc.dma[channel].int_count; + src = cpustate->dma[channel].ext_index; + src_modifier = cpustate->dma[channel].ext_modifier; + src_count = cpustate->dma[channel].ext_count; + dst = cpustate->dma[channel].int_index; + dst_modifier = cpustate->dma[channel].int_modifier; + dst_count = cpustate->dma[channel].int_count; if (dst < 0x20000) { @@ -199,6 +199,6 @@ static void sharc_dma_exec(int channel) pmode = DMA_PMODE_8_48; } - schedule_dma_op(channel, src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode); + schedule_dma_op(cpustate, channel, src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode); } } diff --git a/src/emu/cpu/sharc/sharcmem.c b/src/emu/cpu/sharc/sharcmem.c index 55dec19da1f..3b275f06be5 100644 --- a/src/emu/cpu/sharc/sharcmem.c +++ b/src/emu/cpu/sharc/sharcmem.c @@ -1,35 +1,35 @@ /* SHARC memory operations */ -static UINT32 pm_read32(UINT32 address) +static UINT32 pm_read32(SHARC_REGS *cpustate, UINT32 address) { if (address >= 0x20000 && address < 0x28000) { UINT32 addr = (address & 0x7fff) * 3; - return (UINT32)(sharc.internal_ram_block0[addr + 0] << 16) | - (sharc.internal_ram_block0[addr + 1]); + return (UINT32)(cpustate->internal_ram_block0[addr + 0] << 16) | + (cpustate->internal_ram_block0[addr + 1]); } else if (address >= 0x28000 && address < 0x40000) { // block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff UINT32 addr = (address & 0x7fff) * 3; - return (UINT32)(sharc.internal_ram_block1[addr + 0] << 16) | - (sharc.internal_ram_block1[addr + 1]); + return (UINT32)(cpustate->internal_ram_block1[addr + 0] << 16) | + (cpustate->internal_ram_block1[addr + 1]); } else { - fatalerror("SHARC: PM Bus Read %08X at %08X", address, sharc.pc); + fatalerror("SHARC: PM Bus Read %08X at %08X", address, cpustate->pc); } } -static void pm_write32(UINT32 address, UINT32 data) +static void pm_write32(SHARC_REGS *cpustate, UINT32 address, UINT32 data) { if (address >= 0x20000 && address < 0x28000) { UINT32 addr = (address & 0x7fff) * 3; - sharc.internal_ram_block0[addr + 0] = (UINT16)(data >> 16); - sharc.internal_ram_block0[addr + 1] = (UINT16)(data); + cpustate->internal_ram_block0[addr + 0] = (UINT16)(data >> 16); + cpustate->internal_ram_block0[addr + 1] = (UINT16)(data); return; } else if (address >= 0x28000 && address < 0x40000) @@ -37,50 +37,50 @@ static void pm_write32(UINT32 address, UINT32 data) // block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff UINT32 addr = (address & 0x7fff) * 3; - sharc.internal_ram_block1[addr + 0] = (UINT16)(data >> 16); - sharc.internal_ram_block1[addr + 1] = (UINT16)(data); + cpustate->internal_ram_block1[addr + 0] = (UINT16)(data >> 16); + cpustate->internal_ram_block1[addr + 1] = (UINT16)(data); return; } else { - fatalerror("SHARC: PM Bus Write %08X, %08X at %08X", address, data, sharc.pc); + fatalerror("SHARC: PM Bus Write %08X, %08X at %08X", address, data, cpustate->pc); } } -static UINT64 pm_read48(UINT32 address) +static UINT64 pm_read48(SHARC_REGS *cpustate, UINT32 address) { if (address >= 0x20000 && address < 0x28000) { UINT32 addr = (address & 0x7fff) * 3; - return ((UINT64)(sharc.internal_ram_block0[addr + 0]) << 32) | - ((UINT64)(sharc.internal_ram_block0[addr + 1]) << 16) | - ((UINT64)(sharc.internal_ram_block0[addr + 2]) << 0); + return ((UINT64)(cpustate->internal_ram_block0[addr + 0]) << 32) | + ((UINT64)(cpustate->internal_ram_block0[addr + 1]) << 16) | + ((UINT64)(cpustate->internal_ram_block0[addr + 2]) << 0); } else if (address >= 0x28000 && address < 0x40000) { // block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff UINT32 addr = (address & 0x7fff) * 3; - return ((UINT64)(sharc.internal_ram_block1[addr + 0]) << 32) | - ((UINT64)(sharc.internal_ram_block1[addr + 1]) << 16) | - ((UINT64)(sharc.internal_ram_block1[addr + 2]) << 0); + return ((UINT64)(cpustate->internal_ram_block1[addr + 0]) << 32) | + ((UINT64)(cpustate->internal_ram_block1[addr + 1]) << 16) | + ((UINT64)(cpustate->internal_ram_block1[addr + 2]) << 0); } else { - fatalerror("SHARC: PM Bus Read %08X at %08X", address, sharc.pc); + fatalerror("SHARC: PM Bus Read %08X at %08X", address, cpustate->pc); } return 0; } -static void pm_write48(UINT32 address, UINT64 data) +static void pm_write48(SHARC_REGS *cpustate, UINT32 address, UINT64 data) { if (address >= 0x20000 && address < 0x28000) { UINT32 addr = (address & 0x7fff) * 3; - sharc.internal_ram_block0[addr + 0] = (UINT16)(data >> 32); - sharc.internal_ram_block0[addr + 1] = (UINT16)(data >> 16); - sharc.internal_ram_block0[addr + 2] = (UINT16)(data); + cpustate->internal_ram_block0[addr + 0] = (UINT16)(data >> 32); + cpustate->internal_ram_block0[addr + 1] = (UINT16)(data >> 16); + cpustate->internal_ram_block0[addr + 2] = (UINT16)(data); return; } else if (address >= 0x28000 && address < 0x40000) @@ -88,36 +88,36 @@ static void pm_write48(UINT32 address, UINT64 data) // block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff UINT32 addr = (address & 0x7fff) * 3; - sharc.internal_ram_block1[addr + 0] = (UINT16)(data >> 32); - sharc.internal_ram_block1[addr + 1] = (UINT16)(data >> 16); - sharc.internal_ram_block1[addr + 2] = (UINT16)(data); + cpustate->internal_ram_block1[addr + 0] = (UINT16)(data >> 32); + cpustate->internal_ram_block1[addr + 1] = (UINT16)(data >> 16); + cpustate->internal_ram_block1[addr + 2] = (UINT16)(data); return; } else { - fatalerror("SHARC: PM Bus Write %08X, %04X%08X at %08X", address, (UINT16)(data >> 32),(UINT32)data, sharc.pc); + fatalerror("SHARC: PM Bus Write %08X, %04X%08X at %08X", address, (UINT16)(data >> 32),(UINT32)data, cpustate->pc); } } -static UINT32 dm_read32(UINT32 address) +static UINT32 dm_read32(SHARC_REGS *cpustate, UINT32 address) { if (address < 0x100) { - return sharc_iop_r(address); + return sharc_iop_r(cpustate, address); } else if (address >= 0x20000 && address < 0x28000) { UINT32 addr = (address & 0x7fff) * 2; - return (UINT32)(sharc.internal_ram_block0[addr + 0] << 16) | - (sharc.internal_ram_block0[addr + 1]); + return (UINT32)(cpustate->internal_ram_block0[addr + 0] << 16) | + (cpustate->internal_ram_block0[addr + 1]); } else if (address >= 0x28000 && address < 0x40000) { // block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff UINT32 addr = (address & 0x7fff) * 2; - return (UINT32)(sharc.internal_ram_block1[addr + 0] << 16) | - (sharc.internal_ram_block1[addr + 1]); + return (UINT32)(cpustate->internal_ram_block1[addr + 0] << 16) | + (cpustate->internal_ram_block1[addr + 1]); } // short word addressing @@ -125,8 +125,8 @@ static UINT32 dm_read32(UINT32 address) { UINT32 addr = address & 0xffff; - UINT16 r = sharc.internal_ram_block0[addr ^ 1]; - if (sharc.mode1 & 0x4000) + UINT16 r = cpustate->internal_ram_block0[addr ^ 1]; + if (cpustate->mode1 & 0x4000) { // sign-extend return (INT32)(INT16)(r); @@ -141,8 +141,8 @@ static UINT32 dm_read32(UINT32 address) // block 1 is mirrored in 0x50000...5ffff, 0x60000...0x6ffff and 0x70000...7ffff UINT32 addr = address & 0xffff; - UINT16 r = sharc.internal_ram_block1[addr ^ 1]; - if (sharc.mode1 & 0x4000) + UINT16 r = cpustate->internal_ram_block1[addr ^ 1]; + if (cpustate->mode1 & 0x4000) { // sign-extend return (INT32)(INT16)(r); @@ -153,22 +153,22 @@ static UINT32 dm_read32(UINT32 address) } } - return memory_read_dword_32le(sharc.data, address << 2); + return memory_read_dword_32le(cpustate->data, address << 2); } -static void dm_write32(UINT32 address, UINT32 data) +static void dm_write32(SHARC_REGS *cpustate, UINT32 address, UINT32 data) { if (address < 0x100) { - sharc_iop_w(address, data); + sharc_iop_w(cpustate, address, data); return; } else if (address >= 0x20000 && address < 0x28000) { UINT32 addr = (address & 0x7fff) * 2; - sharc.internal_ram_block0[addr + 0] = (UINT16)(data >> 16); - sharc.internal_ram_block0[addr + 1] = (UINT16)(data); + cpustate->internal_ram_block0[addr + 0] = (UINT16)(data >> 16); + cpustate->internal_ram_block0[addr + 1] = (UINT16)(data); return; } else if (address >= 0x28000 && address < 0x40000) @@ -176,8 +176,8 @@ static void dm_write32(UINT32 address, UINT32 data) // block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff UINT32 addr = (address & 0x7fff) * 2; - sharc.internal_ram_block1[addr + 0] = (UINT16)(data >> 16); - sharc.internal_ram_block1[addr + 1] = (UINT16)(data); + cpustate->internal_ram_block1[addr + 0] = (UINT16)(data >> 16); + cpustate->internal_ram_block1[addr + 1] = (UINT16)(data); return; } @@ -186,7 +186,7 @@ static void dm_write32(UINT32 address, UINT32 data) { UINT32 addr = address & 0xffff; - sharc.internal_ram_block0[addr ^ 1] = data; + cpustate->internal_ram_block0[addr ^ 1] = data; return; } else if (address >= 0x50000 && address < 0x80000) @@ -194,9 +194,9 @@ static void dm_write32(UINT32 address, UINT32 data) // block 1 is mirrored in 0x50000...5ffff, 0x60000...0x6ffff and 0x70000...7ffff UINT32 addr = address & 0xffff; - sharc.internal_ram_block1[addr ^ 1] = data; + cpustate->internal_ram_block1[addr ^ 1] = data; return; } - memory_write_dword_32le(sharc.data, address << 2, data); + memory_write_dword_32le(cpustate->data, address << 2, data); } diff --git a/src/emu/cpu/sharc/sharcops.c b/src/emu/cpu/sharc/sharcops.c index fc73cbb8c5f..dbcc94548a2 100644 --- a/src/emu/cpu/sharc/sharcops.c +++ b/src/emu/cpu/sharc/sharcops.c @@ -1,14 +1,14 @@ #define SIGN_EXTEND6(x) (((x) & 0x20) ? (0xffffffc0 | (x)) : (x)) #define SIGN_EXTEND24(x) (((x) & 0x800000) ? (0xff000000 | (x)) : (x)) -#define PM_REG_I(x) (sharc.dag2.i[x]) -#define PM_REG_M(x) (sharc.dag2.m[x]) -#define PM_REG_B(x) (sharc.dag2.b[x]) -#define PM_REG_L(x) (sharc.dag2.l[x]) -#define DM_REG_I(x) (sharc.dag1.i[x]) -#define DM_REG_M(x) (sharc.dag1.m[x]) -#define DM_REG_B(x) (sharc.dag1.b[x]) -#define DM_REG_L(x) (sharc.dag1.l[x]) +#define PM_REG_I(x) (cpustate->dag2.i[x]) +#define PM_REG_M(x) (cpustate->dag2.m[x]) +#define PM_REG_B(x) (cpustate->dag2.b[x]) +#define PM_REG_L(x) (cpustate->dag2.l[x]) +#define DM_REG_I(x) (cpustate->dag1.i[x]) +#define DM_REG_M(x) (cpustate->dag1.m[x]) +#define DM_REG_B(x) (cpustate->dag1.b[x]) +#define DM_REG_L(x) (cpustate->dag1.l[x]) // ASTAT flags #define AZ 0x1 /* ALU result zero */ @@ -87,8 +87,8 @@ -#define REG(x) (sharc.r[x].r) -#define FREG(x) (sharc.r[x].f) +#define REG(x) (cpustate->r[x].r) +#define FREG(x) (cpustate->r[x].f) #define UPDATE_CIRCULAR_BUFFER_PM(x) \ { \ @@ -123,20 +123,20 @@ /*****************************************************************************/ -static void systemreg_write_latency_effect(void); +static void systemreg_write_latency_effect(SHARC_REGS *cpustate); -static void add_systemreg_write_latency_effect(int sysreg, UINT32 data, UINT32 prev_data) +static void add_systemreg_write_latency_effect(SHARC_REGS *cpustate, int sysreg, UINT32 data, UINT32 prev_data) { - if (sharc.systemreg_latency_cycles > 0) + if (cpustate->systemreg_latency_cycles > 0) { - //fatalerror("SHARC: add_systemreg_write_latency_effect: already scheduled! (reg: %02X, data: %08X, PC: %08X)\n", systemreg_latency_reg, systemreg_latency_data, sharc.pc); - systemreg_write_latency_effect(); + //fatalerror("SHARC: add_systemreg_write_latency_effect: already scheduled! (reg: %02X, data: %08X, PC: %08X)\n", systemreg_latency_reg, systemreg_latency_data, cpustate->pc); + systemreg_write_latency_effect(cpustate); } - sharc.systemreg_latency_cycles = 2; - sharc.systemreg_latency_reg = sysreg; - sharc.systemreg_latency_data = data; - sharc.systemreg_previous_data = prev_data; + cpustate->systemreg_latency_cycles = 2; + cpustate->systemreg_latency_reg = sysreg; + cpustate->systemreg_latency_data = data; + cpustate->systemreg_previous_data = prev_data; } INLINE void swap_register(UINT32 *a, UINT32 *b) @@ -146,18 +146,18 @@ INLINE void swap_register(UINT32 *a, UINT32 *b) *b = temp; } -static void systemreg_write_latency_effect(void) +static void systemreg_write_latency_effect(SHARC_REGS *cpustate) { int i; - UINT32 data = sharc.systemreg_latency_data; - UINT32 old_data = sharc.systemreg_previous_data; + UINT32 data = cpustate->systemreg_latency_data; + UINT32 old_data = cpustate->systemreg_previous_data; - switch(sharc.systemreg_latency_reg) + switch(cpustate->systemreg_latency_reg) { case 0xb: /* MODE1 */ { UINT32 oldreg = old_data; - sharc.mode1 = data; + cpustate->mode1 = data; if ((data & 0x1) != (oldreg & 0x1)) { @@ -174,117 +174,117 @@ static void systemreg_write_latency_effect(void) if ((data & 0x8) != (oldreg & 0x8)) /* Switch DAG1 7-4 */ { - swap_register(&sharc.dag1.i[4], &sharc.dag1_alt.i[4]); - swap_register(&sharc.dag1.i[5], &sharc.dag1_alt.i[5]); - swap_register(&sharc.dag1.i[6], &sharc.dag1_alt.i[6]); - swap_register(&sharc.dag1.i[7], &sharc.dag1_alt.i[7]); - swap_register(&sharc.dag1.m[4], &sharc.dag1_alt.m[4]); - swap_register(&sharc.dag1.m[5], &sharc.dag1_alt.m[5]); - swap_register(&sharc.dag1.m[6], &sharc.dag1_alt.m[6]); - swap_register(&sharc.dag1.m[7], &sharc.dag1_alt.m[7]); - swap_register(&sharc.dag1.l[4], &sharc.dag1_alt.l[4]); - swap_register(&sharc.dag1.l[5], &sharc.dag1_alt.l[5]); - swap_register(&sharc.dag1.l[6], &sharc.dag1_alt.l[6]); - swap_register(&sharc.dag1.l[7], &sharc.dag1_alt.l[7]); - swap_register(&sharc.dag1.b[4], &sharc.dag1_alt.b[4]); - swap_register(&sharc.dag1.b[5], &sharc.dag1_alt.b[5]); - swap_register(&sharc.dag1.b[6], &sharc.dag1_alt.b[6]); - swap_register(&sharc.dag1.b[7], &sharc.dag1_alt.b[7]); + swap_register(&cpustate->dag1.i[4], &cpustate->dag1_alt.i[4]); + swap_register(&cpustate->dag1.i[5], &cpustate->dag1_alt.i[5]); + swap_register(&cpustate->dag1.i[6], &cpustate->dag1_alt.i[6]); + swap_register(&cpustate->dag1.i[7], &cpustate->dag1_alt.i[7]); + swap_register(&cpustate->dag1.m[4], &cpustate->dag1_alt.m[4]); + swap_register(&cpustate->dag1.m[5], &cpustate->dag1_alt.m[5]); + swap_register(&cpustate->dag1.m[6], &cpustate->dag1_alt.m[6]); + swap_register(&cpustate->dag1.m[7], &cpustate->dag1_alt.m[7]); + swap_register(&cpustate->dag1.l[4], &cpustate->dag1_alt.l[4]); + swap_register(&cpustate->dag1.l[5], &cpustate->dag1_alt.l[5]); + swap_register(&cpustate->dag1.l[6], &cpustate->dag1_alt.l[6]); + swap_register(&cpustate->dag1.l[7], &cpustate->dag1_alt.l[7]); + swap_register(&cpustate->dag1.b[4], &cpustate->dag1_alt.b[4]); + swap_register(&cpustate->dag1.b[5], &cpustate->dag1_alt.b[5]); + swap_register(&cpustate->dag1.b[6], &cpustate->dag1_alt.b[6]); + swap_register(&cpustate->dag1.b[7], &cpustate->dag1_alt.b[7]); } if ((data & 0x10) != (oldreg & 0x10)) /* Switch DAG1 3-0 */ { - swap_register(&sharc.dag1.i[0], &sharc.dag1_alt.i[0]); - swap_register(&sharc.dag1.i[1], &sharc.dag1_alt.i[1]); - swap_register(&sharc.dag1.i[2], &sharc.dag1_alt.i[2]); - swap_register(&sharc.dag1.i[3], &sharc.dag1_alt.i[3]); - swap_register(&sharc.dag1.m[0], &sharc.dag1_alt.m[0]); - swap_register(&sharc.dag1.m[1], &sharc.dag1_alt.m[1]); - swap_register(&sharc.dag1.m[2], &sharc.dag1_alt.m[2]); - swap_register(&sharc.dag1.m[3], &sharc.dag1_alt.m[3]); - swap_register(&sharc.dag1.l[0], &sharc.dag1_alt.l[0]); - swap_register(&sharc.dag1.l[1], &sharc.dag1_alt.l[1]); - swap_register(&sharc.dag1.l[2], &sharc.dag1_alt.l[2]); - swap_register(&sharc.dag1.l[3], &sharc.dag1_alt.l[3]); - swap_register(&sharc.dag1.b[0], &sharc.dag1_alt.b[0]); - swap_register(&sharc.dag1.b[1], &sharc.dag1_alt.b[1]); - swap_register(&sharc.dag1.b[2], &sharc.dag1_alt.b[2]); - swap_register(&sharc.dag1.b[3], &sharc.dag1_alt.b[3]); + swap_register(&cpustate->dag1.i[0], &cpustate->dag1_alt.i[0]); + swap_register(&cpustate->dag1.i[1], &cpustate->dag1_alt.i[1]); + swap_register(&cpustate->dag1.i[2], &cpustate->dag1_alt.i[2]); + swap_register(&cpustate->dag1.i[3], &cpustate->dag1_alt.i[3]); + swap_register(&cpustate->dag1.m[0], &cpustate->dag1_alt.m[0]); + swap_register(&cpustate->dag1.m[1], &cpustate->dag1_alt.m[1]); + swap_register(&cpustate->dag1.m[2], &cpustate->dag1_alt.m[2]); + swap_register(&cpustate->dag1.m[3], &cpustate->dag1_alt.m[3]); + swap_register(&cpustate->dag1.l[0], &cpustate->dag1_alt.l[0]); + swap_register(&cpustate->dag1.l[1], &cpustate->dag1_alt.l[1]); + swap_register(&cpustate->dag1.l[2], &cpustate->dag1_alt.l[2]); + swap_register(&cpustate->dag1.l[3], &cpustate->dag1_alt.l[3]); + swap_register(&cpustate->dag1.b[0], &cpustate->dag1_alt.b[0]); + swap_register(&cpustate->dag1.b[1], &cpustate->dag1_alt.b[1]); + swap_register(&cpustate->dag1.b[2], &cpustate->dag1_alt.b[2]); + swap_register(&cpustate->dag1.b[3], &cpustate->dag1_alt.b[3]); } if ((data & 0x20) != (oldreg & 0x20)) /* Switch DAG2 15-12 */ { - swap_register(&sharc.dag2.i[4], &sharc.dag2_alt.i[4]); - swap_register(&sharc.dag2.i[5], &sharc.dag2_alt.i[5]); - swap_register(&sharc.dag2.i[6], &sharc.dag2_alt.i[6]); - swap_register(&sharc.dag2.i[7], &sharc.dag2_alt.i[7]); - swap_register(&sharc.dag2.m[4], &sharc.dag2_alt.m[4]); - swap_register(&sharc.dag2.m[5], &sharc.dag2_alt.m[5]); - swap_register(&sharc.dag2.m[6], &sharc.dag2_alt.m[6]); - swap_register(&sharc.dag2.m[7], &sharc.dag2_alt.m[7]); - swap_register(&sharc.dag2.l[4], &sharc.dag2_alt.l[4]); - swap_register(&sharc.dag2.l[5], &sharc.dag2_alt.l[5]); - swap_register(&sharc.dag2.l[6], &sharc.dag2_alt.l[6]); - swap_register(&sharc.dag2.l[7], &sharc.dag2_alt.l[7]); - swap_register(&sharc.dag2.b[4], &sharc.dag2_alt.b[4]); - swap_register(&sharc.dag2.b[5], &sharc.dag2_alt.b[5]); - swap_register(&sharc.dag2.b[6], &sharc.dag2_alt.b[6]); - swap_register(&sharc.dag2.b[7], &sharc.dag2_alt.b[7]); + swap_register(&cpustate->dag2.i[4], &cpustate->dag2_alt.i[4]); + swap_register(&cpustate->dag2.i[5], &cpustate->dag2_alt.i[5]); + swap_register(&cpustate->dag2.i[6], &cpustate->dag2_alt.i[6]); + swap_register(&cpustate->dag2.i[7], &cpustate->dag2_alt.i[7]); + swap_register(&cpustate->dag2.m[4], &cpustate->dag2_alt.m[4]); + swap_register(&cpustate->dag2.m[5], &cpustate->dag2_alt.m[5]); + swap_register(&cpustate->dag2.m[6], &cpustate->dag2_alt.m[6]); + swap_register(&cpustate->dag2.m[7], &cpustate->dag2_alt.m[7]); + swap_register(&cpustate->dag2.l[4], &cpustate->dag2_alt.l[4]); + swap_register(&cpustate->dag2.l[5], &cpustate->dag2_alt.l[5]); + swap_register(&cpustate->dag2.l[6], &cpustate->dag2_alt.l[6]); + swap_register(&cpustate->dag2.l[7], &cpustate->dag2_alt.l[7]); + swap_register(&cpustate->dag2.b[4], &cpustate->dag2_alt.b[4]); + swap_register(&cpustate->dag2.b[5], &cpustate->dag2_alt.b[5]); + swap_register(&cpustate->dag2.b[6], &cpustate->dag2_alt.b[6]); + swap_register(&cpustate->dag2.b[7], &cpustate->dag2_alt.b[7]); } if ((data & 0x40) != (oldreg & 0x40)) /* Switch DAG2 11-8 */ { - swap_register(&sharc.dag2.i[0], &sharc.dag2_alt.i[0]); - swap_register(&sharc.dag2.i[1], &sharc.dag2_alt.i[1]); - swap_register(&sharc.dag2.i[2], &sharc.dag2_alt.i[2]); - swap_register(&sharc.dag2.i[3], &sharc.dag2_alt.i[3]); - swap_register(&sharc.dag2.m[0], &sharc.dag2_alt.m[0]); - swap_register(&sharc.dag2.m[1], &sharc.dag2_alt.m[1]); - swap_register(&sharc.dag2.m[2], &sharc.dag2_alt.m[2]); - swap_register(&sharc.dag2.m[3], &sharc.dag2_alt.m[3]); - swap_register(&sharc.dag2.l[0], &sharc.dag2_alt.l[0]); - swap_register(&sharc.dag2.l[1], &sharc.dag2_alt.l[1]); - swap_register(&sharc.dag2.l[2], &sharc.dag2_alt.l[2]); - swap_register(&sharc.dag2.l[3], &sharc.dag2_alt.l[3]); - swap_register(&sharc.dag2.b[0], &sharc.dag2_alt.b[0]); - swap_register(&sharc.dag2.b[1], &sharc.dag2_alt.b[1]); - swap_register(&sharc.dag2.b[2], &sharc.dag2_alt.b[2]); - swap_register(&sharc.dag2.b[3], &sharc.dag2_alt.b[3]); + swap_register(&cpustate->dag2.i[0], &cpustate->dag2_alt.i[0]); + swap_register(&cpustate->dag2.i[1], &cpustate->dag2_alt.i[1]); + swap_register(&cpustate->dag2.i[2], &cpustate->dag2_alt.i[2]); + swap_register(&cpustate->dag2.i[3], &cpustate->dag2_alt.i[3]); + swap_register(&cpustate->dag2.m[0], &cpustate->dag2_alt.m[0]); + swap_register(&cpustate->dag2.m[1], &cpustate->dag2_alt.m[1]); + swap_register(&cpustate->dag2.m[2], &cpustate->dag2_alt.m[2]); + swap_register(&cpustate->dag2.m[3], &cpustate->dag2_alt.m[3]); + swap_register(&cpustate->dag2.l[0], &cpustate->dag2_alt.l[0]); + swap_register(&cpustate->dag2.l[1], &cpustate->dag2_alt.l[1]); + swap_register(&cpustate->dag2.l[2], &cpustate->dag2_alt.l[2]); + swap_register(&cpustate->dag2.l[3], &cpustate->dag2_alt.l[3]); + swap_register(&cpustate->dag2.b[0], &cpustate->dag2_alt.b[0]); + swap_register(&cpustate->dag2.b[1], &cpustate->dag2_alt.b[1]); + swap_register(&cpustate->dag2.b[2], &cpustate->dag2_alt.b[2]); + swap_register(&cpustate->dag2.b[3], &cpustate->dag2_alt.b[3]); } if ((data & 0x80) != (oldreg & 0x80)) { for (i=8; i<16; i++) - swap_register((UINT32*)&sharc.r[i].r, (UINT32*)&sharc.reg_alt[i].r); + swap_register((UINT32*)&cpustate->r[i].r, (UINT32*)&cpustate->reg_alt[i].r); } if ((data & 0x400) != (oldreg & 0x400)) { for (i=0; i<8; i++) - swap_register((UINT32*)&sharc.r[i].r, (UINT32*)&sharc.reg_alt[i].r); + swap_register((UINT32*)&cpustate->r[i].r, (UINT32*)&cpustate->reg_alt[i].r); } break; } - default: fatalerror("SHARC: systemreg_latency_op: unknown register %02X at %08X", sharc.systemreg_latency_reg, sharc.pc); + default: fatalerror("SHARC: systemreg_latency_op: unknown register %02X at %08X", cpustate->systemreg_latency_reg, cpustate->pc); } - sharc.systemreg_latency_reg = -1; + cpustate->systemreg_latency_reg = -1; } -static UINT32 GET_UREG(int ureg) +static UINT32 GET_UREG(SHARC_REGS *cpustate, int ureg) { int reg = ureg & 0xf; switch((ureg >> 4) & 0xf) { case 0x0: /* R0 - R15 */ { - return sharc.r[reg].r; + return cpustate->r[reg].r; } case 0x1: { if (reg & 0x8) /* I8 - I15 */ { - return sharc.dag2.i[reg & 0x7]; + return cpustate->dag2.i[reg & 0x7]; } else /* I0 - I7 */ { - return sharc.dag1.i[reg & 0x7]; + return cpustate->dag1.i[reg & 0x7]; } } @@ -292,14 +292,14 @@ static UINT32 GET_UREG(int ureg) { if (reg & 0x8) /* M8 - M15 */ { - INT32 r = sharc.dag2.m[reg & 0x7]; + INT32 r = cpustate->dag2.m[reg & 0x7]; if (r & 0x800000) r |= 0xff000000; return r; } else /* M0 - M7 */ { - return sharc.dag1.m[reg & 0x7]; + return cpustate->dag1.m[reg & 0x7]; } } @@ -307,11 +307,11 @@ static UINT32 GET_UREG(int ureg) { if (reg & 0x8) /* L8 - L15 */ { - return sharc.dag2.l[reg & 0x7]; + return cpustate->dag2.l[reg & 0x7]; } else /* L0 - L7 */ { - return sharc.dag1.l[reg & 0x7]; + return cpustate->dag1.l[reg & 0x7]; } } @@ -319,11 +319,11 @@ static UINT32 GET_UREG(int ureg) { if (reg & 0x8) /* B8 - B15 */ { - return sharc.dag2.b[reg & 0x7]; + return cpustate->dag2.b[reg & 0x7]; } else /* B0 - B7 */ { - return sharc.dag1.b[reg & 0x7]; + return cpustate->dag1.b[reg & 0x7]; } } @@ -331,8 +331,8 @@ static UINT32 GET_UREG(int ureg) { switch(reg) { - case 0x4: return sharc.pcstack[sharc.pcstkp]; /* PCSTK */ - default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, sharc.pc); + case 0x4: return cpustate->pcstack[cpustate->pcstkp]; /* PCSTK */ + default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); } break; } @@ -341,24 +341,24 @@ static UINT32 GET_UREG(int ureg) { switch(reg) { - case 0x0: return sharc.ustat1; /* USTAT1 */ - case 0x1: return sharc.ustat2; /* USTAT2 */ - case 0x9: return sharc.irptl; /* IRPTL */ - case 0xa: return sharc.mode2; /* MODE2 */ - case 0xb: return sharc.mode1; /* MODE1 */ + case 0x0: return cpustate->ustat1; /* USTAT1 */ + case 0x1: return cpustate->ustat2; /* USTAT2 */ + case 0x9: return cpustate->irptl; /* IRPTL */ + case 0xa: return cpustate->mode2; /* MODE2 */ + case 0xb: return cpustate->mode1; /* MODE1 */ case 0xc: /* ASTAT */ { - UINT32 r = sharc.astat; + UINT32 r = cpustate->astat; r &= ~0x00780000; - r |= (sharc.flag[0] << 19); - r |= (sharc.flag[1] << 20); - r |= (sharc.flag[2] << 21); - r |= (sharc.flag[3] << 22); + r |= (cpustate->flag[0] << 19); + r |= (cpustate->flag[1] << 20); + r |= (cpustate->flag[2] << 21); + r |= (cpustate->flag[3] << 22); return r; } - case 0xd: return sharc.imask; /* IMASK */ - case 0xe: return sharc.stky; /* STKY */ - default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, sharc.pc); + case 0xd: return cpustate->imask; /* IMASK */ + case 0xe: return cpustate->stky; /* STKY */ + default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); } break; } @@ -368,57 +368,57 @@ static UINT32 GET_UREG(int ureg) switch(reg) { /* PX needs to be handled separately if the whole 48 bits are needed */ - case 0xb: return (UINT32)(sharc.px); /* PX */ - case 0xc: return (UINT16)(sharc.px); /* PX1 */ - case 0xd: return (UINT32)(sharc.px >> 16); /* PX2 */ - default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, sharc.pc); + case 0xb: return (UINT32)(cpustate->px); /* PX */ + case 0xc: return (UINT16)(cpustate->px); /* PX1 */ + case 0xd: return (UINT32)(cpustate->px >> 16); /* PX2 */ + default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); } break; } - default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, sharc.pc); + default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); } } -static void SET_UREG(int ureg, UINT32 data) +static void SET_UREG(SHARC_REGS *cpustate, int ureg, UINT32 data) { int reg = ureg & 0xf; switch((ureg >> 4) & 0xf) { case 0x0: /* R0 - R15 */ - sharc.r[reg].r = data; + cpustate->r[reg].r = data; break; case 0x1: if (reg & 0x8) /* I8 - I15 */ { - sharc.dag2.i[reg & 0x7] = data; + cpustate->dag2.i[reg & 0x7] = data; } else /* I0 - I7 */ { - sharc.dag1.i[reg & 0x7] = data; + cpustate->dag1.i[reg & 0x7] = data; } break; case 0x2: if (reg & 0x8) /* M8 - M15 */ { - sharc.dag2.m[reg & 0x7] = data; + cpustate->dag2.m[reg & 0x7] = data; } else /* M0 - M7 */ { - sharc.dag1.m[reg & 0x7] = data; + cpustate->dag1.m[reg & 0x7] = data; } break; case 0x3: if (reg & 0x8) /* L8 - L15 */ { - sharc.dag2.l[reg & 0x7] = data; + cpustate->dag2.l[reg & 0x7] = data; } else /* L0 - L7 */ { - sharc.dag1.l[reg & 0x7] = data; + cpustate->dag1.l[reg & 0x7] = data; } break; @@ -426,83 +426,83 @@ static void SET_UREG(int ureg, UINT32 data) // Note: loading B also loads the same value in I if (reg & 0x8) /* B8 - B15 */ { - sharc.dag2.b[reg & 0x7] = data; - sharc.dag2.i[reg & 0x7] = data; + cpustate->dag2.b[reg & 0x7] = data; + cpustate->dag2.i[reg & 0x7] = data; } else /* B0 - B7 */ { - sharc.dag1.b[reg & 0x7] = data; - sharc.dag1.i[reg & 0x7] = data; + cpustate->dag1.b[reg & 0x7] = data; + cpustate->dag1.i[reg & 0x7] = data; } break; case 0x6: switch (reg) { - case 0x5: sharc.pcstkp = data; break; /* PCSTKP */ - case 0x8: sharc.lcntr = data; break; /* LCNTR */ - default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, sharc.pc); + case 0x5: cpustate->pcstkp = data; break; /* PCSTKP */ + case 0x8: cpustate->lcntr = data; break; /* LCNTR */ + default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); } break; case 0x7: /* system regs */ switch(reg) { - case 0x0: sharc.ustat1 = data; break; /* USTAT1 */ - case 0x1: sharc.ustat2 = data; break; /* USTAT2 */ + case 0x0: cpustate->ustat1 = data; break; /* USTAT1 */ + case 0x1: cpustate->ustat2 = data; break; /* USTAT2 */ - case 0x9: sharc.irptl = data; break; /* IRPTL */ - case 0xa: sharc.mode2 = data; break; /* MODE2 */ + case 0x9: cpustate->irptl = data; break; /* IRPTL */ + case 0xa: cpustate->mode2 = data; break; /* MODE2 */ case 0xb: /* MODE1 */ { - add_systemreg_write_latency_effect(reg, data, sharc.mode1); - sharc.mode1 = data; + add_systemreg_write_latency_effect(cpustate, reg, data, cpustate->mode1); + cpustate->mode1 = data; break; } - case 0xc: sharc.astat = data; break; /* ASTAT */ + case 0xc: cpustate->astat = data; break; /* ASTAT */ case 0xd: /* IMASK */ { - check_interrupts(); - sharc.imask = data; + check_interrupts(cpustate); + cpustate->imask = data; break; } - case 0xe: sharc.stky = data; break; /* STKY */ - default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, sharc.pc); + case 0xe: cpustate->stky = data; break; /* STKY */ + default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); } break; case 0xd: switch(reg) { - case 0xc: sharc.px &= U64(0xffffffffffff0000); sharc.px |= (data & 0xffff); break; /* PX1 */ - case 0xd: sharc.px &= U64(0x000000000000ffff); sharc.px |= (UINT64)data << 16; break; /* PX2 */ - default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, sharc.pc); + case 0xc: cpustate->px &= U64(0xffffffffffff0000); cpustate->px |= (data & 0xffff); break; /* PX1 */ + case 0xd: cpustate->px &= U64(0x000000000000ffff); cpustate->px |= (UINT64)data << 16; break; /* PX2 */ + default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); } break; - default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, sharc.pc); + default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); } } /*****************************************************************************/ -#define SET_FLAG_SV_LSHIFT(x, shift) if((x) & ((UINT32)0xffffffff << shift)) sharc.astat |= SV -#define SET_FLAG_SV_RSHIFT(x, shift) if((x) & ((UINT32)0xffffffff >> shift)) sharc.astat |= SV +#define SET_FLAG_SV_LSHIFT(x, shift) if((x) & ((UINT32)0xffffffff << shift)) cpustate->astat |= SV +#define SET_FLAG_SV_RSHIFT(x, shift) if((x) & ((UINT32)0xffffffff >> shift)) cpustate->astat |= SV -#define SET_FLAG_SZ(x) if((x) == 0) sharc.astat |= SZ +#define SET_FLAG_SZ(x) if((x) == 0) cpustate->astat |= SZ #define MAKE_EXTRACT_MASK(start_bit, length) ((0xffffffff << start_bit) & (((UINT32)0xffffffff) >> (32 - (start_bit + length)))) -static void SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx) +static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int rn, int rx) { INT8 shift = data & 0xff; int bit = data & 0x3f; int len = (data >> 6) & 0x3f; - sharc.astat &= ~(SZ|SV|SS); + cpustate->astat &= ~(SZ|SV|SS); switch(shiftop) { @@ -514,7 +514,7 @@ static void SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx) REG(rn) = (shift < 32) ? (REG(rx) << shift) : 0; if (shift > 0) { - sharc.astat |= SV; + cpustate->astat |= SV; } } SET_FLAG_SZ(REG(rn)); @@ -532,7 +532,7 @@ static void SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx) REG(rn) = (shift < 32) ? ((INT32)REG(rx) << shift) : 0; if (shift > 0) { - sharc.astat |= SV; + cpustate->astat |= SV; } } SET_FLAG_SZ(REG(rn)); @@ -566,7 +566,7 @@ static void SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx) r = (shift < 32) ? (REG(rx) << shift) : 0; if (shift > 0) { - sharc.astat |= SV; + cpustate->astat |= SV; } } SET_FLAG_SZ(r); @@ -583,7 +583,7 @@ static void SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx) SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - sharc.astat |= SV; + cpustate->astat |= SV; } break; } @@ -599,7 +599,7 @@ static void SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx) SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - sharc.astat |= SV; + cpustate->astat |= SV; } break; } @@ -615,7 +615,7 @@ static void SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx) SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - sharc.astat |= SV; + cpustate->astat |= SV; } break; } @@ -629,7 +629,7 @@ static void SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx) SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - sharc.astat |= SV; + cpustate->astat |= SV; } break; } @@ -643,7 +643,7 @@ static void SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx) } else { - sharc.astat |= SV; + cpustate->astat |= SV; } SET_FLAG_SZ(REG(rn)); break; @@ -658,7 +658,7 @@ static void SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx) } else { - sharc.astat |= SV; + cpustate->astat |= SV; } SET_FLAG_SZ(REG(rn)); break; @@ -673,7 +673,7 @@ static void SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx) } else { - sharc.astat |= SV; + cpustate->astat |= SV; } SET_FLAG_SZ(REG(rn)); break; @@ -689,18 +689,18 @@ static void SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx) } else { - sharc.astat |= SZ | SV; + cpustate->astat |= SZ | SV; } break; } - default: fatalerror("SHARC: unimplemented shift operation %02X at %08X", shiftop, sharc.pc); + default: fatalerror("SHARC: unimplemented shift operation %02X at %08X", shiftop, cpustate->pc); } } #include "compute.c" -static void COMPUTE(UINT32 opcode) +static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) { int multiop; int op = (opcode >> 12) & 0xff; @@ -724,54 +724,54 @@ static void COMPUTE(UINT32 opcode) multiop = (opcode >> 16) & 0x3f; switch(multiop) { - case 0x00: compute_multi_mr_to_reg(op & 0xf, rn); break; - case 0x01: compute_multi_reg_to_mr(op & 0xf, rn); break; + case 0x00: compute_multi_mr_to_reg(cpustate, op & 0xf, rn); break; + case 0x01: compute_multi_reg_to_mr(cpustate, op & 0xf, rn); break; case 0x04: /* Rm = Rxm * Rym (SSFR), Ra = Rxa + Rya */ { - compute_mul_ssfr_add(fm, fxm, fym, fa, fxa, fya); + compute_mul_ssfr_add(cpustate, fm, fxm, fym, fa, fxa, fya); break; } case 0x05: /* Rm = Rxm * Rym (SSFR), Ra = Rxa - Rya */ { - compute_mul_ssfr_sub(fm, fxm, fym, fa, fxa, fya); + compute_mul_ssfr_sub(cpustate, fm, fxm, fym, fa, fxa, fya); break; } case 0x18: /* Fm = Fxm * Fym, Fa = Fxa + Fya */ { - compute_fmul_fadd(fm, fxm, fym, fa, fxa, fya); + compute_fmul_fadd(cpustate, fm, fxm, fym, fa, fxa, fya); break; } case 0x19: /* Fm = Fxm * Fym, Fa = Fxa - Fya */ { - compute_fmul_fsub(fm, fxm, fym, fa, fxa, fya); + compute_fmul_fsub(cpustate, fm, fxm, fym, fa, fxa, fya); break; } case 0x1a: /* Fm = Fxm * Fym, Fa = FLOAT Fxa BY Fya */ { - compute_fmul_float_scaled(fm, fxm, fym, fa, fxa, fya); + compute_fmul_float_scaled(cpustate, fm, fxm, fym, fa, fxa, fya); break; } case 0x1b: /* Fm = Fxm * Fym, Fa = FIX Fxa BY Fya */ { - compute_fmul_fix_scaled(fm, fxm, fym, fa, fxa, fya); + compute_fmul_fix_scaled(cpustate, fm, fxm, fym, fa, fxa, fya); break; } case 0x1e: /* Fm = Fxm * Fym, Fa = MAX(Fxa, Fya) */ { - compute_fmul_fmax(fm, fxm, fym, fa, fxa, fya); + compute_fmul_fmax(cpustate, fm, fxm, fym, fa, fxa, fya); break; } case 0x1f: /* Fm = Fxm * Fym, Fa = MIN(Fxa, Fya) */ { - compute_fmul_fmin(fm, fxm, fym, fa, fxa, fya); + compute_fmul_fmin(cpustate, fm, fxm, fym, fa, fxa, fya); break; } @@ -781,12 +781,12 @@ static void COMPUTE(UINT32 opcode) /* Parallel Multiplier & Dual Add/Subtract */ /* Floating-point */ int fs = (opcode >> 16) & 0xf; - compute_fmul_dual_fadd_fsub(fm, fxm, fym, fa, fs, fxa, fya); + compute_fmul_dual_fadd_fsub(cpustate, fm, fxm, fym, fa, fs, fxa, fya); break; } default: - fatalerror("SHARC: compute: multi-function opcode %02X not implemented ! (%08X, %08X)", multiop, sharc.pc, opcode); + fatalerror("SHARC: compute: multi-function opcode %02X not implemented ! (%08X, %08X)", multiop, cpustate->pc, opcode); break; } } @@ -799,39 +799,39 @@ static void COMPUTE(UINT32 opcode) { switch(op) { - case 0x01: compute_add(rn, rx, ry); break; - case 0x02: compute_sub(rn, rx, ry); break; - case 0x05: compute_add_ci(rn, rx, ry); break; - case 0x06: compute_sub_ci(rn, rx, ry); break; - case 0x0a: compute_comp(rx, ry); break; - case 0x21: compute_pass(rn, rx); break; - case 0x22: compute_neg(rn, rx); break; - case 0x29: compute_inc(rn, rx); break; - case 0x2a: compute_dec(rn, rx); break; - case 0x40: compute_and(rn, rx, ry); break; - case 0x41: compute_or(rn, rx, ry); break; - case 0x42: compute_xor(rn, rx, ry); break; - case 0x43: compute_not(rn, rx); break; - case 0x61: compute_min(rn, rx, ry); break; - case 0x62: compute_max(rn, rx, ry); break; - case 0x81: compute_fadd(rn, rx, ry); break; - case 0x82: compute_fsub(rn, rx, ry); break; - case 0x8a: compute_fcomp(rx, ry); break; - case 0x91: compute_fabs_plus(rn, rx, ry); break; - case 0xa1: compute_fpass(rn, rx); break; - case 0xa2: compute_fneg(rn, rx); break; - case 0xb0: compute_fabs(rn, rx); break; - case 0xbd: compute_scalb(rn, rx, ry); break; - case 0xc1: compute_logb(rn, rx); break; - case 0xc4: compute_recips(rn, rx); break; - case 0xc5: compute_rsqrts(rn, rx); break; - case 0xc9: compute_fix(rn, rx); break; - case 0xca: compute_float(rn, rx); break; - case 0xd9: compute_fix_scaled(rn, rx, ry); break; - case 0xda: compute_float_scaled(rn, rx, ry); break; - case 0xe1: compute_fmin(rn, rx, ry); break; - case 0xe2: compute_fmax(rn, rx, ry); break; - case 0xe3: compute_fclip(rn, rx, ry); break; + case 0x01: compute_add(cpustate, rn, rx, ry); break; + case 0x02: compute_sub(cpustate, rn, rx, ry); break; + case 0x05: compute_add_ci(cpustate, rn, rx, ry); break; + case 0x06: compute_sub_ci(cpustate, rn, rx, ry); break; + case 0x0a: compute_comp(cpustate, rx, ry); break; + case 0x21: compute_pass(cpustate, rn, rx); break; + case 0x22: compute_neg(cpustate, rn, rx); break; + case 0x29: compute_inc(cpustate, rn, rx); break; + case 0x2a: compute_dec(cpustate, rn, rx); break; + case 0x40: compute_and(cpustate, rn, rx, ry); break; + case 0x41: compute_or(cpustate, rn, rx, ry); break; + case 0x42: compute_xor(cpustate, rn, rx, ry); break; + case 0x43: compute_not(cpustate, rn, rx); break; + case 0x61: compute_min(cpustate, rn, rx, ry); break; + case 0x62: compute_max(cpustate, rn, rx, ry); break; + case 0x81: compute_fadd(cpustate, rn, rx, ry); break; + case 0x82: compute_fsub(cpustate, rn, rx, ry); break; + case 0x8a: compute_fcomp(cpustate, rx, ry); break; + case 0x91: compute_fabs_plus(cpustate, rn, rx, ry); break; + case 0xa1: compute_fpass(cpustate, rn, rx); break; + case 0xa2: compute_fneg(cpustate, rn, rx); break; + case 0xb0: compute_fabs(cpustate, rn, rx); break; + case 0xbd: compute_scalb(cpustate, rn, rx, ry); break; + case 0xc1: compute_logb(cpustate, rn, rx); break; + case 0xc4: compute_recips(cpustate, rn, rx); break; + case 0xc5: compute_rsqrts(cpustate, rn, rx); break; + case 0xc9: compute_fix(cpustate, rn, rx); break; + case 0xca: compute_float(cpustate, rn, rx); break; + case 0xd9: compute_fix_scaled(cpustate, rn, rx, ry); break; + case 0xda: compute_float_scaled(cpustate, rn, rx, ry); break; + case 0xe1: compute_fmin(cpustate, rn, rx, ry); break; + case 0xe2: compute_fmax(cpustate, rn, rx, ry); break; + case 0xe3: compute_fclip(cpustate, rn, rx, ry); break; case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77: case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: @@ -839,7 +839,7 @@ static void COMPUTE(UINT32 opcode) /* Fixed-point Dual Add/Subtract */ int rs = (opcode >> 12) & 0xf; int ra = (opcode >> 8) & 0xf; - compute_dual_add_sub(ra, rs, rx, ry); + compute_dual_add_sub(cpustate, ra, rs, rx, ry); break; } @@ -849,11 +849,11 @@ static void COMPUTE(UINT32 opcode) /* Floating-point Dual Add/Subtract */ int rs = (opcode >> 12) & 0xf; int ra = (opcode >> 8) & 0xf; - compute_dual_fadd_fsub(ra, rs, rx, ry); + compute_dual_fadd_fsub(cpustate, ra, rs, rx, ry); break; } - default: fatalerror("SHARC: compute: unimplemented ALU operation %02X (%08X, %08X)", op, sharc.pc, opcode); + default: fatalerror("SHARC: compute: unimplemented ALU operation %02X (%08X, %08X)", op, cpustate->pc, opcode); } break; } @@ -864,18 +864,18 @@ static void COMPUTE(UINT32 opcode) { switch(op) { - case 0x14: sharc.mrf = 0; break; - case 0x16: sharc.mrb = 0; break; + case 0x14: cpustate->mrf = 0; break; + case 0x16: cpustate->mrb = 0; break; - case 0x30: compute_fmul(rn, rx, ry); break; - case 0x40: compute_mul_uuin(rn, rx, ry); break; - case 0x70: compute_mul_ssin(rn, rx, ry); break; + case 0x30: compute_fmul(cpustate, rn, rx, ry); break; + case 0x40: compute_mul_uuin(cpustate, rn, rx, ry); break; + case 0x70: compute_mul_ssin(cpustate, rn, rx, ry); break; - case 0xb0: REG(rn) = compute_mrf_plus_mul_ssin(rx, ry); break; - case 0xb2: REG(rn) = compute_mrb_plus_mul_ssin(rx, ry); break; + case 0xb0: REG(rn) = compute_mrf_plus_mul_ssin(cpustate, rx, ry); break; + case 0xb2: REG(rn) = compute_mrb_plus_mul_ssin(cpustate, rx, ry); break; default: - fatalerror("SHARC: compute: multiplier operation %02X not implemented ! (%08X, %08X)", op, sharc.pc, opcode); + fatalerror("SHARC: compute: multiplier operation %02X not implemented ! (%08X, %08X)", op, cpustate->pc, opcode); break; } break; @@ -885,7 +885,7 @@ static void COMPUTE(UINT32 opcode) /* Shifter operations */ case 2: { - sharc.astat &= ~(SZ|SV|SS); + cpustate->astat &= ~(SZ|SV|SS); op >>= 2; switch(op) @@ -902,7 +902,7 @@ static void COMPUTE(UINT32 opcode) REG(rn) = (shift < 32) ? (REG(rx) << shift) : 0; if (shift > 0) { - sharc.astat |= SV; + cpustate->astat |= SV; } } SET_FLAG_SZ(REG(rn)); @@ -925,7 +925,7 @@ static void COMPUTE(UINT32 opcode) (((UINT32)REG(rx) >> (32-s)) & ((UINT32)(0xffffffff) >> (32-s))); if (shift > 0) { - sharc.astat |= SV; + cpustate->astat |= SV; } } SET_FLAG_SZ(REG(rn)); @@ -941,7 +941,7 @@ static void COMPUTE(UINT32 opcode) REG(rn) = REG(rn) | ((shift < 32) ? (REG(rx) << shift) : 0); if (shift > 0) { - sharc.astat |= SV; + cpustate->astat |= SV; } } SET_FLAG_SZ(REG(rn)); @@ -958,7 +958,7 @@ static void COMPUTE(UINT32 opcode) SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - sharc.astat |= SV; + cpustate->astat |= SV; } break; } @@ -976,7 +976,7 @@ static void COMPUTE(UINT32 opcode) SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - sharc.astat |= SV; + cpustate->astat |= SV; } break; } @@ -992,7 +992,7 @@ static void COMPUTE(UINT32 opcode) SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - sharc.astat |= SV; + cpustate->astat |= SV; } break; } @@ -1007,7 +1007,7 @@ static void COMPUTE(UINT32 opcode) } else { - sharc.astat |= SV; + cpustate->astat |= SV; } SET_FLAG_SZ(REG(rn)); break; @@ -1023,7 +1023,7 @@ static void COMPUTE(UINT32 opcode) } else { - sharc.astat |= SV; + cpustate->astat |= SV; } SET_FLAG_SZ(REG(rn)); break; @@ -1040,13 +1040,13 @@ static void COMPUTE(UINT32 opcode) } else { - sharc.astat |= SZ | SV; + cpustate->astat |= SZ | SV; } break; } default: - fatalerror("SHARC: compute: shift operation %02X not implemented ! (%08X, %08X)", op, sharc.pc, opcode); + fatalerror("SHARC: compute: shift operation %02X not implemented ! (%08X, %08X)", op, cpustate->pc, opcode); } break; } @@ -1057,216 +1057,216 @@ static void COMPUTE(UINT32 opcode) } } -INLINE void PUSH_PC(UINT32 pc) +INLINE void PUSH_PC(SHARC_REGS *cpustate, UINT32 pc) { - sharc.pcstkp++; - if(sharc.pcstkp >= 32) + cpustate->pcstkp++; + if(cpustate->pcstkp >= 32) { fatalerror("SHARC: PC Stack overflow !"); } - if (sharc.pcstkp == 0) + if (cpustate->pcstkp == 0) { - sharc.stky |= 0x400000; + cpustate->stky |= 0x400000; } else { - sharc.stky &= ~0x400000; + cpustate->stky &= ~0x400000; } - sharc.pcstk = pc; - sharc.pcstack[sharc.pcstkp] = pc; + cpustate->pcstk = pc; + cpustate->pcstack[cpustate->pcstkp] = pc; } -INLINE UINT32 POP_PC(void) +INLINE UINT32 POP_PC(SHARC_REGS *cpustate) { - sharc.pcstk = sharc.pcstack[sharc.pcstkp]; + cpustate->pcstk = cpustate->pcstack[cpustate->pcstkp]; - if(sharc.pcstkp == 0) + if(cpustate->pcstkp == 0) { fatalerror("SHARC: PC Stack underflow !"); } - sharc.pcstkp--; + cpustate->pcstkp--; - if (sharc.pcstkp == 0) + if (cpustate->pcstkp == 0) { - sharc.stky |= 0x400000; + cpustate->stky |= 0x400000; } else { - sharc.stky &= ~0x400000; + cpustate->stky &= ~0x400000; } - return sharc.pcstk; + return cpustate->pcstk; } -INLINE UINT32 TOP_PC(void) +INLINE UINT32 TOP_PC(SHARC_REGS *cpustate) { - return sharc.pcstack[sharc.pcstkp]; + return cpustate->pcstack[cpustate->pcstkp]; } -INLINE void PUSH_LOOP(UINT32 pc, UINT32 count) +INLINE void PUSH_LOOP(SHARC_REGS *cpustate, UINT32 pc, UINT32 count) { - sharc.lstkp++; - if(sharc.lstkp >= 6) + cpustate->lstkp++; + if(cpustate->lstkp >= 6) { fatalerror("SHARC: Loop Stack overflow !"); } - if (sharc.lstkp == 0) + if (cpustate->lstkp == 0) { - sharc.stky |= 0x4000000; + cpustate->stky |= 0x4000000; } else { - sharc.stky &= ~0x4000000; + cpustate->stky &= ~0x4000000; } - sharc.lcstack[sharc.lstkp] = count; - sharc.lastack[sharc.lstkp] = pc; - sharc.curlcntr = count; - sharc.laddr = pc; + cpustate->lcstack[cpustate->lstkp] = count; + cpustate->lastack[cpustate->lstkp] = pc; + cpustate->curlcntr = count; + cpustate->laddr = pc; } -INLINE void POP_LOOP(void) +INLINE void POP_LOOP(SHARC_REGS *cpustate) { - if(sharc.lstkp == 0) + if(cpustate->lstkp == 0) { fatalerror("SHARC: Loop Stack underflow !"); } - sharc.lstkp--; + cpustate->lstkp--; - if (sharc.lstkp == 0) + if (cpustate->lstkp == 0) { - sharc.stky |= 0x4000000; + cpustate->stky |= 0x4000000; } else { - sharc.stky &= ~0x4000000; + cpustate->stky &= ~0x4000000; } - sharc.curlcntr = sharc.lcstack[sharc.lstkp]; - sharc.laddr = sharc.lastack[sharc.lstkp]; + cpustate->curlcntr = cpustate->lcstack[cpustate->lstkp]; + cpustate->laddr = cpustate->lastack[cpustate->lstkp]; } -INLINE void PUSH_STATUS_STACK(void) +INLINE void PUSH_STATUS_STACK(SHARC_REGS *cpustate) { - sharc.status_stkp++; - if (sharc.status_stkp >= 5) + cpustate->status_stkp++; + if (cpustate->status_stkp >= 5) { fatalerror("SHARC: Status stack overflow !"); } - if (sharc.status_stkp == 0) + if (cpustate->status_stkp == 0) { - sharc.stky |= 0x1000000; + cpustate->stky |= 0x1000000; } else { - sharc.stky &= ~0x1000000; + cpustate->stky &= ~0x1000000; } - sharc.status_stack[sharc.status_stkp].mode1 = GET_UREG(REG_MODE1); - sharc.status_stack[sharc.status_stkp].astat = GET_UREG(REG_ASTAT); + cpustate->status_stack[cpustate->status_stkp].mode1 = GET_UREG(cpustate, REG_MODE1); + cpustate->status_stack[cpustate->status_stkp].astat = GET_UREG(cpustate, REG_ASTAT); } -INLINE void POP_STATUS_STACK(void) +INLINE void POP_STATUS_STACK(SHARC_REGS *cpustate) { - SET_UREG(REG_MODE1, sharc.status_stack[sharc.status_stkp].mode1); - SET_UREG(REG_ASTAT, sharc.status_stack[sharc.status_stkp].astat); + SET_UREG(cpustate, REG_MODE1, cpustate->status_stack[cpustate->status_stkp].mode1); + SET_UREG(cpustate, REG_ASTAT, cpustate->status_stack[cpustate->status_stkp].astat); - sharc.status_stkp--; - if (sharc.status_stkp < 0) + cpustate->status_stkp--; + if (cpustate->status_stkp < 0) { fatalerror("SHARC: Status stack underflow !"); } - if (sharc.status_stkp == 0) + if (cpustate->status_stkp == 0) { - sharc.stky |= 0x1000000; + cpustate->stky |= 0x1000000; } else { - sharc.stky &= ~0x1000000; + cpustate->stky &= ~0x1000000; } } -INLINE int IF_CONDITION_CODE(int cond) +INLINE int IF_CONDITION_CODE(SHARC_REGS *cpustate, int cond) { switch(cond) { - case 0x00: return sharc.astat & AZ; /* EQ */ - case 0x01: return !(sharc.astat & AZ) && (sharc.astat & AN); /* LT */ - case 0x02: return (sharc.astat & AZ) || (sharc.astat & AN); /* LE */ - case 0x03: return (sharc.astat & AC); /* AC */ - case 0x04: return (sharc.astat & AV); /* AV */ - case 0x05: return (sharc.astat & MV); /* MV */ - case 0x06: return (sharc.astat & MN); /* MS */ - case 0x07: return (sharc.astat & SV); /* SV */ - case 0x08: return (sharc.astat & SZ); /* SZ */ - case 0x09: return (sharc.flag[0] != 0); /* FLAG0 */ - case 0x0a: return (sharc.flag[1] != 0); /* FLAG1 */ - case 0x0b: return (sharc.flag[2] != 0); /* FLAG2 */ - case 0x0c: return (sharc.flag[3] != 0); /* FLAG3 */ - case 0x0d: return (sharc.astat & BTF); /* TF */ + case 0x00: return cpustate->astat & AZ; /* EQ */ + case 0x01: return !(cpustate->astat & AZ) && (cpustate->astat & AN); /* LT */ + case 0x02: return (cpustate->astat & AZ) || (cpustate->astat & AN); /* LE */ + case 0x03: return (cpustate->astat & AC); /* AC */ + case 0x04: return (cpustate->astat & AV); /* AV */ + case 0x05: return (cpustate->astat & MV); /* MV */ + case 0x06: return (cpustate->astat & MN); /* MS */ + case 0x07: return (cpustate->astat & SV); /* SV */ + case 0x08: return (cpustate->astat & SZ); /* SZ */ + case 0x09: return (cpustate->flag[0] != 0); /* FLAG0 */ + case 0x0a: return (cpustate->flag[1] != 0); /* FLAG1 */ + case 0x0b: return (cpustate->flag[2] != 0); /* FLAG2 */ + case 0x0c: return (cpustate->flag[3] != 0); /* FLAG3 */ + case 0x0d: return (cpustate->astat & BTF); /* TF */ case 0x0e: return 0; /* BM */ - case 0x0f: return (sharc.curlcntr!=1); /* NOT LCE */ - case 0x10: return !(sharc.astat & AZ); /* NOT EQUAL */ - case 0x11: return (sharc.astat & AZ) || !(sharc.astat & AN); /* GE */ - case 0x12: return !(sharc.astat & AZ) && !(sharc.astat & AN); /* GT */ - case 0x13: return !(sharc.astat & AC); /* NOT AC */ - case 0x14: return !(sharc.astat & AV); /* NOT AV */ - case 0x15: return !(sharc.astat & MV); /* NOT MV */ - case 0x16: return !(sharc.astat & MN); /* NOT MS */ - case 0x17: return !(sharc.astat & SV); /* NOT SV */ - case 0x18: return !(sharc.astat & SZ); /* NOT SZ */ - case 0x19: return (sharc.flag[0] == 0); /* NOT FLAG0 */ - case 0x1a: return (sharc.flag[1] == 0); /* NOT FLAG1 */ - case 0x1b: return (sharc.flag[2] == 0); /* NOT FLAG2 */ - case 0x1c: return (sharc.flag[3] == 0); /* NOT FLAG3 */ - case 0x1d: return !(sharc.astat & BTF); /* NOT TF */ + case 0x0f: return (cpustate->curlcntr!=1); /* NOT LCE */ + case 0x10: return !(cpustate->astat & AZ); /* NOT EQUAL */ + case 0x11: return (cpustate->astat & AZ) || !(cpustate->astat & AN); /* GE */ + case 0x12: return !(cpustate->astat & AZ) && !(cpustate->astat & AN); /* GT */ + case 0x13: return !(cpustate->astat & AC); /* NOT AC */ + case 0x14: return !(cpustate->astat & AV); /* NOT AV */ + case 0x15: return !(cpustate->astat & MV); /* NOT MV */ + case 0x16: return !(cpustate->astat & MN); /* NOT MS */ + case 0x17: return !(cpustate->astat & SV); /* NOT SV */ + case 0x18: return !(cpustate->astat & SZ); /* NOT SZ */ + case 0x19: return (cpustate->flag[0] == 0); /* NOT FLAG0 */ + case 0x1a: return (cpustate->flag[1] == 0); /* NOT FLAG1 */ + case 0x1b: return (cpustate->flag[2] == 0); /* NOT FLAG2 */ + case 0x1c: return (cpustate->flag[3] == 0); /* NOT FLAG3 */ + case 0x1d: return !(cpustate->astat & BTF); /* NOT TF */ case 0x1e: return 1; /* NOT BM */ case 0x1f: return 1; /* TRUE */ } return 1; } -INLINE int DO_CONDITION_CODE(int cond) +INLINE int DO_CONDITION_CODE(SHARC_REGS *cpustate, int cond) { switch(cond) { - case 0x00: return sharc.astat & AZ; /* EQ */ - case 0x01: return !(sharc.astat & AZ) && (sharc.astat & AN); /* LT */ - case 0x02: return (sharc.astat & AZ) || (sharc.astat & AN); /* LE */ - case 0x03: return (sharc.astat & AC); /* AC */ - case 0x04: return (sharc.astat & AV); /* AV */ - case 0x05: return (sharc.astat & MV); /* MV */ - case 0x06: return (sharc.astat & MN); /* MS */ - case 0x07: return (sharc.astat & SV); /* SV */ - case 0x08: return (sharc.astat & SZ); /* SZ */ - case 0x09: return (sharc.flag[0] != 0); /* FLAG0 */ - case 0x0a: return (sharc.flag[1] != 0); /* FLAG1 */ - case 0x0b: return (sharc.flag[2] != 0); /* FLAG2 */ - case 0x0c: return (sharc.flag[3] != 0); /* FLAG3 */ - case 0x0d: return (sharc.astat & BTF); /* TF */ + case 0x00: return cpustate->astat & AZ; /* EQ */ + case 0x01: return !(cpustate->astat & AZ) && (cpustate->astat & AN); /* LT */ + case 0x02: return (cpustate->astat & AZ) || (cpustate->astat & AN); /* LE */ + case 0x03: return (cpustate->astat & AC); /* AC */ + case 0x04: return (cpustate->astat & AV); /* AV */ + case 0x05: return (cpustate->astat & MV); /* MV */ + case 0x06: return (cpustate->astat & MN); /* MS */ + case 0x07: return (cpustate->astat & SV); /* SV */ + case 0x08: return (cpustate->astat & SZ); /* SZ */ + case 0x09: return (cpustate->flag[0] != 0); /* FLAG0 */ + case 0x0a: return (cpustate->flag[1] != 0); /* FLAG1 */ + case 0x0b: return (cpustate->flag[2] != 0); /* FLAG2 */ + case 0x0c: return (cpustate->flag[3] != 0); /* FLAG3 */ + case 0x0d: return (cpustate->astat & BTF); /* TF */ case 0x0e: return 0; /* BM */ - case 0x0f: return (sharc.curlcntr==1); /* LCE */ - case 0x10: return !(sharc.astat & AZ); /* NOT EQUAL */ - case 0x11: return (sharc.astat & AZ) || !(sharc.astat & AN); /* GE */ - case 0x12: return !(sharc.astat & AZ) && !(sharc.astat & AN); /* GT */ - case 0x13: return !(sharc.astat & AC); /* NOT AC */ - case 0x14: return !(sharc.astat & AV); /* NOT AV */ - case 0x15: return !(sharc.astat & MV); /* NOT MV */ - case 0x16: return !(sharc.astat & MN); /* NOT MS */ - case 0x17: return !(sharc.astat & SV); /* NOT SV */ - case 0x18: return !(sharc.astat & SZ); /* NOT SZ */ - case 0x19: return (sharc.flag[0] == 0); /* NOT FLAG0 */ - case 0x1a: return (sharc.flag[1] == 0); /* NOT FLAG1 */ - case 0x1b: return (sharc.flag[2] == 0); /* NOT FLAG2 */ - case 0x1c: return (sharc.flag[3] == 0); /* NOT FLAG3 */ - case 0x1d: return !(sharc.astat & BTF); /* NOT TF */ + case 0x0f: return (cpustate->curlcntr==1); /* LCE */ + case 0x10: return !(cpustate->astat & AZ); /* NOT EQUAL */ + case 0x11: return (cpustate->astat & AZ) || !(cpustate->astat & AN); /* GE */ + case 0x12: return !(cpustate->astat & AZ) && !(cpustate->astat & AN); /* GT */ + case 0x13: return !(cpustate->astat & AC); /* NOT AC */ + case 0x14: return !(cpustate->astat & AV); /* NOT AV */ + case 0x15: return !(cpustate->astat & MV); /* NOT MV */ + case 0x16: return !(cpustate->astat & MN); /* NOT MS */ + case 0x17: return !(cpustate->astat & SV); /* NOT SV */ + case 0x18: return !(cpustate->astat & SZ); /* NOT SZ */ + case 0x19: return (cpustate->flag[0] == 0); /* NOT FLAG0 */ + case 0x1a: return (cpustate->flag[1] == 0); /* NOT FLAG1 */ + case 0x1b: return (cpustate->flag[2] == 0); /* NOT FLAG2 */ + case 0x1c: return (cpustate->flag[3] == 0); /* NOT FLAG3 */ + case 0x1d: return !(cpustate->astat & BTF); /* NOT TF */ case 0x1e: return 1; /* NOT BM */ case 0x1f: return 0; /* FALSE (FOREVER) */ } @@ -1277,17 +1277,17 @@ INLINE int DO_CONDITION_CODE(int cond) /* | 001xxxxxx | */ /* compute / dreg <-> DM / dreg <-> PM */ -static void sharcop_compute_dreg_dm_dreg_pm(void) +static void sharcop_compute_dreg_dm_dreg_pm(SHARC_REGS *cpustate) { - int pm_dreg = (sharc.opcode >> 23) & 0xf; - int pmm = (sharc.opcode >> 27) & 0x7; - int pmi = (sharc.opcode >> 30) & 0x7; - int dm_dreg = (sharc.opcode >> 33) & 0xf; - int dmm = (sharc.opcode >> 38) & 0x7; - int dmi = (sharc.opcode >> 41) & 0x7; - int pmd = (sharc.opcode >> 37) & 0x1; - int dmd = (sharc.opcode >> 44) & 0x1; - int compute = sharc.opcode & 0x7fffff; + int pm_dreg = (cpustate->opcode >> 23) & 0xf; + int pmm = (cpustate->opcode >> 27) & 0x7; + int pmi = (cpustate->opcode >> 30) & 0x7; + int dm_dreg = (cpustate->opcode >> 33) & 0xf; + int dmm = (cpustate->opcode >> 38) & 0x7; + int dmi = (cpustate->opcode >> 41) & 0x7; + int pmd = (cpustate->opcode >> 37) & 0x1; + int dmd = (cpustate->opcode >> 44) & 0x1; + int compute = cpustate->opcode & 0x7fffff; /* due to parallelity issues, source DREGs must be saved */ /* because the compute operation may change them */ @@ -1296,31 +1296,31 @@ static void sharcop_compute_dreg_dm_dreg_pm(void) if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (pmd) // dreg -> PM { - pm_write32(PM_REG_I(pmi), parallel_pm_dreg); + pm_write32(cpustate, PM_REG_I(pmi), parallel_pm_dreg); PM_REG_I(pmi) += PM_REG_M(pmm); UPDATE_CIRCULAR_BUFFER_PM(pmi); } else // PM -> dreg { - REG(pm_dreg) = pm_read32(PM_REG_I(pmi)); + REG(pm_dreg) = pm_read32(cpustate, PM_REG_I(pmi)); PM_REG_I(pmi) += PM_REG_M(pmm); UPDATE_CIRCULAR_BUFFER_PM(pmi); } if (dmd) // dreg -> DM { - dm_write32(DM_REG_I(dmi), parallel_dm_dreg); + dm_write32(cpustate, DM_REG_I(dmi), parallel_dm_dreg); DM_REG_I(dmi) += DM_REG_M(dmm); UPDATE_CIRCULAR_BUFFER_DM(dmi); } else // DM -> dreg { - REG(dm_dreg) = dm_read32(DM_REG_I(dmi)); + REG(dm_dreg) = dm_read32(cpustate, DM_REG_I(dmi)); DM_REG_I(dmi) += DM_REG_M(dmm); UPDATE_CIRCULAR_BUFFER_DM(dmi); } @@ -1330,14 +1330,14 @@ static void sharcop_compute_dreg_dm_dreg_pm(void) /* | 00000001x | */ /* compute */ -static void sharcop_compute(void) +static void sharcop_compute(SHARC_REGS *cpustate) { - int cond = (sharc.opcode >> 33) & 0x1f; - int compute = sharc.opcode & 0x7fffff; + int cond = (cpustate->opcode >> 33) & 0x1f; + int compute = cpustate->opcode & 0x7fffff; - if (IF_CONDITION_CODE(cond) && compute != 0) + if (IF_CONDITION_CODE(cpustate, cond) && compute != 0) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } } @@ -1345,25 +1345,25 @@ static void sharcop_compute(void) /* | 010xxxxxx | */ /* compute / ureg <-> DM|PM, pre-modify */ -static void sharcop_compute_ureg_dmpm_premod(void) +static void sharcop_compute_ureg_dmpm_premod(SHARC_REGS *cpustate) { - int i = (sharc.opcode >> 41) & 0x7; - int m = (sharc.opcode >> 38) & 0x7; - int cond = (sharc.opcode >> 33) & 0x1f; - int g = (sharc.opcode >> 32) & 0x1; - int d = (sharc.opcode >> 31) & 0x1; - int ureg = (sharc.opcode >> 23) & 0xff; - int compute = sharc.opcode & 0x7fffff; + int i = (cpustate->opcode >> 41) & 0x7; + int m = (cpustate->opcode >> 38) & 0x7; + int cond = (cpustate->opcode >> 33) & 0x1f; + int g = (cpustate->opcode >> 32) & 0x1; + int d = (cpustate->opcode >> 31) & 0x1; + int ureg = (cpustate->opcode >> 23) & 0xff; + int compute = cpustate->opcode & 0x7fffff; - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { /* due to parallelity issues, source UREG must be saved */ /* because the compute operation may change it */ - UINT32 parallel_ureg = GET_UREG(ureg); + UINT32 parallel_ureg = GET_UREG(cpustate, ureg); if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (g) /* PM */ @@ -1372,22 +1372,22 @@ static void sharcop_compute_ureg_dmpm_premod(void) { if (ureg == 0xdb) /* PX register access is always 48-bit */ { - pm_write48(PM_REG_I(i)+PM_REG_M(m), sharc.px); + pm_write48(cpustate, PM_REG_I(i)+PM_REG_M(m), cpustate->px); } else { - pm_write32(PM_REG_I(i)+PM_REG_M(m), parallel_ureg); + pm_write32(cpustate, PM_REG_I(i)+PM_REG_M(m), parallel_ureg); } } else /* PM <- ureg */ { if (ureg == 0xdb) /* PX register access is always 48-bit */ { - sharc.px = pm_read48(PM_REG_I(i)+PM_REG_M(m)); + cpustate->px = pm_read48(cpustate, PM_REG_I(i)+PM_REG_M(m)); } else { - SET_UREG(ureg, pm_read32(PM_REG_I(i)+PM_REG_M(m))); + SET_UREG(cpustate, ureg, pm_read32(cpustate, PM_REG_I(i)+PM_REG_M(m))); } } } @@ -1395,36 +1395,36 @@ static void sharcop_compute_ureg_dmpm_premod(void) { if (d) /* ureg -> DM */ { - dm_write32(DM_REG_I(i)+DM_REG_M(m), parallel_ureg); + dm_write32(cpustate, DM_REG_I(i)+DM_REG_M(m), parallel_ureg); } else /* DM <- ureg */ { - SET_UREG(ureg, dm_read32(DM_REG_I(i)+DM_REG_M(m))); + SET_UREG(cpustate, ureg, dm_read32(cpustate, DM_REG_I(i)+DM_REG_M(m))); } } } } /* compute / ureg <-> DM|PM, post-modify */ -static void sharcop_compute_ureg_dmpm_postmod(void) +static void sharcop_compute_ureg_dmpm_postmod(SHARC_REGS *cpustate) { - int i = (sharc.opcode >> 41) & 0x7; - int m = (sharc.opcode >> 38) & 0x7; - int cond = (sharc.opcode >> 33) & 0x1f; - int g = (sharc.opcode >> 32) & 0x1; - int d = (sharc.opcode >> 31) & 0x1; - int ureg = (sharc.opcode >> 23) & 0xff; - int compute = sharc.opcode & 0x7fffff; + int i = (cpustate->opcode >> 41) & 0x7; + int m = (cpustate->opcode >> 38) & 0x7; + int cond = (cpustate->opcode >> 33) & 0x1f; + int g = (cpustate->opcode >> 32) & 0x1; + int d = (cpustate->opcode >> 31) & 0x1; + int ureg = (cpustate->opcode >> 23) & 0xff; + int compute = cpustate->opcode & 0x7fffff; - if(IF_CONDITION_CODE(cond)) + if(IF_CONDITION_CODE(cpustate, cond)) { /* due to parallelity issues, source UREG must be saved */ /* because the compute operation may change it */ - UINT32 parallel_ureg = GET_UREG(ureg); + UINT32 parallel_ureg = GET_UREG(cpustate, ureg); if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (g) /* PM */ @@ -1433,11 +1433,11 @@ static void sharcop_compute_ureg_dmpm_postmod(void) { if (ureg == 0xdb) /* PX register access is always 48-bit */ { - pm_write48(PM_REG_I(i), sharc.px); + pm_write48(cpustate, PM_REG_I(i), cpustate->px); } else { - pm_write32(PM_REG_I(i), parallel_ureg); + pm_write32(cpustate, PM_REG_I(i), parallel_ureg); } PM_REG_I(i) += PM_REG_M(m); UPDATE_CIRCULAR_BUFFER_PM(i); @@ -1446,11 +1446,11 @@ static void sharcop_compute_ureg_dmpm_postmod(void) { if (ureg == 0xdb) /* PX register access is always 48-bit */ { - sharc.px = pm_read48(PM_REG_I(i)); + cpustate->px = pm_read48(cpustate, PM_REG_I(i)); } else { - SET_UREG(ureg, pm_read32(PM_REG_I(i))); + SET_UREG(cpustate, ureg, pm_read32(cpustate, PM_REG_I(i))); } PM_REG_I(i) += PM_REG_M(m); UPDATE_CIRCULAR_BUFFER_PM(i); @@ -1460,13 +1460,13 @@ static void sharcop_compute_ureg_dmpm_postmod(void) { if (d) /* ureg -> DM */ { - dm_write32(DM_REG_I(i), parallel_ureg); + dm_write32(cpustate, DM_REG_I(i), parallel_ureg); DM_REG_I(i) += DM_REG_M(m); UPDATE_CIRCULAR_BUFFER_DM(i); } else /* DM <- ureg */ { - SET_UREG(ureg, dm_read32(DM_REG_I(i))); + SET_UREG(cpustate, ureg, dm_read32(cpustate, DM_REG_I(i))); DM_REG_I(i) += DM_REG_M(m); UPDATE_CIRCULAR_BUFFER_DM(i); } @@ -1478,129 +1478,129 @@ static void sharcop_compute_ureg_dmpm_postmod(void) /* | 0110xxxxx | */ /* compute / dreg <- DM, immediate modify */ -static void sharcop_compute_dm_to_dreg_immmod(void) +static void sharcop_compute_dm_to_dreg_immmod(SHARC_REGS *cpustate) { - int cond = (sharc.opcode >> 33) & 0x1f; - int u = (sharc.opcode >> 38) & 0x1; - int dreg = (sharc.opcode >> 23) & 0xf; - int i = (sharc.opcode >> 41) & 0x7; - int mod = SIGN_EXTEND6((sharc.opcode >> 27) & 0x3f); - int compute = sharc.opcode & 0x7fffff; + int cond = (cpustate->opcode >> 33) & 0x1f; + int u = (cpustate->opcode >> 38) & 0x1; + int dreg = (cpustate->opcode >> 23) & 0xf; + int i = (cpustate->opcode >> 41) & 0x7; + int mod = SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f); + int compute = cpustate->opcode & 0x7fffff; - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (compute != 0) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (u) /* post-modify with update */ { - REG(dreg) = dm_read32(DM_REG_I(i)); + REG(dreg) = dm_read32(cpustate, DM_REG_I(i)); DM_REG_I(i) += mod; UPDATE_CIRCULAR_BUFFER_DM(i); } else /* pre-modify, no update */ { - REG(dreg) = dm_read32(DM_REG_I(i) + mod); + REG(dreg) = dm_read32(cpustate, DM_REG_I(i) + mod); } } } /* compute / dreg -> DM, immediate modify */ -static void sharcop_compute_dreg_to_dm_immmod(void) +static void sharcop_compute_dreg_to_dm_immmod(SHARC_REGS *cpustate) { - int cond = (sharc.opcode >> 33) & 0x1f; - int u = (sharc.opcode >> 38) & 0x1; - int dreg = (sharc.opcode >> 23) & 0xf; - int i = (sharc.opcode >> 41) & 0x7; - int mod = SIGN_EXTEND6((sharc.opcode >> 27) & 0x3f); - int compute = sharc.opcode & 0x7fffff; + int cond = (cpustate->opcode >> 33) & 0x1f; + int u = (cpustate->opcode >> 38) & 0x1; + int dreg = (cpustate->opcode >> 23) & 0xf; + int i = (cpustate->opcode >> 41) & 0x7; + int mod = SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f); + int compute = cpustate->opcode & 0x7fffff; /* due to parallelity issues, source REG must be saved */ /* because the shift operation may change it */ UINT32 parallel_dreg = REG(dreg); - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (compute != 0) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (u) /* post-modify with update */ { - dm_write32(DM_REG_I(i), parallel_dreg); + dm_write32(cpustate, DM_REG_I(i), parallel_dreg); DM_REG_I(i) += mod; UPDATE_CIRCULAR_BUFFER_DM(i); } else /* pre-modify, no update */ { - dm_write32(DM_REG_I(i) + mod, parallel_dreg); + dm_write32(cpustate, DM_REG_I(i) + mod, parallel_dreg); } } } /* compute / dreg <- PM, immediate modify */ -static void sharcop_compute_pm_to_dreg_immmod(void) +static void sharcop_compute_pm_to_dreg_immmod(SHARC_REGS *cpustate) { - int cond = (sharc.opcode >> 33) & 0x1f; - int u = (sharc.opcode >> 38) & 0x1; - int dreg = (sharc.opcode >> 23) & 0xf; - int i = (sharc.opcode >> 41) & 0x7; - int mod = SIGN_EXTEND6((sharc.opcode >> 27) & 0x3f); - int compute = sharc.opcode & 0x7fffff; + int cond = (cpustate->opcode >> 33) & 0x1f; + int u = (cpustate->opcode >> 38) & 0x1; + int dreg = (cpustate->opcode >> 23) & 0xf; + int i = (cpustate->opcode >> 41) & 0x7; + int mod = SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f); + int compute = cpustate->opcode & 0x7fffff; - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (compute != 0) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (u) /* post-modify with update */ { - REG(dreg) = pm_read32(PM_REG_I(i)); + REG(dreg) = pm_read32(cpustate, PM_REG_I(i)); PM_REG_I(i) += mod; UPDATE_CIRCULAR_BUFFER_PM(i); } else /* pre-modify, no update */ { - REG(dreg) = pm_read32(PM_REG_I(i) + mod); + REG(dreg) = pm_read32(cpustate, PM_REG_I(i) + mod); } } } /* compute / dreg -> PM, immediate modify */ -static void sharcop_compute_dreg_to_pm_immmod(void) +static void sharcop_compute_dreg_to_pm_immmod(SHARC_REGS *cpustate) { - int cond = (sharc.opcode >> 33) & 0x1f; - int u = (sharc.opcode >> 38) & 0x1; - int dreg = (sharc.opcode >> 23) & 0xf; - int i = (sharc.opcode >> 41) & 0x7; - int mod = SIGN_EXTEND6((sharc.opcode >> 27) & 0x3f); - int compute = sharc.opcode & 0x7fffff; + int cond = (cpustate->opcode >> 33) & 0x1f; + int u = (cpustate->opcode >> 38) & 0x1; + int dreg = (cpustate->opcode >> 23) & 0xf; + int i = (cpustate->opcode >> 41) & 0x7; + int mod = SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f); + int compute = cpustate->opcode & 0x7fffff; /* due to parallelity issues, source REG must be saved */ /* because the compute operation may change it */ UINT32 parallel_dreg = REG(dreg); - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (compute != 0) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (u) /* post-modify with update */ { - pm_write32(PM_REG_I(i), parallel_dreg); + pm_write32(cpustate, PM_REG_I(i), parallel_dreg); PM_REG_I(i) += mod; UPDATE_CIRCULAR_BUFFER_PM(i); } else /* pre-modify, no update */ { - pm_write32(PM_REG_I(i) + mod, parallel_dreg); + pm_write32(cpustate, PM_REG_I(i) + mod, parallel_dreg); } } } @@ -1609,25 +1609,25 @@ static void sharcop_compute_dreg_to_pm_immmod(void) /* | 0111xxxxx | */ /* compute / ureg <-> ureg */ -static void sharcop_compute_ureg_to_ureg(void) +static void sharcop_compute_ureg_to_ureg(SHARC_REGS *cpustate) { - int src_ureg = (sharc.opcode >> 36) & 0xff; - int dst_ureg = (sharc.opcode >> 23) & 0xff; - int cond = (sharc.opcode >> 31) & 0x1f; - int compute = sharc.opcode & 0x7fffff; + int src_ureg = (cpustate->opcode >> 36) & 0xff; + int dst_ureg = (cpustate->opcode >> 23) & 0xff; + int cond = (cpustate->opcode >> 31) & 0x1f; + int compute = cpustate->opcode & 0x7fffff; - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { /* due to parallelity issues, source UREG must be saved */ /* because the compute operation may change it */ - UINT32 parallel_ureg = GET_UREG(src_ureg); + UINT32 parallel_ureg = GET_UREG(cpustate, src_ureg); if (compute != 0) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } - SET_UREG(dst_ureg, parallel_ureg); + SET_UREG(cpustate, dst_ureg, parallel_ureg); } } @@ -1635,38 +1635,38 @@ static void sharcop_compute_ureg_to_ureg(void) /* | 1000xxxxx | */ /* immediate shift / dreg <-> DM|PM */ -static void sharcop_imm_shift_dreg_dmpm(void) +static void sharcop_imm_shift_dreg_dmpm(SHARC_REGS *cpustate) { - int i = (sharc.opcode >> 41) & 0x7; - int m = (sharc.opcode >> 38) & 0x7; - int g = (sharc.opcode >> 32) & 0x1; - int d = (sharc.opcode >> 31) & 0x1; - int dreg = (sharc.opcode >> 23) & 0xf; - int cond = (sharc.opcode >> 33) & 0x1f; - int data = ((sharc.opcode >> 8) & 0xff) | ((sharc.opcode >> 19) & 0xf00); - int shiftop = (sharc.opcode >> 16) & 0x3f; - int rn = (sharc.opcode >> 4) & 0xf; - int rx = (sharc.opcode & 0xf); + int i = (cpustate->opcode >> 41) & 0x7; + int m = (cpustate->opcode >> 38) & 0x7; + int g = (cpustate->opcode >> 32) & 0x1; + int d = (cpustate->opcode >> 31) & 0x1; + int dreg = (cpustate->opcode >> 23) & 0xf; + int cond = (cpustate->opcode >> 33) & 0x1f; + int data = ((cpustate->opcode >> 8) & 0xff) | ((cpustate->opcode >> 19) & 0xf00); + int shiftop = (cpustate->opcode >> 16) & 0x3f; + int rn = (cpustate->opcode >> 4) & 0xf; + int rx = (cpustate->opcode & 0xf); - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { /* due to parallelity issues, source REG must be saved */ /* because the shift operation may change it */ UINT32 parallel_dreg = REG(dreg); - SHIFT_OPERATION_IMM(shiftop, data, rn, rx); + SHIFT_OPERATION_IMM(cpustate, shiftop, data, rn, rx); if (g) /* PM */ { if (d) /* dreg -> PM */ { - pm_write32(PM_REG_I(i), parallel_dreg); + pm_write32(cpustate, PM_REG_I(i), parallel_dreg); PM_REG_I(i) += PM_REG_M(m); UPDATE_CIRCULAR_BUFFER_PM(i); } else /* PM <- dreg */ { - REG(dreg) = pm_read32(PM_REG_I(i)); + REG(dreg) = pm_read32(cpustate, PM_REG_I(i)); PM_REG_I(i) += PM_REG_M(m); UPDATE_CIRCULAR_BUFFER_PM(i); } @@ -1675,13 +1675,13 @@ static void sharcop_imm_shift_dreg_dmpm(void) { if (d) /* dreg -> DM */ { - dm_write32(DM_REG_I(i), parallel_dreg); + dm_write32(cpustate, DM_REG_I(i), parallel_dreg); DM_REG_I(i) += DM_REG_M(m); UPDATE_CIRCULAR_BUFFER_DM(i); } else /* DM <- dreg */ { - REG(dreg) = dm_read32(DM_REG_I(i)); + REG(dreg) = dm_read32(cpustate, DM_REG_I(i)); DM_REG_I(i) += DM_REG_M(m); UPDATE_CIRCULAR_BUFFER_DM(i); } @@ -1693,17 +1693,17 @@ static void sharcop_imm_shift_dreg_dmpm(void) /* | 00000010x | */ /* immediate shift */ -static void sharcop_imm_shift(void) +static void sharcop_imm_shift(SHARC_REGS *cpustate) { - int cond = (sharc.opcode >> 33) & 0x1f; - int data = ((sharc.opcode >> 8) & 0xff) | ((sharc.opcode >> 19) & 0xf00); - int shiftop = (sharc.opcode >> 16) & 0x3f; - int rn = (sharc.opcode >> 4) & 0xf; - int rx = (sharc.opcode & 0xf); + int cond = (cpustate->opcode >> 33) & 0x1f; + int data = ((cpustate->opcode >> 8) & 0xff) | ((cpustate->opcode >> 19) & 0xf00); + int shiftop = (cpustate->opcode >> 16) & 0x3f; + int rn = (cpustate->opcode >> 4) & 0xf; + int rx = (cpustate->opcode & 0xf); - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { - SHIFT_OPERATION_IMM(shiftop, data, rn, rx); + SHIFT_OPERATION_IMM(cpustate, shiftop, data, rn, rx); } } @@ -1711,19 +1711,19 @@ static void sharcop_imm_shift(void) /* | 00000100x | */ /* compute / modify */ -static void sharcop_compute_modify(void) +static void sharcop_compute_modify(SHARC_REGS *cpustate) { - int cond = (sharc.opcode >> 33) & 0x1f; - int compute = sharc.opcode & 0x7fffff; - int g = (sharc.opcode >> 38) & 0x1; - int m = (sharc.opcode >> 27) & 0x7; - int i = (sharc.opcode >> 30) & 0x7; + int cond = (cpustate->opcode >> 33) & 0x1f; + int compute = cpustate->opcode & 0x7fffff; + int g = (cpustate->opcode >> 38) & 0x1; + int m = (cpustate->opcode >> 27) & 0x7; + int i = (cpustate->opcode >> 30) & 0x7; - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (compute != 0) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (g) /* Modify PM */ @@ -1743,66 +1743,66 @@ static void sharcop_compute_modify(void) /* | 00000110x | */ /* direct call to absolute address */ -static void sharcop_direct_call(void) +static void sharcop_direct_call(SHARC_REGS *cpustate) { - int j = (sharc.opcode >> 26) & 0x1; - int cond = (sharc.opcode >> 33) & 0x1f; - UINT32 address = sharc.opcode & 0xffffff; + int j = (cpustate->opcode >> 26) & 0x1; + int cond = (cpustate->opcode >> 33) & 0x1f; + UINT32 address = cpustate->opcode & 0xffffff; - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (j) { - //PUSH_PC(sharc.pc+3); /* 1 instruction + 2 delayed instructions */ - PUSH_PC(sharc.nfaddr); /* 1 instruction + 2 delayed instructions */ - CHANGE_PC_DELAYED(address); + //PUSH_PC(cpustate, cpustate->pc+3); /* 1 instruction + 2 delayed instructions */ + PUSH_PC(cpustate, cpustate->nfaddr); /* 1 instruction + 2 delayed instructions */ + CHANGE_PC_DELAYED(cpustate, address); } else { - //PUSH_PC(sharc.pc+1); - PUSH_PC(sharc.daddr); - CHANGE_PC(address); + //PUSH_PC(cpustate, cpustate->pc+1); + PUSH_PC(cpustate, cpustate->daddr); + CHANGE_PC(cpustate, address); } } } /* direct jump to absolute address */ -static void sharcop_direct_jump(void) +static void sharcop_direct_jump(SHARC_REGS *cpustate) { - int la = (sharc.opcode >> 38) & 0x1; - int ci = (sharc.opcode >> 24) & 0x1; - int j = (sharc.opcode >> 26) & 0x1; - int cond = (sharc.opcode >> 33) & 0x1f; - UINT32 address = sharc.opcode & 0xffffff; + int la = (cpustate->opcode >> 38) & 0x1; + int ci = (cpustate->opcode >> 24) & 0x1; + int j = (cpustate->opcode >> 26) & 0x1; + int cond = (cpustate->opcode >> 33) & 0x1f; + UINT32 address = cpustate->opcode & 0xffffff; - if(IF_CONDITION_CODE(cond)) + if(IF_CONDITION_CODE(cpustate, cond)) { // Clear Interrupt if (ci) { // TODO: anything else? - if (sharc.status_stkp > 0) + if (cpustate->status_stkp > 0) { - POP_STATUS_STACK(); + POP_STATUS_STACK(cpustate); } - sharc.interrupt_active = 0; - sharc.irptl &= ~(1 << sharc.active_irq_num); + cpustate->interrupt_active = 0; + cpustate->irptl &= ~(1 << cpustate->active_irq_num); } if (la) { - POP_PC(); - POP_LOOP(); + POP_PC(cpustate); + POP_LOOP(cpustate); } if (j) { - CHANGE_PC_DELAYED(address); + CHANGE_PC_DELAYED(cpustate, address); } else { - CHANGE_PC(address); + CHANGE_PC(cpustate, address); } } } @@ -1811,64 +1811,64 @@ static void sharcop_direct_jump(void) /* | 00000111x | */ /* direct call to relative address */ -static void sharcop_relative_call(void) +static void sharcop_relative_call(SHARC_REGS *cpustate) { - int j = (sharc.opcode >> 26) & 0x1; - int cond = (sharc.opcode >> 33) & 0x1f; - UINT32 address = sharc.opcode & 0xffffff; + int j = (cpustate->opcode >> 26) & 0x1; + int cond = (cpustate->opcode >> 33) & 0x1f; + UINT32 address = cpustate->opcode & 0xffffff; - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (j) { - PUSH_PC(sharc.pc+3); /* 1 instruction + 2 delayed instructions */ - CHANGE_PC_DELAYED(sharc.pc + SIGN_EXTEND24(address)); + PUSH_PC(cpustate, cpustate->pc+3); /* 1 instruction + 2 delayed instructions */ + CHANGE_PC_DELAYED(cpustate, cpustate->pc + SIGN_EXTEND24(address)); } else { - PUSH_PC(sharc.pc+1); - CHANGE_PC(sharc.pc + SIGN_EXTEND24(address)); + PUSH_PC(cpustate, cpustate->pc+1); + CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND24(address)); } } } /* direct jump to relative address */ -static void sharcop_relative_jump(void) +static void sharcop_relative_jump(SHARC_REGS *cpustate) { - int la = (sharc.opcode >> 38) & 0x1; - int ci = (sharc.opcode >> 24) & 0x1; - int j = (sharc.opcode >> 26) & 0x1; - int cond = (sharc.opcode >> 33) & 0x1f; - UINT32 address = sharc.opcode & 0xffffff; + int la = (cpustate->opcode >> 38) & 0x1; + int ci = (cpustate->opcode >> 24) & 0x1; + int j = (cpustate->opcode >> 26) & 0x1; + int cond = (cpustate->opcode >> 33) & 0x1f; + UINT32 address = cpustate->opcode & 0xffffff; - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { // Clear Interrupt if (ci) { // TODO: anything else? - if (sharc.status_stkp > 0) + if (cpustate->status_stkp > 0) { - POP_STATUS_STACK(); + POP_STATUS_STACK(cpustate); } - sharc.interrupt_active = 0; - sharc.irptl &= ~(1 << sharc.active_irq_num); + cpustate->interrupt_active = 0; + cpustate->irptl &= ~(1 << cpustate->active_irq_num); } if (la) { - POP_PC(); - POP_LOOP(); + POP_PC(cpustate); + POP_LOOP(cpustate); } if (j) { - CHANGE_PC_DELAYED(sharc.pc + SIGN_EXTEND24(address)); + CHANGE_PC_DELAYED(cpustate, cpustate->pc + SIGN_EXTEND24(address)); } else { - CHANGE_PC(sharc.pc + SIGN_EXTEND24(address)); + CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND24(address)); } } } @@ -1877,139 +1877,139 @@ static void sharcop_relative_jump(void) /* | 00001000x | */ /* indirect jump */ -static void sharcop_indirect_jump(void) +static void sharcop_indirect_jump(SHARC_REGS *cpustate) { - int la = (sharc.opcode >> 38) & 0x1; - int ci = (sharc.opcode >> 24) & 0x1; - int j = (sharc.opcode >> 26) & 0x1; - int e = (sharc.opcode >> 25) & 0x1; - int pmi = (sharc.opcode >> 30) & 0x7; - int pmm = (sharc.opcode >> 27) & 0x7; - int cond = (sharc.opcode >> 33) & 0x1f; - int compute = sharc.opcode & 0x7fffff; + int la = (cpustate->opcode >> 38) & 0x1; + int ci = (cpustate->opcode >> 24) & 0x1; + int j = (cpustate->opcode >> 26) & 0x1; + int e = (cpustate->opcode >> 25) & 0x1; + int pmi = (cpustate->opcode >> 30) & 0x7; + int pmm = (cpustate->opcode >> 27) & 0x7; + int cond = (cpustate->opcode >> 33) & 0x1f; + int compute = cpustate->opcode & 0x7fffff; // Clear Interrupt if (ci) { // TODO: anything else? - if (sharc.status_stkp > 0) + if (cpustate->status_stkp > 0) { - POP_STATUS_STACK(); + POP_STATUS_STACK(cpustate); } - sharc.interrupt_active = 0; - sharc.irptl &= ~(1 << sharc.active_irq_num); + cpustate->interrupt_active = 0; + cpustate->irptl &= ~(1 << cpustate->active_irq_num); } if (e) /* IF...ELSE */ { - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (la) { - POP_PC(); - POP_LOOP(); + POP_PC(cpustate); + POP_LOOP(cpustate); } if(j) { - CHANGE_PC_DELAYED(PM_REG_I(pmi) + PM_REG_M(pmm)); + CHANGE_PC_DELAYED(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); } else { - CHANGE_PC(PM_REG_I(pmi) + PM_REG_M(pmm)); + CHANGE_PC(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); } } else { if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } } } else /* IF */ { - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (la) { - POP_PC(); - POP_LOOP(); + POP_PC(cpustate); + POP_LOOP(cpustate); } if(j) { - CHANGE_PC_DELAYED(PM_REG_I(pmi) + PM_REG_M(pmm)); + CHANGE_PC_DELAYED(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); } else { - CHANGE_PC(PM_REG_I(pmi) + PM_REG_M(pmm)); + CHANGE_PC(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); } } } } /* indirect call */ -static void sharcop_indirect_call(void) +static void sharcop_indirect_call(SHARC_REGS *cpustate) { - int j = (sharc.opcode >> 26) & 0x1; - int e = (sharc.opcode >> 25) & 0x1; - int pmi = (sharc.opcode >> 30) & 0x7; - int pmm = (sharc.opcode >> 27) & 0x7; - int cond = (sharc.opcode >> 33) & 0x1f; - int compute = sharc.opcode & 0x7fffff; + int j = (cpustate->opcode >> 26) & 0x1; + int e = (cpustate->opcode >> 25) & 0x1; + int pmi = (cpustate->opcode >> 30) & 0x7; + int pmm = (cpustate->opcode >> 27) & 0x7; + int cond = (cpustate->opcode >> 33) & 0x1f; + int compute = cpustate->opcode & 0x7fffff; if (e) /* IF...ELSE */ { - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (j) { - //PUSH_PC(sharc.pc+3); /* 1 instruction + 2 delayed instructions */ - PUSH_PC(sharc.nfaddr); /* 1 instruction + 2 delayed instructions */ - CHANGE_PC_DELAYED(PM_REG_I(pmi) + PM_REG_M(pmm)); + //PUSH_PC(cpustate, cpustate->pc+3); /* 1 instruction + 2 delayed instructions */ + PUSH_PC(cpustate, cpustate->nfaddr); /* 1 instruction + 2 delayed instructions */ + CHANGE_PC_DELAYED(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); } else { - //PUSH_PC(sharc.pc+1); - PUSH_PC(sharc.daddr); - CHANGE_PC(PM_REG_I(pmi) + PM_REG_M(pmm)); + //PUSH_PC(cpustate, cpustate->pc+1); + PUSH_PC(cpustate, cpustate->daddr); + CHANGE_PC(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); } } else { if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } } } else /* IF */ { - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (j) { - //PUSH_PC(sharc.pc+3); /* 1 instruction + 2 delayed instructions */ - PUSH_PC(sharc.nfaddr); /* 1 instruction + 2 delayed instructions */ - CHANGE_PC_DELAYED(PM_REG_I(pmi) + PM_REG_M(pmm)); + //PUSH_PC(cpustate, cpustate->pc+3); /* 1 instruction + 2 delayed instructions */ + PUSH_PC(cpustate, cpustate->nfaddr); /* 1 instruction + 2 delayed instructions */ + CHANGE_PC_DELAYED(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); } else { - //PUSH_PC(sharc.pc+1); - PUSH_PC(sharc.daddr); - CHANGE_PC(PM_REG_I(pmi) + PM_REG_M(pmm)); + //PUSH_PC(cpustate, cpustate->pc+1); + PUSH_PC(cpustate, cpustate->daddr); + CHANGE_PC(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); } } } @@ -2019,135 +2019,135 @@ static void sharcop_indirect_call(void) /* | 00001001x | */ /* indirect jump to relative address */ -static void sharcop_relative_jump_compute(void) +static void sharcop_relative_jump_compute(SHARC_REGS *cpustate) { - int la = (sharc.opcode >> 38) & 0x1; - int ci = (sharc.opcode >> 24) & 0x1; - int j = (sharc.opcode >> 26) & 0x1; - int e = (sharc.opcode >> 25) & 0x1; - int cond = (sharc.opcode >> 33) & 0x1f; - int compute = sharc.opcode & 0x7fffff; + int la = (cpustate->opcode >> 38) & 0x1; + int ci = (cpustate->opcode >> 24) & 0x1; + int j = (cpustate->opcode >> 26) & 0x1; + int e = (cpustate->opcode >> 25) & 0x1; + int cond = (cpustate->opcode >> 33) & 0x1f; + int compute = cpustate->opcode & 0x7fffff; // Clear Interrupt if (ci) { // TODO: anything else? - if (sharc.status_stkp > 0) + if (cpustate->status_stkp > 0) { - POP_STATUS_STACK(); + POP_STATUS_STACK(cpustate); } - sharc.interrupt_active = 0; - sharc.irptl &= ~(1 << sharc.active_irq_num); + cpustate->interrupt_active = 0; + cpustate->irptl &= ~(1 << cpustate->active_irq_num); } if (e) /* IF...ELSE */ { - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (la) { - POP_PC(); - POP_LOOP(); + POP_PC(cpustate); + POP_LOOP(cpustate); } if (j) { - CHANGE_PC_DELAYED(sharc.pc + SIGN_EXTEND6((sharc.opcode >> 27) & 0x3f)); + CHANGE_PC_DELAYED(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); } else { - CHANGE_PC(sharc.pc + SIGN_EXTEND6((sharc.opcode >> 27) & 0x3f)); + CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); } } else { if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } } } else /* IF */ { - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (la) { - POP_PC(); - POP_LOOP(); + POP_PC(cpustate); + POP_LOOP(cpustate); } if (j) { - CHANGE_PC_DELAYED(sharc.pc + SIGN_EXTEND6((sharc.opcode >> 27) & 0x3f)); + CHANGE_PC_DELAYED(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); } else { - CHANGE_PC(sharc.pc + SIGN_EXTEND6((sharc.opcode >> 27) & 0x3f)); + CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); } } } } /* indirect call to relative address */ -static void sharcop_relative_call_compute(void) +static void sharcop_relative_call_compute(SHARC_REGS *cpustate) { - int j = (sharc.opcode >> 26) & 0x1; - int e = (sharc.opcode >> 25) & 0x1; - int cond = (sharc.opcode >> 33) & 0x1f; - int compute = sharc.opcode & 0x7fffff; + int j = (cpustate->opcode >> 26) & 0x1; + int e = (cpustate->opcode >> 25) & 0x1; + int cond = (cpustate->opcode >> 33) & 0x1f; + int compute = cpustate->opcode & 0x7fffff; if (e) /* IF...ELSE */ { - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (j) { - //PUSH_PC(sharc.pc+3); /* 1 instruction + 2 delayed instructions */ - PUSH_PC(sharc.nfaddr); /* 1 instruction + 2 delayed instructions */ - CHANGE_PC_DELAYED(sharc.pc + SIGN_EXTEND6((sharc.opcode >> 27) & 0x3f)); + //PUSH_PC(cpustate, cpustate->pc+3); /* 1 instruction + 2 delayed instructions */ + PUSH_PC(cpustate, cpustate->nfaddr); /* 1 instruction + 2 delayed instructions */ + CHANGE_PC_DELAYED(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); } else { - //PUSH_PC(sharc.pc+1); - PUSH_PC(sharc.daddr); - CHANGE_PC(sharc.pc + SIGN_EXTEND6((sharc.opcode >> 27) & 0x3f)); + //PUSH_PC(cpustate, cpustate->pc+1); + PUSH_PC(cpustate, cpustate->daddr); + CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); } } else { if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } } } else /* IF */ { - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (j) { - //PUSH_PC(sharc.pc+3); /* 1 instruction + 2 delayed instructions */ - PUSH_PC(sharc.nfaddr); /* 1 instruction + 2 delayed instructions */ - CHANGE_PC_DELAYED(sharc.pc + SIGN_EXTEND6((sharc.opcode >> 27) & 0x3f)); + //PUSH_PC(cpustate, cpustate->pc+3); /* 1 instruction + 2 delayed instructions */ + PUSH_PC(cpustate, cpustate->nfaddr); /* 1 instruction + 2 delayed instructions */ + CHANGE_PC_DELAYED(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); } else { - //PUSH_PC(sharc.pc+1); - PUSH_PC(sharc.daddr); - CHANGE_PC(sharc.pc + SIGN_EXTEND6((sharc.opcode >> 27) & 0x3f)); + //PUSH_PC(cpustate, cpustate->pc+1); + PUSH_PC(cpustate, cpustate->daddr); + CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); } } } @@ -2157,41 +2157,41 @@ static void sharcop_relative_call_compute(void) /* | 110xxxxxx | */ /* indirect jump / compute / dreg <-> DM */ -static void sharcop_indirect_jump_compute_dreg_dm(void) +static void sharcop_indirect_jump_compute_dreg_dm(SHARC_REGS *cpustate) { - int d = (sharc.opcode >> 44) & 0x1; - int dmi = (sharc.opcode >> 41) & 0x7; - int dmm = (sharc.opcode >> 38) & 0x7; - int pmi = (sharc.opcode >> 30) & 0x7; - int pmm = (sharc.opcode >> 27) & 0x7; - int cond = (sharc.opcode >> 33) & 0x1f; - int dreg = (sharc.opcode >> 23) & 0xf; + int d = (cpustate->opcode >> 44) & 0x1; + int dmi = (cpustate->opcode >> 41) & 0x7; + int dmm = (cpustate->opcode >> 38) & 0x7; + int pmi = (cpustate->opcode >> 30) & 0x7; + int pmm = (cpustate->opcode >> 27) & 0x7; + int cond = (cpustate->opcode >> 33) & 0x1f; + int dreg = (cpustate->opcode >> 23) & 0xf; - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { - CHANGE_PC(PM_REG_I(pmi) + PM_REG_M(pmm)); + CHANGE_PC(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); } else { - UINT32 compute = sharc.opcode & 0x7fffff; + UINT32 compute = cpustate->opcode & 0x7fffff; /* due to parallelity issues, source REG must be saved */ /* because the compute operation may change it */ UINT32 parallel_dreg = REG(dreg); if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (d) /* dreg -> DM */ { - dm_write32(DM_REG_I(dmi), parallel_dreg); + dm_write32(cpustate, DM_REG_I(dmi), parallel_dreg); DM_REG_I(dmi) += DM_REG_M(dmm); UPDATE_CIRCULAR_BUFFER_DM(dmi); } else /* DM <- dreg */ { - REG(dreg) = dm_read32(DM_REG_I(dmi)); + REG(dreg) = dm_read32(cpustate, DM_REG_I(dmi)); DM_REG_I(dmi) += DM_REG_M(dmm); UPDATE_CIRCULAR_BUFFER_DM(dmi); } @@ -2202,39 +2202,39 @@ static void sharcop_indirect_jump_compute_dreg_dm(void) /* | 111xxxxxx | */ /* relative jump / compute / dreg <-> DM */ -static void sharcop_relative_jump_compute_dreg_dm(void) +static void sharcop_relative_jump_compute_dreg_dm(SHARC_REGS *cpustate) { - int d = (sharc.opcode >> 44) & 0x1; - int dmi = (sharc.opcode >> 41) & 0x7; - int dmm = (sharc.opcode >> 38) & 0x7; - int cond = (sharc.opcode >> 33) & 0x1f; - int dreg = (sharc.opcode >> 23) & 0xf; + int d = (cpustate->opcode >> 44) & 0x1; + int dmi = (cpustate->opcode >> 41) & 0x7; + int dmm = (cpustate->opcode >> 38) & 0x7; + int cond = (cpustate->opcode >> 33) & 0x1f; + int dreg = (cpustate->opcode >> 23) & 0xf; - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { - CHANGE_PC(sharc.pc + SIGN_EXTEND6((sharc.opcode >> 27) & 0x3f)); + CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); } else { - UINT32 compute = sharc.opcode & 0x7fffff; + UINT32 compute = cpustate->opcode & 0x7fffff; /* due to parallelity issues, source REG must be saved */ /* because the compute operation may change it */ UINT32 parallel_dreg = REG(dreg); if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (d) /* dreg -> DM */ { - dm_write32(DM_REG_I(dmi), parallel_dreg); + dm_write32(cpustate, DM_REG_I(dmi), parallel_dreg); DM_REG_I(dmi) += DM_REG_M(dmm); UPDATE_CIRCULAR_BUFFER_DM(dmi); } else /* DM <- dreg */ { - REG(dreg) = dm_read32(DM_REG_I(dmi)); + REG(dreg) = dm_read32(cpustate, DM_REG_I(dmi)); DM_REG_I(dmi) += DM_REG_M(dmm); UPDATE_CIRCULAR_BUFFER_DM(dmi); } @@ -2245,54 +2245,54 @@ static void sharcop_relative_jump_compute_dreg_dm(void) /* | 00001010x | */ /* return from subroutine / compute */ -static void sharcop_rts(void) +static void sharcop_rts(SHARC_REGS *cpustate) { - int cond = (sharc.opcode >> 33) & 0x1f; - int j = (sharc.opcode >> 26) & 0x1; - int e = (sharc.opcode >> 25) & 0x1; - //int lr = (sharc.opcode >> 24) & 0x1; - int compute = sharc.opcode & 0x7fffff; + int cond = (cpustate->opcode >> 33) & 0x1f; + int j = (cpustate->opcode >> 26) & 0x1; + int e = (cpustate->opcode >> 25) & 0x1; + //int lr = (cpustate->opcode >> 24) & 0x1; + int compute = cpustate->opcode & 0x7fffff; //if(lr) // fatalerror("SHARC: rts: loop reentry not implemented !"); if (e) /* IF...ELSE */ { - if(IF_CONDITION_CODE(cond)) + if(IF_CONDITION_CODE(cpustate, cond)) { if (j) { - CHANGE_PC_DELAYED(POP_PC()); + CHANGE_PC_DELAYED(cpustate, POP_PC(cpustate)); } else { - CHANGE_PC(POP_PC()); + CHANGE_PC(cpustate, POP_PC(cpustate)); } } else { if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } } } else /* IF */ { - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (j) { - CHANGE_PC_DELAYED(POP_PC()); + CHANGE_PC_DELAYED(cpustate, POP_PC(cpustate)); } else { - CHANGE_PC(POP_PC()); + CHANGE_PC(cpustate, POP_PC(cpustate)); } } } @@ -2302,74 +2302,74 @@ static void sharcop_rts(void) /* | 00001011x | */ /* return from interrupt / compute */ -static void sharcop_rti(void) +static void sharcop_rti(SHARC_REGS *cpustate) { - int cond = (sharc.opcode >> 33) & 0x1f; - int j = (sharc.opcode >> 26) & 0x1; - int e = (sharc.opcode >> 25) & 0x1; - int compute = sharc.opcode & 0x7fffff; + int cond = (cpustate->opcode >> 33) & 0x1f; + int j = (cpustate->opcode >> 26) & 0x1; + int e = (cpustate->opcode >> 25) & 0x1; + int compute = cpustate->opcode & 0x7fffff; - sharc.irptl &= ~(1 << sharc.active_irq_num); + cpustate->irptl &= ~(1 << cpustate->active_irq_num); if(e) /* IF...ELSE */ { - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (j) { - CHANGE_PC_DELAYED(POP_PC()); + CHANGE_PC_DELAYED(cpustate, POP_PC(cpustate)); } else { - CHANGE_PC(POP_PC()); + CHANGE_PC(cpustate, POP_PC(cpustate)); } } else { if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } } } else /* IF */ { - if (IF_CONDITION_CODE(cond)) + if (IF_CONDITION_CODE(cpustate, cond)) { if (compute) { - COMPUTE(compute); + COMPUTE(cpustate, compute); } if (j) { - CHANGE_PC_DELAYED(POP_PC()); + CHANGE_PC_DELAYED(cpustate, POP_PC(cpustate)); } else { - CHANGE_PC(POP_PC()); + CHANGE_PC(cpustate, POP_PC(cpustate)); } } } - if (sharc.status_stkp > 0) + if (cpustate->status_stkp > 0) { - POP_STATUS_STACK(); + POP_STATUS_STACK(cpustate); } - sharc.interrupt_active = 0; - check_interrupts(); + cpustate->interrupt_active = 0; + check_interrupts(cpustate); } /*****************************************************************************/ /* | 00001100x | */ /* do until counter expired, LCNTR immediate */ -static void sharcop_do_until_counter_imm(void) +static void sharcop_do_until_counter_imm(SHARC_REGS *cpustate) { - UINT16 data = (UINT16)(sharc.opcode >> 24); - int offset = SIGN_EXTEND24(sharc.opcode & 0xffffff); - UINT32 address = sharc.pc + offset; + UINT16 data = (UINT16)(cpustate->opcode >> 24); + int offset = SIGN_EXTEND24(cpustate->opcode & 0xffffff); + UINT32 address = cpustate->pc + offset; int type; int cond = 0xf; /* until LCE (loop counter expired */ int distance = abs(offset); @@ -2387,11 +2387,11 @@ static void sharcop_do_until_counter_imm(void) type = 3; } - sharc.lcntr = data; - if (sharc.lcntr > 0) + cpustate->lcntr = data; + if (cpustate->lcntr > 0) { - PUSH_PC(sharc.pc+1); - PUSH_LOOP(address | (type << 30) | (cond << 24), sharc.lcntr); + PUSH_PC(cpustate, cpustate->pc+1); + PUSH_LOOP(cpustate, address | (type << 30) | (cond << 24), cpustate->lcntr); } } @@ -2399,11 +2399,11 @@ static void sharcop_do_until_counter_imm(void) /* | 00001101x | */ /* do until counter expired, LCNTR from UREG */ -static void sharcop_do_until_counter_ureg(void) +static void sharcop_do_until_counter_ureg(SHARC_REGS *cpustate) { - int ureg = (sharc.opcode >> 32) & 0xff; - int offset = SIGN_EXTEND24(sharc.opcode & 0xffffff); - UINT32 address = sharc.pc + offset; + int ureg = (cpustate->opcode >> 32) & 0xff; + int offset = SIGN_EXTEND24(cpustate->opcode & 0xffffff); + UINT32 address = cpustate->pc + offset; int type; int cond = 0xf; /* until LCE (loop counter expired */ int distance = abs(offset); @@ -2421,11 +2421,11 @@ static void sharcop_do_until_counter_ureg(void) type = 3; } - sharc.lcntr = GET_UREG(ureg); - if (sharc.lcntr > 0) + cpustate->lcntr = GET_UREG(cpustate, ureg); + if (cpustate->lcntr > 0) { - PUSH_PC(sharc.pc+1); - PUSH_LOOP(address | (type << 30) | (cond << 24), sharc.lcntr); + PUSH_PC(cpustate, cpustate->pc+1); + PUSH_LOOP(cpustate, address | (type << 30) | (cond << 24), cpustate->lcntr); } } @@ -2433,66 +2433,66 @@ static void sharcop_do_until_counter_ureg(void) /* | 00001110x | */ /* do until */ -static void sharcop_do_until(void) +static void sharcop_do_until(SHARC_REGS *cpustate) { - int cond = (sharc.opcode >> 33) & 0x1f; - int offset = SIGN_EXTEND24(sharc.opcode & 0xffffff); - UINT32 address = (sharc.pc + offset); + int cond = (cpustate->opcode >> 33) & 0x1f; + int offset = SIGN_EXTEND24(cpustate->opcode & 0xffffff); + UINT32 address = (cpustate->pc + offset); - PUSH_PC(sharc.pc+1); - PUSH_LOOP(address | (cond << 24), 0); + PUSH_PC(cpustate, cpustate->pc+1); + PUSH_LOOP(cpustate, address | (cond << 24), 0); } /*****************************************************************************/ /* | 000100 | G | D | */ /* ureg <- DM (direct addressing) */ -static void sharcop_dm_to_ureg_direct(void) +static void sharcop_dm_to_ureg_direct(SHARC_REGS *cpustate) { - int ureg = (sharc.opcode >> 32) & 0xff; - UINT32 address = (UINT32)(sharc.opcode); + int ureg = (cpustate->opcode >> 32) & 0xff; + UINT32 address = (UINT32)(cpustate->opcode); - SET_UREG(ureg, dm_read32(address)); + SET_UREG(cpustate, ureg, dm_read32(cpustate, address)); } /* ureg -> DM (direct addressing) */ -static void sharcop_ureg_to_dm_direct(void) +static void sharcop_ureg_to_dm_direct(SHARC_REGS *cpustate) { - int ureg = (sharc.opcode >> 32) & 0xff; - UINT32 address = (UINT32)(sharc.opcode); + int ureg = (cpustate->opcode >> 32) & 0xff; + UINT32 address = (UINT32)(cpustate->opcode); - dm_write32(address, GET_UREG(ureg)); + dm_write32(cpustate, address, GET_UREG(cpustate, ureg)); } /* ureg <- PM (direct addressing) */ -static void sharcop_pm_to_ureg_direct(void) +static void sharcop_pm_to_ureg_direct(SHARC_REGS *cpustate) { - int ureg = (sharc.opcode >> 32) & 0xff; - UINT32 address = (UINT32)(sharc.opcode); + int ureg = (cpustate->opcode >> 32) & 0xff; + UINT32 address = (UINT32)(cpustate->opcode); if (ureg == 0xdb) // PX is 48-bit { - sharc.px = pm_read48(address); + cpustate->px = pm_read48(cpustate, address); } else { - SET_UREG(ureg, pm_read32(address)); + SET_UREG(cpustate, ureg, pm_read32(cpustate, address)); } } /* ureg -> PM (direct addressing) */ -static void sharcop_ureg_to_pm_direct(void) +static void sharcop_ureg_to_pm_direct(SHARC_REGS *cpustate) { - int ureg = (sharc.opcode >> 32) & 0xff; - UINT32 address = (UINT32)(sharc.opcode); + int ureg = (cpustate->opcode >> 32) & 0xff; + UINT32 address = (UINT32)(cpustate->opcode); if (ureg == 0xdb) // PX is 48-bit { - pm_write48(address, sharc.px); + pm_write48(cpustate, address, cpustate->px); } else { - pm_write32(address, GET_UREG(ureg)); + pm_write32(cpustate, address, GET_UREG(cpustate, ureg)); } } @@ -2500,56 +2500,56 @@ static void sharcop_ureg_to_pm_direct(void) /* | 101 | G | III | D | */ /* ureg <- DM (indirect addressing) */ -static void sharcop_dm_to_ureg_indirect(void) +static void sharcop_dm_to_ureg_indirect(SHARC_REGS *cpustate) { - int ureg = (sharc.opcode >> 32) & 0xff; - UINT32 offset = (UINT32)sharc.opcode; - int i = (sharc.opcode >> 41) & 0x7; + int ureg = (cpustate->opcode >> 32) & 0xff; + UINT32 offset = (UINT32)cpustate->opcode; + int i = (cpustate->opcode >> 41) & 0x7; - SET_UREG(ureg, dm_read32(DM_REG_I(i) + offset)); + SET_UREG(cpustate, ureg, dm_read32(cpustate, DM_REG_I(i) + offset)); } /* ureg -> DM (indirect addressing) */ -static void sharcop_ureg_to_dm_indirect(void) +static void sharcop_ureg_to_dm_indirect(SHARC_REGS *cpustate) { - int ureg = (sharc.opcode >> 32) & 0xff; - UINT32 offset = (UINT32)sharc.opcode; - int i = (sharc.opcode >> 41) & 0x7; + int ureg = (cpustate->opcode >> 32) & 0xff; + UINT32 offset = (UINT32)cpustate->opcode; + int i = (cpustate->opcode >> 41) & 0x7; - dm_write32(DM_REG_I(i) + offset, GET_UREG(ureg)); + dm_write32(cpustate, DM_REG_I(i) + offset, GET_UREG(cpustate, ureg)); } /* ureg <- PM (indirect addressing) */ -static void sharcop_pm_to_ureg_indirect(void) +static void sharcop_pm_to_ureg_indirect(SHARC_REGS *cpustate) { - int ureg = (sharc.opcode >> 32) & 0xff; - UINT32 offset = sharc.opcode & 0xffffff; - int i = (sharc.opcode >> 41) & 0x7; + int ureg = (cpustate->opcode >> 32) & 0xff; + UINT32 offset = cpustate->opcode & 0xffffff; + int i = (cpustate->opcode >> 41) & 0x7; if (ureg == 0xdb) /* PX is 48-bit */ { - sharc.px = pm_read48(PM_REG_I(i) + offset); + cpustate->px = pm_read48(cpustate, PM_REG_I(i) + offset); } else { - SET_UREG(ureg, pm_read32(PM_REG_I(i) + offset)); + SET_UREG(cpustate, ureg, pm_read32(cpustate, PM_REG_I(i) + offset)); } } /* ureg -> PM (indirect addressing) */ -static void sharcop_ureg_to_pm_indirect(void) +static void sharcop_ureg_to_pm_indirect(SHARC_REGS *cpustate) { - int ureg = (sharc.opcode >> 32) & 0xff; - UINT32 offset = (UINT32)sharc.opcode; - int i = (sharc.opcode >> 41) & 0x7; + int ureg = (cpustate->opcode >> 32) & 0xff; + UINT32 offset = (UINT32)cpustate->opcode; + int i = (cpustate->opcode >> 41) & 0x7; if (ureg == 0xdb) /* PX is 48-bit */ { - pm_write48(PM_REG_I(i) + offset, sharc.px); + pm_write48(cpustate, PM_REG_I(i) + offset, cpustate->px); } else { - pm_write32(PM_REG_I(i) + offset, GET_UREG(ureg)); + pm_write32(cpustate, PM_REG_I(i) + offset, GET_UREG(cpustate, ureg)); } } @@ -2557,24 +2557,24 @@ static void sharcop_ureg_to_pm_indirect(void) /* | 1001xxxxx | */ /* immediate data -> DM|PM */ -static void sharcop_imm_to_dmpm(void) +static void sharcop_imm_to_dmpm(SHARC_REGS *cpustate) { - int i = (sharc.opcode >> 41) & 0x7; - int m = (sharc.opcode >> 38) & 0x7; - int g = (sharc.opcode >> 37) & 0x1; - UINT32 data = (UINT32)sharc.opcode; + int i = (cpustate->opcode >> 41) & 0x7; + int m = (cpustate->opcode >> 38) & 0x7; + int g = (cpustate->opcode >> 37) & 0x1; + UINT32 data = (UINT32)cpustate->opcode; if (g) { /* program memory (PM) */ - pm_write32(PM_REG_I(i), data); + pm_write32(cpustate, PM_REG_I(i), data); PM_REG_I(i) += PM_REG_M(m); UPDATE_CIRCULAR_BUFFER_PM(i); } else { /* data memory (DM) */ - dm_write32(DM_REG_I(i), data); + dm_write32(cpustate, DM_REG_I(i), data); DM_REG_I(i) += DM_REG_M(m); UPDATE_CIRCULAR_BUFFER_DM(i); } @@ -2584,25 +2584,25 @@ static void sharcop_imm_to_dmpm(void) /* | 00001111x | */ /* immediate data -> ureg */ -static void sharcop_imm_to_ureg(void) +static void sharcop_imm_to_ureg(SHARC_REGS *cpustate) { - int ureg = (sharc.opcode >> 32) & 0xff; - UINT32 data = (UINT32)sharc.opcode; + int ureg = (cpustate->opcode >> 32) & 0xff; + UINT32 data = (UINT32)cpustate->opcode; - SET_UREG(ureg, data); + SET_UREG(cpustate, ureg, data); } /*****************************************************************************/ /* | 00010100x | */ /* system register bit manipulation */ -static void sharcop_sysreg_bitop(void) +static void sharcop_sysreg_bitop(SHARC_REGS *cpustate) { - int bop = (sharc.opcode >> 37) & 0x7; - int sreg = (sharc.opcode >> 32) & 0xf; - UINT32 data = (UINT32)sharc.opcode; + int bop = (cpustate->opcode >> 37) & 0x7; + int sreg = (cpustate->opcode >> 32) & 0xf; + UINT32 data = (UINT32)cpustate->opcode; - UINT32 src = GET_UREG(0x70 | sreg); + UINT32 src = GET_UREG(cpustate, 0x70 | sreg); switch(bop) { @@ -2625,11 +2625,11 @@ static void sharcop_sysreg_bitop(void) { if ((src & data) == data) { - sharc.astat |= BTF; + cpustate->astat |= BTF; } else { - sharc.astat &= ~BTF; + cpustate->astat &= ~BTF; } break; } @@ -2637,11 +2637,11 @@ static void sharcop_sysreg_bitop(void) { if (src == data) { - sharc.astat |= BTF; + cpustate->astat |= BTF; } else { - sharc.astat &= ~BTF; + cpustate->astat &= ~BTF; } break; } @@ -2650,18 +2650,18 @@ static void sharcop_sysreg_bitop(void) break; } - SET_UREG(0x70 | sreg, src); + SET_UREG(cpustate, 0x70 | sreg, src); } /*****************************************************************************/ /* | 000101100 | */ /* I register modify */ -static void sharcop_modify(void) +static void sharcop_modify(SHARC_REGS *cpustate) { - int g = (sharc.opcode >> 38) & 0x1; - int i = (sharc.opcode >> 32) & 0x7; - INT32 data = (sharc.opcode); + int g = (cpustate->opcode >> 38) & 0x1; + int i = (cpustate->opcode >> 32) & 0x7; + INT32 data = (cpustate->opcode); if (g) // PM { @@ -2679,7 +2679,7 @@ static void sharcop_modify(void) /* | 000101101 | */ /* I register bit-reverse */ -static void sharcop_bit_reverse(void) +static void sharcop_bit_reverse(SHARC_REGS *cpustate) { fatalerror("SHARC: sharcop_bit_reverse unimplemented"); } @@ -2688,40 +2688,40 @@ static void sharcop_bit_reverse(void) /* | 00010111x | */ /* push/pop stacks / flush cache */ -static void sharcop_push_pop_stacks(void) +static void sharcop_push_pop_stacks(SHARC_REGS *cpustate) { - if (sharc.opcode & U64(0x008000000000)) + if (cpustate->opcode & U64(0x008000000000)) { fatalerror("sharcop_push_pop_stacks: push loop not implemented"); } - if (sharc.opcode & U64(0x004000000000)) + if (cpustate->opcode & U64(0x004000000000)) { fatalerror("sharcop_push_pop_stacks: pop loop not implemented"); } - if (sharc.opcode & U64(0x002000000000)) + if (cpustate->opcode & U64(0x002000000000)) { //fatalerror("sharcop_push_pop_stacks: push sts not implemented"); - PUSH_STATUS_STACK(); + PUSH_STATUS_STACK(cpustate); } - if (sharc.opcode & U64(0x001000000000)) + if (cpustate->opcode & U64(0x001000000000)) { //fatalerror("sharcop_push_pop_stacks: pop sts not implemented"); - POP_STATUS_STACK(); + POP_STATUS_STACK(cpustate); } - if (sharc.opcode & U64(0x000800000000)) + if (cpustate->opcode & U64(0x000800000000)) { - PUSH_PC(sharc.pcstk); + PUSH_PC(cpustate, cpustate->pcstk); } - if (sharc.opcode & U64(0x000400000000)) + if (cpustate->opcode & U64(0x000400000000)) { - POP_PC(); + POP_PC(cpustate); } } /*****************************************************************************/ /* | 000000000 | */ -static void sharcop_nop(void) +static void sharcop_nop(SHARC_REGS *cpustate) { } @@ -2729,26 +2729,26 @@ static void sharcop_nop(void) /*****************************************************************************/ /* | 000000001 | */ -static void sharcop_idle(void) +static void sharcop_idle(SHARC_REGS *cpustate) { - //CHANGE_PC(sharc.pc); + //CHANGE_PC(cpustate, cpustate->pc); - sharc.daddr = sharc.pc; - sharc.faddr = sharc.pc+1; - sharc.nfaddr = sharc.pc+2; + cpustate->daddr = cpustate->pc; + cpustate->faddr = cpustate->pc+1; + cpustate->nfaddr = cpustate->pc+2; - sharc.decode_opcode = ROPCODE(sharc.daddr); - sharc.fetch_opcode = ROPCODE(sharc.faddr); + cpustate->decode_opcode = ROPCODE(cpustate->daddr); + cpustate->fetch_opcode = ROPCODE(cpustate->faddr); - sharc.idle = 1; + cpustate->idle = 1; } /*****************************************************************************/ -static void sharcop_unimplemented(void) +static void sharcop_unimplemented(SHARC_REGS *cpustate) { char dasm[1000]; - CPU_DISASSEMBLE_NAME(sharc)(NULL, dasm, sharc.pc, NULL, NULL); - mame_printf_debug("SHARC: %08X: %s\n", sharc.pc, dasm); - fatalerror("SHARC: Unimplemented opcode %04X%08X at %08X", (UINT16)(sharc.opcode >> 32), (UINT32)(sharc.opcode), sharc.pc); + CPU_DISASSEMBLE_NAME(sharc)(NULL, dasm, cpustate->pc, NULL, NULL); + mame_printf_debug("SHARC: %08X: %s\n", cpustate->pc, dasm); + fatalerror("SHARC: Unimplemented opcode %04X%08X at %08X", (UINT16)(cpustate->opcode >> 32), (UINT32)(cpustate->opcode), cpustate->pc); } diff --git a/src/emu/cpu/sharc/sharcops.h b/src/emu/cpu/sharc/sharcops.h index 17a6a70b0c0..115cfb757b9 100644 --- a/src/emu/cpu/sharc/sharcops.h +++ b/src/emu/cpu/sharc/sharcops.h @@ -2,7 +2,7 @@ typedef struct { UINT32 op_mask; UINT32 op_bits; - void (* handler)(void); + void (*handler)(SHARC_REGS *cpustate); } SHARC_OP; static const SHARC_OP sharc_opcode_table[] = diff --git a/src/mame/drivers/model2.c b/src/mame/drivers/model2.c index 5fa90286e38..2ef1960dae2 100644 --- a/src/mame/drivers/model2.c +++ b/src/mame/drivers/model2.c @@ -116,15 +116,11 @@ static int copro_fifoin_pop(const device_config *device, UINT32 *result) { if (copro_fifoin_num == 0) { - cpu_push_context(device); - sharc_set_flag_input(0, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(device, 0, ASSERT_LINE); } else { - cpu_push_context(device); - sharc_set_flag_input(0, CLEAR_LINE); - cpu_pop_context(); + sharc_set_flag_input(device, 0, CLEAR_LINE); } } @@ -154,9 +150,7 @@ static void copro_fifoin_push(const device_config *device, UINT32 data) // clear FIFO empty flag on SHARC if (dsp_type == DSP_TYPE_SHARC) { - cpu_push_context(device); - sharc_set_flag_input(0, CLEAR_LINE); - cpu_pop_context(); + sharc_set_flag_input(device, 0, CLEAR_LINE); } } @@ -196,15 +190,11 @@ static UINT32 copro_fifoout_pop(const address_space *space) { if (copro_fifoout_num == COPRO_FIFOOUT_SIZE) { - cpu_push_context(Machine->cpu[2]); - sharc_set_flag_input(1, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(space->machine->cpu[2], 1, ASSERT_LINE); } else { - cpu_push_context(Machine->cpu[2]); - sharc_set_flag_input(1, CLEAR_LINE); - cpu_pop_context(); + sharc_set_flag_input(space->machine->cpu[2], 1, CLEAR_LINE); } } @@ -235,17 +225,13 @@ static void copro_fifoout_push(const device_config *device, UINT32 data) { if (copro_fifoout_num == COPRO_FIFOOUT_SIZE) { - cpu_push_context(device); - sharc_set_flag_input(1, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(device, 1, ASSERT_LINE); //cpu_set_input_line(device, SHARC_INPUT_FLAG1, ASSERT_LINE); } else { - cpu_push_context(device); - sharc_set_flag_input(1, CLEAR_LINE); - cpu_pop_context(); + sharc_set_flag_input(device, 1, CLEAR_LINE); //cpu_set_input_line(device, SHARC_INPUT_FLAG1, CLEAR_LINE); } @@ -571,9 +557,7 @@ static WRITE32_HANDLER(copro_fifo_w) { if (dsp_type == DSP_TYPE_SHARC) { - cpu_push_context(space->machine->cpu[2]); - sharc_external_dma_write(model2_coprocnt, data & 0xffff); - cpu_pop_context(); + sharc_external_dma_write(space->machine->cpu[2], model2_coprocnt, data & 0xffff); } else if (dsp_type == DSP_TYPE_TGP) { @@ -598,9 +582,7 @@ static WRITE32_HANDLER(copro_sharc_iop_w) (strcmp(space->machine->gamedrv->name, "vstriker" ) == 0) || (strcmp(space->machine->gamedrv->name, "gunblade" ) == 0)) { - cpu_push_context(space->machine->cpu[2]); - sharc_external_iop_write(offset, data); - cpu_pop_context(); + sharc_external_iop_write(space->machine->cpu[2], offset, data); } else { @@ -611,9 +593,7 @@ static WRITE32_HANDLER(copro_sharc_iop_w) else { iop_data |= (data & 0xffff) << 16; - cpu_push_context(space->machine->cpu[2]); - sharc_external_iop_write(offset, iop_data); - cpu_pop_context(); + sharc_external_iop_write(space->machine->cpu[2], offset, iop_data); } iop_write_num++; } @@ -688,9 +668,7 @@ static WRITE32_HANDLER(geo_sharc_fifo_w) { if (model2_geoctl & 0x80000000) { - cpu_push_context(space->machine->cpu[3]); - sharc_external_dma_write(model2_geocnt, data & 0xffff); - cpu_pop_context(); + sharc_external_dma_write(space->machine->cpu[3], model2_geocnt, data & 0xffff); model2_geocnt++; } @@ -706,9 +684,7 @@ static WRITE32_HANDLER(geo_sharc_iop_w) { if ((strcmp(space->machine->gamedrv->name, "schamp" ) == 0)) { - cpu_push_context(space->machine->cpu[3]); - sharc_external_iop_write(offset, data); - cpu_pop_context(); + sharc_external_iop_write(space->machine->cpu[3], offset, data); } else { @@ -719,9 +695,7 @@ static WRITE32_HANDLER(geo_sharc_iop_w) else { geo_iop_data |= (data & 0xffff) << 16; - cpu_push_context(space->machine->cpu[3]); - sharc_external_iop_write(offset, geo_iop_data); - cpu_pop_context(); + sharc_external_iop_write(space->machine->cpu[3], offset, geo_iop_data); } geo_iop_write_num++; } @@ -1744,7 +1718,7 @@ static const scsp_interface scsp_config = static READ32_HANDLER(copro_sharc_input_fifo_r) { - UINT32 result; + UINT32 result = 0; //mame_printf_debug("SHARC FIFOIN pop at %08X\n", cpu_get_pc(space->cpu)); copro_fifoin_pop(space->machine->cpu[2], &result); diff --git a/src/mame/drivers/zr107.c b/src/mame/drivers/zr107.c index a0a05e7ab79..bba01f066d1 100644 --- a/src/mame/drivers/zr107.c +++ b/src/mame/drivers/zr107.c @@ -237,9 +237,7 @@ static VIDEO_UPDATE( jetwave ) draw_7segment_led(bitmap, 3, 3, led_reg0); draw_7segment_led(bitmap, 9, 3, led_reg1); - cpu_push_context(screen->machine->cpu[2]); - sharc_set_flag_input(1, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(screen->machine->cpu[2], 1, ASSERT_LINE); return 0; } @@ -293,9 +291,7 @@ static VIDEO_UPDATE( zr107 ) draw_7segment_led(bitmap, 3, 3, led_reg0); draw_7segment_led(bitmap, 9, 3, led_reg1); - cpu_push_context(screen->machine->cpu[2]); - sharc_set_flag_input(1, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(screen->machine->cpu[2], 1, ASSERT_LINE); return 0; } diff --git a/src/mame/machine/konppc.c b/src/mame/machine/konppc.c index 5934e5aa9ff..668499c3eba 100644 --- a/src/mame/machine/konppc.c +++ b/src/mame/machine/konppc.c @@ -225,9 +225,7 @@ static void dsp_comm_sharc_w(const address_space *space, int board, int offset, case CGBOARD_TYPE_GTICLUB: { //cpu_set_input_line(machine->cpu[2], SHARC_INPUT_FLAG0, ASSERT_LINE); - cpu_push_context(space->machine->cpu[2]); - sharc_set_flag_input(0, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(space->machine->cpu[2], 0, ASSERT_LINE); if (offset == 1) { @@ -246,9 +244,7 @@ static void dsp_comm_sharc_w(const address_space *space, int board, int offset, if (data & 0x01 || data & 0x10) { - cpu_push_context(space->machine->cpu[board == 0 ? 2 : 3]); - sharc_set_flag_input(1, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(space->machine->cpu[board == 0 ? 2 : 3], 1, ASSERT_LINE); } if (texture_bank[board] != -1) @@ -359,28 +355,20 @@ static UINT32 nwk_fifo_r(int board) if (nwk_fifo_read_ptr[board] < nwk_fifo_half_full_r) { - cpu_push_context(Machine->cpu[cpu]); - sharc_set_flag_input(1, CLEAR_LINE); - cpu_pop_context(); + sharc_set_flag_input(Machine->cpu[cpu], 1, CLEAR_LINE); } else { - cpu_push_context(Machine->cpu[cpu]); - sharc_set_flag_input(1, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(Machine->cpu[cpu], 1, ASSERT_LINE); } if (nwk_fifo_read_ptr[board] < nwk_fifo_full) { - cpu_push_context(Machine->cpu[cpu]); - sharc_set_flag_input(2, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(Machine->cpu[cpu], 2, ASSERT_LINE); } else { - cpu_push_context(Machine->cpu[cpu]); - sharc_set_flag_input(2, CLEAR_LINE); - cpu_pop_context(); + sharc_set_flag_input(Machine->cpu[cpu], 2, CLEAR_LINE); } data = nwk_fifo[board][nwk_fifo_read_ptr[board]]; @@ -396,20 +384,14 @@ static void nwk_fifo_w(int board, UINT32 data) if (nwk_fifo_write_ptr[board] < nwk_fifo_half_full_w) { - cpu_push_context(Machine->cpu[cpu]); - sharc_set_flag_input(1, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(Machine->cpu[cpu], 1, ASSERT_LINE); } else { - cpu_push_context(Machine->cpu[cpu]); - sharc_set_flag_input(1, CLEAR_LINE); - cpu_pop_context(); + sharc_set_flag_input(Machine->cpu[cpu], 1, CLEAR_LINE); } - cpu_push_context(Machine->cpu[cpu]); - sharc_set_flag_input(2, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(Machine->cpu[cpu], 2, ASSERT_LINE); nwk_fifo[board][nwk_fifo_write_ptr[board]] = data; nwk_fifo_write_ptr[board]++; diff --git a/src/mame/video/gticlub.c b/src/mame/video/gticlub.c index 227fc6bb8d2..af467e7faa6 100644 --- a/src/mame/video/gticlub.c +++ b/src/mame/video/gticlub.c @@ -317,24 +317,18 @@ READ32_HANDLER( K001005_r ) if (K001005_fifo_read_ptr < 0x3ff) { //cpu_set_input_line(space->machine->cpu[2], SHARC_INPUT_FLAG1, CLEAR_LINE); - cpu_push_context(space->machine->cpu[2]); - sharc_set_flag_input(1, CLEAR_LINE); - cpu_pop_context(); + sharc_set_flag_input(space->machine->cpu[2], 1, CLEAR_LINE); } else { //cpu_set_input_line(space->machine->cpu[2], SHARC_INPUT_FLAG1, ASSERT_LINE); - cpu_push_context(space->machine->cpu[2]); - sharc_set_flag_input(1, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(space->machine->cpu[2], 1, ASSERT_LINE); } } else { //cpu_set_input_line(space->machine->cpu[2], SHARC_INPUT_FLAG1, ASSERT_LINE); - cpu_push_context(space->machine->cpu[2]); - sharc_set_flag_input(1, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(space->machine->cpu[2], 1, ASSERT_LINE); } K001005_fifo_read_ptr++; @@ -376,24 +370,18 @@ WRITE32_HANDLER( K001005_w ) if (K001005_fifo_write_ptr < 0x400) { //cpu_set_input_line(space->machine->cpu[2], SHARC_INPUT_FLAG1, ASSERT_LINE); - cpu_push_context(space->machine->cpu[2]); - sharc_set_flag_input(1, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(space->machine->cpu[2], 1, ASSERT_LINE); } else { //cpu_set_input_line(space->machine->cpu[2], SHARC_INPUT_FLAG1, CLEAR_LINE); - cpu_push_context(space->machine->cpu[2]); - sharc_set_flag_input(1, CLEAR_LINE); - cpu_pop_context(); + sharc_set_flag_input(space->machine->cpu[2], 1, CLEAR_LINE); } } else { //cpu_set_input_line(space->machine->cpu[2], SHARC_INPUT_FLAG1, ASSERT_LINE); - cpu_push_context(space->machine->cpu[2]); - sharc_set_flag_input(1, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(space->machine->cpu[2], 1, ASSERT_LINE); } // mame_printf_debug("K001005 FIFO write: %08X at %08X\n", data, cpu_get_pc(space->cpu)); @@ -1059,9 +1047,7 @@ VIDEO_UPDATE( gticlub ) draw_7segment_led(bitmap, 9, 3, gticlub_led_reg1); //cpu_set_input_line(screen->machine->cpu[2], SHARC_INPUT_FLAG1, ASSERT_LINE); - cpu_push_context(screen->machine->cpu[2]); - sharc_set_flag_input(1, ASSERT_LINE); - cpu_pop_context(); + sharc_set_flag_input(screen->machine->cpu[2], 1, ASSERT_LINE); return 0; }