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i8085.c: Modernized cpu core (nw)

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This commit is contained in:
Wilbert Pol 2013-08-03 13:15:43 +00:00
parent da2504eddb
commit f0a18ca7a6
18 changed files with 757 additions and 922 deletions
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1194
src/emu/cpu/i8085/i8085.c
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File diff suppressed because it is too large Load Diff

154
src/emu/cpu/i8085/i8085.h
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@ -32,29 +32,149 @@ enum
#define I8085_STATUS_INP 0x40
#define I8085_STATUS_MEMR 0x80
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/
struct i8085_config
/* STATUS changed callback */
#define MCFG_I8085A_STATUS(_devcb) \
i8085a_cpu_device::set_out_status_func(*device, DEVCB2_##_devcb);
/* INTE changed callback */
#define MCFG_I8085A_INTE(_devcb) \
i8085a_cpu_device::set_out_inte_func(*device, DEVCB2_##_devcb);
/* SID changed callback (8085A only) */
#define MCFG_I8085A_SID(_devcb) \
i8085a_cpu_device::set_in_sid_func(*device, DEVCB2_##_devcb);
/* SOD changed callback (8085A only) */
#define MCFG_I8085A_SOD(_devcb) \
i8085a_cpu_device::set_out_sod_func(*device, DEVCB2_##_devcb);
class i8085a_cpu_device : public cpu_device
{
devcb_write8 out_status_func; /* STATUS changed callback */
devcb_write_line out_inte_func; /* INTE changed callback */
devcb_read_line in_sid_func; /* SID changed callback (8085A only) */
devcb_write_line out_sod_func; /* SOD changed callback (8085A only) */
public:
// construction/destruction
i8085a_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
i8085a_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, int cputype);
// static configuration helpers
template<class _Object> static devcb2_base &set_out_status_func(device_t &device, _Object object) { return downcast<i8085a_cpu_device &>(device).m_out_status_func.set_callback(object); }
template<class _Object> static devcb2_base &set_out_inte_func(device_t &device, _Object object) { return downcast<i8085a_cpu_device &>(device).m_out_inte_func.set_callback(object); }
template<class _Object> static devcb2_base &set_in_sid_func(device_t &device, _Object object) { return downcast<i8085a_cpu_device &>(device).m_in_sid_func.set_callback(object); }
template<class _Object> static devcb2_base &set_out_sod_func(device_t &device, _Object object) { return downcast<i8085a_cpu_device &>(device).m_out_sod_func.set_callback(object); }
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const { return 4; }
virtual UINT32 execute_max_cycles() const { return 16; }
virtual UINT32 execute_input_lines() const { return 4; }
virtual UINT32 execute_default_irq_vector() const { return 0xff; }
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 2 - 1) / 2; }
virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 2); }
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); }
// device_state_interface overrides
void state_string_export(const device_state_entry &entry, astring &string);
void state_export(const device_state_entry &entry);
void state_import(const device_state_entry &entry);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
virtual UINT32 disasm_max_opcode_bytes() const { return 3; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
private:
address_space_config m_program_config;
address_space_config m_io_config;
devcb2_write8 m_out_status_func;
devcb2_write_line m_out_inte_func;
devcb2_read_line m_in_sid_func;
devcb2_write_line m_out_sod_func;
int m_cputype; /* 0 8080, 1 8085A */
PAIR m_PC,m_SP,m_AF,m_BC,m_DE,m_HL,m_WZ;
UINT8 m_HALT;
UINT8 m_IM; /* interrupt mask (8085A only) */
UINT8 m_STATUS; /* status word */
UINT8 m_after_ei; /* post-EI processing; starts at 2, check for ints at 0 */
UINT8 m_nmi_state; /* raw NMI line state */
UINT8 m_irq_state[4]; /* raw IRQ line states */
UINT8 m_trap_pending; /* TRAP interrupt latched? */
UINT8 m_trap_im_copy; /* copy of IM register when TRAP was taken */
UINT8 m_sod_state; /* state of the SOD line */
UINT8 m_ietemp; /* import/export temp space */
device_irq_acknowledge_callback m_irq_callback;
legacy_cpu_device *m_device;
address_space *m_program;
direct_read_data *m_direct;
address_space *m_io;
int m_icount;
/* cycles lookup */
static const UINT8 lut_cycles_8080[256];
static const UINT8 lut_cycles_8085[256];
UINT8 lut_cycles[256];
/* flags lookup */
UINT8 ZS[256];
UINT8 ZSP[256];
void set_sod(int state);
void set_inte(int state);
void set_status(UINT8 status);
UINT8 get_rim_value();
void break_halt_for_interrupt();
UINT8 ROP();
UINT8 ARG();
UINT16 ARG16();
UINT8 RM(UINT32 a);
void WM(UINT32 a, UINT8 v);
void check_for_interrupts();
void execute_one(int opcode);
void init_tables();
};
#define I8085_CONFIG(name) const i8085_config (name) =
/***************************************************************************
FUNCTION PROTOTYPES
***************************************************************************/
DECLARE_LEGACY_CPU_DEVICE(I8080, i8080);
DECLARE_LEGACY_CPU_DEVICE(I8080A, i8080a);
DECLARE_LEGACY_CPU_DEVICE(I8085A, i8085);
class i8080_cpu_device : public i8085a_cpu_device
{
public:
// construction/destruction
i8080_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
CPU_DISASSEMBLE( i8085 );
protected:
virtual UINT32 execute_input_lines() const { return 1; }
virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return clocks; }
virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return cycles; }
};
#define i8085_set_sid(cpu, sid) (cpu)->state().set_state_int(I8085_SID, sid)
class i8080a_cpu_device : public i8085a_cpu_device
{
public:
// construction/destruction
i8080a_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
protected:
virtual UINT32 execute_input_lines() const { return 1; }
virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return clocks; }
virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return cycles; }
};
extern const device_type I8080;
extern const device_type I8080A;
extern const device_type I8085A;
#endif

132
src/emu/cpu/i8085/i8085cpu.h
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@ -36,122 +36,122 @@
#define ADDR_INTR 0x0038
#define M_MVI(R) R=ARG(cpustate)
#define M_MVI(R) R=ARG()
/* rotate */
#define M_RLC { \
cpustate->AF.b.h = (cpustate->AF.b.h << 1) | (cpustate->AF.b.h >> 7); \
cpustate->AF.b.l = (cpustate->AF.b.l & 0xfe) | (cpustate->AF.b.h & CF); \
m_AF.b.h = (m_AF.b.h << 1) | (m_AF.b.h >> 7); \
m_AF.b.l = (m_AF.b.l & 0xfe) | (m_AF.b.h & CF); \
}
#define M_RRC { \
cpustate->AF.b.l = (cpustate->AF.b.l & 0xfe) | (cpustate->AF.b.h & CF); \
cpustate->AF.b.h = (cpustate->AF.b.h >> 1) | (cpustate->AF.b.h << 7); \
m_AF.b.l = (m_AF.b.l & 0xfe) | (m_AF.b.h & CF); \
m_AF.b.h = (m_AF.b.h >> 1) | (m_AF.b.h << 7); \
}
#define M_RAL { \
int c = cpustate->AF.b.l&CF; \
cpustate->AF.b.l = (cpustate->AF.b.l & 0xfe) | (cpustate->AF.b.h >> 7); \
cpustate->AF.b.h = (cpustate->AF.b.h << 1) | c; \
int c = m_AF.b.l&CF; \
m_AF.b.l = (m_AF.b.l & 0xfe) | (m_AF.b.h >> 7); \
m_AF.b.h = (m_AF.b.h << 1) | c; \
}
#define M_RAR { \
int c = (cpustate->AF.b.l&CF) << 7; \
cpustate->AF.b.l = (cpustate->AF.b.l & 0xfe) | (cpustate->AF.b.h & CF); \
cpustate->AF.b.h = (cpustate->AF.b.h >> 1) | c; \
int c = (m_AF.b.l&CF) << 7; \
m_AF.b.l = (m_AF.b.l & 0xfe) | (m_AF.b.h & CF); \
m_AF.b.h = (m_AF.b.h >> 1) | c; \
}
/* logical */
#define M_ORA(R) cpustate->AF.b.h|=R; cpustate->AF.b.l=ZSP[cpustate->AF.b.h]
#define M_XRA(R) cpustate->AF.b.h^=R; cpustate->AF.b.l=ZSP[cpustate->AF.b.h]
#define M_ANA(R) {UINT8 hc = ((cpustate->AF.b.h | R)<<1) & HF; cpustate->AF.b.h&=R; cpustate->AF.b.l=ZSP[cpustate->AF.b.h]; if(IS_8085(cpustate)) { cpustate->AF.b.l |= HF; } else {cpustate->AF.b.l |= hc; } }
#define M_ORA(R) m_AF.b.h|=R; m_AF.b.l=ZSP[m_AF.b.h]
#define M_XRA(R) m_AF.b.h^=R; m_AF.b.l=ZSP[m_AF.b.h]
#define M_ANA(R) {UINT8 hc = ((m_AF.b.h | R)<<1) & HF; m_AF.b.h&=R; m_AF.b.l=ZSP[m_AF.b.h]; if(IS_8085()) { m_AF.b.l |= HF; } else {m_AF.b.l |= hc; } }
/* increase / decrease */
#define M_INR(R) {UINT8 hc = ((R & 0x0f) == 0x0f) ? HF : 0; ++R; cpustate->AF.b.l= (cpustate->AF.b.l & CF ) | ZSP[R] | hc; }
#define M_DCR(R) {UINT8 hc = ((R & 0x0f) != 0x00) ? HF : 0; --R; cpustate->AF.b.l= (cpustate->AF.b.l & CF ) | ZSP[R] | hc | VF; }
#define M_INR(R) {UINT8 hc = ((R & 0x0f) == 0x0f) ? HF : 0; ++R; m_AF.b.l= (m_AF.b.l & CF ) | ZSP[R] | hc; }
#define M_DCR(R) {UINT8 hc = ((R & 0x0f) != 0x00) ? HF : 0; --R; m_AF.b.l= (m_AF.b.l & CF ) | ZSP[R] | hc | VF; }
/* arithmetic */
#define M_ADD(R) { \
int q = cpustate->AF.b.h+R; \
cpustate->AF.b.l=ZSP[q&255]|((q>>8)&CF)|((cpustate->AF.b.h^q^R)&HF); \
cpustate->AF.b.h=q; \
int q = m_AF.b.h+R; \
m_AF.b.l=ZSP[q&255]|((q>>8)&CF)|((m_AF.b.h^q^R)&HF); \
m_AF.b.h=q; \
}
#define M_ADC(R) { \
int q = cpustate->AF.b.h+R+(cpustate->AF.b.l&CF); \
cpustate->AF.b.l=ZSP[q&255]|((q>>8)&CF)|((cpustate->AF.b.h^q^R)&HF); \
cpustate->AF.b.h=q; \
int q = m_AF.b.h+R+(m_AF.b.l&CF); \
m_AF.b.l=ZSP[q&255]|((q>>8)&CF)|((m_AF.b.h^q^R)&HF); \
m_AF.b.h=q; \
}
#define M_SUB(R) { \
int q = cpustate->AF.b.h-R; \
cpustate->AF.b.l=ZSP[q&255]|((q>>8)&CF)|(~(cpustate->AF.b.h^q^R)&HF)|VF; \
cpustate->AF.b.h=q; \
int q = m_AF.b.h-R; \
m_AF.b.l=ZSP[q&255]|((q>>8)&CF)|(~(m_AF.b.h^q^R)&HF)|VF; \
m_AF.b.h=q; \
}
#define M_SBB(R) { \
int q = cpustate->AF.b.h-R-(cpustate->AF.b.l&CF); \
cpustate->AF.b.l=ZSP[q&255]|((q>>8)&CF)|(~(cpustate->AF.b.h^q^R)&HF)|VF; \
cpustate->AF.b.h=q; \
int q = m_AF.b.h-R-(m_AF.b.l&CF); \
m_AF.b.l=ZSP[q&255]|((q>>8)&CF)|(~(m_AF.b.h^q^R)&HF)|VF; \
m_AF.b.h=q; \
}
#define M_CMP(R) { \
int q = cpustate->AF.b.h-R; \
cpustate->AF.b.l=ZSP[q&255]|((q>>8)&CF)|(~(cpustate->AF.b.h^q^R)&HF)|VF; \
int q = m_AF.b.h-R; \
m_AF.b.l=ZSP[q&255]|((q>>8)&CF)|(~(m_AF.b.h^q^R)&HF)|VF; \
}
#define M_DAD(R) { \
int q = cpustate->HL.d + cpustate->R.d; \
cpustate->AF.b.l = (cpustate->AF.b.l & ~CF) | (q>>16 & CF ); \
cpustate->HL.w.l = q; \
int q = m_HL.d + m_##R.d; \
m_AF.b.l = (m_AF.b.l & ~CF) | (q>>16 & CF ); \
m_HL.w.l = q; \
}
// DSUB is 8085-only, not sure if H flag handling is correct
#define M_DSUB(cpustate) { \
int q = cpustate->HL.b.l-cpustate->BC.b.l; \
cpustate->AF.b.l=ZS[q&255]|((q>>8)&CF)|VF| \
((cpustate->HL.b.l^q^cpustate->BC.b.l)&HF)| \
(((cpustate->BC.b.l^cpustate->HL.b.l)&(cpustate->HL.b.l^q)&SF)>>5); \
cpustate->HL.b.l=q; \
q = cpustate->HL.b.h-cpustate->BC.b.h-(cpustate->AF.b.l&CF); \
cpustate->AF.b.l=ZS[q&255]|((q>>8)&CF)|VF| \
((cpustate->HL.b.h^q^cpustate->BC.b.h)&HF)| \
(((cpustate->BC.b.h^cpustate->HL.b.h)&(cpustate->HL.b.h^q)&SF)>>5); \
if (cpustate->HL.b.l!=0) cpustate->AF.b.l&=~ZF; \
#define M_DSUB() { \
int q = m_HL.b.l-m_BC.b.l; \
m_AF.b.l=ZS[q&255]|((q>>8)&CF)|VF| \
((m_HL.b.l^q^m_BC.b.l)&HF)| \
(((m_BC.b.l^m_HL.b.l)&(m_HL.b.l^q)&SF)>>5); \
m_HL.b.l=q; \
q = m_HL.b.h-m_BC.b.h-(m_AF.b.l&CF); \
m_AF.b.l=ZS[q&255]|((q>>8)&CF)|VF| \
((m_HL.b.h^q^m_BC.b.h)&HF)| \
(((m_BC.b.h^m_HL.b.h)&(m_HL.b.h^q)&SF)>>5); \
if (m_HL.b.l!=0) m_AF.b.l&=~ZF; \
}
/* i/o */
#define M_IN \
cpustate->STATUS = 0x42; \
cpustate->WZ.d=ARG(cpustate); \
cpustate->AF.b.h=cpustate->io->read_byte(cpustate->WZ.d);
m_STATUS = 0x42; \
m_WZ.d=ARG(); \
m_AF.b.h=m_io->read_byte(m_WZ.d);
#define M_OUT \
cpustate->STATUS = 0x10; \
cpustate->WZ.d=ARG(cpustate); \
cpustate->io->write_byte(cpustate->WZ.d,cpustate->AF.b.h)
m_STATUS = 0x10; \
m_WZ.d=ARG(); \
m_io->write_byte(m_WZ.d,m_AF.b.h)
/* stack */
#define M_PUSH(R) { \
cpustate->STATUS = 0x04; \
cpustate->program->write_byte(--cpustate->SP.w.l, cpustate->R.b.h); \
cpustate->program->write_byte(--cpustate->SP.w.l, cpustate->R.b.l); \
m_STATUS = 0x04; \
m_program->write_byte(--m_SP.w.l, m_##R.b.h); \
m_program->write_byte(--m_SP.w.l, m_##R.b.l); \
}
#define M_POP(R) { \
cpustate->STATUS = 0x86; \
cpustate->R.b.l = cpustate->program->read_byte(cpustate->SP.w.l++); \
cpustate->R.b.h = cpustate->program->read_byte(cpustate->SP.w.l++); \
m_STATUS = 0x86; \
m_##R.b.l = m_program->read_byte(m_SP.w.l++); \
m_##R.b.h = m_program->read_byte(m_SP.w.l++); \
}
/* jumps */
// On 8085 jump if condition is not satisfied is shorter
#define M_JMP(cc) { \
if (cc) { \
cpustate->PC.w.l = ARG16(cpustate); \
m_PC.w.l = ARG16(); \
} else { \
cpustate->PC.w.l += 2; \
cpustate->icount += (IS_8085(cpustate)) ? 3 : 0; \
m_PC.w.l += 2; \
m_icount += (IS_8085()) ? 3 : 0; \
} \
}
@ -160,13 +160,13 @@
{ \
if (cc) \
{ \
UINT16 a = ARG16(cpustate); \
cpustate->icount -= (IS_8085(cpustate)) ? 7 : 6 ; \
UINT16 a = ARG16(); \
m_icount -= (IS_8085()) ? 7 : 6 ; \
M_PUSH(PC); \
cpustate->PC.d = a; \
m_PC.d = a; \
} else { \
cpustate->PC.w.l += 2; \
cpustate->icount += (IS_8085(cpustate)) ? 2 : 0; \
m_PC.w.l += 2; \
m_icount += (IS_8085()) ? 2 : 0; \
} \
}
@ -175,12 +175,12 @@
{ \
if (cc) \
{ \
cpustate->icount -= 6; \
m_icount -= 6; \
M_POP(PC); \
} \
}
#define M_RST(nn) { \
M_PUSH(PC); \
cpustate->PC.d = 8 * nn; \
m_PC.d = 8 * nn; \
}

12
src/mame/audio/redalert.c
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@ -171,15 +171,6 @@ READ_LINE_MEMBER(redalert_state::sid_callback)
}
static I8085_CONFIG( redalert_voice_i8085_config )
{
DEVCB_NULL, /* STATUS changed callback */
DEVCB_NULL, /* INTE changed callback */
DEVCB_DRIVER_LINE_MEMBER(redalert_state,sid_callback), /* SID changed callback (8085A only) */
DEVCB_DRIVER_LINE_MEMBER(redalert_state,sod_callback) /* SOD changed callback (8085A only) */
};
static ADDRESS_MAP_START( redalert_voice_map, AS_PROGRAM, 8, redalert_state )
AM_RANGE(0x0000, 0x3fff) AM_ROM
AM_RANGE(0x4000, 0x7fff) AM_NOP
@ -231,8 +222,9 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_FRAGMENT( redalert_audio_voice )
MCFG_CPU_ADD("voice", I8085A, REDALERT_VOICE_CPU_CLOCK)
MCFG_CPU_CONFIG(redalert_voice_i8085_config)
MCFG_CPU_PROGRAM_MAP(redalert_voice_map)
MCFG_I8085A_SID(READLINE(redalert_state,sid_callback))
MCFG_I8085A_SOD(WRITELINE(redalert_state,sod_callback))
MCFG_SOUND_ADD("cvsd", HC55516, REDALERT_HC55516_CLOCK)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)

12
src/mame/drivers/dwarfd.c
View File

@ -856,16 +856,6 @@ WRITE_LINE_MEMBER(dwarfd_state::dwarfd_sod_callback)
m_crt_access = state;
}
static I8085_CONFIG( dwarfd_i8085_config )
{
DEVCB_NULL, /* STATUS changed callback */
DEVCB_NULL, /* INTE changed callback */
DEVCB_NULL, /* SID changed callback (8085A only) */
DEVCB_DRIVER_LINE_MEMBER(dwarfd_state,dwarfd_sod_callback) /* SOD changed callback (8085A only) */
};
TIMER_DEVICE_CALLBACK_MEMBER(dwarfd_state::dwarfd_interrupt)
{
int scanline = param;
@ -1062,7 +1052,7 @@ static MACHINE_CONFIG_START( dwarfd, dwarfd_state )
/* basic machine hardware */
/* FIXME: The 8085A had a max clock of 6MHz, internally divided by 2! */
MCFG_CPU_ADD("maincpu", I8085A, 10595000/3*2) /* ? MHz */
MCFG_CPU_CONFIG(dwarfd_i8085_config)
MCFG_I8085A_SOD(WRITELINE(dwarfd_state,dwarfd_sod_callback))
MCFG_CPU_PROGRAM_MAP(mem_map)
MCFG_CPU_IO_MAP(io_map)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", dwarfd_state, dwarfd_interrupt, "screen", 0, 1)

20
src/mame/drivers/n8080.c
View File

@ -458,14 +458,6 @@ WRITE8_MEMBER(n8080_state::n8080_status_callback)
}
}
static I8085_CONFIG( n8080_cpu_config )
{
DEVCB_DRIVER_MEMBER(n8080_state,n8080_status_callback), /* STATUS changed callback */
DEVCB_DRIVER_LINE_MEMBER(n8080_state,n8080_inte_callback), /* INTE changed callback */
DEVCB_NULL, /* SID changed callback (8085A only) */
DEVCB_NULL /* SOD changed callback (8085A only) */
};
MACHINE_START_MEMBER(n8080_state,n8080)
{
save_item(NAME(m_shift_data));
@ -532,7 +524,8 @@ static MACHINE_CONFIG_START( spacefev, n8080_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", I8080, MASTER_CLOCK / 10)
MCFG_CPU_CONFIG(n8080_cpu_config)
MCFG_I8085A_STATUS(WRITE8(n8080_state,n8080_status_callback))
MCFG_I8085A_INTE(WRITELINE(n8080_state,n8080_inte_callback))
MCFG_CPU_PROGRAM_MAP(main_cpu_map)
MCFG_CPU_IO_MAP(main_io_map)
@ -562,7 +555,8 @@ static MACHINE_CONFIG_START( sheriff, n8080_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", I8080, MASTER_CLOCK / 10)
MCFG_CPU_CONFIG(n8080_cpu_config)
MCFG_I8085A_STATUS(WRITE8(n8080_state,n8080_status_callback))
MCFG_I8085A_INTE(WRITELINE(n8080_state,n8080_inte_callback))
MCFG_CPU_PROGRAM_MAP(main_cpu_map)
MCFG_CPU_IO_MAP(main_io_map)
@ -592,7 +586,8 @@ static MACHINE_CONFIG_DERIVED( westgun2, sheriff )
/* basic machine hardware */
MCFG_CPU_REPLACE("maincpu", I8080, XTAL_19_968MHz / 10)
MCFG_CPU_CONFIG(n8080_cpu_config)
MCFG_I8085A_STATUS(WRITE8(n8080_state,n8080_status_callback))
MCFG_I8085A_INTE(WRITELINE(n8080_state,n8080_inte_callback))
MCFG_CPU_PROGRAM_MAP(main_cpu_map)
MCFG_CPU_IO_MAP(main_io_map)
@ -603,7 +598,8 @@ static MACHINE_CONFIG_START( helifire, n8080_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", I8080, MASTER_CLOCK / 10)
MCFG_CPU_CONFIG(n8080_cpu_config)
MCFG_I8085A_STATUS(WRITE8(n8080_state,n8080_status_callback))
MCFG_I8085A_INTE(WRITELINE(n8080_state,n8080_inte_callback))
MCFG_CPU_PROGRAM_MAP(helifire_main_cpu_map)
MCFG_CPU_IO_MAP(main_io_map)

10
src/mame/drivers/phoenix.c
View File

@ -509,19 +509,11 @@ MACHINE_CONFIG_END
/* Same as Phoenix, but uses an AY8910 and an extra visible line (column) */
static I8085_CONFIG( survival_i8085_config )
{
DEVCB_NULL, /* STATUS changed callback */
DEVCB_NULL, /* INTE changed callback */
DEVCB_DRIVER_LINE_MEMBER(phoenix_state, survival_sid_callback), /* SID changed callback (8085A only) */
DEVCB_NULL /* SOD changed callback (8085A only) */
};
static MACHINE_CONFIG_START( survival, phoenix_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", I8085A, CPU_CLOCK) /* 5.50 MHz */
MCFG_CPU_CONFIG(survival_i8085_config)
MCFG_I8085A_SID(READLINE(phoenix_state, survival_sid_callback))
MCFG_CPU_PROGRAM_MAP(survival_memory_map)
MCFG_MACHINE_RESET_OVERRIDE(phoenix_state,phoenix)

2
src/mame/video/phoenix.c
View File

@ -431,7 +431,7 @@ READ8_MEMBER(phoenix_state::survival_protection_r)
READ_LINE_MEMBER(phoenix_state::survival_sid_callback)
{
return m_survival_sid_value;
return m_survival_sid_value ? ASSERT_LINE : CLEAR_LINE;
}

11
src/mess/drivers/bob85.c
View File

@ -205,20 +205,13 @@ READ_LINE_MEMBER( bob85_state::sid_r )
return m_cass->input() > 0.0;
}
static I8085_CONFIG( cpu_config )
{
DEVCB_NULL, /* STATUS changed callback */
DEVCB_NULL, /* INTE changed callback */
DEVCB_DRIVER_LINE_MEMBER(bob85_state, sid_r), /* SID changed callback (I8085A only) */
DEVCB_DRIVER_LINE_MEMBER(bob85_state, sod_w) /* SOD changed callback (I8085A only) */
};
static MACHINE_CONFIG_START( bob85, bob85_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", I8085A, XTAL_5MHz)
MCFG_CPU_PROGRAM_MAP(bob85_mem)
MCFG_CPU_IO_MAP(bob85_io)
MCFG_CPU_CONFIG(cpu_config)
MCFG_I8085A_SID(READLINE(bob85_state, sid_r))
MCFG_I8085A_SOD(WRITELINE(bob85_state, sod_w))
/* video hardware */
MCFG_DEFAULT_LAYOUT(layout_bob85)

11
src/mess/drivers/exp85.c
View File

@ -171,14 +171,6 @@ WRITE_LINE_MEMBER( exp85_state::sod_w )
}
}
static I8085_CONFIG( exp85_i8085_config )
{
DEVCB_NULL,
DEVCB_NULL,
DEVCB_DRIVER_LINE_MEMBER(exp85_state, sid_r),
DEVCB_DRIVER_LINE_MEMBER(exp85_state, sod_w)
};
/* Terminal Interface */
static DEVICE_INPUT_DEFAULTS_START( terminal )
@ -221,7 +213,8 @@ static MACHINE_CONFIG_START( exp85, exp85_state )
MCFG_CPU_ADD(I8085A_TAG, I8085A, XTAL_6_144MHz)
MCFG_CPU_PROGRAM_MAP(exp85_mem)
MCFG_CPU_IO_MAP(exp85_io)
MCFG_CPU_CONFIG(exp85_i8085_config)
MCFG_I8085A_SID(READLINE(exp85_state, sid_r))
MCFG_I8085A_SOD(WRITELINE(exp85_state, sod_w))
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")

11
src/mess/drivers/fp200.c
View File

@ -575,21 +575,14 @@ READ_LINE_MEMBER( fp200_state::sid_r )
return (ioport("KEYMOD")->read() >> m_keyb_mux) & 1;
}
static I8085_CONFIG( cpu_config )
{
DEVCB_NULL, /* STATUS changed callback */
DEVCB_NULL, /* INTE changed callback */
DEVCB_DRIVER_LINE_MEMBER(fp200_state, sid_r), /* SID changed callback (I8085A only) */
DEVCB_DRIVER_LINE_MEMBER(fp200_state, sod_w) /* SOD changed callback (I8085A only) */
};
static MACHINE_CONFIG_START( fp200, fp200_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu",I8085A,MAIN_CLOCK)
MCFG_CPU_PROGRAM_MAP(fp200_map)
MCFG_CPU_IO_MAP(fp200_io)
MCFG_CPU_CONFIG(cpu_config)
MCFG_I8085A_SID(READLINE(fp200_state, sid_r))
MCFG_I8085A_SOD(WRITELINE(fp200_state, sod_w))
/* video hardware */
MCFG_SCREEN_ADD("screen", LCD)

11
src/mess/drivers/h8.c
View File

@ -283,14 +283,6 @@ static const i8251_interface uart_intf =
DEVCB_NULL
};
static I8085_CONFIG( h8_cpu_config )
{
DEVCB_DRIVER_MEMBER(h8_state, h8_status_callback), /* Status changed callback */
DEVCB_DRIVER_LINE_MEMBER(h8_state, h8_inte_callback), /* INTE changed callback */
DEVCB_NULL, /* SID changed callback (I8085A only) */
DEVCB_NULL /* SOD changed callback (I8085A only) */
};
TIMER_DEVICE_CALLBACK_MEMBER(h8_state::h8_c)
{
m_uart->receive_clock();
@ -332,7 +324,8 @@ static MACHINE_CONFIG_START( h8, h8_state )
MCFG_CPU_ADD("maincpu", I8080, H8_CLOCK)
MCFG_CPU_PROGRAM_MAP(h8_mem)
MCFG_CPU_IO_MAP(h8_io)
MCFG_CPU_CONFIG(h8_cpu_config)
MCFG_I8085A_STATUS(WRITE8(h8_state, h8_status_callback))
MCFG_I8085A_INTE(WRITELINE(h8_state, h8_inte_callback))
/* video hardware */
MCFG_DEFAULT_LAYOUT(layout_h8)

20
src/mess/drivers/kyocera.c
View File

@ -1312,14 +1312,6 @@ READ_LINE_MEMBER( kc85_state::kc85_sid_r )
return m_cassette->input() > 0.0;
}
static I8085_CONFIG( kc85_i8085_config )
{
DEVCB_NULL, /* STATUS changed callback */
DEVCB_NULL, /* INTE changed callback */
DEVCB_DRIVER_LINE_MEMBER(kc85_state,kc85_sid_r), /* SID changed callback (I8085A only) */
DEVCB_DRIVER_LINE_MEMBER(kc85_state,kc85_sod_w) /* SOD changed callback (I8085A only) */
};
TIMER_DEVICE_CALLBACK_MEMBER(tandy200_state::tandy200_tp_tick)
{
m_maincpu->set_input_line(I8085_RST75_LINE, m_tp);
@ -1332,7 +1324,8 @@ static MACHINE_CONFIG_START( kc85, kc85_state )
MCFG_CPU_ADD(I8085_TAG, I8085A, XTAL_4_9152MHz)
MCFG_CPU_PROGRAM_MAP(kc85_mem)
MCFG_CPU_IO_MAP(kc85_io)
MCFG_CPU_CONFIG(kc85_i8085_config)
MCFG_I8085A_SID(READLINE(kc85_state,kc85_sid_r))
MCFG_I8085A_SOD(WRITELINE(kc85_state,kc85_sod_w))
/* video hardware */
MCFG_FRAGMENT_ADD(kc85_video)
@ -1370,7 +1363,8 @@ static MACHINE_CONFIG_START( pc8201, pc8201_state )
MCFG_CPU_ADD(I8085_TAG, I8085A, XTAL_4_9152MHz)
MCFG_CPU_PROGRAM_MAP(pc8201_mem)
MCFG_CPU_IO_MAP(pc8201_io)
MCFG_CPU_CONFIG(kc85_i8085_config)
MCFG_I8085A_SID(READLINE(kc85_state,kc85_sid_r))
MCFG_I8085A_SOD(WRITELINE(kc85_state,kc85_sod_w))
/* video hardware */
MCFG_FRAGMENT_ADD(kc85_video)
@ -1414,7 +1408,8 @@ static MACHINE_CONFIG_START( trsm100, trsm100_state )
MCFG_CPU_ADD(I8085_TAG, I8085A, XTAL_4_9152MHz)
MCFG_CPU_PROGRAM_MAP(kc85_mem)
MCFG_CPU_IO_MAP(trsm100_io)
MCFG_CPU_CONFIG(kc85_i8085_config)
MCFG_I8085A_SID(READLINE(kc85_state,kc85_sid_r))
MCFG_I8085A_SOD(WRITELINE(kc85_state,kc85_sod_w))
/* video hardware */
MCFG_FRAGMENT_ADD(kc85_video)
@ -1459,7 +1454,8 @@ static MACHINE_CONFIG_START( tandy200, tandy200_state )
MCFG_CPU_ADD(I8085_TAG, I8085A, XTAL_4_9152MHz)
MCFG_CPU_PROGRAM_MAP(tandy200_mem)
MCFG_CPU_IO_MAP(tandy200_io)
MCFG_CPU_CONFIG(kc85_i8085_config)
MCFG_I8085A_SID(READLINE(kc85_state,kc85_sid_r))
MCFG_I8085A_SOD(WRITELINE(kc85_state,kc85_sod_w))
/* video hardware */
MCFG_FRAGMENT_ADD(tandy200_video)

15
src/mess/drivers/mikromik.c
View File

@ -648,23 +648,11 @@ static UPD7201_INTERFACE( mpsc_intf )
};
//-------------------------------------------------
// I8085_CONFIG( i8085_intf )
//-------------------------------------------------
READ_LINE_MEMBER( mm1_state::dsra_r )
{
return 1;
}
static I8085_CONFIG( i8085_intf )
{
DEVCB_NULL, // STATUS changed callback
DEVCB_NULL, // INTE changed callback
DEVCB_DRIVER_LINE_MEMBER(mm1_state, dsra_r), // SID changed callback (I8085A only)
DEVCB_DEVICE_LINE_MEMBER("speaker", speaker_sound_device, level_w) // SOD changed callback (I8085A only)
};
//-------------------------------------------------
// upd765_interface fdc_intf
@ -794,7 +782,8 @@ static MACHINE_CONFIG_START( mm1, mm1_state )
// basic system hardware
MCFG_CPU_ADD(I8085A_TAG, I8085A, XTAL_6_144MHz)
MCFG_CPU_PROGRAM_MAP(mm1_map)
MCFG_CPU_CONFIG(i8085_intf)
MCFG_I8085A_SID(READLINE(mm1_state, dsra_r))
MCFG_I8085A_SOD(DEVWRITELINE("speaker", speaker_sound_device, level_w))
MCFG_QUANTUM_PERFECT_CPU(I8085A_TAG)
MCFG_TIMER_DRIVER_ADD_PERIODIC("kbclk", mm1_state, kbclk_tick, attotime::from_hz(2500))

11
src/mess/drivers/mmd1.c
View File

@ -435,14 +435,6 @@ WRITE_LINE_MEMBER( mmd1_state::mmd2_inte_callback )
output_set_value("led_inte", state);
}
static I8085_CONFIG( mmd2_cpu_config )
{
DEVCB_DRIVER_MEMBER(mmd1_state, mmd2_status_callback), /* Status changed callback */
DEVCB_DRIVER_LINE_MEMBER(mmd1_state, mmd2_inte_callback), /* INTE changed callback */
DEVCB_NULL, /* SID changed callback (I8085A only) */
DEVCB_NULL /* SOD changed callback (I8085A only) */
};
MACHINE_RESET_MEMBER(mmd1_state,mmd1)
{
m_return_code = 0xff;
@ -510,7 +502,8 @@ static MACHINE_CONFIG_START( mmd2, mmd1_state )
MCFG_CPU_ADD("maincpu",I8080, 6750000 / 9)
MCFG_CPU_PROGRAM_MAP(mmd2_mem)
MCFG_CPU_IO_MAP(mmd2_io)
MCFG_CPU_CONFIG(mmd2_cpu_config)
MCFG_I8085A_STATUS(WRITE8(mmd1_state, mmd2_status_callback))
MCFG_I8085A_INTE(WRITELINE(mmd1_state, mmd2_inte_callback))
MCFG_MACHINE_RESET_OVERRIDE(mmd1_state,mmd2)

11
src/mess/drivers/sitcom.c
View File

@ -114,20 +114,13 @@ WRITE_LINE_MEMBER( sitcom_state::sod_led )
output_set_value("sod_led", state);
}
static I8085_CONFIG( sitcom_cpu_config )
{
DEVCB_NULL, /* Status changed callback */
DEVCB_NULL, /* INTE changed callback */
DEVCB_DRIVER_LINE_MEMBER(sitcom_state, sid_line), /* SID changed callback (I8085A only) */
DEVCB_DRIVER_LINE_MEMBER(sitcom_state, sod_led) /* SOD changed callback (I8085A only) */
};
static MACHINE_CONFIG_START( sitcom, sitcom_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", I8085A, XTAL_6_144MHz) // 3.072MHz can be used for an old slow 8085
MCFG_CPU_PROGRAM_MAP(sitcom_mem)
MCFG_CPU_IO_MAP(sitcom_io)
MCFG_CPU_CONFIG(sitcom_cpu_config)
MCFG_I8085A_SID(READLINE(sitcom_state, sid_line))
MCFG_I8085A_SOD(WRITELINE(sitcom_state, sod_led))
/* video hardware */
MCFG_DL1416B_ADD("ds0", sitcom_ds0_intf)

28
src/mess/drivers/tdv2324.c
View File

@ -241,32 +241,6 @@ UINT32 tdv2324_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap,
// DEVICE CONFIGURATION
//**************************************************************************
//-------------------------------------------------
// I8085_CONFIG( i8085_intf )
//-------------------------------------------------
static I8085_CONFIG( i8085_intf )
{
DEVCB_NULL, /* STATUS changed callback */
DEVCB_NULL, /* INTE changed callback */
DEVCB_NULL, /* SID changed callback (I8085A only) */
DEVCB_NULL /* SOD changed callback (I8085A only) */
};
//-------------------------------------------------
// I8085_CONFIG( i8085_sub_intf )
//-------------------------------------------------
static I8085_CONFIG( i8085_sub_intf )
{
DEVCB_NULL, /* STATUS changed callback */
DEVCB_NULL, /* INTE changed callback */
DEVCB_NULL, /* SID changed callback (I8085A only) */
DEVCB_NULL /* SOD changed callback (I8085A only) */
};
//-------------------------------------------------
// pit8253_config pit0_intf
//-------------------------------------------------
@ -375,12 +349,10 @@ static MACHINE_CONFIG_START( tdv2324, tdv2324_state )
MCFG_CPU_ADD(P8085AH_0_TAG, I8085A, 8700000/2) // ???
MCFG_CPU_PROGRAM_MAP(tdv2324_mem)
MCFG_CPU_IO_MAP(tdv2324_io)
MCFG_CPU_CONFIG(i8085_intf)
MCFG_CPU_ADD(P8085AH_1_TAG, I8085A, 8000000/2) // ???
MCFG_CPU_PROGRAM_MAP(tdv2324_sub_mem)
MCFG_CPU_IO_MAP(tdv2324_sub_io)
MCFG_CPU_CONFIG(i8085_sub_intf)
MCFG_CPU_ADD(MC68B02P_TAG, M6802, 8000000/2) // ???
MCFG_CPU_PROGRAM_MAP(tdv2324_fdc_mem)

14
src/mess/machine/shark.c
View File

@ -71,19 +71,6 @@ static ADDRESS_MAP_START( shark_io, AS_IO, 8, shark_device )
ADDRESS_MAP_END
//-------------------------------------------------
// I8085_CONFIG( cpu_intf )
//-------------------------------------------------
static I8085_CONFIG( cpu_intf )
{
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL
};
//-------------------------------------------------
// rs232_port_interface rs232_intf
//-------------------------------------------------
@ -105,7 +92,6 @@ static const rs232_port_interface rs232_intf =
static MACHINE_CONFIG_FRAGMENT( shark )
// basic machine hardware
MCFG_CPU_ADD(I8085_TAG, I8085A, 1000000)
MCFG_CPU_CONFIG(cpu_intf)
MCFG_CPU_PROGRAM_MAP(shark_mem)
MCFG_CPU_IO_MAP(shark_io)