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pci/z36057.cpp: implement enough to make it reach i2c negotiations
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@ -1,5 +1,5 @@
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// license:BSD-3-Clause
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// copyright-holders:
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// copyright-holders: Angelo Salese
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/**************************************************************************************************
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Zoran ZR36057 / ZR36067 PCI-based chipsets
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@ -8,8 +8,18 @@ PCI glue logic for multimedia MJPEG, MPEG1 & DVD.
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Paired with every single TV standard for video capture in the fairly decent number of subvendor
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iterations.
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- https://www.kernel.org/doc/html/v4.14/media/v4l-drivers/zoran.html
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- misc/sliver.cpp uses ZR36050
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- misc/magictg.cpp uses ZR36016
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- Currently using DC10+ configuration:
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ZR36067 + ZR36060 (ZR36050 + ZR36016 glued together)
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SAA7110a (TV decoder) + adv7176 (TV encoder)
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- misc/sliver.cpp uses ZR36050 + ZR36011
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- misc/magictg.cpp uses ZR36120 + ZR36050 + ZR36016
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ZR36057 is known to have two HW quirks that are been fixed with ZR36067.
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TODO:
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- Currently at dc10plus HW test "Error at video decoder", requires SAA7110a to continue;
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- Hookup busmaster;
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- Stub, eventually decouple AV PCI controller part from the actual client cards;
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- Soft Reset & Write lock mechanisms (each register have separate macro-groups);
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**************************************************************************************************/
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@ -41,7 +51,7 @@ zr36057_device::zr36057_device(const machine_config &mconfig, device_type type,
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// - 0x13ca4231: Iomega JPEG/TV Card
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// NOTE: subvendor is omitted in '36057 design (missing?), driven at PCIRST time to 32 pins in
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// '36067 thru pull-up or pull-down resistors (subvendor responsibility?)
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set_ids(0x11de6057, 0x01, 0x040000, 0x10317efe);
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set_ids(0x11de6057, 0x02, 0x040000, 0x10317efe);
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}
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zr36057_device::zr36057_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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@ -58,7 +68,7 @@ void zr36057_device::device_start()
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{
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pci_card_device::device_start();
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add_map(4096, M_MEM, FUNC(zr36057_device::map));
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add_map(4 * 1024, M_MEM, FUNC(zr36057_device::asr_map));
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// INTA#
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intr_pin = 1;
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@ -68,20 +78,124 @@ void zr36057_device::device_reset()
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{
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pci_card_device::device_reset();
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// fast DEVSEL#
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// fast DEVSEL# (00), can enable busmaster
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command = 0x0000;
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command_mask = 0x0006;
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status = 0x0000;
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intr_line = 0x0a;
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// TODO: PCI regs 0x3e/0x3f max_lat = 0x10 (4 usec), min_gnt = 0x02 (0.5 usec)
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remap_cb();
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m_softreset = 0;
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software_reset();
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}
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void zr36057_device::software_reset()
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{
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LOG("SoftReset\n");
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m_video_frontend.horizontal_config = (0 << 30) | (0x001 << 10) | (0x3ff << 0);
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m_video_frontend.vertical_config = (0 << 30) | (0x001 << 10) | (0x3ff << 0);
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m_pci_waitstate_control = 0;
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m_gpio_ddr = 0xff; // all inputs
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// GuestBus ID default
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// m_gpio_data = 0xf0;
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for (int i = 0; i < 4; i++)
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m_guestbus.time[i] = 0;
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}
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void zr36057_device::config_map(address_map &map)
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{
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pci_card_device::config_map(map);
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map(0x3e, 0x3e).lr8(NAME([] () { return 0x02; }));
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map(0x3f, 0x3f).lr8(NAME([] () { return 0x10; }));
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}
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void zr36057_device::map(address_map &map)
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// Application Specific Register
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void zr36057_device::asr_map(address_map &map)
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{
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map(0x000, 0x003).lrw32(
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NAME([this] (offs_t offset) {
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// NOTE: wants to read-back here, throws "Bus Master ASIC error" otherwise (?)
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LOG("Video Front End Horizontal Configuration R\n");
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return m_video_frontend.horizontal_config;
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}),
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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COMBINE_DATA(&m_video_frontend.horizontal_config);
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LOG("Video Front End Horizontal Configuration W %08x & %08x\n", data, mem_mask);
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})
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);
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map(0x004, 0x007).lrw32(
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NAME([this] (offs_t offset) {
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LOG("Video Front End Vertical Configuration R\n");
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return m_video_frontend.vertical_config;
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}),
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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COMBINE_DATA(&m_video_frontend.vertical_config);
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LOG("Video Front End Vertical Configuration %08x & %08\n", data, mem_mask);
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})
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);
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// ...
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map(0x028, 0x02b).lrw32(
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NAME([this] (offs_t offset) {
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return (m_softreset << 24) | (m_pci_waitstate_control << 16) | m_gpio_ddr;
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}),
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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LOG("System, PCI and General Purpose Pins Control %08x & %08x\n", data, mem_mask);
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if (ACCESSING_BITS_24_31)
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{
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m_softreset = !!BIT(data, 24);
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// TODO: will lock all writes in config_map but this bit
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// (inclusive of the "all" group?)
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if (!m_softreset)
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{
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software_reset();
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return;
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}
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}
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if (ACCESSING_BITS_16_23)
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m_pci_waitstate_control = (data >> 16) & 7;
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if (ACCESSING_BITS_0_7)
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m_gpio_ddr = data & 0xff;
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})
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);
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map(0x02c, 0x02f).lrw32(
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NAME([this] (offs_t offset) {
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LOG("General Purpose Pins and GuestBus Control R\n");
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// The doc claims 0xf0 default for GPIO, but win98 driver will throw "subvendor ID failed"
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// while testing various ID combinations here
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return (0x7e << 24) | (m_guestbus.time[3] << 12) | (m_guestbus.time[2] << 8) | (m_guestbus.time[1] << 4) | (m_guestbus.time[0] << 0);
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}),
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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LOG("General Purpose Pins and GuestBus Control W %08x & %08x\n", data, mem_mask);
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// if (ACCESSING_BITS_24_31)
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// GenPurIO writes, TBD
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if (ACCESSING_BITS_8_15)
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{
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m_guestbus.time[3] = (data >> 12) & 0xf;
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m_guestbus.time[2] = (data >> 8) & 0xf;
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}
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if (ACCESSING_BITS_0_7)
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{
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m_guestbus.time[1] = (data >> 4) & 0xf;
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m_guestbus.time[0] = (data >> 0) & 0xf;
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}
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})
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);
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map(0x044, 0x047).lr32(
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NAME([this] (offs_t offset) {
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LOG("I2C R\n");
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// avoid win98 stall for now
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return 0x3;
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})
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);
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}
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@ -1,5 +1,5 @@
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// license:BSD-3-Clause
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// copyright-holders:
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// copyright-holders: Angelo Salese
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#ifndef MAME_BUS_PCI_ZR36057_H
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#define MAME_BUS_PCI_ZR36057_H
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@ -31,7 +31,21 @@ protected:
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virtual void config_map(address_map &map) override ATTR_COLD;
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private:
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void map(address_map &map) ATTR_COLD;
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void asr_map(address_map &map) ATTR_COLD;
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void software_reset();
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struct {
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u32 horizontal_config;
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u32 vertical_config;
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} m_video_frontend;
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bool m_softreset;
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u8 m_gpio_ddr, m_pci_waitstate_control;
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struct {
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u8 time[4];
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} m_guestbus;
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};
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DECLARE_DEVICE_TYPE(ZR36057_PCI, zr36057_device)
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