mirror of
https://github.com/holub/mame
synced 2025-10-05 16:50:57 +03:00
interpro: use new 28f010 device (nw)
Sapphire systems can now re-flash themselves from floppy.
This commit is contained in:
parent
b1e0fad856
commit
f12b3fb4b7
@ -104,8 +104,10 @@
|
|||||||
* U35 128 kB EPROM (MPRGW510B) Boot ROM
|
* U35 128 kB EPROM (MPRGW510B) Boot ROM
|
||||||
* U43? (MPRGM610P) Bitstream for XC3020?
|
* U43? (MPRGM610P) Bitstream for XC3020?
|
||||||
* U44 Intel 82596SX Ethernet controller (20MHz)
|
* U44 Intel 82596SX Ethernet controller (20MHz)
|
||||||
|
* U67 Intel N28F010-200 128Kx8 flash memory (200ns)
|
||||||
* U68 CYID21603 TC150G89AF
|
* U68 CYID21603 TC150G89AF
|
||||||
* U71 LSI L1A6104 CICD 95801 Intergraph I/O gate array
|
* U71 LSI L1A6104 CICD 95801 Intergraph I/O gate array
|
||||||
|
* U76 Intel N28F010-200 128Kx8 flash memory (200ns)
|
||||||
* U81 NCR 53C94 SCSI controller
|
* U81 NCR 53C94 SCSI controller
|
||||||
* U86 24.0 MHz crystal Clock source for 53C94?
|
* U86 24.0 MHz crystal Clock source for 53C94?
|
||||||
* U87 4.9152 MHz crystal Clock source for 8530s?
|
* U87 4.9152 MHz crystal Clock source for 8530s?
|
||||||
@ -129,7 +131,9 @@
|
|||||||
* U43? (MPRGM610P) Bitstream for XC3020?
|
* U43? (MPRGM610P) Bitstream for XC3020?
|
||||||
* U44 Intel 82596SX? Ethernet controller
|
* U44 Intel 82596SX? Ethernet controller
|
||||||
* U68 CYID21603 TC150G89AF
|
* U68 CYID21603 TC150G89AF
|
||||||
|
* U67 Intel N28F010 128Kx8 flash memory
|
||||||
* U71 LSI L1A7374 CIDC094A3 Intergraph I/O gate array
|
* U71 LSI L1A7374 CIDC094A3 Intergraph I/O gate array
|
||||||
|
* U76 Intel N28F010 128Kx8 flash memory
|
||||||
* U81 NCR 53C94 SCSI controller
|
* U81 NCR 53C94 SCSI controller
|
||||||
* U86 24.0 MHz crystal Clock source for 53C94?
|
* U86 24.0 MHz crystal Clock source for 53C94?
|
||||||
* U87 4.9152 MHz crystal Clock source for 8530s?
|
* U87 4.9152 MHz crystal Clock source for 8530s?
|
||||||
@ -155,14 +159,6 @@
|
|||||||
#define VERBOSE 0
|
#define VERBOSE 0
|
||||||
#include "logmacro.h"
|
#include "logmacro.h"
|
||||||
|
|
||||||
// FIXME: eeprom/flash device embedded here until real device is known
|
|
||||||
DEFINE_DEVICE_TYPE(INTERPRO_EEPROM, interpro_eeprom_device, "interpro_eeprom", "InterPro Flash EEPROM");
|
|
||||||
|
|
||||||
interpro_eeprom_device::interpro_eeprom_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
|
|
||||||
: eeprom_base_device(mconfig, INTERPRO_EEPROM, tag, owner)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
void interpro_state::machine_start()
|
void interpro_state::machine_start()
|
||||||
{
|
{
|
||||||
// FIXME: disabled for now to avoid cold start diagnostic errors
|
// FIXME: disabled for now to avoid cold start diagnostic errors
|
||||||
@ -242,7 +238,9 @@ WRITE16_MEMBER(sapphire_state::sreg_ctrl2_w)
|
|||||||
{
|
{
|
||||||
interpro_state::sreg_ctrl2_w(space, offset, data, mem_mask);
|
interpro_state::sreg_ctrl2_w(space, offset, data, mem_mask);
|
||||||
|
|
||||||
m_eeprom->write_enable(data & CTRL2_FLASHEN ? ASSERT_LINE : CLEAR_LINE);
|
// enable/disable programming power on both flash devices
|
||||||
|
m_flash_lo->vpp(data & CTRL2_FLASHEN ? ASSERT_LINE : CLEAR_LINE);
|
||||||
|
m_flash_hi->vpp(data & CTRL2_FLASHEN ? ASSERT_LINE : CLEAR_LINE);
|
||||||
}
|
}
|
||||||
|
|
||||||
READ16_MEMBER(interpro_state::sreg_error_r)
|
READ16_MEMBER(interpro_state::sreg_error_r)
|
||||||
@ -376,7 +374,8 @@ ADDRESS_MAP_END
|
|||||||
static ADDRESS_MAP_START(sapphire_main_map, 0, 32, sapphire_state)
|
static ADDRESS_MAP_START(sapphire_main_map, 0, 32, sapphire_state)
|
||||||
AM_RANGE(0x00000000, 0x00ffffff) AM_RAM AM_SHARE(RAM_TAG)
|
AM_RANGE(0x00000000, 0x00ffffff) AM_RAM AM_SHARE(RAM_TAG)
|
||||||
AM_RANGE(0x7f100000, 0x7f11ffff) AM_ROM AM_REGION(INTERPRO_EPROM_TAG, 0)
|
AM_RANGE(0x7f100000, 0x7f11ffff) AM_ROM AM_REGION(INTERPRO_EPROM_TAG, 0)
|
||||||
AM_RANGE(0x7f180000, 0x7f1bffff) AM_DEVREADWRITE16(INTERPRO_EEPROM_TAG, interpro_eeprom_device, eeprom_r, eeprom_w, 0xffffffff)
|
AM_RANGE(0x7f180000, 0x7f1fffff) AM_DEVREADWRITE8(INTERPRO_FLASH_TAG "_lo", intel_28f010_device, read, write, 0x00ff00ff) AM_MASK(0x3ffff)
|
||||||
|
AM_RANGE(0x7f180000, 0x7f1fffff) AM_DEVREADWRITE8(INTERPRO_FLASH_TAG "_hi", intel_28f010_device, read, write, 0xff00ff00) AM_MASK(0x3ffff)
|
||||||
|
|
||||||
AM_IMPORT_FROM(sapphire_base_map)
|
AM_IMPORT_FROM(sapphire_base_map)
|
||||||
ADDRESS_MAP_END
|
ADDRESS_MAP_END
|
||||||
@ -635,10 +634,9 @@ static MACHINE_CONFIG_DERIVED(sapphire, interpro)
|
|||||||
MCFG_DEVICE_ADD(INTERPRO_IOGA_TAG, SAPPHIRE_IOGA, 0)
|
MCFG_DEVICE_ADD(INTERPRO_IOGA_TAG, SAPPHIRE_IOGA, 0)
|
||||||
MCFG_FRAGMENT_ADD(ioga)
|
MCFG_FRAGMENT_ADD(ioga)
|
||||||
|
|
||||||
// eeprom
|
// flash memory
|
||||||
MCFG_DEVICE_ADD(INTERPRO_EEPROM_TAG, INTERPRO_EEPROM, 0)
|
MCFG_DEVICE_ADD(INTERPRO_FLASH_TAG "_lo", INTEL_28F010, 0)
|
||||||
MCFG_EEPROM_SIZE(0x20000, 16)
|
MCFG_DEVICE_ADD(INTERPRO_FLASH_TAG "_hi", INTEL_28F010, 0)
|
||||||
MCFG_EEPROM_WRITE_TIME(attotime::from_usec(1000))
|
|
||||||
MACHINE_CONFIG_END
|
MACHINE_CONFIG_END
|
||||||
|
|
||||||
MACHINE_CONFIG_DERIVED(ip2000, turquoise)
|
MACHINE_CONFIG_DERIVED(ip2000, turquoise)
|
||||||
@ -684,8 +682,11 @@ ROM_START(ip2400)
|
|||||||
ROM_SYSTEM_BIOS(0, "ip2400", "InterPro 2400 EPROM")
|
ROM_SYSTEM_BIOS(0, "ip2400", "InterPro 2400 EPROM")
|
||||||
ROMX_LOAD("mprgw510b__05_16_92.u35", 0x00000, 0x20000, CRC(3b2c4545) SHA1(4e4c98d1cd1035a04be8527223f44d0b687ec3ef), ROM_BIOS(1))
|
ROMX_LOAD("mprgw510b__05_16_92.u35", 0x00000, 0x20000, CRC(3b2c4545) SHA1(4e4c98d1cd1035a04be8527223f44d0b687ec3ef), ROM_BIOS(1))
|
||||||
|
|
||||||
ROM_REGION16_LE(0x0040000, INTERPRO_EEPROM_TAG, 0)
|
ROM_REGION(0x20000, INTERPRO_FLASH_TAG "_lo", 0)
|
||||||
ROM_LOAD_OPTIONAL("c4saph.bin", 0x00000, 0x40000, CRC(a0c0899f) SHA1(dda6fbca81f9885a1a76ca3c25e80463a83a0ef7))
|
ROM_LOAD_OPTIONAL("y225.u76", 0x00000, 0x20000, CRC(46c0b105) SHA1(7c4a104e4fb3d0e5e8db7c911cdfb3f5c4fb0218))
|
||||||
|
|
||||||
|
ROM_REGION(0x20000, INTERPRO_FLASH_TAG "_hi", 0)
|
||||||
|
ROM_LOAD_OPTIONAL("y226.u67", 0x00000, 0x20000, CRC(54d95730) SHA1(a4e114dee1567d8aa31eed770f7cc366588f395c))
|
||||||
ROM_END
|
ROM_END
|
||||||
|
|
||||||
ROM_START(ip2500)
|
ROM_START(ip2500)
|
||||||
@ -696,8 +697,11 @@ ROM_START(ip2500)
|
|||||||
ROM_SYSTEM_BIOS(0, "ip2500", "InterPro 2500 EPROM")
|
ROM_SYSTEM_BIOS(0, "ip2500", "InterPro 2500 EPROM")
|
||||||
ROMX_LOAD("ip2500_eprom.bin", 0x00000, 0x20000, NO_DUMP, ROM_BIOS(1))
|
ROMX_LOAD("ip2500_eprom.bin", 0x00000, 0x20000, NO_DUMP, ROM_BIOS(1))
|
||||||
|
|
||||||
ROM_REGION16_LE(0x0040000, INTERPRO_EEPROM_TAG, 0)
|
ROM_REGION(0x20000, INTERPRO_FLASH_TAG "_lo", 0)
|
||||||
ROM_LOAD_OPTIONAL("c4saph.bin", 0x00000, 0x40000, CRC(a0c0899f) SHA1(dda6fbca81f9885a1a76ca3c25e80463a83a0ef7))
|
ROM_LOAD_OPTIONAL("y225.u76", 0x00000, 0x20000, CRC(46c0b105) SHA1(7c4a104e4fb3d0e5e8db7c911cdfb3f5c4fb0218))
|
||||||
|
|
||||||
|
ROM_REGION(0x20000, INTERPRO_FLASH_TAG "_hi", 0)
|
||||||
|
ROM_LOAD_OPTIONAL("y226.u67", 0x00000, 0x20000, CRC(54d95730) SHA1(a4e114dee1567d8aa31eed770f7cc366588f395c))
|
||||||
ROM_END
|
ROM_END
|
||||||
|
|
||||||
ROM_START(ip2700)
|
ROM_START(ip2700)
|
||||||
@ -708,8 +712,11 @@ ROM_START(ip2700)
|
|||||||
ROM_SYSTEM_BIOS(0, "ip2700", "InterPro 2700 EPROM")
|
ROM_SYSTEM_BIOS(0, "ip2700", "InterPro 2700 EPROM")
|
||||||
ROMX_LOAD("mprgz530a__9405181.u35", 0x00000, 0x20000, CRC(467ce7bd) SHA1(53faee40d5df311f53b24c930e434cbf94a5c4aa), ROM_BIOS(1))
|
ROMX_LOAD("mprgz530a__9405181.u35", 0x00000, 0x20000, CRC(467ce7bd) SHA1(53faee40d5df311f53b24c930e434cbf94a5c4aa), ROM_BIOS(1))
|
||||||
|
|
||||||
ROM_REGION16_LE(0x0040000, INTERPRO_EEPROM_TAG, 0)
|
ROM_REGION(0x20000, INTERPRO_FLASH_TAG "_lo", 0)
|
||||||
ROM_LOAD_OPTIONAL("c4saph.bin", 0x00000, 0x40000, CRC(a0c0899f) SHA1(dda6fbca81f9885a1a76ca3c25e80463a83a0ef7))
|
ROM_LOAD_OPTIONAL("y225.u76", 0x00000, 0x20000, CRC(46c0b105) SHA1(7c4a104e4fb3d0e5e8db7c911cdfb3f5c4fb0218))
|
||||||
|
|
||||||
|
ROM_REGION(0x20000, INTERPRO_FLASH_TAG "_hi", 0)
|
||||||
|
ROM_LOAD_OPTIONAL("y226.u67", 0x00000, 0x20000, CRC(54d95730) SHA1(a4e114dee1567d8aa31eed770f7cc366588f395c))
|
||||||
ROM_END
|
ROM_END
|
||||||
|
|
||||||
ROM_START(ip2800)
|
ROM_START(ip2800)
|
||||||
@ -720,8 +727,11 @@ ROM_START(ip2800)
|
|||||||
ROM_SYSTEM_BIOS(0, "ip2800", "InterPro 2800 EPROM")
|
ROM_SYSTEM_BIOS(0, "ip2800", "InterPro 2800 EPROM")
|
||||||
ROMX_LOAD("ip2800_eprom.bin", 0x00000, 0x20000, CRC(467ce7bd) SHA1(53faee40d5df311f53b24c930e434cbf94a5c4aa), ROM_BIOS(1))
|
ROMX_LOAD("ip2800_eprom.bin", 0x00000, 0x20000, CRC(467ce7bd) SHA1(53faee40d5df311f53b24c930e434cbf94a5c4aa), ROM_BIOS(1))
|
||||||
|
|
||||||
ROM_REGION16_LE(0x0040000, INTERPRO_EEPROM_TAG, 0)
|
ROM_REGION(0x20000, INTERPRO_FLASH_TAG "_lo", 0)
|
||||||
ROM_LOAD_OPTIONAL("c4saph.bin", 0x00000, 0x40000, CRC(a0c0899f) SHA1(dda6fbca81f9885a1a76ca3c25e80463a83a0ef7))
|
ROM_LOAD_OPTIONAL("y225.u76", 0x00000, 0x20000, CRC(46c0b105) SHA1(7c4a104e4fb3d0e5e8db7c911cdfb3f5c4fb0218))
|
||||||
|
|
||||||
|
ROM_REGION(0x20000, INTERPRO_FLASH_TAG "_hi", 0)
|
||||||
|
ROM_LOAD_OPTIONAL("y226.u67", 0x00000, 0x20000, CRC(54d95730) SHA1(a4e114dee1567d8aa31eed770f7cc366588f395c))
|
||||||
ROM_END
|
ROM_END
|
||||||
|
|
||||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
|
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
|
||||||
|
@ -15,7 +15,7 @@
|
|||||||
#include "machine/interpro_arbga.h"
|
#include "machine/interpro_arbga.h"
|
||||||
|
|
||||||
#include "machine/ram.h"
|
#include "machine/ram.h"
|
||||||
#include "machine/eeprom.h"
|
#include "machine/28fxxx.h"
|
||||||
#include "machine/mc146818.h"
|
#include "machine/mc146818.h"
|
||||||
#include "machine/z80scc.h"
|
#include "machine/z80scc.h"
|
||||||
#include "machine/upd765.h"
|
#include "machine/upd765.h"
|
||||||
@ -55,30 +55,10 @@
|
|||||||
|
|
||||||
#define INTERPRO_IDPROM_TAG "idprom"
|
#define INTERPRO_IDPROM_TAG "idprom"
|
||||||
#define INTERPRO_EPROM_TAG "eprom"
|
#define INTERPRO_EPROM_TAG "eprom"
|
||||||
#define INTERPRO_EEPROM_TAG "eeprom"
|
#define INTERPRO_FLASH_TAG "flash"
|
||||||
|
|
||||||
#define INTERPRO_SRBUS_TAG "sr"
|
#define INTERPRO_SRBUS_TAG "sr"
|
||||||
|
|
||||||
class interpro_eeprom_device : public eeprom_base_device
|
|
||||||
{
|
|
||||||
public:
|
|
||||||
interpro_eeprom_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
|
||||||
|
|
||||||
DECLARE_READ16_MEMBER(eeprom_r) { return read(offset); }
|
|
||||||
DECLARE_WRITE16_MEMBER(eeprom_w) { if (m_write_enable) write(offset, data); }
|
|
||||||
|
|
||||||
DECLARE_WRITE_LINE_MEMBER(write_enable) { m_write_enable = state; }
|
|
||||||
|
|
||||||
protected:
|
|
||||||
virtual void device_start() override { eeprom_base_device::device_start(); }
|
|
||||||
virtual void device_reset() override { eeprom_base_device::device_reset(); }
|
|
||||||
|
|
||||||
private:
|
|
||||||
int m_write_enable;
|
|
||||||
};
|
|
||||||
|
|
||||||
DECLARE_DEVICE_TYPE(INTERPRO_EEPROM, interpro_eeprom_device)
|
|
||||||
|
|
||||||
class interpro_state : public driver_device
|
class interpro_state : public driver_device
|
||||||
{
|
{
|
||||||
public:
|
public:
|
||||||
@ -210,10 +190,12 @@ class sapphire_state : public interpro_state
|
|||||||
public:
|
public:
|
||||||
sapphire_state(const machine_config &mconfig, device_type type, const char *tag)
|
sapphire_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||||
: interpro_state(mconfig, type, tag)
|
: interpro_state(mconfig, type, tag)
|
||||||
, m_eeprom(*this, INTERPRO_EEPROM_TAG)
|
, m_flash_lo(*this, INTERPRO_FLASH_TAG "_lo")
|
||||||
|
, m_flash_hi(*this, INTERPRO_FLASH_TAG "_hi")
|
||||||
{}
|
{}
|
||||||
|
|
||||||
required_device<interpro_eeprom_device> m_eeprom;
|
required_device<intel_28f010_device> m_flash_lo;
|
||||||
|
required_device<intel_28f010_device> m_flash_hi;
|
||||||
|
|
||||||
virtual DECLARE_WRITE16_MEMBER(sreg_ctrl2_w) override;
|
virtual DECLARE_WRITE16_MEMBER(sreg_ctrl2_w) override;
|
||||||
};
|
};
|
||||||
|
Loading…
Reference in New Issue
Block a user