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tms340x0_device: converted to use inline config, devcb and delegates. (nw)

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This commit is contained in:
Ivan Vangelista 2014-09-24 14:46:27 +00:00
parent 20e602471e
commit f137016156
47 changed files with 517 additions and 875 deletions
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8
src/emu/cpu/tms34010/34010gfx.c
View File

@ -215,16 +215,16 @@ UINT16 tms340x0_device::memory_r(address_space &space, offs_t offset)
void tms340x0_device::shiftreg_w(address_space &space, offs_t offset,UINT16 data)
{
if (m_config->from_shiftreg)
(*m_config->from_shiftreg)(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]);
if (!m_from_shiftreg_cb.isnull())
m_from_shiftreg_cb(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]);
else
logerror("From ShiftReg function not set. PC = %08X\n", m_pc);
}
UINT16 tms340x0_device::shiftreg_r(address_space &space, offs_t offset)
{
if (m_config->to_shiftreg)
(*m_config->to_shiftreg)(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]);
if (!m_to_shiftreg_cb.isnull())
m_to_shiftreg_cb(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]);
else
logerror("To ShiftReg function not set. PC = %08X\n", m_pc);
return m_shiftreg[0];

67
src/emu/cpu/tms34010/tms34010.c
View File

@ -31,17 +31,14 @@ const device_type TMS34020 = &device_creator<tms34020_device>;
GLOBAL VARIABLES
***************************************************************************/
/* default configuration */
static const tms340x0_config default_config =
{
0
};
tms340x0_device::tms340x0_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname)
: cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__)
, device_video_interface(mconfig, *this)
, m_program_config("program", ENDIANNESS_LITTLE, 16, 32, 3)
, m_config(&default_config)
, m_reset_deferred(FALSE)
, m_pixclock(0)
, m_pixperclock(0)
, m_output_int_cb(*this)
{
}
@ -271,8 +268,8 @@ UINT32 tms340x0_device::read_pixel_32(offs_t offset)
/* Shift register read */
UINT32 tms340x0_device::read_pixel_shiftreg(offs_t offset)
{
if (m_config->to_shiftreg)
m_config->to_shiftreg(*m_program, offset, &m_shiftreg[0]);
if (!m_to_shiftreg_cb.isnull())
m_to_shiftreg_cb(*m_program, offset, &m_shiftreg[0]);
else
fatalerror("To ShiftReg function not set. PC = %08X\n", m_pc);
return m_shiftreg[0];
@ -413,8 +410,8 @@ void tms340x0_device::write_pixel_r_t_32(offs_t offset, UINT32 data)
/* Shift register write */
void tms340x0_device::write_pixel_shiftreg(offs_t offset, UINT32 data)
{
if (m_config->from_shiftreg)
m_config->from_shiftreg(*m_program, offset, &m_shiftreg[0]);
if (!m_from_shiftreg_cb.isnull())
m_from_shiftreg_cb(*m_program, offset, &m_shiftreg[0]);
else
fatalerror("From ShiftReg function not set. PC = %08X\n", m_pc);
}
@ -572,11 +569,16 @@ void tms340x0_device::check_interrupt()
void tms340x0_device::device_start()
{
m_scanline_ind16_cb.bind_relative_to(*owner());
m_scanline_rgb32_cb.bind_relative_to(*owner());
m_output_int_cb.resolve();
m_to_shiftreg_cb.bind_relative_to(*owner());
m_from_shiftreg_cb.bind_relative_to(*owner());
m_external_host_access = FALSE;
m_program = &space(AS_PROGRAM);
m_direct = &m_program->direct();
m_screen = downcast<screen_device *>(machine().device(m_config->screen_tag));
/* set up the state table */
{
@ -646,8 +648,7 @@ void tms340x0_device::device_reset()
/* HALT the CPU if requested, and remember to re-read the starting PC */
/* the first time we are run */
m_reset_deferred = m_config->halt_on_reset;
if (m_config->halt_on_reset)
if (m_reset_deferred)
{
io_register_w(*m_program, REG_HSTCTLH, 0x8000, 0xffff);
}
@ -883,19 +884,19 @@ TIMER_CALLBACK_MEMBER( tms340x0_device::scanline_callback )
{
/* only do this if we have an incoming pixel clock */
/* also, only do it if the HEBLNK/HSBLNK values are stable */
if (master && (m_config->scanline_callback_ind16 != NULL || m_config->scanline_callback_rgb32 != NULL))
if (master && (!m_scanline_ind16_cb.isnull() || !m_scanline_rgb32_cb.isnull()))
{
int htotal = SMART_IOREG(HTOTAL);
if (htotal > 0 && vtotal > 0)
{
attoseconds_t refresh = HZ_TO_ATTOSECONDS(m_config->pixclock) * (htotal + 1) * (vtotal + 1);
int width = (htotal + 1) * m_config->pixperclock;
attoseconds_t refresh = HZ_TO_ATTOSECONDS(m_pixclock) * (htotal + 1) * (vtotal + 1);
int width = (htotal + 1) * m_pixperclock;
int height = vtotal + 1;
rectangle visarea;
/* extract the visible area */
visarea.min_x = SMART_IOREG(HEBLNK) * m_config->pixperclock;
visarea.max_x = SMART_IOREG(HSBLNK) * m_config->pixperclock - 1;
visarea.min_x = SMART_IOREG(HEBLNK) * m_pixperclock;
visarea.max_x = SMART_IOREG(HSBLNK) * m_pixperclock - 1;
visarea.min_y = veblnk;
visarea.max_y = vsblnk - 1;
@ -927,7 +928,7 @@ TIMER_CALLBACK_MEMBER( tms340x0_device::scanline_callback )
}
/* force a partial update within the visible area */
if (vcount >= current_visarea.min_y && vcount <= current_visarea.max_y && (m_config->scanline_callback_ind16 != NULL || m_config->scanline_callback_rgb32 != NULL))
if (vcount >= current_visarea.min_y && vcount <= current_visarea.max_y && (!m_scanline_ind16_cb.isnull() || !m_scanline_rgb32_cb.isnull()))
m_screen->update_partial(vcount);
/* if we are in the visible area, increment DPYADR by DUDATE */
@ -974,8 +975,8 @@ void tms340x0_device::get_display_params(tms34010_display_params *params)
params->vcount = SMART_IOREG(VCOUNT);
params->veblnk = SMART_IOREG(VEBLNK);
params->vsblnk = SMART_IOREG(VSBLNK);
params->heblnk = SMART_IOREG(HEBLNK) * m_config->pixperclock;
params->hsblnk = SMART_IOREG(HSBLNK) * m_config->pixperclock;
params->heblnk = SMART_IOREG(HEBLNK) * m_pixperclock;
params->hsblnk = SMART_IOREG(HSBLNK) * m_pixperclock;
/* 34010 gets its address from DPYADR and DPYTAP */
if (!m_is_34020)
@ -1013,7 +1014,7 @@ UINT32 tms340x0_device::tms340x0_ind16(screen_device &screen, bitmap_ind16 &bitm
{
/* call through to the callback */
LOG((" Update: scan=%3d ROW=%04X COL=%04X\n", cliprect.min_y, params.rowaddr, params.coladdr));
(*m_config->scanline_callback_ind16)(screen, bitmap, cliprect.min_y, &params);
m_scanline_ind16_cb(screen, bitmap, cliprect.min_y, &params);
}
/* otherwise, just blank the current scanline */
@ -1044,7 +1045,7 @@ UINT32 tms340x0_device::tms340x0_rgb32(screen_device &screen, bitmap_rgb32 &bitm
{
/* call through to the callback */
LOG((" Update: scan=%3d ROW=%04X COL=%04X\n", cliprect.min_y, params.rowaddr, params.coladdr));
(*m_config->scanline_callback_rgb32)(screen, bitmap, cliprect.min_y, &params);
m_scanline_rgb32_cb(screen, bitmap, cliprect.min_y, &params);
}
/* otherwise, just blank the current scanline */
@ -1155,13 +1156,13 @@ WRITE16_MEMBER( tms34010_device::io_register_w )
/* the TMS34010 can set output interrupt? */
if (!(oldreg & 0x0080) && (newreg & 0x0080))
{
if (m_config->output_int)
(*m_config->output_int)(&space.device(), 1);
if (!m_output_int_cb.isnull())
m_output_int_cb(1);
}
else if ((oldreg & 0x0080) && !(newreg & 0x0080))
{
if (m_config->output_int)
(*m_config->output_int)(&space.device(), 0);
if (!m_output_int_cb.isnull())
m_output_int_cb(0);
}
/* input interrupt? (should really be state-based, but the functions don't exist!) */
@ -1308,13 +1309,13 @@ WRITE16_MEMBER( tms34020_device::io_register_w )
/* the TMS34010 can set output interrupt? */
if (!(oldreg & 0x0080) && (newreg & 0x0080))
{
if (m_config->output_int)
(*m_config->output_int)(&space.device(), 1);
if (!m_output_int_cb.isnull())
m_output_int_cb(1);
}
else if ((oldreg & 0x0080) && !(newreg & 0x0080))
{
if (m_config->output_int)
(*m_config->output_int)(&space.device(), 0);
if (!m_output_int_cb.isnull())
m_output_int_cb(0);
}
/* input interrupt? (should really be state-based, but the functions don't exist!) */

79
src/emu/cpu/tms34010/tms34010.h
View File

@ -188,31 +188,66 @@ struct tms34010_display_params
};
struct tms340x0_config
{
UINT8 halt_on_reset; /* /HCS pin, which determines HALT state after reset */
const char *screen_tag; /* the screen operated on */
UINT32 pixclock; /* the pixel clock (0 means don't adjust screen size) */
int pixperclock; /* pixels per clock */
void (*scanline_callback_ind16)(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);
void (*scanline_callback_rgb32)(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params);
void (*output_int)(device_t *device, int state); /* output interrupt callback */
void (*to_shiftreg)(address_space &space, offs_t, UINT16 *); /* shift register write */
void (*from_shiftreg)(address_space &space, offs_t, UINT16 *); /* shift register read */
};
#define MCFG_TMS340X0_HALT_ON_RESET(_value) \
tms340x0_device::set_halt_on_reset(*device, _value);
#define MCFG_TMS340X0_PIXEL_CLOCK(_value) \
tms340x0_device::set_pixel_clock(*device, _value);
#define MCFG_TMS340X0_PIXELS_PER_CLOCK(_value) \
tms340x0_device::set_pixels_per_clock(*device, _value);
typedef device_delegate<void (screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)> scanline_ind16_cb_delegate;
#define TMS340X0_SCANLINE_IND16_CB_MEMBER(_name) void _name(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)
#define MCFG_TMS340X0_SCANLINE_IND16_CB(_class, _method) \
tms340x0_device::set_scanline_ind16_callback(*device, scanline_ind16_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
typedef device_delegate<void (screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)> scanline_rgb32_cb_delegate;
#define TMS340X0_SCANLINE_RGB32_CB_MEMBER(_name) void _name(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
#define MCFG_TMS340X0_SCANLINE_RGB32_CB(_class, _method) \
tms340x0_device::set_scanline_rgb32_callback(*device, scanline_rgb32_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
#define MCFG_TMS340X0_OUTPUT_INT_CB(_devcb) \
devcb = &tms340x0_device::set_output_int_callback(*device, DEVCB_##_devcb);
#define MCFG_TMS340X0_CONFIG(_config) \
tms340x0_device::set_tms340x0_config(*device, &_config);
typedef device_delegate<void (address_space &space, offs_t address, UINT16 *shiftreg)> to_shiftreg_cb_delegate;
#define TMS340X0_TO_SHIFTREG_CB_MEMBER(_name) void _name(address_space &space, offs_t address, UINT16 *shiftreg)
#define MCFG_TMS340X0_TO_SHIFTREG_CB(_class, _method) \
tms340x0_device::set_to_shiftreg_callback(*device, to_shiftreg_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
class tms340x0_device : public cpu_device
typedef device_delegate<void (address_space &space, offs_t address, UINT16 *shiftreg)> from_shiftreg_cb_delegate;
#define TMS340X0_FROM_SHIFTREG_CB_MEMBER(_name) void _name(address_space &space, offs_t address, UINT16 *shiftreg)
#define MCFG_TMS340X0_FROM_SHIFTREG_CB(_class, _method) \
tms340x0_device::set_from_shiftreg_callback(*device, from_shiftreg_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
class tms340x0_device : public cpu_device,
public device_video_interface
{
public:
// construction/destruction
tms340x0_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname);
static void set_tms340x0_config(device_t &device, const tms340x0_config *config) { downcast<tms340x0_device &>(device).m_config = config; }
static void set_halt_on_reset(device_t &device, bool reset_deferred) { downcast<tms340x0_device &>(device).m_reset_deferred = reset_deferred; }
static void set_pixel_clock(device_t &device, UINT32 pixclock) { downcast<tms340x0_device &>(device).m_pixclock = pixclock; }
static void set_pixels_per_clock(device_t &device, int pixperclock) { downcast<tms340x0_device &>(device).m_pixperclock = pixperclock; }
static void set_scanline_ind16_callback(device_t &device, scanline_ind16_cb_delegate callback) { downcast<tms340x0_device &>(device).m_scanline_ind16_cb = callback; }
static void set_scanline_rgb32_callback(device_t &device, scanline_rgb32_cb_delegate callback) { downcast<tms340x0_device &>(device).m_scanline_rgb32_cb = callback; }
template<class _Object> static devcb_base &set_output_int_callback(device_t &device, _Object object) { return downcast<tms340x0_device &>(device).m_output_int_cb.set_callback(object); }
static void set_to_shiftreg_callback(device_t &device, to_shiftreg_cb_delegate callback) { downcast<tms340x0_device &>(device).m_to_shiftreg_cb = callback; }
static void set_from_shiftreg_callback(device_t &device, from_shiftreg_cb_delegate callback) { downcast<tms340x0_device &>(device).m_from_shiftreg_cb = callback; }
void get_display_params(tms34010_display_params *params);
void tms34010_state_postload();
@ -292,16 +327,22 @@ protected:
INT32 m_gfxcycles;
UINT8 m_pixelshift;
UINT8 m_is_34020;
UINT8 m_reset_deferred;
bool m_reset_deferred; /* /HCS pin, which determines HALT state after reset */
UINT8 m_hblank_stable;
UINT8 m_external_host_access;
UINT8 m_executing;
address_space *m_program;
direct_read_data *m_direct;
const tms340x0_config *m_config;
screen_device *m_screen;
UINT32 m_pixclock; /* the pixel clock (0 means don't adjust screen size) */
int m_pixperclock; /* pixels per clock */
emu_timer *m_scantimer;
int m_icount;
scanline_ind16_cb_delegate m_scanline_ind16_cb;
scanline_rgb32_cb_delegate m_scanline_rgb32_cb;
devcb_write_line m_output_int_cb; /* output interrupt callback */
to_shiftreg_cb_delegate m_to_shiftreg_cb; /* shift register write */
from_shiftreg_cb_delegate m_from_shiftreg_cb; /* shift register read */
struct XY
{

42
src/mame/drivers/artmagic.c
View File

@ -44,19 +44,17 @@
*
*************************************/
static void update_irq_state(running_machine &machine)
void artmagic_state::update_irq_state()
{
artmagic_state *state = machine.driver_data<artmagic_state>();
state->m_maincpu->set_input_line(4, state->m_tms_irq ? ASSERT_LINE : CLEAR_LINE);
state->m_maincpu->set_input_line(5, state->m_hack_irq ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(4, m_tms_irq ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(5, m_hack_irq ? ASSERT_LINE : CLEAR_LINE);
}
static void m68k_gen_int(device_t *device, int state)
WRITE_LINE_MEMBER(artmagic_state::m68k_gen_int)
{
artmagic_state *drvstate = device->machine().driver_data<artmagic_state>();
drvstate->m_tms_irq = state;
update_irq_state(device->machine());
m_tms_irq = state;
update_irq_state();
}
@ -83,7 +81,7 @@ void artmagic_state::machine_start()
void artmagic_state::machine_reset()
{
m_tms_irq = m_hack_irq = 0;
update_irq_state(machine());
update_irq_state();
}
@ -121,7 +119,7 @@ void artmagic_state::device_timer(emu_timer &timer, device_timer_id id, int para
{
case TIMER_IRQ_OFF:
m_hack_irq = 0;
update_irq_state(machine());
update_irq_state();
break;
default:
assert_always(FALSE, "Unknown id in artmagic_state::device_timer");
@ -136,7 +134,7 @@ READ16_MEMBER(artmagic_state::ultennis_hack_r)
if (pc == 0x18c2 || pc == 0x18e4)
{
m_hack_irq = 1;
update_irq_state(machine());
update_irq_state();
timer_set(attotime::from_usec(1), TIMER_IRQ_OFF);
}
return ioport("300000")->read();
@ -475,20 +473,6 @@ ADDRESS_MAP_END
*
*************************************/
static const tms340x0_config tms_config =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
MASTER_CLOCK_40MHz/6, /* pixel clock */
1, /* pixels per clock */
NULL, /* scanline update (indexed16) */
artmagic_scanline, /* scanline update (rgb32) */
m68k_gen_int, /* generate interrupt */
artmagic_to_shiftreg, /* write to shiftreg function */
artmagic_from_shiftreg /* read from shiftreg function */
};
static ADDRESS_MAP_START( tms_map, AS_PROGRAM, 16, artmagic_state )
AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_SHARE("vram0")
AM_RANGE(0x00400000, 0x005fffff) AM_RAM AM_SHARE("vram1")
@ -827,8 +811,14 @@ static MACHINE_CONFIG_START( artmagic, artmagic_state )
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_CPU_ADD("tms", TMS34010, MASTER_CLOCK_40MHz)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(tms_map)
MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(MASTER_CLOCK_40MHz/6) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_RGB32_CB(artmagic_state, scanline) /* scanline update (rgb32) */
MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(artmagic_state, m68k_gen_int))
MCFG_TMS340X0_TO_SHIFTREG_CB(artmagic_state, to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(artmagic_state, from_shiftreg) /* read from shiftreg function */
MCFG_QUANTUM_TIME(attotime::from_hz(6000))
MCFG_NVRAM_ADD_1FILL("nvram")

29
src/mame/drivers/btoads.c
View File

@ -292,28 +292,6 @@ static INPUT_PORTS_START( btoads )
INPUT_PORTS_END
/*************************************
*
* 34010 configuration
*
*************************************/
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
VIDEO_CLOCK/2, /* pixel clock */
1, /* pixels per clock */
NULL, /* scanline callback (indexed16) */
btoads_state::static_scanline_update, /* scanline callback (rgb32) */
NULL, /* generate interrupt */
btoads_state::static_to_shiftreg, /* write to shiftreg function */
btoads_state::static_from_shiftreg /* read from shiftreg function */
};
/*************************************
*
* Machine drivers
@ -323,8 +301,13 @@ static const tms340x0_config tms_config =
static MACHINE_CONFIG_START( btoads, btoads_state )
MCFG_CPU_ADD("maincpu", TMS34020, CPU_CLOCK/2)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_RGB32_CB(btoads_state, scanline_update) /* scanline updater (RGB32) */
MCFG_TMS340X0_TO_SHIFTREG_CB(btoads_state, to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(btoads_state, from_shiftreg) /* read from shiftreg function */
MCFG_CPU_ADD("audiocpu", Z80, SOUND_CLOCK/4)
MCFG_CPU_PROGRAM_MAP(sound_map)

80
src/mame/drivers/coolpool.c
View File

@ -57,11 +57,9 @@ static const UINT16 nvram_unlock_seq[] =
*
*************************************/
static void amerdart_scanline(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_RGB32_CB_MEMBER(coolpool_state::amerdart_scanline)
{
coolpool_state *state = screen.machine().driver_data<coolpool_state>();
UINT16 *vram = &state->m_vram_base[(params->rowaddr << 8) & 0xff00];
UINT16 *vram = &m_vram_base[(params->rowaddr << 8) & 0xff00];
UINT32 *dest = &bitmap.pix32(scanline);
rgb_t pens[16];
int coladdr = params->coladdr;
@ -71,7 +69,7 @@ static void amerdart_scanline(screen_device &screen, bitmap_rgb32 &bitmap, int s
if (scanline < 256)
for (x = 0; x < 16; x++)
{
UINT16 pal = state->m_vram_base[x];
UINT16 pal = m_vram_base[x];
pens[x] = rgb_t(pal4bit(pal >> 4), pal4bit(pal >> 8), pal4bit(pal >> 12));
}
@ -86,13 +84,11 @@ static void amerdart_scanline(screen_device &screen, bitmap_rgb32 &bitmap, int s
}
static void coolpool_scanline(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_RGB32_CB_MEMBER(coolpool_state::coolpool_scanline)
{
coolpool_state *state = screen.machine().driver_data<coolpool_state>();
UINT16 *vram = &state->m_vram_base[(params->rowaddr << 8) & 0x1ff00];
UINT16 *vram = &m_vram_base[(params->rowaddr << 8) & 0x1ff00];
UINT32 *dest = &bitmap.pix32(scanline);
const rgb_t *pens = state->m_tlc34076->get_pens();
const rgb_t *pens = m_tlc34076->get_pens();
int coladdr = params->coladdr;
int x;
@ -112,19 +108,15 @@ static void coolpool_scanline(screen_device &screen, bitmap_rgb32 &bitmap, int s
*
*************************************/
static void coolpool_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_TO_SHIFTREG_CB_MEMBER(coolpool_state::to_shiftreg)
{
coolpool_state *state = space.machine().driver_data<coolpool_state>();
memcpy(shiftreg, &state->m_vram_base[TOWORD(address) & ~TOWORD(0xfff)], TOBYTE(0x1000));
memcpy(shiftreg, &m_vram_base[TOWORD(address) & ~TOWORD(0xfff)], TOBYTE(0x1000));
}
static void coolpool_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_FROM_SHIFTREG_CB_MEMBER(coolpool_state::from_shiftreg)
{
coolpool_state *state = space.machine().driver_data<coolpool_state>();
memcpy(&state->m_vram_base[TOWORD(address) & ~TOWORD(0xfff)], shiftreg, TOBYTE(0x1000));
memcpy(&m_vram_base[TOWORD(address) & ~TOWORD(0xfff)], shiftreg, TOBYTE(0x1000));
}
@ -790,42 +782,6 @@ static INPUT_PORTS_START( 9ballsht )
INPUT_PORTS_END
/*************************************
*
* 34010 configuration
*
*************************************/
static const tms340x0_config tms_config_amerdart =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
XTAL_40MHz/12, /* pixel clock */
2, /* pixels per clock */
NULL, /* scanline callback (indexed16) */
amerdart_scanline, /* scanline callback (rgb32) */
NULL, /* generate interrupt */
coolpool_to_shiftreg, /* write to shiftreg function */
coolpool_from_shiftreg /* read from shiftreg function */
};
static const tms340x0_config tms_config_coolpool =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
XTAL_40MHz/6, /* pixel clock */
1, /* pixels per clock */
NULL, /* scanline callback (indexed16) */
coolpool_scanline, /* scanline callback (rgb32) */
NULL, /* generate interrupt */
coolpool_to_shiftreg, /* write to shiftreg function */
coolpool_from_shiftreg /* read from shiftreg function */
};
/*************************************
*
* Machine drivers
@ -836,8 +792,13 @@ static MACHINE_CONFIG_START( amerdart, coolpool_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
MCFG_TMS340X0_CONFIG(tms_config_amerdart)
MCFG_CPU_PROGRAM_MAP(amerdart_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(XTAL_40MHz/12) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_RGB32_CB(coolpool_state, amerdart_scanline) /* scanline callback (rgb32) */
MCFG_TMS340X0_TO_SHIFTREG_CB(coolpool_state, to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(coolpool_state, from_shiftreg) /* read from shiftreg function */
MCFG_CPU_ADD("dsp", TMS32015, XTAL_40MHz/2)
MCFG_CPU_PROGRAM_MAP(amerdart_dsp_pgm_map)
@ -867,9 +828,14 @@ static MACHINE_CONFIG_START( coolpool, coolpool_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
MCFG_TMS340X0_CONFIG(tms_config_coolpool)
MCFG_CPU_PROGRAM_MAP(coolpool_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(XTAL_40MHz/6) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_RGB32_CB(coolpool_state, coolpool_scanline) /* scanline callback (rgb32) */
MCFG_TMS340X0_TO_SHIFTREG_CB(coolpool_state, to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(coolpool_state, from_shiftreg) /* read from shiftreg function */
MCFG_CPU_ADD("dsp", TMS32026,XTAL_40MHz)
MCFG_CPU_PROGRAM_MAP(coolpool_dsp_pgm_map)
MCFG_CPU_IO_MAP(coolpool_dsp_io_map)

48
src/mame/drivers/exterm.c
View File

@ -393,41 +393,6 @@ static INPUT_PORTS_START( exterm )
INPUT_PORTS_END
/*************************************
*
* 34010 configurations
*
*************************************/
static const tms340x0_config master_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
40000000/8, /* pixel clock */
1, /* pixels per clock */
exterm_scanline_update, /* scanline updater (indexed16) */
NULL, /* scanline updater (rgb32) */
NULL, /* generate interrupt */
exterm_to_shiftreg_master, /* write to shiftreg function */
exterm_from_shiftreg_master /* read from shiftreg function */
};
static const tms340x0_config slave_config =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
40000000/8, /* pixel clock */
1, /* pixels per clock */
NULL, /* scanline updater (indexed16) */
NULL, /* scanline updater (rgb32) */
NULL, /* generate interrupt */
exterm_to_shiftreg_slave, /* write to shiftreg function */
exterm_from_shiftreg_slave /* read from shiftreg function */
};
/*************************************
*
* Machine drivers
@ -438,12 +403,21 @@ static MACHINE_CONFIG_START( exterm, exterm_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, 40000000)
MCFG_TMS340X0_CONFIG(master_config)
MCFG_CPU_PROGRAM_MAP(master_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(40000000/8) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_IND16_CB(exterm_state, scanline_update) /* scanline updater (indexed16) */
MCFG_TMS340X0_TO_SHIFTREG_CB(exterm_state, to_shiftreg_master) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(exterm_state, from_shiftreg_master) /* read from shiftreg function */
MCFG_CPU_ADD("slave", TMS34010, 40000000)
MCFG_TMS340X0_CONFIG(slave_config)
MCFG_CPU_PROGRAM_MAP(slave_map)
MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(40000000/8) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_TO_SHIFTREG_CB(exterm_state, to_shiftreg_slave) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(exterm_state, from_shiftreg_slave) /* read from shiftreg function */
MCFG_CPU_ADD("audiocpu", M6502, 2000000)
MCFG_CPU_PROGRAM_MAP(sound_master_map)

86
src/mame/drivers/harddriv.c
View File

@ -331,68 +331,6 @@ Notes:
#include "includes/harddriv.h"
/*************************************
*
* CPU configs
*
*************************************/
/* used on the medium-resolution driver boards */
static const tms340x0_config gsp_config_driver =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
4000000, /* pixel clock */
4, /* pixels per clock */
harddriv_scanline_driver, /* scanline callback (indexed16) */
NULL, /* scanline callback (rgb32) */
hdgsp_irq_gen, /* generate interrupt */
hdgsp_write_to_shiftreg, /* write to shiftreg function */
hdgsp_read_from_shiftreg /* read from shiftreg function */
};
/* used on the low-resolution multisync boards for harddrivc, racedrivc, steeltal */
static const tms340x0_config gsp_config_multisync =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
6000000, /* pixel clock */
2, /* pixels per clock */
harddriv_scanline_multisync, /* scanline callback (indexed16) */
NULL, /* scanline callback (rgb32 */
hdgsp_irq_gen, /* generate interrupt */
hdgsp_write_to_shiftreg, /* write to shiftreg function */
hdgsp_read_from_shiftreg /* read from shiftreg function */
};
/* used on the low-resolution multisync board for stunrun */
static const tms340x0_config gsp_config_multisync_stunrun =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
5000000, /* pixel clock */
2, /* pixels per clock */
harddriv_scanline_multisync, /* scanline callback (indexed16) */
NULL, /* scanline callback (rgb32 */
hdgsp_irq_gen, /* generate interrupt */
hdgsp_write_to_shiftreg, /* write to shiftreg function */
hdgsp_read_from_shiftreg /* read from shiftreg function */
};
static const tms340x0_config msp_config =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
5000000, /* pixel clock */
2, /* pixels per clock */
NULL, /* scanline callback (indexed16) */
NULL, /* scanline callback (rgb32 */
hdmsp_irq_gen /* generate interrupt */
};
/*************************************
*
* Driver board memory maps
@ -1296,7 +1234,13 @@ static MACHINE_CONFIG_START( driver_nomsp, harddriv_state )
MCFG_CPU_ADD("gsp", TMS34010, HARDDRIV_GSP_CLOCK)
MCFG_CPU_PROGRAM_MAP(driver_gsp_map)
MCFG_TMS340X0_CONFIG(gsp_config_driver)
MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(4000000) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(4) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_IND16_CB(harddriv_state, scanline_driver) /* scanline callback (indexed16) */
MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(harddriv_state, hdgsp_irq_gen))
MCFG_TMS340X0_TO_SHIFTREG_CB(harddriv_state, hdgsp_write_to_shiftreg)
MCFG_TMS340X0_FROM_SHIFTREG_CB(harddriv_state, hdgsp_read_from_shiftreg)
MCFG_QUANTUM_TIME(attotime::from_hz(30000))
@ -1328,7 +1272,10 @@ static MACHINE_CONFIG_DERIVED( driver_msp, driver_nomsp )
/* basic machine hardware */
MCFG_CPU_ADD("msp", TMS34010, XTAL_50MHz)
MCFG_CPU_PROGRAM_MAP(driver_msp_map)
MCFG_TMS340X0_CONFIG(msp_config)
MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(5000000) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(harddriv_state, hdmsp_irq_gen))
MACHINE_CONFIG_END
@ -1340,8 +1287,10 @@ static MACHINE_CONFIG_DERIVED( multisync_nomsp, driver_nomsp )
MCFG_CPU_PROGRAM_MAP(multisync_68k_map)
MCFG_CPU_MODIFY("gsp")
MCFG_TMS340X0_CONFIG(gsp_config_multisync)
MCFG_CPU_PROGRAM_MAP(multisync_gsp_map)
MCFG_TMS340X0_PIXEL_CLOCK(6000000) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_IND16_CB(harddriv_state, scanline_multisync) /* scanline callback (indexed16) */
/* video hardware */
MCFG_SCREEN_MODIFY("screen")
@ -1355,7 +1304,10 @@ static MACHINE_CONFIG_DERIVED( multisync_msp, multisync_nomsp )
/* basic machine hardware */
MCFG_CPU_ADD("msp", TMS34010, XTAL_50MHz)
MCFG_CPU_PROGRAM_MAP(driver_msp_map)
MCFG_TMS340X0_CONFIG(msp_config)
MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(5000000) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(harddriv_state, hdmsp_irq_gen))
MACHINE_CONFIG_END
@ -1530,7 +1482,7 @@ static MACHINE_CONFIG_DERIVED( stunrun, multisync_nomsp )
/* basic machine hardware */ /* multisync board without MSP */
MCFG_CPU_MODIFY("gsp")
MCFG_TMS340X0_CONFIG(gsp_config_multisync_stunrun)
MCFG_TMS340X0_PIXEL_CLOCK(5000000) /* pixel clock */
MCFG_FRAGMENT_ADD( adsp ) /* ADSP board */
/* video hardware */

28
src/mame/drivers/jpmimpct.c
View File

@ -819,26 +819,12 @@ INPUT_PORTS_END
*
*************************************/
static void jpmimpct_tms_irq(device_t *device, int state)
WRITE_LINE_MEMBER(jpmimpct_state::tms_irq)
{
jpmimpct_state *drvstate = device->machine().driver_data<jpmimpct_state>();
drvstate->m_tms_irq = state;
drvstate->update_irqs();
m_tms_irq = state;
update_irqs();
}
static const tms340x0_config tms_config =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
40000000/16, /* pixel clock */
4, /* pixels per clock */
NULL, /* scanline updater (indexed16) */
jpmimpct_scanline_update, /* scanline updater (rgb32) */
jpmimpct_tms_irq, /* generate interrupt */
jpmimpct_to_shiftreg, /* write to shiftreg function */
jpmimpct_from_shiftreg /* read from shiftreg function */
};
/*************************************
*
@ -851,8 +837,14 @@ static MACHINE_CONFIG_START( jpmimpct, jpmimpct_state )
MCFG_CPU_PROGRAM_MAP(m68k_program_map)
MCFG_CPU_ADD("dsp", TMS34010, 40000000)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(tms_program_map)
MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(40000000/16) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(4) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_RGB32_CB(jpmimpct_state, scanline_update) /* scanline updater (rgb32) */
MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(jpmimpct_state, tms_irq))
MCFG_TMS340X0_TO_SHIFTREG_CB(jpmimpct_state, to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(jpmimpct_state, from_shiftreg) /* read from shiftreg function */
MCFG_QUANTUM_TIME(attotime::from_hz(30000))
MCFG_MACHINE_START_OVERRIDE(jpmimpct_state,jpmimpct)

39
src/mame/drivers/lethalj.c
View File

@ -623,38 +623,6 @@ static INPUT_PORTS_START( franticf ) // how do the directional inputs work?
INPUT_PORTS_END
/*************************************
*
* 34010 configuration
*
*************************************/
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
VIDEO_CLOCK, /* pixel clock */
1, /* pixels per clock */
lethalj_scanline_update, /* scanline update */
NULL, /* generate interrupt */
NULL, /* write to shiftreg function */
NULL /* read from shiftreg function */
};
static const tms340x0_config tms_config_lethalj =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
VIDEO_CLOCK_LETHALJ, /* pixel clock */
1, /* pixels per clock */
lethalj_scanline_update, /* scanline update */
NULL, /* generate interrupt */
NULL, /* write to shiftreg function */
NULL /* read from shiftreg function */
};
/*************************************
*
* Machine drivers
@ -665,8 +633,11 @@ static MACHINE_CONFIG_START( gameroom, lethalj_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, MASTER_CLOCK)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(lethalj_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_IND16_CB(lethalj_state, scanline_update) /* scanline updater (indexed16) */
MCFG_TICKET_DISPENSER_ADD("ticket", attotime::from_msec(200), TICKET_MOTOR_ACTIVE_HIGH, TICKET_STATUS_ACTIVE_HIGH)
@ -695,7 +666,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( lethalj, gameroom )
MCFG_CPU_MODIFY("maincpu")
MCFG_TMS340X0_CONFIG(tms_config_lethalj)
MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK_LETHALJ) /* pixel clock */
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_RAW_PARAMS(VIDEO_CLOCK_LETHALJ, 689, 0, 512, 259, 0, 236)

27
src/mame/drivers/metalmx.c
View File

@ -480,10 +480,9 @@ WRITE32_MEMBER(metalmx_state::host_vram_w)
COMBINE_DATA(m_gsp_vram + offset * 2);
}
static void tms_interrupt(device_t *device, int state)
WRITE_LINE_MEMBER(metalmx_state::tms_interrupt)
{
metalmx_state *drvstate = device->machine().driver_data<metalmx_state>();
drvstate->m_maincpu->set_input_line(4, state ? HOLD_LINE : CLEAR_LINE);
m_maincpu->set_input_line(4, state ? HOLD_LINE : CLEAR_LINE);
}
@ -682,23 +681,6 @@ static INPUT_PORTS_START( metalmx )
INPUT_PORTS_END
/*************************************
*
* CPU configuration
*
*************************************/
static const tms340x0_config gsp_config =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
4000000, /* pixel clock */
2, /* pixels per clock */
NULL, /* scanline callback (indexed16) */
NULL, /* scanline callback (rgb32) */
tms_interrupt, /* generate interrupt */
};
/*************************************
*
* Machine driver
@ -715,8 +697,11 @@ static MACHINE_CONFIG_START( metalmx, metalmx_state )
MCFG_CPU_DATA_MAP(adsp_data_map)
MCFG_CPU_ADD("gsp", TMS34020, 40000000) /* Unverified */
MCFG_TMS340X0_CONFIG(gsp_config)
MCFG_CPU_PROGRAM_MAP(gsp_map)
MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(4000000) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(metalmx_state, tms_interrupt))
MCFG_CPU_ADD("dsp32c_1", DSP32C, 40000000) /* Unverified */
MCFG_CPU_PROGRAM_MAP(dsp32c_1_map)

25
src/mame/drivers/micro3d.c
View File

@ -280,25 +280,6 @@ static ADDRESS_MAP_START( soundmem_io, AS_IO, 8, micro3d_state )
ADDRESS_MAP_END
/*************************************
*
* Device Configuration
*
*************************************/
static const tms340x0_config vgb_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
XTAL_40MHz / 8, /* pixel clock */
4, /* pixels per clock */
micro3d_scanline_update, /* scanline updater (indexed16) */
NULL, /* scanline updater (rgb32) */
micro3d_tms_interrupt, /* Generate interrupt */
NULL,
NULL
};
/*************************************
*
* Machine driver
@ -312,8 +293,12 @@ static MACHINE_CONFIG_START( micro3d, micro3d_state )
MCFG_CPU_VBLANK_INT_DRIVER("screen", micro3d_state, micro3d_vblank)
MCFG_CPU_ADD("vgb", TMS34010, XTAL_40MHz)
MCFG_TMS340X0_CONFIG(vgb_config)
MCFG_CPU_PROGRAM_MAP(vgbmem)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(XTAL_40MHz / 8) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(4) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_IND16_CB(micro3d_state, scanline_update) /* scanline updater (indexed16) */
MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(micro3d_state, tms_interrupt))
MCFG_CPU_ADD("drmath", AM29000, XTAL_32MHz / 2)
MCFG_CPU_PROGRAM_MAP(drmath_prg)

27
src/mame/drivers/midtunit.c
View File

@ -573,26 +573,6 @@ static INPUT_PORTS_START( nbajamte )
INPUT_PORTS_END
/*************************************
*
* 34010 configuration
*
*************************************/
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
PIXEL_CLOCK, /* pixel clock */
2, /* pixels per clock */
midtunit_scanline_update, /* scanline updater (indexed16) */
NULL, /* scanline updater (rgb32) */
NULL, /* generate interrupt */
midtunit_to_shiftreg, /* write to shiftreg function */
midtunit_from_shiftreg /* read from shiftreg function */
};
/*************************************
*
@ -604,8 +584,13 @@ static MACHINE_CONFIG_START( tunit_core, midtunit_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, CPU_CLOCK)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(PIXEL_CLOCK) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_IND16_CB(midtunit_state, scanline_update) /* scanline updater (indexed16) */
MCFG_TMS340X0_TO_SHIFTREG_CB(midtunit_state, to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(midtunit_state, from_shiftreg) /* read from shiftreg function */
MCFG_MACHINE_RESET_OVERRIDE(midtunit_state,midtunit)
MCFG_NVRAM_ADD_0FILL("nvram")

28
src/mame/drivers/midwunit.c
View File

@ -609,27 +609,6 @@ INPUT_PORTS_END
/*************************************
*
* 34010 configuration
*
*************************************/
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
PIXEL_CLOCK, /* pixel clock */
1, /* pixels per clock */
midtunit_scanline_update, /* scanline updater (indexed16) */
NULL, /* scanline updater (rgb32) */
NULL, /* generate interrupt */
midtunit_to_shiftreg, /* write to shiftreg function */
midtunit_from_shiftreg /* read from shiftreg function */
};
/*************************************
*
* Machine drivers
@ -639,8 +618,13 @@ static const tms340x0_config tms_config =
static MACHINE_CONFIG_START( wunit, midwunit_state )
MCFG_CPU_ADD("maincpu", TMS34010, 50000000)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(PIXEL_CLOCK) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_IND16_CB(midtunit_state, scanline_update) /* scanline updater (indexed16) */
MCFG_TMS340X0_TO_SHIFTREG_CB(midtunit_state, to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(midtunit_state, from_shiftreg) /* read from shiftreg function */
MCFG_MACHINE_RESET_OVERRIDE(midwunit_state,midwunit)
MCFG_NVRAM_ADD_0FILL("nvram")

29
src/mame/drivers/midxunit.c
View File

@ -232,28 +232,6 @@ static INPUT_PORTS_START( revx )
INPUT_PORTS_END
/*************************************
*
* 34010 configuration
*
*************************************/
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
PIXEL_CLOCK, /* pixel clock */
1, /* pixels per clock */
midxunit_scanline_update, /* scanline updater (indexed16) */
NULL, /* scanline updater (rgb32) */
NULL, /* generate interrupt */
midtunit_to_shiftreg, /* write to shiftreg function */
midtunit_from_shiftreg /* read from shiftreg function */
};
/*************************************
*
* Machine drivers
@ -264,8 +242,13 @@ static MACHINE_CONFIG_START( midxunit, midxunit_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34020, 40000000)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(PIXEL_CLOCK) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_IND16_CB(midxunit_state, scanline_update) /* scanline updater (indexed16) */
MCFG_TMS340X0_TO_SHIFTREG_CB(midtunit_state, to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(midtunit_state, from_shiftreg) /* read from shiftreg function */
MCFG_MACHINE_RESET_OVERRIDE(midxunit_state,midxunit)
MCFG_NVRAM_ADD_0FILL("nvram")

48
src/mame/drivers/midyunit.c
View File

@ -1060,40 +1060,6 @@ INPUT_PORTS_END
/*************************************
*
* 34010 configuration
*
*************************************/
static const tms340x0_config zunit_tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
MEDRES_PIXEL_CLOCK, /* pixel clock */
2, /* pixels per clock */
midyunit_scanline_update, /* scanline updater (indexed16) */
NULL, /* scanline updater (rgb32) */
NULL, /* generate interrupt */
midyunit_to_shiftreg, /* write to shiftreg function */
midyunit_from_shiftreg /* read from shiftreg function */
};
static const tms340x0_config yunit_tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
STDRES_PIXEL_CLOCK, /* pixel clock */
2, /* pixels per clock */
midyunit_scanline_update, /* scanline updater (indexed16) */
NULL, /* scanline updater (rgb32) */
NULL, /* generate interrupt */
midyunit_to_shiftreg, /* write to shiftreg function */
midyunit_from_shiftreg /* read from shiftreg function */
};
/*************************************
*
* Z-unit machine driver
@ -1104,8 +1070,13 @@ static MACHINE_CONFIG_START( zunit, midyunit_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, FAST_MASTER_CLOCK)
MCFG_TMS340X0_CONFIG(zunit_tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(MEDRES_PIXEL_CLOCK) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_IND16_CB(midyunit_state, scanline_update) /* scanline updater (indexed16) */
MCFG_TMS340X0_TO_SHIFTREG_CB(midyunit_state, to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(midyunit_state, from_shiftreg) /* read from shiftreg function */
MCFG_MACHINE_RESET_OVERRIDE(midyunit_state,midyunit)
MCFG_NVRAM_ADD_0FILL("nvram")
@ -1141,8 +1112,13 @@ static MACHINE_CONFIG_START( yunit_core, midyunit_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, SLOW_MASTER_CLOCK)
MCFG_TMS340X0_CONFIG(yunit_tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(STDRES_PIXEL_CLOCK) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_IND16_CB(midyunit_state, scanline_update) /* scanline updater (indexed16) */
MCFG_TMS340X0_TO_SHIFTREG_CB(midyunit_state, to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(midyunit_state, from_shiftreg) /* read from shiftreg function */
MCFG_MACHINE_RESET_OVERRIDE(midyunit_state,midyunit)
MCFG_NVRAM_ADD_0FILL("nvram")

1
src/mame/drivers/midzeus.c
View File

@ -28,7 +28,6 @@ The Grid v1.2 10/18/2000
#include "emu.h"
#include "cpu/tms32031/tms32031.h"
#include "cpu/tms34010/tms34010.h"
#include "cpu/adsp2100/adsp2100.h"
#include "cpu/pic16c5x/pic16c5x.h"
#include "includes/midzeus.h"

29
src/mame/drivers/potgoldu.c
View File

@ -27,9 +27,13 @@ public:
potgold_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu") { }
required_device<cpu_device> m_maincpu;
virtual void machine_reset();
virtual void video_start();
required_device<cpu_device> m_maincpu;
TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
};
@ -45,7 +49,7 @@ void potgold_state::video_start()
{
}
static void scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_RGB32_CB_MEMBER(potgold_state::scanline_update)
{
}
@ -64,28 +68,15 @@ static INPUT_PORTS_START( potgold )
INPUT_PORTS_END
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
VIDEO_CLOCK/2, /* pixel clock */
1, /* pixels per clock */
NULL, /* scanline callback (indexed16) */
scanline_update, /* scanline callback (rgb32) */
NULL, /* generate interrupt */
NULL, /* write to shiftreg function */
NULL /* read from shiftreg function */
};
static MACHINE_CONFIG_START( potgold, potgold_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(potgold_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_RGB32_CB(potgold_state, scanline_update) /* scanline callback (rgb32) */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_RAW_PARAMS(VIDEO_CLOCK/2, 444, 0, 320, 233, 0, 200)

41
src/mame/drivers/skeetsht.c
View File

@ -46,6 +46,8 @@ public:
DECLARE_READ8_MEMBER(hc11_porta_r);
DECLARE_WRITE8_MEMBER(hc11_porta_w);
DECLARE_WRITE8_MEMBER(ay8910_w);
DECLARE_WRITE_LINE_MEMBER(tms_irq);
TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
virtual void machine_reset();
virtual void video_start();
required_device<cpu_device> m_68hc11;
@ -75,11 +77,10 @@ void skeetsht_state::video_start()
{
}
static void skeetsht_scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_RGB32_CB_MEMBER(skeetsht_state::scanline_update)
{
skeetsht_state *state = screen.machine().driver_data<skeetsht_state>();
const rgb_t *const pens = state->m_tlc34076->get_pens();
UINT16 *vram = &state->m_tms_vram[(params->rowaddr << 8) & 0x3ff00];
const rgb_t *const pens = m_tlc34076->get_pens();
UINT16 *vram = &m_tms_vram[(params->rowaddr << 8) & 0x3ff00];
UINT32 *dest = &bitmap.pix32(scanline);
int coladdr = params->coladdr;
int x;
@ -119,10 +120,9 @@ WRITE16_MEMBER(skeetsht_state::ramdac_w)
*
*************************************/
static void skeetsht_tms_irq(device_t *device, int state)
WRITE_LINE_MEMBER(skeetsht_state::tms_irq)
{
skeetsht_state *drvstate = device->machine().driver_data<skeetsht_state>();
drvstate->m_68hc11->set_input_line(MC68HC11_IRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
m_68hc11->set_input_line(MC68HC11_IRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
}
@ -213,26 +213,6 @@ static INPUT_PORTS_START( skeetsht )
INPUT_PORTS_END
/*************************************
*
* TMS34010 configuration
*
*************************************/
static const tms340x0_config tms_config =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
48000000 / 8, /* pixel clock */
1, /* pixels per clock */
NULL, /* scanline updater (indexed16) */
skeetsht_scanline_update, /* scanline updater (rgb32) */
skeetsht_tms_irq, /* generate interrupt */
NULL, /* write to shiftreg function */
NULL /* read from shiftreg function */
};
/*************************************
*
@ -248,9 +228,12 @@ static MACHINE_CONFIG_START( skeetsht, skeetsht_state )
MCFG_MC68HC11_CONFIG( 0, 0x100, 0x01 ) // And 512 bytes EEPROM? (68HC11A1)
MCFG_CPU_ADD("tms", TMS34010, 48000000)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(tms_program_map)
MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(48000000 / 8) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_RGB32_CB(skeetsht_state, scanline_update) /* scanline updater (rgb32) */
MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(skeetsht_state, tms_irq))
MCFG_TLC34076_ADD("tlc34076", TLC34076_6_BIT)

64
src/mame/drivers/skimaxx.c
View File

@ -45,16 +45,21 @@ class skimaxx_state : public driver_device
public:
skimaxx_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_blitter_regs(*this, "blitter_regs"),
m_fpga_ctrl(*this, "fpga_ctrl"),
m_fg_buffer(*this, "fg_buffer"),
m_maincpu(*this, "maincpu"),
m_subcpu(*this, "subcpu"),
m_tms(*this, "tms") { }
m_tms(*this, "tms"),
m_blitter_regs(*this, "blitter_regs"),
m_fpga_ctrl(*this, "fpga_ctrl"),
m_fg_buffer(*this, "fg_buffer") { }
required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_subcpu;
required_device<tms34010_device> m_tms;
required_shared_ptr<UINT32> m_blitter_regs;
required_shared_ptr<UINT32> m_fpga_ctrl;
required_shared_ptr<UINT16> m_fg_buffer;
UINT32 *m_bg_buffer;
UINT32 *m_bg_buffer_front;
UINT32 *m_bg_buffer_back;
@ -64,6 +69,7 @@ public:
UINT32 m_blitter_src_dx;
UINT32 m_blitter_src_y;
UINT32 m_blitter_src_dy;
DECLARE_WRITE32_MEMBER(skimaxx_blitter_w);
DECLARE_READ32_MEMBER(skimaxx_blitter_r);
DECLARE_WRITE32_MEMBER(skimaxx_fpga_ctrl_w);
@ -72,11 +78,14 @@ public:
DECLARE_WRITE32_MEMBER(skimaxx_unk1_w);
DECLARE_WRITE32_MEMBER(skimaxx_sub_ctrl_w);
DECLARE_READ32_MEMBER(skimaxx_analog_r);
DECLARE_WRITE_LINE_MEMBER(tms_irq);
TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
virtual void machine_reset();
virtual void video_start();
required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_subcpu;
required_device<tms34010_device> m_tms;
};
@ -160,16 +169,14 @@ void skimaxx_state::video_start()
*************************************/
// TODO: Might not be used
static void skimaxx_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_TO_SHIFTREG_CB_MEMBER(skimaxx_state::to_shiftreg)
{
skimaxx_state *state = space.machine().driver_data<skimaxx_state>();
memcpy(shiftreg, &state->m_fg_buffer[TOWORD(address)], 512 * sizeof(UINT16));
memcpy(shiftreg, &m_fg_buffer[TOWORD(address)], 512 * sizeof(UINT16));
}
static void skimaxx_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_FROM_SHIFTREG_CB_MEMBER(skimaxx_state::from_shiftreg)
{
skimaxx_state *state = space.machine().driver_data<skimaxx_state>();
memcpy(&state->m_fg_buffer[TOWORD(address)], shiftreg, 512 * sizeof(UINT16));
memcpy(&m_fg_buffer[TOWORD(address)], shiftreg, 512 * sizeof(UINT16));
}
@ -179,16 +186,15 @@ static void skimaxx_from_shiftreg(address_space &space, UINT32 address, UINT16 *
*
*************************************/
static void skimaxx_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_IND16_CB_MEMBER(skimaxx_state::scanline_update)
{
skimaxx_state *state = screen.machine().driver_data<skimaxx_state>();
// TODO: This isn't correct. I just hacked it together quickly so I could see something!
if (params->rowaddr >= 0x220)
{
UINT32 rowaddr = (params->rowaddr - 0x220);
UINT16 *fg = &state->m_fg_buffer[rowaddr << 8];
UINT32 *bg = &state->m_bg_buffer_front[rowaddr/2 * 1024/2];
UINT16 *fg = &m_fg_buffer[rowaddr << 8];
UINT32 *bg = &m_bg_buffer_front[rowaddr/2 * 1024/2];
UINT16 *dest = &bitmap.pix16(scanline);
//int coladdr = params->coladdr;
int x;
@ -462,25 +468,11 @@ INPUT_PORTS_END
*
*************************************/
static void skimaxx_tms_irq(device_t *device, int state)
WRITE_LINE_MEMBER(skimaxx_state::tms_irq)
{
// TODO
}
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
50000000/8, /* pixel clock */
2, /* pixels per clock */
skimaxx_scanline_update, /* scanline updater (indexed16) */
NULL, /* scanline updater (rgb32) */
skimaxx_tms_irq, /* generate interrupt */
skimaxx_to_shiftreg, /* write to shiftreg function */
skimaxx_from_shiftreg /* read from shiftreg function */
};
/*************************************
*
* Initialisation
@ -508,8 +500,14 @@ static MACHINE_CONFIG_START( skimaxx, skimaxx_state )
/* video hardware */
MCFG_CPU_ADD("tms", TMS34010, XTAL_50MHz)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(tms_program_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(50000000/8) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_IND16_CB(skimaxx_state, scanline_update) /* scanline updater (indexed16) */
MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(skimaxx_state, tms_irq))
MCFG_TMS340X0_TO_SHIFTREG_CB(skimaxx_state, to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(skimaxx_state, from_shiftreg) /* read from shiftreg function */
MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_RAW_PARAMS(40000000/4, 156*4, 0, 100*4, 328, 0, 300) // TODO - Wrong but TMS overrides it anyway

104
src/mame/drivers/tickee.c
View File

@ -42,22 +42,28 @@ public:
tickee_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_tlc34076(*this, "tlc34076"),
m_vram(*this, "vram"),
m_control(*this, "control"),
m_maincpu(*this, "maincpu"),
m_oki(*this, "oki"),
m_screen(*this, "screen") { }
m_screen(*this, "screen"),
m_tlc34076(*this, "tlc34076"),
m_vram(*this, "vram"),
m_control(*this, "control") { }
required_device<cpu_device> m_maincpu;
optional_device<okim6295_device> m_oki;
required_device<screen_device> m_screen;
required_device<tlc34076_device> m_tlc34076;
required_shared_ptr<UINT16> m_vram;
optional_shared_ptr<UINT16> m_control;
emu_timer *m_setup_gun_timer;
int m_beamxadd;
int m_beamyadd;
int m_palette_bank;
UINT8 m_gunx[2];
void get_crosshair_xy(int player, int &x, int &y);
DECLARE_WRITE16_MEMBER(rapidfir_transparent_w);
DECLARE_READ16_MEMBER(rapidfir_transparent_r);
DECLARE_WRITE16_MEMBER(tickee_control_w);
@ -74,9 +80,11 @@ public:
TIMER_CALLBACK_MEMBER(trigger_gun_interrupt);
TIMER_CALLBACK_MEMBER(clear_gun_interrupt);
TIMER_CALLBACK_MEMBER(setup_gun_interrupts);
required_device<cpu_device> m_maincpu;
optional_device<okim6295_device> m_oki;
required_device<screen_device> m_screen;
TMS340X0_TO_SHIFTREG_CB_MEMBER(rapidfir_to_shiftreg);
TMS340X0_FROM_SHIFTREG_CB_MEMBER(rapidfir_from_shiftreg);
TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
TMS340X0_SCANLINE_RGB32_CB_MEMBER(rapidfir_scanline_update);
protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
@ -195,17 +203,16 @@ VIDEO_START_MEMBER(tickee_state,tickee)
*
*************************************/
static void scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_RGB32_CB_MEMBER(tickee_state::scanline_update)
{
tickee_state *state = screen.machine().driver_data<tickee_state>();
UINT16 *src = &state->m_vram[(params->rowaddr << 8) & 0x3ff00];
UINT16 *src = &m_vram[(params->rowaddr << 8) & 0x3ff00];
UINT32 *dest = &bitmap.pix32(scanline);
const rgb_t *pens = state->m_tlc34076->get_pens();
const rgb_t *pens = m_tlc34076->get_pens();
int coladdr = params->coladdr << 1;
int x;
/* blank palette: fill with pen 255 */
if (state->m_control[2])
if (m_control[2])
{
for (x = params->heblnk; x < params->hsblnk; x++)
dest[x] = pens[0xff];
@ -221,16 +228,15 @@ static void scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int sca
}
static void rapidfir_scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_RGB32_CB_MEMBER(tickee_state::rapidfir_scanline_update)
{
tickee_state *state = screen.machine().driver_data<tickee_state>();
UINT16 *src = &state->m_vram[(params->rowaddr << 8) & 0x3ff00];
UINT16 *src = &m_vram[(params->rowaddr << 8) & 0x3ff00];
UINT32 *dest = &bitmap.pix32(scanline);
const rgb_t *pens = state->m_tlc34076->get_pens();
const rgb_t *pens = m_tlc34076->get_pens();
int coladdr = params->coladdr << 1;
int x;
if (state->m_palette_bank)
if (m_palette_bank)
{
/* blank palette: fill with pen 255 */
for (x = params->heblnk; x < params->hsblnk; x += 2)
@ -291,19 +297,17 @@ READ16_MEMBER(tickee_state::rapidfir_transparent_r)
}
static void rapidfir_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_TO_SHIFTREG_CB_MEMBER(tickee_state::rapidfir_to_shiftreg)
{
tickee_state *state = space.machine().driver_data<tickee_state>();
if (address < 0x800000)
memcpy(shiftreg, &state->m_vram[TOWORD(address)], TOBYTE(0x2000));
memcpy(shiftreg, &m_vram[TOWORD(address)], TOBYTE(0x2000));
}
static void rapidfir_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_FROM_SHIFTREG_CB_MEMBER(tickee_state::rapidfir_from_shiftreg)
{
tickee_state *state = space.machine().driver_data<tickee_state>();
if (address < 0x800000)
memcpy(&state->m_vram[TOWORD(address)], shiftreg, TOBYTE(0x2000));
memcpy(&m_vram[TOWORD(address)], shiftreg, TOBYTE(0x2000));
}
@ -729,41 +733,6 @@ static INPUT_PORTS_START( rapidfir )
PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10) PORT_PLAYER(2)
INPUT_PORTS_END
/*************************************
*
* 34010 configuration
*
*************************************/
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
VIDEO_CLOCK/2, /* pixel clock */
1, /* pixels per clock */
NULL, /* scanline callback (indexed16) */
scanline_update, /* scanline callback (rgb32) */
NULL, /* generate interrupt */
NULL, /* write to shiftreg function */
NULL /* read from shiftreg function */
};
static const tms340x0_config rapidfir_tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
VIDEO_CLOCK/2, /* pixel clock */
1, /* pixels per clock */
NULL, /* scanline callback (indexed16) */
rapidfir_scanline_update, /* scanline callback (rgb32) */
NULL, /* generate interrupt */
rapidfir_to_shiftreg, /* write to shiftreg function */
rapidfir_from_shiftreg /* read from shiftreg function */
};
/*************************************
*
* Machine drivers
@ -774,8 +743,11 @@ static MACHINE_CONFIG_START( tickee, tickee_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(tickee_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_RGB32_CB(tickee_state, scanline_update) /* scanline callback (rgb32) */
MCFG_MACHINE_RESET_OVERRIDE(tickee_state,tickee)
MCFG_NVRAM_ADD_1FILL("nvram")
@ -819,8 +791,13 @@ static MACHINE_CONFIG_START( rapidfir, tickee_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, XTAL_50MHz)
MCFG_TMS340X0_CONFIG(rapidfir_tms_config)
MCFG_CPU_PROGRAM_MAP(rapidfir_map)
MCFG_CPU_PROGRAM_MAP(rapidfir_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_RGB32_CB(tickee_state, rapidfir_scanline_update) /* scanline callback (rgb32) */
MCFG_TMS340X0_TO_SHIFTREG_CB(tickee_state, rapidfir_to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(tickee_state, rapidfir_from_shiftreg) /* read from shiftreg function */
MCFG_MACHINE_RESET_OVERRIDE(tickee_state,rapidfir)
MCFG_NVRAM_ADD_1FILL("nvram")
@ -846,8 +823,11 @@ static MACHINE_CONFIG_START( mouseatk, tickee_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(mouseatk_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_RGB32_CB(tickee_state, scanline_update) /* scanline callback (rgb32) */
MCFG_MACHINE_RESET_OVERRIDE(tickee_state,tickee)
MCFG_NVRAM_ADD_1FILL("nvram")

65
src/mame/drivers/xtheball.c
View File

@ -21,13 +21,14 @@ class xtheball_state : public driver_device
public:
xtheball_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_tlc34076(*this, "tlc34076"),
m_vram_bg(*this, "vrabg"),
m_vram_fg(*this, "vrafg"),
m_analog_x(*this, "ANALOGX"),
m_analog_y(*this, "ANALOGY"),
m_maincpu(*this, "maincpu") { }
m_analog_y(*this, "ANALOGY") { }
required_device<cpu_device> m_maincpu;
required_device<tlc34076_device> m_tlc34076;
required_shared_ptr<UINT16> m_vram_bg;
required_shared_ptr<UINT16> m_vram_fg;
@ -37,7 +38,9 @@ public:
DECLARE_WRITE16_MEMBER(bit_controls_w);
DECLARE_READ16_MEMBER(analogx_r);
DECLARE_READ16_MEMBER(analogy_watchdog_r);
required_device<cpu_device> m_maincpu;
TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
};
@ -49,20 +52,19 @@ public:
*
*************************************/
static void xtheball_scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_RGB32_CB_MEMBER(xtheball_state::scanline_update)
{
xtheball_state *state = screen.machine().driver_data<xtheball_state>();
UINT16 *srcbg = &state->m_vram_bg[(params->rowaddr << 8) & 0xff00];
UINT16 *srcbg = &m_vram_bg[(params->rowaddr << 8) & 0xff00];
UINT32 *dest = &bitmap.pix32(scanline);
const rgb_t *pens = state->m_tlc34076->get_pens();
const rgb_t *pens = m_tlc34076->get_pens();
int coladdr = params->coladdr;
int x;
/* bit value 0x13 controls which foreground mode to use */
if (!state->m_bitvals[0x13])
if (!m_bitvals[0x13])
{
/* mode 0: foreground is the same as background */
UINT16 *srcfg = &state->m_vram_fg[(params->rowaddr << 8) & 0xff00];
UINT16 *srcfg = &m_vram_fg[(params->rowaddr << 8) & 0xff00];
for (x = params->heblnk; x < params->hsblnk; x += 2, coladdr++)
{
@ -77,7 +79,7 @@ static void xtheball_scanline_update(screen_device &screen, bitmap_rgb32 &bitmap
{
/* mode 1: foreground is half background resolution in */
/* X and supports two pages */
UINT16 *srcfg = &state->m_vram_fg[(params->rowaddr << 7) & 0xff00];
UINT16 *srcfg = &m_vram_fg[(params->rowaddr << 7) & 0xff00];
for (x = params->heblnk; x < params->hsblnk; x += 2, coladdr++)
{
@ -99,25 +101,23 @@ static void xtheball_scanline_update(screen_device &screen, bitmap_rgb32 &bitmap
*
*************************************/
static void xtheball_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_TO_SHIFTREG_CB_MEMBER(xtheball_state::to_shiftreg)
{
xtheball_state *state = space.machine().driver_data<xtheball_state>();
if (address >= 0x01000000 && address <= 0x010fffff)
memcpy(shiftreg, &state->m_vram_bg[TOWORD(address & 0xff000)], TOBYTE(0x1000));
memcpy(shiftreg, &m_vram_bg[TOWORD(address & 0xff000)], TOBYTE(0x1000));
else if (address >= 0x02000000 && address <= 0x020fffff)
memcpy(shiftreg, &state->m_vram_fg[TOWORD(address & 0xff000)], TOBYTE(0x1000));
memcpy(shiftreg, &m_vram_fg[TOWORD(address & 0xff000)], TOBYTE(0x1000));
else
logerror("%s:xtheball_to_shiftreg(%08X)\n", space.machine().describe_context(), address);
}
static void xtheball_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_FROM_SHIFTREG_CB_MEMBER(xtheball_state::from_shiftreg)
{
xtheball_state *state = space.machine().driver_data<xtheball_state>();
if (address >= 0x01000000 && address <= 0x010fffff)
memcpy(&state->m_vram_bg[TOWORD(address & 0xff000)], shiftreg, TOBYTE(0x1000));
memcpy(&m_vram_bg[TOWORD(address & 0xff000)], shiftreg, TOBYTE(0x1000));
else if (address >= 0x02000000 && address <= 0x020fffff)
memcpy(&state->m_vram_fg[TOWORD(address & 0xff000)], shiftreg, TOBYTE(0x1000));
memcpy(&m_vram_fg[TOWORD(address & 0xff000)], shiftreg, TOBYTE(0x1000));
else
logerror("%s:xtheball_from_shiftreg(%08X)\n", space.machine().describe_context(), address);
}
@ -315,28 +315,6 @@ static INPUT_PORTS_START( xtheball )
INPUT_PORTS_END
/*************************************
*
* 34010 configuration
*
*************************************/
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
10000000, /* pixel clock */
1, /* pixels per clock */
NULL, /* scanline callback (indexed16) */
xtheball_scanline_update, /* scanline callback (rgb32) */
NULL, /* generate interrupt */
xtheball_to_shiftreg, /* write to shiftreg function */
xtheball_from_shiftreg /* read from shiftreg function */
};
/*************************************
*
* Machine drivers
@ -346,8 +324,13 @@ static const tms340x0_config tms_config =
static MACHINE_CONFIG_START( xtheball, xtheball_state )
MCFG_CPU_ADD("maincpu", TMS34010, 40000000)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(10000000) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_RGB32_CB(xtheball_state, scanline_update) /* scanline updater (rgb32) */
MCFG_TMS340X0_TO_SHIFTREG_CB(xtheball_state, to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(xtheball_state, from_shiftreg) /* read from shiftreg function */
MCFG_CPU_PERIODIC_INT_DRIVER(xtheball_state, irq1_line_hold, 15000)
MCFG_NVRAM_ADD_1FILL("nvram")

11
src/mame/includes/artmagic.h
View File

@ -58,6 +58,10 @@ public:
DECLARE_READ16_MEMBER(unk_r);
DECLARE_READ16_MEMBER(artmagic_blitter_r);
DECLARE_WRITE16_MEMBER(artmagic_blitter_w);
DECLARE_WRITE_LINE_MEMBER(m68k_gen_int);
TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline);
DECLARE_CUSTOM_INPUT_MEMBER(prot_r);
DECLARE_DRIVER_INIT(shtstar);
DECLARE_DRIVER_INIT(cheesech);
@ -69,14 +73,9 @@ public:
void decrypt_cheesech();
void decrypt_ultennis();
void execute_blit();
void update_irq_state();
inline UINT16 *address_to_vram(offs_t *address);
protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
};
/*----------- defined in video/artmagic.c -----------*/
void artmagic_to_shiftreg(address_space &space, offs_t address, UINT16 *data);
void artmagic_from_shiftreg(address_space &space, offs_t address, UINT16 *data);
void artmagic_scanline(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params);

9
src/mame/includes/btoads.h
View File

@ -61,12 +61,9 @@ public:
DECLARE_READ16_MEMBER( vram_fg_display_r );
DECLARE_READ16_MEMBER( vram_fg_draw_r );
void render_sprite_row(UINT16 *sprite_source, UINT32 address);
void to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
static void static_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg) { space.machine().driver_data<btoads_state>()->to_shiftreg(space, address, shiftreg); }
void from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
static void static_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg) { space.machine().driver_data<btoads_state>()->from_shiftreg(space, address, shiftreg); }
void scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params);
static void static_scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params) { screen.machine().driver_data<btoads_state>()->scanline_update(screen, bitmap, scanline, params); }
TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
protected:
// device overrides

4
src/mame/includes/coolpool.h
View File

@ -61,6 +61,10 @@ public:
DECLARE_WRITE16_MEMBER(dsp_romaddr_w);
DECLARE_READ16_MEMBER(coolpool_input_r);
DECLARE_WRITE16_MEMBER(dsp_dac_w);
TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
TMS340X0_SCANLINE_RGB32_CB_MEMBER(amerdart_scanline);
TMS340X0_SCANLINE_RGB32_CB_MEMBER(coolpool_scanline);
DECLARE_DRIVER_INIT(coolpool);
DECLARE_DRIVER_INIT(amerdart);
DECLARE_DRIVER_INIT(9ballsht);

13
src/mame/includes/exterm.h
View File

@ -44,17 +44,14 @@ public:
DECLARE_PALETTE_INIT(exterm);
TIMER_CALLBACK_MEMBER(sound_delayed_w);
TIMER_DEVICE_CALLBACK_MEMBER(master_sound_nmi_callback);
TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg_master);
TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg_master);
TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg_slave);
TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg_slave);
required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_audiocpu;
required_device<cpu_device> m_audioslave;
required_device<tms34010_device> m_slave;
required_device<dac_device> m_dac;
};
/*----------- defined in video/exterm.c -----------*/
void exterm_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);
void exterm_to_shiftreg_master(address_space &space, UINT32 address, UINT16* shiftreg);
void exterm_from_shiftreg_master(address_space &space, UINT32 address, UINT16* shiftreg);
void exterm_to_shiftreg_slave(address_space &space, UINT32 address, UINT16* shiftreg);
void exterm_from_shiftreg_slave(address_space &space, UINT32 address, UINT16* shiftreg);

29
src/mame/includes/harddriv.h
View File

@ -331,6 +331,9 @@ public:
DECLARE_WRITE16_MEMBER( hdgsp_io_w );
DECLARE_WRITE16_MEMBER( hdgsp_protection_w );
DECLARE_WRITE_LINE_MEMBER( hdgsp_irq_gen );
DECLARE_WRITE_LINE_MEMBER( hdmsp_irq_gen );
/* ADSP board */
DECLARE_READ16_MEMBER( hd68k_adsp_program_r );
@ -436,6 +439,11 @@ public:
DECLARE_READ32_MEMBER(hdds3xdsp_serial_rx_callback);
/*----------- defined in video/harddriv.c -----------*/
TMS340X0_TO_SHIFTREG_CB_MEMBER(hdgsp_write_to_shiftreg);
TMS340X0_FROM_SHIFTREG_CB_MEMBER(hdgsp_read_from_shiftreg);
void update_palette_bank(int newbank);
DECLARE_READ16_MEMBER( hdgsp_control_lo_r );
DECLARE_WRITE16_MEMBER( hdgsp_control_lo_w );
DECLARE_READ16_MEMBER( hdgsp_control_hi_r );
@ -456,22 +464,7 @@ public:
/* DS III/IV board */
TIMER_DEVICE_CALLBACK_MEMBER( ds3sdsp_internal_timer_callback );
TIMER_DEVICE_CALLBACK_MEMBER( ds3xdsp_internal_timer_callback );
TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_driver);
TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_multisync);
};
/*----------- defined in machine/harddriv.c -----------*/
/* Driver/Multisync board */
void hdgsp_irq_gen(device_t *device, int state);
void hdmsp_irq_gen(device_t *device, int state);
/*----------- defined in video/harddriv.c -----------*/
void hdgsp_write_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
void hdgsp_read_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
void harddriv_scanline_driver(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);
void harddriv_scanline_multisync(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);

13
src/mame/includes/jpmimpct.h
View File

@ -106,7 +106,12 @@ public:
DECLARE_READ8_MEMBER(hopper_c_r);
DECLARE_WRITE8_MEMBER(payen_a_w);
DECLARE_WRITE8_MEMBER(display_c_w);
DECLARE_WRITE_LINE_MEMBER(tms_irq);
TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
DECLARE_MACHINE_START(jpmimpct);
DECLARE_MACHINE_RESET(jpmimpct);
DECLARE_VIDEO_START(jpmimpct);
@ -119,9 +124,3 @@ public:
optional_device<palette_device> m_palette;
optional_device<tms34010_device> m_dsp;
};
/*----------- defined in video/jpmimpct.c -----------*/
void jpmimpct_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
void jpmimpct_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
void jpmimpct_scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params);

5
src/mame/includes/lethalj.h
View File

@ -19,6 +19,8 @@ public:
m_maincpu(*this, "maincpu"),
m_screen(*this, "screen") { }
required_device<cpu_device> m_maincpu;
required_device<screen_device> m_screen;
UINT16 m_blitter_data[8];
UINT16 *m_screenram;
UINT8 m_vispage;
@ -39,8 +41,7 @@ public:
DECLARE_DRIVER_INIT(cclownz);
virtual void video_start();
inline void get_crosshair_xy(int player, int *x, int *y);
required_device<cpu_device> m_maincpu;
required_device<screen_device> m_screen;
TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);

1
src/mame/includes/metalmx.h
View File

@ -49,6 +49,7 @@ public:
DECLARE_WRITE32_MEMBER(timer_w);
DECLARE_DRIVER_INIT(metalmx);
DECLARE_WRITE8_MEMBER(cage_irq_callback);
DECLARE_WRITE_LINE_MEMBER(tms_interrupt);
virtual void machine_reset();
virtual void video_start();
UINT32 screen_update_metalmx(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

6
src/mame/includes/micro3d.h
View File

@ -137,6 +137,8 @@ public:
DECLARE_READ8_MEMBER(duart_input_r);
DECLARE_WRITE8_MEMBER(duart_output_w);
DECLARE_WRITE_LINE_MEMBER(duart_txb);
DECLARE_WRITE_LINE_MEMBER(tms_interrupt);
TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
required_device<cpu_device> m_maincpu;
required_device<i8051_device> m_audiocpu;
@ -220,7 +222,3 @@ private:
};
extern const device_type MICRO3D;
/*----------- defined in video/micro3d.c -----------*/
void micro3d_tms_interrupt(device_t *device, int state);
void micro3d_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);

15
src/mame/includes/midtunit.h
View File

@ -66,6 +66,9 @@ public:
DECLARE_READ16_MEMBER(midxunit_paletteram_r);
DECLARE_READ16_MEMBER(midtunit_dma_r);
DECLARE_WRITE16_MEMBER(midtunit_dma_w);
TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
DECLARE_DRIVER_INIT(mktunit);
DECLARE_DRIVER_INIT(mkturbo);
DECLARE_DRIVER_INIT(nbajamte);
@ -101,17 +104,9 @@ public:
const UINT8 *jdredd_prot_table;
UINT8 jdredd_prot_index;
UINT8 jdredd_prot_max;
UINT8 m_gfx_rom_large;
protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
};
/*----------- defined in video/midtunit.c -----------*/
extern UINT8 midtunit_gfx_rom_large;
void midtunit_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
void midtunit_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
void midtunit_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);
void midxunit_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);

1
src/mame/includes/midxunit.h
View File

@ -45,4 +45,5 @@ public:
DECLARE_MACHINE_RESET(midxunit);
DECLARE_VIDEO_START(midxunit);
void register_state_saving();
TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
};

8
src/mame/includes/midyunit.h
View File

@ -99,6 +99,9 @@ public:
DECLARE_CUSTOM_INPUT_MEMBER(narc_talkback_data_r);
DECLARE_CUSTOM_INPUT_MEMBER(adpcm_irq_state_r);
DECLARE_WRITE8_MEMBER(yawdim_oki_bank_w);
TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
DECLARE_DRIVER_INIT(smashtv);
DECLARE_DRIVER_INIT(strkforc);
DECLARE_DRIVER_INIT(narc);
@ -129,8 +132,3 @@ public:
protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
};
/*----------- defined in video/midyunit.c -----------*/
void midyunit_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
void midyunit_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
void midyunit_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);

14
src/mame/machine/harddriv.c
View File

@ -118,19 +118,17 @@ WRITE16_MEMBER( harddriv_state::hd68k_irq_ack_w )
}
void hdgsp_irq_gen(device_t *device, int irqstate)
WRITE_LINE_MEMBER(harddriv_state::hdgsp_irq_gen)
{
harddriv_state *state = device->machine().driver_data<harddriv_state>();
state->m_gsp_irq_state = irqstate;
state->update_interrupts();
m_gsp_irq_state = state;
update_interrupts();
}
void hdmsp_irq_gen(device_t *device, int irqstate)
WRITE_LINE_MEMBER(harddriv_state::hdmsp_irq_gen)
{
harddriv_state *state = device->machine().driver_data<harddriv_state>();
state->m_msp_irq_state = irqstate;
state->update_interrupts();
m_msp_irq_state = state;
update_interrupts();
}

55
src/mame/machine/inder_vid.c
View File

@ -33,14 +33,12 @@ static ADDRESS_MAP_START( megaphx_tms_map, AS_PROGRAM, 16, inder_vid_device )
ADDRESS_MAP_END
static void megaphx_scanline(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_RGB32_CB_MEMBER(inder_vid_device::scanline)
{
inder_vid_device *state = (inder_vid_device*)screen.machine().device("inder_vid");
UINT16 *vram = &state->m_vram[(params->rowaddr << 8) & 0x3ff00];
UINT16 *vram = &m_vram[(params->rowaddr << 8) & 0x3ff00];
UINT32 *dest = &bitmap.pix32(scanline);
const pen_t *paldata = state->m_palette->pens();
const pen_t *paldata = m_palette->pens();
int coladdr = params->coladdr;
int x;
@ -55,63 +53,48 @@ static void megaphx_scanline(screen_device &screen, bitmap_rgb32 &bitmap, int sc
}
static void megaphx_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_TO_SHIFTREG_CB_MEMBER(inder_vid_device::to_shiftreg)
{
inder_vid_device *state = (inder_vid_device*)space.machine().device("inder_vid");
if (state->m_shiftfull == 0)
if (m_shiftfull == 0)
{
//printf("read to shift regs address %08x (%08x)\n", address, TOWORD(address) * 2);
memcpy(shiftreg, &state->m_vram[TOWORD(address) & ~TOWORD(0x1fff)], TOBYTE(0x2000)); // & ~TOWORD(0x1fff) is needed for round 6
state->m_shiftfull = 1;
memcpy(shiftreg, &m_vram[TOWORD(address) & ~TOWORD(0x1fff)], TOBYTE(0x2000)); // & ~TOWORD(0x1fff) is needed for round 6
m_shiftfull = 1;
}
}
static void megaphx_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_FROM_SHIFTREG_CB_MEMBER(inder_vid_device::from_shiftreg)
{
// printf("write from shift regs address %08x (%08x)\n", address, TOWORD(address) * 2);
inder_vid_device *state = (inder_vid_device*)space.machine().device("inder_vid");
memcpy(&m_vram[TOWORD(address) & ~TOWORD(0x1fff)], shiftreg, TOBYTE(0x2000));
memcpy(&state->m_vram[TOWORD(address) & ~TOWORD(0x1fff)], shiftreg, TOBYTE(0x2000));
state->m_shiftfull = 0;
m_shiftfull = 0;
}
static void m68k_gen_int(device_t *device, int state)
WRITE_LINE_MEMBER(inder_vid_device::m68k_gen_int)
{
cpu_device *maincpu = (cpu_device*)device->machine().device("maincpu");
cpu_device *maincpu = (cpu_device*)machine().device("maincpu");
if (state) maincpu->set_input_line(4, ASSERT_LINE);
else maincpu->set_input_line(4, CLEAR_LINE);
}
static const tms340x0_config tms_config_megaphx =
{
TRUE, /* halt on reset */
"inder_vid:inder_screen", /* the screen operated on */
XTAL_40MHz/12, /* pixel clock */
2, /* pixels per clock */
NULL, /* scanline callback (indexed16) */
megaphx_scanline, /* scanline callback (rgb32) */
m68k_gen_int, /* generate interrupt */
megaphx_to_shiftreg, /* write to shiftreg function */
megaphx_from_shiftreg /* read from shiftreg function */
};
static ADDRESS_MAP_START( ramdac_map, AS_0, 8, inder_vid_device )
AM_RANGE(0x000, 0x3ff) AM_DEVREADWRITE("ramdac",ramdac_device,ramdac_pal_r,ramdac_rgb888_w)
ADDRESS_MAP_END
static MACHINE_CONFIG_FRAGMENT( inder_vid )
MCFG_CPU_ADD("tms", TMS34010, XTAL_40MHz)
MCFG_TMS340X0_CONFIG(tms_config_megaphx)
MCFG_CPU_PROGRAM_MAP(megaphx_tms_map)
MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
MCFG_TMS340X0_PIXEL_CLOCK(XTAL_40MHz/12) /* pixel clock */
MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
MCFG_TMS340X0_SCANLINE_RGB32_CB(inder_vid_device, scanline) /* scanline updater (RGB32) */
MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(inder_vid_device, m68k_gen_int))
MCFG_TMS340X0_TO_SHIFTREG_CB(inder_vid_device, to_shiftreg) /* write to shiftreg function */
MCFG_TMS340X0_FROM_SHIFTREG_CB(inder_vid_device, from_shiftreg) /* read from shiftreg function */
MCFG_SCREEN_ADD("inder_screen", RASTER)
MCFG_SCREEN_RAW_PARAMS(XTAL_40MHz/12, 424, 0, 338-1, 262, 0, 246-1)

11
src/mame/machine/inder_vid.h
View File

@ -29,19 +29,20 @@ public:
required_shared_ptr<UINT16> m_vram;
required_device<palette_device> m_palette;
required_device<tms34010_device> m_tms;
DECLARE_WRITE_LINE_MEMBER(m68k_gen_int);
int m_shiftfull; // this might be a driver specific hack for a TMS bug.
TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline);
protected:
virtual machine_config_constructor device_mconfig_additions() const;
virtual void device_start();
virtual void device_reset();
private:
};
#endif

4
src/mame/machine/midtunit.c
View File

@ -396,7 +396,7 @@ void midtunit_state::init_tunit_generic(int sound)
/* default graphics functionality */
midtunit_gfx_rom_large = 0;
m_gfx_rom_large = 0;
}
@ -500,7 +500,7 @@ DRIVER_INIT_MEMBER(midtunit_state,mk2)
{
/* common init */
init_tunit_generic(SOUND_DCS);
midtunit_gfx_rom_large = 1;
m_gfx_rom_large = 1;
/* protection */
m_maincpu->space(AS_PROGRAM).install_write_handler(0x00f20c60, 0x00f20c7f, write16_delegate(FUNC(midtunit_state::mk2_prot_w),this));

21
src/mame/video/artmagic.c
View File

@ -59,21 +59,19 @@ void artmagic_state::video_start()
*
*************************************/
void artmagic_to_shiftreg(address_space &space, offs_t address, UINT16 *data)
TMS340X0_TO_SHIFTREG_CB_MEMBER(artmagic_state::to_shiftreg)
{
artmagic_state *state = space.machine().driver_data<artmagic_state>();
UINT16 *vram = state->address_to_vram(&address);
UINT16 *vram = address_to_vram(&address);
if (vram)
memcpy(data, &vram[address], TOBYTE(0x2000));
memcpy(shiftreg, &vram[address], TOBYTE(0x2000));
}
void artmagic_from_shiftreg(address_space &space, offs_t address, UINT16 *data)
TMS340X0_FROM_SHIFTREG_CB_MEMBER(artmagic_state::from_shiftreg)
{
artmagic_state *state = space.machine().driver_data<artmagic_state>();
UINT16 *vram = state->address_to_vram(&address);
UINT16 *vram = address_to_vram(&address);
if (vram)
memcpy(&vram[address], data, TOBYTE(0x2000));
memcpy(&vram[address], shiftreg, TOBYTE(0x2000));
}
@ -336,13 +334,12 @@ WRITE16_MEMBER(artmagic_state::artmagic_blitter_w)
*
*************************************/
void artmagic_scanline(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_RGB32_CB_MEMBER(artmagic_state::scanline)
{
artmagic_state *state = screen.machine().driver_data<artmagic_state>();
offs_t offset = (params->rowaddr << 12) & 0x7ff000;
UINT16 *vram = state->address_to_vram(&offset);
UINT16 *vram = address_to_vram(&offset);
UINT32 *dest = &bitmap.pix32(scanline);
const rgb_t *pens = state->m_tlc34076->get_pens();
const rgb_t *pens = m_tlc34076->get_pens();
int coladdr = params->coladdr << 1;
int x;

6
src/mame/video/btoads.c
View File

@ -259,7 +259,7 @@ void btoads_state::render_sprite_row(UINT16 *sprite_source, UINT32 address)
*
*************************************/
void btoads_state::to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_TO_SHIFTREG_CB_MEMBER(btoads_state::to_shiftreg)
{
address &= ~0x40000000;
@ -286,7 +286,7 @@ void btoads_state::to_shiftreg(address_space &space, UINT32 address, UINT16 *shi
}
void btoads_state::from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_FROM_SHIFTREG_CB_MEMBER(btoads_state::from_shiftreg)
{
address &= ~0x40000000;
@ -318,7 +318,7 @@ void btoads_state::from_shiftreg(address_space &space, UINT32 address, UINT16 *s
*
*************************************/
void btoads_state::scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_RGB32_CB_MEMBER(btoads_state::scanline_update)
{
UINT32 fulladdr = ((params->rowaddr << 16) | params->coladdr) >> 4;
UINT16 *bg0_base = &m_vram_bg0[(fulladdr + (m_yscroll0 << 10)) & 0x3fc00];

29
src/mame/video/exterm.c
View File

@ -32,31 +32,27 @@ PALETTE_INIT_MEMBER(exterm_state, exterm)
*
*************************************/
void exterm_to_shiftreg_master(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_TO_SHIFTREG_CB_MEMBER(exterm_state::to_shiftreg_master)
{
exterm_state *state = space.machine().driver_data<exterm_state>();
memcpy(shiftreg, &state->m_master_videoram[TOWORD(address)], 256 * sizeof(UINT16));
memcpy(shiftreg, &m_master_videoram[TOWORD(address)], 256 * sizeof(UINT16));
}
void exterm_from_shiftreg_master(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_FROM_SHIFTREG_CB_MEMBER(exterm_state::from_shiftreg_master)
{
exterm_state *state = space.machine().driver_data<exterm_state>();
memcpy(&state->m_master_videoram[TOWORD(address)], shiftreg, 256 * sizeof(UINT16));
memcpy(&m_master_videoram[TOWORD(address)], shiftreg, 256 * sizeof(UINT16));
}
void exterm_to_shiftreg_slave(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_TO_SHIFTREG_CB_MEMBER(exterm_state::to_shiftreg_slave)
{
exterm_state *state = space.machine().driver_data<exterm_state>();
memcpy(shiftreg, &state->m_slave_videoram[TOWORD(address)], 256 * 2 * sizeof(UINT8));
memcpy(shiftreg, &m_slave_videoram[TOWORD(address)], 256 * 2 * sizeof(UINT8));
}
void exterm_from_shiftreg_slave(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_FROM_SHIFTREG_CB_MEMBER(exterm_state::from_shiftreg_slave)
{
exterm_state *state = space.machine().driver_data<exterm_state>();
memcpy(&state->m_slave_videoram[TOWORD(address)], shiftreg, 256 * 2 * sizeof(UINT8));
memcpy(&m_slave_videoram[TOWORD(address)], shiftreg, 256 * 2 * sizeof(UINT8));
}
@ -67,10 +63,9 @@ void exterm_from_shiftreg_slave(address_space &space, UINT32 address, UINT16 *sh
*
*************************************/
void exterm_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_IND16_CB_MEMBER(exterm_state::scanline_update)
{
exterm_state *state = screen.machine().driver_data<exterm_state>();
UINT16 *bgsrc = &state->m_master_videoram[(params->rowaddr << 8) & 0xff00];
UINT16 *bgsrc = &m_master_videoram[(params->rowaddr << 8) & 0xff00];
UINT16 *fgsrc = NULL;
UINT16 *dest = &bitmap.pix16(scanline);
tms34010_display_params fgparams;
@ -79,12 +74,12 @@ void exterm_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int sca
int x;
/* get parameters for the slave CPU */
state->m_slave->get_display_params(&fgparams);
m_slave->get_display_params(&fgparams);
/* compute info about the slave vram */
if (fgparams.enabled && scanline >= fgparams.veblnk && scanline < fgparams.vsblnk && fgparams.heblnk < fgparams.hsblnk)
{
fgsrc = &state->m_slave_videoram[((fgparams.rowaddr << 8) + (fgparams.yoffset << 7)) & 0xff80];
fgsrc = &m_slave_videoram[((fgparams.rowaddr << 8) + (fgparams.yoffset << 7)) & 0xff80];
fgcoladdr = (fgparams.coladdr >> 1);
}

65
src/mame/video/harddriv.c
View File

@ -97,18 +97,16 @@ VIDEO_START_MEMBER(harddriv_state,harddriv)
*
*************************************/
void hdgsp_write_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_TO_SHIFTREG_CB_MEMBER(harddriv_state::hdgsp_write_to_shiftreg)
{
harddriv_state *state = space.machine().driver_data<harddriv_state>();
/* access to the 1bpp/2bpp area */
if (address >= 0x02000000 && address <= 0x020fffff)
{
address -= 0x02000000;
address >>= state->m_gsp_multisync;
address &= state->m_vram_mask;
address &= ~((512*8 >> state->m_gsp_multisync) - 1);
state->m_gsp_shiftreg_source = &state->m_gsp_vram[address];
address >>= m_gsp_multisync;
address &= m_vram_mask;
address &= ~((512*8 >> m_gsp_multisync) - 1);
m_gsp_shiftreg_source = &m_gsp_vram[address];
}
/* access to normal VRAM area */
@ -116,30 +114,28 @@ void hdgsp_write_to_shiftreg(address_space &space, UINT32 address, UINT16 *shift
{
address -= 0xff800000;
address /= 8;
address &= state->m_vram_mask;
address &= m_vram_mask;
address &= ~511;
state->m_gsp_shiftreg_source = &state->m_gsp_vram[address];
m_gsp_shiftreg_source = &m_gsp_vram[address];
}
else
logerror("Unknown shiftreg write %08X\n", address);
}
void hdgsp_read_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_FROM_SHIFTREG_CB_MEMBER(harddriv_state::hdgsp_read_from_shiftreg)
{
harddriv_state *state = space.machine().driver_data<harddriv_state>();
if (!state->m_shiftreg_enable)
if (!m_shiftreg_enable)
return;
/* access to the 1bpp/2bpp area */
if (address >= 0x02000000 && address <= 0x020fffff)
{
address -= 0x02000000;
address >>= state->m_gsp_multisync;
address &= state->m_vram_mask;
address &= ~((512*8 >> state->m_gsp_multisync) - 1);
memmove(&state->m_gsp_vram[address], state->m_gsp_shiftreg_source, 512*8 >> state->m_gsp_multisync);
address >>= m_gsp_multisync;
address &= m_vram_mask;
address &= ~((512*8 >> m_gsp_multisync) - 1);
memmove(&m_gsp_vram[address], m_gsp_shiftreg_source, 512*8 >> m_gsp_multisync);
}
/* access to normal VRAM area */
@ -147,9 +143,9 @@ void hdgsp_read_from_shiftreg(address_space &space, UINT32 address, UINT16 *shif
{
address -= 0xff800000;
address /= 8;
address &= state->m_vram_mask;
address &= m_vram_mask;
address &= ~511;
memmove(&state->m_gsp_vram[address], state->m_gsp_shiftreg_source, 512);
memmove(&m_gsp_vram[address], m_gsp_shiftreg_source, 512);
}
else
logerror("Unknown shiftreg read %08X\n", address);
@ -163,11 +159,10 @@ void hdgsp_read_from_shiftreg(address_space &space, UINT32 address, UINT16 *shif
*
*************************************/
static void update_palette_bank(running_machine &machine, int newbank)
void harddriv_state::update_palette_bank(int newbank)
{
harddriv_state *state = machine.driver_data<harddriv_state>();
machine.first_screen()->update_partial(machine.first_screen()->vpos());
state->m_gfx_palettebank = newbank;
m_screen->update_partial(m_screen->vpos());
m_gfx_palettebank = newbank;
}
@ -233,16 +228,16 @@ WRITE16_MEMBER( harddriv_state::hdgsp_control_hi_w )
break;
case 0x02:
update_palette_bank(space.machine(), (m_gfx_palettebank & ~1) | val);
update_palette_bank((m_gfx_palettebank & ~1) | val);
break;
case 0x03:
update_palette_bank(space.machine(), (m_gfx_palettebank & ~2) | (val << 1));
update_palette_bank((m_gfx_palettebank & ~2) | (val << 1));
break;
case 0x04:
if (m_palette->entries() >= 256 * 8)
update_palette_bank(space.machine(), (m_gfx_palettebank & ~4) | (val << 2));
update_palette_bank((m_gfx_palettebank & ~4) | (val << 2));
break;
case 0x07:
@ -410,32 +405,30 @@ static void display_speedups(void)
}
void harddriv_scanline_driver(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_IND16_CB_MEMBER(harddriv_state::scanline_driver)
{
harddriv_state *state = screen.machine().driver_data<harddriv_state>();
UINT8 *vram_base = &state->m_gsp_vram[(params->rowaddr << 12) & state->m_vram_mask];
UINT8 *vram_base = &m_gsp_vram[(params->rowaddr << 12) & m_vram_mask];
UINT16 *dest = &bitmap.pix16(scanline);
int coladdr = (params->yoffset << 9) + ((params->coladdr & 0xff) << 4) - 15 + (state->m_gfx_finescroll & 0x0f);
int coladdr = (params->yoffset << 9) + ((params->coladdr & 0xff) << 4) - 15 + (m_gfx_finescroll & 0x0f);
int x;
for (x = params->heblnk; x < params->hsblnk; x++)
dest[x] = state->m_gfx_palettebank * 256 + vram_base[BYTE_XOR_LE(coladdr++ & 0xfff)];
dest[x] = m_gfx_palettebank * 256 + vram_base[BYTE_XOR_LE(coladdr++ & 0xfff)];
if (scanline == screen.visible_area().max_y)
display_speedups();
}
void harddriv_scanline_multisync(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_IND16_CB_MEMBER(harddriv_state::scanline_multisync)
{
harddriv_state *state = screen.machine().driver_data<harddriv_state>();
UINT8 *vram_base = &state->m_gsp_vram[(params->rowaddr << 11) & state->m_vram_mask];
UINT8 *vram_base = &m_gsp_vram[(params->rowaddr << 11) & m_vram_mask];
UINT16 *dest = &bitmap.pix16(scanline);
int coladdr = (params->yoffset << 9) + ((params->coladdr & 0xff) << 3) - 7 + (state->m_gfx_finescroll & 0x07);
int coladdr = (params->yoffset << 9) + ((params->coladdr & 0xff) << 3) - 7 + (m_gfx_finescroll & 0x07);
int x;
for (x = params->heblnk; x < params->hsblnk; x++)
dest[x] = state->m_gfx_palettebank * 256 + vram_base[BYTE_XOR_LE(coladdr++ & 0x7ff)];
dest[x] = m_gfx_palettebank * 256 + vram_base[BYTE_XOR_LE(coladdr++ & 0x7ff)];
if (scanline == screen.visible_area().max_y)
display_speedups();

19
src/mame/video/jpmimpct.c
View File

@ -86,16 +86,14 @@ READ16_MEMBER(jpmimpct_state::jpmimpct_bt477_r)
*
*************************************/
void jpmimpct_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_TO_SHIFTREG_CB_MEMBER(jpmimpct_state::to_shiftreg)
{
jpmimpct_state *state = space.machine().driver_data<jpmimpct_state>();
memcpy(shiftreg, &state->m_vram[TOWORD(address)], 512 * sizeof(UINT16));
memcpy(shiftreg, &m_vram[TOWORD(address)], 512 * sizeof(UINT16));
}
void jpmimpct_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_FROM_SHIFTREG_CB_MEMBER(jpmimpct_state::from_shiftreg)
{
jpmimpct_state *state = space.machine().driver_data<jpmimpct_state>();
memcpy(&state->m_vram[TOWORD(address)], shiftreg, 512 * sizeof(UINT16));
memcpy(&m_vram[TOWORD(address)], shiftreg, 512 * sizeof(UINT16));
}
@ -105,10 +103,9 @@ void jpmimpct_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftr
*
*************************************/
void jpmimpct_scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_RGB32_CB_MEMBER(jpmimpct_state::scanline_update)
{
jpmimpct_state *state = screen.machine().driver_data<jpmimpct_state>();
UINT16 *vram = &state->m_vram[(params->rowaddr << 8) & 0x3ff00];
UINT16 *vram = &m_vram[(params->rowaddr << 8) & 0x3ff00];
UINT32 *dest = &bitmap.pix32(scanline);
int coladdr = params->coladdr;
int x;
@ -116,8 +113,8 @@ void jpmimpct_scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int s
for (x = params->heblnk; x < params->hsblnk; x += 2)
{
UINT16 pixels = vram[coladdr++ & 0xff];
dest[x + 0] = state->m_palette->pen(pixels & 0xff);
dest[x + 1] = state->m_palette->pen(pixels >> 8);
dest[x + 0] = m_palette->pen(pixels & 0xff);
dest[x + 1] = m_palette->pen(pixels >> 8);
}
}

9
src/mame/video/lethalj.c
View File

@ -178,21 +178,20 @@ WRITE16_MEMBER(lethalj_state::lethalj_blitter_w)
*
*************************************/
void lethalj_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_IND16_CB_MEMBER(lethalj_state::scanline_update)
{
lethalj_state *state = screen.machine().driver_data<lethalj_state>();
UINT16 *src = &state->m_screenram[(state->m_vispage << 17) | ((params->rowaddr << 9) & 0x3fe00)];
UINT16 *src = &m_screenram[(m_vispage << 17) | ((params->rowaddr << 9) & 0x3fe00)];
UINT16 *dest = &bitmap.pix16(scanline);
int coladdr = params->coladdr << 1;
int x;
/* blank palette: fill with white */
if (state->m_blank_palette)
if (m_blank_palette)
{
for (x = params->heblnk; x < params->hsblnk; x++)
dest[x] = 0x7fff;
if (scanline == screen.visible_area().max_y)
state->m_blank_palette = 0;
m_blank_palette = 0;
return;
}

12
src/mame/video/micro3d.c
View File

@ -60,20 +60,18 @@ void micro3d_state::video_reset()
*
*************************************/
void micro3d_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_IND16_CB_MEMBER(micro3d_state::scanline_update)
{
micro3d_state *state = screen.machine().driver_data<micro3d_state>();
UINT16 *src = &state->m_micro3d_sprite_vram[(params->rowaddr << 8) & 0x7fe00];
UINT16 *src = &m_micro3d_sprite_vram[(params->rowaddr << 8) & 0x7fe00];
UINT16 *dest = &bitmap.pix16(scanline);
int coladdr = params->coladdr;
int sd_11_7 = (state->m_creg & 0x1f) << 7;
int sd_11_7 = (m_creg & 0x1f) << 7;
int x;
UINT16 *frame_src;
scanline = MAX((scanline - params->veblnk), 0);
frame_src = state->m_frame_buffers[state->m_display_buffer] + (scanline << 10);
frame_src = m_frame_buffers[m_display_buffer] + (scanline << 10);
/* TODO: XFER3DK - X/Y offsets for 3D */
@ -125,7 +123,7 @@ WRITE16_MEMBER(micro3d_state::micro3d_xfer3dk_w)
m_xfer3dk = data;
}
void micro3d_tms_interrupt(device_t *device, int state)
WRITE_LINE_MEMBER(micro3d_state::tms_interrupt)
{
// mc68901_int_gen(device->machine(), GPIP4);
}

17
src/mame/video/midtunit.c
View File

@ -41,7 +41,6 @@ enum
/* graphics-related variables */
UINT8 midtunit_gfx_rom_large;
static UINT16 midtunit_control;
/* videoram-related variables */
@ -111,14 +110,14 @@ VIDEO_START_MEMBER(midtunit_state,midtunit)
VIDEO_START_MEMBER(midwunit_state,midwunit)
{
VIDEO_START_CALL_MEMBER(midtunit);
midtunit_gfx_rom_large = 1;
m_gfx_rom_large = 1;
}
VIDEO_START_MEMBER(midxunit_state,midxunit)
{
VIDEO_START_CALL_MEMBER(midtunit);
midtunit_gfx_rom_large = 1;
m_gfx_rom_large = 1;
videobank_select = 1;
}
@ -224,13 +223,13 @@ READ16_MEMBER(midtunit_state::midtunit_vram_color_r)
*
*************************************/
void midtunit_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_TO_SHIFTREG_CB_MEMBER(midtunit_state::to_shiftreg)
{
memcpy(shiftreg, &local_videoram[address >> 3], 2 * 512 * sizeof(UINT16));
}
void midtunit_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_FROM_SHIFTREG_CB_MEMBER(midtunit_state::from_shiftreg)
{
memcpy(&local_videoram[address >> 3], shiftreg, 2 * 512 * sizeof(UINT16));
}
@ -254,7 +253,7 @@ WRITE16_MEMBER(midtunit_state::midtunit_control_w)
COMBINE_DATA(&midtunit_control);
/* gfx bank select is bit 7 */
if (!(midtunit_control & 0x0080) || !midtunit_gfx_rom_large)
if (!(midtunit_control & 0x0080) || !m_gfx_rom_large)
gfxbank_offset[0] = 0x000000;
else
gfxbank_offset[0] = 0x800000;
@ -745,7 +744,7 @@ if (LOG_DMA)
gfxoffset = 0;
/* determine the location */
if (!midtunit_gfx_rom_large && gfxoffset >= 0x2000000)
if (!m_gfx_rom_large && gfxoffset >= 0x2000000)
gfxoffset -= 0x2000000;
if (gfxoffset >= 0xf8000000)
gfxoffset -= 0xf8000000;
@ -811,7 +810,7 @@ skipdma:
*
*************************************/
void midtunit_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_IND16_CB_MEMBER(midtunit_state::scanline_update)
{
UINT16 *src = &local_videoram[(params->rowaddr << 9) & 0x3fe00];
UINT16 *dest = &bitmap.pix16(scanline);
@ -823,7 +822,7 @@ void midtunit_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int s
dest[x] = src[coladdr++ & 0x1ff] & 0x7fff;
}
void midxunit_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_IND16_CB_MEMBER(midxunit_state::scanline_update)
{
UINT32 fulladdr = ((params->rowaddr << 16) | params->coladdr) >> 3;
UINT16 *src = &local_videoram[fulladdr & 0x3fe00];

21
src/mame/video/midyunit.c
View File

@ -171,17 +171,15 @@ READ16_MEMBER(midyunit_state::midyunit_vram_r)
*
*************************************/
void midyunit_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_TO_SHIFTREG_CB_MEMBER(midyunit_state::to_shiftreg)
{
midyunit_state *state = space.machine().driver_data<midyunit_state>();
memcpy(shiftreg, &state->m_local_videoram[address >> 3], 2 * 512 * sizeof(UINT16));
memcpy(shiftreg, &m_local_videoram[address >> 3], 2 * 512 * sizeof(UINT16));
}
void midyunit_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
TMS340X0_FROM_SHIFTREG_CB_MEMBER(midyunit_state::from_shiftreg)
{
midyunit_state *state = space.machine().driver_data<midyunit_state>();
memcpy(&state->m_local_videoram[address >> 3], shiftreg, 2 * 512 * sizeof(UINT16));
memcpy(&m_local_videoram[address >> 3], shiftreg, 2 * 512 * sizeof(UINT16));
}
@ -552,23 +550,22 @@ TIMER_CALLBACK_MEMBER(midyunit_state::autoerase_line)
}
void midyunit_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)
TMS340X0_SCANLINE_IND16_CB_MEMBER(midyunit_state::scanline_update)
{
midyunit_state *state = screen.machine().driver_data<midyunit_state>();
UINT16 *src = &state->m_local_videoram[(params->rowaddr << 9) & 0x3fe00];
UINT16 *src = &m_local_videoram[(params->rowaddr << 9) & 0x3fe00];
UINT16 *dest = &bitmap.pix16(scanline);
int coladdr = params->coladdr << 1;
int x;
/* adjust the display address to account for ignored bits */
for (x = params->heblnk; x < params->hsblnk; x++)
dest[x] = state->m_pen_map[src[coladdr++ & 0x1ff]];
dest[x] = m_pen_map[src[coladdr++ & 0x1ff]];
/* handle autoerase on the previous line */
state->autoerase_line(NULL, params->rowaddr - 1);
autoerase_line(NULL, params->rowaddr - 1);
/* if this is the last update of the screen, set a timer to clear out the final line */
/* (since we update one behind) */
if (scanline == screen.visible_area().max_y)
state->timer_set(screen.time_until_pos(scanline + 1), midyunit_state::TIMER_AUTOERASE_LINE, params->rowaddr);
timer_set(screen.time_until_pos(scanline + 1), midyunit_state::TIMER_AUTOERASE_LINE, params->rowaddr);
}