mirror of
https://github.com/holub/mame
synced 2025-04-24 17:30:55 +03:00
added i/o opcodes
This commit is contained in:
hap
parent
8908bdc264
commit
f148f7f609
@ -10,6 +10,19 @@
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*/
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enum
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{
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FAMILY_HMCS42 = 0,
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FAMILY_HMCS43,
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FAMILY_HMCS44,
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FAMILY_HMCS45,
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FAMILY_HMCS46,
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FAMILY_HMCS47,
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};
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#define IS_CMOS true
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#define IS_PMOS false
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#include "hmcs40.h"
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#include "debugger.h"
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@ -75,16 +88,30 @@ ADDRESS_MAP_END
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// device definitions
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hmcs43_cpu_device::hmcs43_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, bool is_cmos, const char *shortname)
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: hmcs40_cpu_device(mconfig, type, name, tag, owner, clock, FAMILY_HMCS43, is_cmos, 3, 12, ADDRESS_MAP_NAME(program_1k), 7, ADDRESS_MAP_NAME(data_80x4), shortname, __FILE__)
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{ }
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hd38750_device::hd38750_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: hmcs40_cpu_device(mconfig, HD38750, "HD38750", tag, owner, clock, 3, 12, ADDRESS_MAP_NAME(program_1k), 7, ADDRESS_MAP_NAME(data_80x4), "hd38750", __FILE__)
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: hmcs43_cpu_device(mconfig, HD38750, "HD38750", tag, owner, clock, IS_PMOS, "hd38750")
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{ }
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hmcs44_cpu_device::hmcs44_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, bool is_cmos, const char *shortname)
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: hmcs40_cpu_device(mconfig, type, name, tag, owner, clock, FAMILY_HMCS44, is_cmos, 4, 13, ADDRESS_MAP_NAME(program_2k), 8, ADDRESS_MAP_NAME(data_160x4), shortname, __FILE__)
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{ }
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hd38800_device::hd38800_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: hmcs40_cpu_device(mconfig, HD38800, "HD38800", tag, owner, clock, 4, 13, ADDRESS_MAP_NAME(program_2k), 8, ADDRESS_MAP_NAME(data_160x4), "hd38800", __FILE__)
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: hmcs44_cpu_device(mconfig, HD38800, "HD38800", tag, owner, clock, IS_PMOS, "hd38800")
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{ }
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hmcs45_cpu_device::hmcs45_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, bool is_cmos, const char *shortname)
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: hmcs40_cpu_device(mconfig, type, name, tag, owner, clock, FAMILY_HMCS45, is_cmos, 4, 13, ADDRESS_MAP_NAME(program_2k), 8, ADDRESS_MAP_NAME(data_160x4), shortname, __FILE__)
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{ }
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hd38820_device::hd38820_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: hmcs40_cpu_device(mconfig, HD38820, "HD38820", tag, owner, clock, 4, 13, ADDRESS_MAP_NAME(program_2k), 8, ADDRESS_MAP_NAME(data_160x4), "hd38820", __FILE__)
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: hmcs45_cpu_device(mconfig, HD38820, "HD38820", tag, owner, clock, IS_PMOS, "hd38820")
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{ }
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@ -101,7 +128,7 @@ void hmcs40_cpu_device::state_string_export(const device_state_entry &entry, ast
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break;
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case STATE_GENPC:
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string.printf("%03X", m_pc << 1);
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string.printf("%04X", m_pc << 1);
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break;
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default: break;
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@ -132,17 +159,35 @@ void hmcs40_cpu_device::device_start()
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m_data = &space(AS_DATA);
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m_prgmask = (1 << m_prgwidth) - 1;
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m_datamask = (1 << m_datawidth) - 1;
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m_xmask = (1 << (m_datawidth - 4)) - 1;
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UINT8 defval = (m_is_cmos) ? 0xf : 0;
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m_read_r0.resolve_safe(defval);
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m_read_r1.resolve_safe(defval);
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m_read_r2.resolve_safe(defval);
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m_read_r3.resolve_safe(defval);
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m_read_r4.resolve_safe(defval);
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m_read_r5.resolve_safe(defval);
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m_read_r6.resolve_safe(defval);
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m_read_r7.resolve_safe(defval);
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m_write_r0.resolve_safe();
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m_write_r1.resolve_safe();
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m_write_r2.resolve_safe();
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m_write_r3.resolve_safe();
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m_write_r4.resolve_safe();
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m_write_r5.resolve_safe();
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m_write_r6.resolve_safe();
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m_write_r7.resolve_safe();
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m_read_d.resolve_safe(0);
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m_read_d.resolve_safe((m_is_cmos) ? 0xffff : 0);
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m_write_d.resolve_safe();
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// zerofill
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memset(m_stack, 0, sizeof(m_stack));
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m_op = 0;
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m_prev_op = 0;
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m_arg = 0;
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m_pc = 0;
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m_prev_pc = 0;
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m_page = 0;
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m_a = 0;
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m_b = 0;
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@ -150,15 +195,17 @@ void hmcs40_cpu_device::device_start()
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m_spx = 0;
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m_y = 0;
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m_spy = 0;
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m_s = 0;
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m_s = 1;
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m_c = 0;
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memset(m_r, 0, sizeof(m_r));
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m_d = 0;
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// register for savestates
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save_item(NAME(m_stack));
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save_item(NAME(m_op));
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save_item(NAME(m_prev_op));
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save_item(NAME(m_arg));
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save_item(NAME(m_pc));
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save_item(NAME(m_prev_pc));
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save_item(NAME(m_page));
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save_item(NAME(m_a));
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save_item(NAME(m_b));
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@ -168,6 +215,8 @@ void hmcs40_cpu_device::device_start()
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save_item(NAME(m_spy));
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save_item(NAME(m_s));
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save_item(NAME(m_c));
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save_item(NAME(m_r));
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save_item(NAME(m_d));
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// register state for debugger
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state_add(HMCS40_PC, "PC", m_pc).formatstr("%04X");
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@ -178,7 +227,7 @@ void hmcs40_cpu_device::device_start()
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state_add(HMCS40_Y, "Y", m_y).formatstr("%01X");
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state_add(HMCS40_SPY, "SPY", m_spy).formatstr("%01X");
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state_add(STATE_GENPC, "curpc", m_pc).formatstr("%03X").noshow();
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state_add(STATE_GENPC, "curpc", m_pc).formatstr("%04X").noshow();
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state_add(STATE_GENFLAGS, "GENFLAGS", m_s).formatstr("%2s").noshow();
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m_icountptr = &m_icount;
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@ -192,8 +241,16 @@ void hmcs40_cpu_device::device_start()
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void hmcs40_cpu_device::device_reset()
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{
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m_pc = 0xffff & m_prgmask;
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m_op = 0;
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m_pc = m_prgmask;
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m_prev_op = m_op = 0;
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// clear i/o
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m_d = (m_is_cmos) ? 0xffff : 0;
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for (int i = 0; i < 16; i++)
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hmcs40_cpu_device::write_d(i, (m_is_cmos) ? 1 : 0);
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for (int i = 0; i < 8; i++)
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hmcs40_cpu_device::write_r(i, (m_is_cmos) ? 0xf : 0);
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}
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@ -217,17 +274,6 @@ inline void hmcs40_cpu_device::increment_pc()
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m_pc = (m_pc & ~mask) | ((m_pc << 1 | fb) & mask);
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}
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inline void hmcs40_cpu_device::fetch_arg()
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{
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// P is the only 2-byte opcode
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if ((m_op & 0x3f8) == 0x368)
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{
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m_icount--;
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m_arg = m_program->read_word(m_pc << 1);
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increment_pc();
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}
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}
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void hmcs40_cpu_device::execute_run()
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{
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while (m_icount > 0)
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@ -238,13 +284,13 @@ void hmcs40_cpu_device::execute_run()
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if ((m_prev_op & 0x3e0) == 0x340)
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m_pc = ((m_page << 6) | (m_pc & 0x3f)) & m_prgmask;
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// remember previous opcode
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// remember previous state
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m_prev_op = m_op;
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m_prev_pc = m_pc;
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// fetch next opcode
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debugger_instruction_hook(this, m_pc << 1);
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m_op = m_program->read_word(m_pc << 1);
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increment_pc();
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fetch_arg();
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}
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}
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@ -13,6 +13,14 @@
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// I/O ports setup
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// max 8 4-bit R ports
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#define MCFG_HMCS40_READ_R_CB(_r, _devcb) \
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hmcs40_cpu_device::set_read_r##_r_callback(*device, DEVCB_##_devcb);
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#define MCFG_HMCS40_WRITE_R_CB(_r, _devcb) \
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hmcs40_cpu_device::set_write_r##_r_callback(*device, DEVCB_##_devcb);
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// 16-bit discrete
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#define MCFG_HMCS40_READ_A_CB(_devcb) \
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hmcs40_cpu_device::set_read_d_callback(*device, DEVCB_##_devcb);
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#define MCFG_HMCS40_WRITE_D_CB(_devcb) \
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@ -24,18 +32,40 @@ class hmcs40_cpu_device : public cpu_device
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{
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public:
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// construction/destruction
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hmcs40_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, int stack_levels, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char *shortname, const char *source)
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hmcs40_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, int family, bool is_cmos, int stack_levels, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char *shortname, const char *source)
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: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
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, m_program_config("program", ENDIANNESS_LITTLE, 16, prgwidth, 0, program)
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, m_data_config("data", ENDIANNESS_LITTLE, 8, datawidth, 0, data)
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, m_prgwidth(prgwidth-1)
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, m_datawidth(datawidth)
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, m_family(family)
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, m_is_cmos(is_cmos)
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, m_stack_levels(stack_levels)
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, m_read_r0(*this), m_read_r1(*this), m_read_r2(*this), m_read_r3(*this), m_read_r4(*this), m_read_r5(*this), m_read_r6(*this), m_read_r7(*this)
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, m_write_r0(*this), m_write_r1(*this), m_write_r2(*this), m_write_r3(*this), m_write_r4(*this), m_write_r5(*this), m_write_r6(*this), m_write_r7(*this)
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, m_read_d(*this)
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, m_write_d(*this)
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{ }
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// static configuration helpers
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template<class _Object> static devcb_base &set_read_r0_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_read_r0.set_callback(object); }
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template<class _Object> static devcb_base &set_read_r1_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_read_r1.set_callback(object); }
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template<class _Object> static devcb_base &set_read_r2_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_read_r2.set_callback(object); }
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template<class _Object> static devcb_base &set_read_r3_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_read_r3.set_callback(object); }
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template<class _Object> static devcb_base &set_read_r4_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_read_r4.set_callback(object); }
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template<class _Object> static devcb_base &set_read_r5_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_read_r5.set_callback(object); }
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template<class _Object> static devcb_base &set_read_r6_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_read_r6.set_callback(object); }
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template<class _Object> static devcb_base &set_read_r7_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_read_r7.set_callback(object); }
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template<class _Object> static devcb_base &set_write_r0_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_write_r0.set_callback(object); }
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template<class _Object> static devcb_base &set_write_r1_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_write_r1.set_callback(object); }
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template<class _Object> static devcb_base &set_write_r2_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_write_r2.set_callback(object); }
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template<class _Object> static devcb_base &set_write_r3_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_write_r3.set_callback(object); }
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template<class _Object> static devcb_base &set_write_r4_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_write_r4.set_callback(object); }
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template<class _Object> static devcb_base &set_write_r5_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_write_r5.set_callback(object); }
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template<class _Object> static devcb_base &set_write_r6_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_write_r6.set_callback(object); }
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template<class _Object> static devcb_base &set_write_r7_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_write_r7.set_callback(object); }
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template<class _Object> static devcb_base &set_read_d_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_read_d.set_callback(object); }
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template<class _Object> static devcb_base &set_write_d_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_write_d.set_callback(object); }
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@ -54,7 +84,7 @@ protected:
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return(spacenum == AS_PROGRAM) ? &m_program_config :((spacenum == AS_DATA) ? &m_data_config : NULL); }
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
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virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
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virtual UINT32 disasm_max_opcode_bytes() const { return 2; }
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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void state_string_export(const device_state_entry &entry, astring &string);
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@ -68,15 +98,16 @@ protected:
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int m_datawidth;
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int m_prgmask;
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int m_datamask;
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int m_xmask;
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int m_family; // MCU family (42-47)
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bool m_is_cmos;
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int m_stack_levels; // number of callstack levels
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UINT16 m_stack[4]; // max 4
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UINT16 m_op;
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UINT16 m_op; // current opcode
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UINT16 m_prev_op;
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UINT16 m_arg;
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int m_icount;
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UINT16 m_pc; // Program Counter
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UINT16 m_prev_pc;
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UINT8 m_page; // LPU prepared page
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UINT8 m_a; // 4-bit Accumulator
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UINT8 m_b; // 4-bit B register
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@ -86,20 +117,28 @@ protected:
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UINT8 m_spy; // 4-bit SPY register
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UINT8 m_s; // Status F/F
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UINT8 m_c; // Carry F/F
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UINT8 m_r[8]; // R outputs state
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UINT16 m_d; // D pins state
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// i/o handlers
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devcb_read8 m_read_r0, m_read_r1, m_read_r2, m_read_r3, m_read_r4, m_read_r5, m_read_r6, m_read_r7;
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devcb_write8 m_write_r0, m_write_r1, m_write_r2, m_write_r3, m_write_r4, m_write_r5, m_write_r6, m_write_r7;
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devcb_read16 m_read_d;
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devcb_write16 m_write_d;
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// misc internal helpers
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void increment_pc();
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void fetch_arg();
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UINT8 ram_r();
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void ram_w(UINT8 data);
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void pop_stack();
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void push_stack();
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virtual UINT8 read_r(int index);
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virtual void write_r(int index, UINT8 data);
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virtual int read_d(int index);
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virtual void write_d(int index, int state);
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// opcode handlers
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void op_lab();
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void op_lba();
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@ -202,21 +241,55 @@ protected:
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};
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class hd38750_device : public hmcs40_cpu_device
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class hmcs43_cpu_device : public hmcs40_cpu_device
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{
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public:
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hmcs43_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, bool is_cmos, const char *shortname);
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protected:
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// overrides
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virtual UINT8 read_r(int index);
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virtual void write_r(int index, UINT8 data);
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virtual int read_d(int index);
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};
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class hd38750_device : public hmcs43_cpu_device
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{
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public:
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hd38750_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class hd38800_device : public hmcs40_cpu_device
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class hmcs44_cpu_device : public hmcs40_cpu_device
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{
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public:
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hmcs44_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, bool is_cmos, const char *shortname);
|
||||
|
||||
protected:
|
||||
// overrides
|
||||
virtual UINT8 read_r(int index);
|
||||
virtual void write_r(int index, UINT8 data);
|
||||
};
|
||||
|
||||
class hd38800_device : public hmcs44_cpu_device
|
||||
{
|
||||
public:
|
||||
hd38800_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
|
||||
class hd38820_device : public hmcs40_cpu_device
|
||||
class hmcs45_cpu_device : public hmcs40_cpu_device
|
||||
{
|
||||
public:
|
||||
hmcs45_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, bool is_cmos, const char *shortname);
|
||||
|
||||
protected:
|
||||
// overrides
|
||||
virtual UINT8 read_r(int index);
|
||||
virtual void write_r(int index, UINT8 data);
|
||||
};
|
||||
|
||||
class hd38820_device : public hmcs45_cpu_device
|
||||
{
|
||||
public:
|
||||
hd38820_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
@ -28,11 +28,144 @@ void hmcs40_cpu_device::push_stack()
|
||||
m_stack[0] = m_pc;
|
||||
}
|
||||
|
||||
void hmcs40_cpu_device::op_illegal()
|
||||
|
||||
// i/o
|
||||
|
||||
UINT8 hmcs40_cpu_device::read_r(int index)
|
||||
{
|
||||
logerror("%s unknown opcode $%03X at $%04X\n", tag(), m_op, m_pc);
|
||||
index &= 7;
|
||||
UINT8 inp = 0xf;
|
||||
|
||||
switch (index)
|
||||
{
|
||||
case 0: inp = m_read_r0(index, 0xff); break;
|
||||
case 1: inp = m_read_r1(index, 0xff); break;
|
||||
case 2: inp = m_read_r2(index, 0xff); break;
|
||||
case 3: inp = m_read_r3(index, 0xff); break;
|
||||
case 4: inp = m_read_r4(index, 0xff); break;
|
||||
case 5: inp = m_read_r5(index, 0xff); break;
|
||||
case 6: inp = m_read_r6(index, 0xff); break;
|
||||
case 7: inp = m_read_r7(index, 0xff); break;
|
||||
}
|
||||
|
||||
if (m_is_cmos)
|
||||
return inp & m_r[index];
|
||||
else
|
||||
return inp | m_r[index];
|
||||
}
|
||||
|
||||
void hmcs40_cpu_device::write_r(int index, UINT8 data)
|
||||
{
|
||||
index &= 7;
|
||||
m_r[index] = data & 0xf;
|
||||
|
||||
switch (index)
|
||||
{
|
||||
case 0: m_write_r0(index, m_r[index], 0xff); break;
|
||||
case 1: m_write_r1(index, m_r[index], 0xff); break;
|
||||
case 2: m_write_r2(index, m_r[index], 0xff); break;
|
||||
case 3: m_write_r3(index, m_r[index], 0xff); break;
|
||||
case 4: m_write_r4(index, m_r[index], 0xff); break;
|
||||
case 5: m_write_r5(index, m_r[index], 0xff); break;
|
||||
case 6: m_write_r6(index, m_r[index], 0xff); break;
|
||||
case 7: m_write_r7(index, m_r[index], 0xff); break;
|
||||
}
|
||||
}
|
||||
|
||||
int hmcs40_cpu_device::read_d(int index)
|
||||
{
|
||||
index &= 15;
|
||||
|
||||
if (m_is_cmos)
|
||||
return (m_read_d(index, 0xffff) & m_d) >> index & 1;
|
||||
else
|
||||
return (m_read_d(index, 0xffff) | m_d) >> index & 1;
|
||||
}
|
||||
|
||||
void hmcs40_cpu_device::write_d(int index, int state)
|
||||
{
|
||||
index &= 15;
|
||||
|
||||
m_d = (m_d & ~(1 << index)) | (state << index);
|
||||
m_write_d(index, m_d, 0xffff);
|
||||
}
|
||||
|
||||
// HMCS43:
|
||||
// R0 is input-only, R1 is i/o, R2,R3 are output-only, no R4-R7
|
||||
// D0-D3 are i/o, D4-D15 are output-only
|
||||
|
||||
UINT8 hmcs43_cpu_device::read_r(int index)
|
||||
{
|
||||
if ((index & 7) >= 4)
|
||||
logerror("%s read from unknown port R%d at $%04X\n", tag(), index & 7, m_prev_pc << 1);
|
||||
|
||||
return hmcs40_cpu_device::read_r(index);
|
||||
}
|
||||
|
||||
void hmcs43_cpu_device::write_r(int index, UINT8 data)
|
||||
{
|
||||
index &= 7;
|
||||
|
||||
if (index != 0 && index < 4)
|
||||
hmcs40_cpu_device::write_r(index, data);
|
||||
else
|
||||
logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
|
||||
}
|
||||
|
||||
int hmcs43_cpu_device::read_d(int index)
|
||||
{
|
||||
if ((index & 15) >= 4)
|
||||
return m_d >> index & 1;
|
||||
else
|
||||
return hmcs40_cpu_device::read_d(index);
|
||||
}
|
||||
|
||||
// HMCS44:
|
||||
// R0-R3 are i/o, R4,R5 are extra registers, no R6,R7
|
||||
// D0-D15 are i/o
|
||||
|
||||
UINT8 hmcs44_cpu_device::read_r(int index)
|
||||
{
|
||||
if ((index & 7) >= 6)
|
||||
logerror("%s read from unknown port R%d at $%04X\n", tag(), index & 7, m_prev_pc << 1);
|
||||
|
||||
return hmcs40_cpu_device::read_r(index);
|
||||
}
|
||||
|
||||
void hmcs44_cpu_device::write_r(int index, UINT8 data)
|
||||
{
|
||||
index &= 7;
|
||||
|
||||
if (index < 6)
|
||||
hmcs40_cpu_device::write_r(index, data);
|
||||
else
|
||||
logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
|
||||
}
|
||||
|
||||
// HMCS45:
|
||||
// R0-R5 are i/o, R6 is output-only, no R7
|
||||
// D0-D15 are i/o
|
||||
|
||||
UINT8 hmcs45_cpu_device::read_r(int index)
|
||||
{
|
||||
if ((index & 7) == 7)
|
||||
logerror("%s read from unknown port R%d at $%04X\n", tag(), index & 7, m_prev_pc << 1);
|
||||
|
||||
return hmcs40_cpu_device::read_r(index);
|
||||
}
|
||||
|
||||
void hmcs45_cpu_device::write_r(int index, UINT8 data)
|
||||
{
|
||||
index &= 7;
|
||||
|
||||
if (index != 7)
|
||||
hmcs40_cpu_device::write_r(index, data);
|
||||
else
|
||||
logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// instruction set
|
||||
@ -461,7 +594,7 @@ void hmcs40_cpu_device::op_lpu()
|
||||
void hmcs40_cpu_device::op_tbr()
|
||||
{
|
||||
// TBR p: Table Branch
|
||||
m_pc = (m_a | m_b << 4 | m_c << 8 | ((m_op & 7) << 9)) & m_prgmask;
|
||||
m_pc = (m_a | m_b << 4 | m_c << 8 | (m_op & 7) << 9) & m_prgmask;
|
||||
}
|
||||
|
||||
void hmcs40_cpu_device::op_rtn()
|
||||
@ -593,61 +726,75 @@ void hmcs40_cpu_device::op_rtni()
|
||||
void hmcs40_cpu_device::op_sed()
|
||||
{
|
||||
// SED: Set Discrete I/O Latch
|
||||
op_illegal();
|
||||
write_d(m_y, 1);
|
||||
}
|
||||
|
||||
void hmcs40_cpu_device::op_red()
|
||||
{
|
||||
// RED: Reset Discrete I/O Latch
|
||||
op_illegal();
|
||||
write_d(m_y, 0);
|
||||
}
|
||||
|
||||
void hmcs40_cpu_device::op_td()
|
||||
{
|
||||
// TD: Test Discrete I/O Latch
|
||||
op_illegal();
|
||||
m_s = read_d(m_y);
|
||||
}
|
||||
|
||||
void hmcs40_cpu_device::op_sedd()
|
||||
{
|
||||
// SEDD n: Set Discrete I/O Latch Direct
|
||||
op_illegal();
|
||||
write_d(m_op & 0xf, 1);
|
||||
}
|
||||
|
||||
void hmcs40_cpu_device::op_redd()
|
||||
{
|
||||
// REDD n: Reset Discrete I/O Latch Direct
|
||||
op_illegal();
|
||||
write_d(m_op & 0xf, 0);
|
||||
}
|
||||
|
||||
void hmcs40_cpu_device::op_lar()
|
||||
{
|
||||
// LAR p: Load A from R-Port Register
|
||||
op_illegal();
|
||||
m_a = read_r(m_op & 7);
|
||||
}
|
||||
|
||||
void hmcs40_cpu_device::op_lbr()
|
||||
{
|
||||
// LBR p: Load B from R-Port Register
|
||||
op_illegal();
|
||||
m_b = read_r(m_op & 7);
|
||||
}
|
||||
|
||||
void hmcs40_cpu_device::op_lra()
|
||||
{
|
||||
// LRA p: Load R-Port Register from A
|
||||
op_illegal();
|
||||
write_r(m_op & 7, m_a);
|
||||
}
|
||||
|
||||
void hmcs40_cpu_device::op_lrb()
|
||||
{
|
||||
// LRB p: Load R-Port Register from B
|
||||
op_illegal();
|
||||
write_r(m_op & 7, m_b);
|
||||
}
|
||||
|
||||
void hmcs40_cpu_device::op_p()
|
||||
{
|
||||
// P p: Pattern Generation
|
||||
op_illegal();
|
||||
m_icount--;
|
||||
UINT16 address = (m_a | m_b << 4 | m_c << 8 | (m_op & 7) << 9) | (m_pc & ~0x3f);
|
||||
UINT16 o = m_program->read_word(address << 1);
|
||||
|
||||
// destination is determined by the 2 highest bits
|
||||
if (o & 0x100)
|
||||
{
|
||||
m_a = o & 0xf;
|
||||
m_b = o >> 4 & 0xf;
|
||||
}
|
||||
if (o & 0x200)
|
||||
{
|
||||
write_r(2, o >> 4 & 0xf);
|
||||
write_r(3, o & 0xf);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -657,3 +804,9 @@ void hmcs40_cpu_device::op_nop()
|
||||
{
|
||||
// NOP: No Operation
|
||||
}
|
||||
|
||||
|
||||
void hmcs40_cpu_device::op_illegal()
|
||||
{
|
||||
logerror("%s unknown opcode $%03X at $%04X\n", tag(), m_op, m_prev_pc << 1);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user