From f27a74bf7056747bc449f5fbcf185f1bb3a7236b Mon Sep 17 00:00:00 2001 From: Ville Linde Date: Wed, 1 Oct 2014 14:13:21 +0000 Subject: [PATCH] powerpc: fix unaligned 64-bit accesses (nw) --- src/emu/cpu/powerpc/ppcdrc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/emu/cpu/powerpc/ppcdrc.c b/src/emu/cpu/powerpc/ppcdrc.c index 67f3cf84f20..50f63b71dcb 100644 --- a/src/emu/cpu/powerpc/ppcdrc.c +++ b/src/emu/cpu/powerpc/ppcdrc.c @@ -1297,6 +1297,7 @@ void ppc_device::static_generate_memory_accessor(int mode, int size, int iswrite UML_MOV(block, mem(&m_core->tempaddr), I0); // mov [tempaddr],i0 UML_DMOV(block, mem(&m_core->tempdata.d), I1); // dmov [tempdata],i1 UML_DSHR(block, I1, I1, 32); // dshr i1,i1,32 + UML_AND(block, I0, I0, ~7); // and i0,i0,~7 UML_DMOV(block, I2, U64(0x00000000ffffffff)); // dmov i2,0x00000000ffffffff UML_CALLH(block, *masked); // callh masked UML_ADD(block, I0, mem(&m_core->tempaddr), 4); // add i0,[tempaddr],4 @@ -1308,6 +1309,7 @@ void ppc_device::static_generate_memory_accessor(int mode, int size, int iswrite { UML_MOV(block, mem(&m_core->tempaddr), I0); // mov [tempaddr],i0 UML_DMOV(block, I2, U64(0x00000000ffffffff)); // mov i2,0x00000000ffffffff + UML_AND(block, I0, I0, ~7); // and i0,i0,~7 UML_CALLH(block, *masked); // callh masked UML_DSHL(block, mem(&m_core->tempdata.d), I0, 32); // dshl [tempdata],i0,32 UML_ADD(block, I0, mem(&m_core->tempaddr), 4); // add i0,[tempaddr],4