Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-10-04 16:34:53 +03:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

move tmpz84c011 specifics to its own files, make z80ctc a subdevice rather than adding it separately it in each driver using a tmpz84c011. (nw)

Browse Source
This commit is contained in:
David Haywood 2014-06-11 13:50:26 +00:00
parent 3b37f871b7
commit f2b2974176
10 changed files with 458 additions and 435 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitattributes vendored
View File

@ -2261,6 +2261,8 @@ src/emu/cpu/z8/z8.h svneol=native#text/plain
src/emu/cpu/z8/z8dasm.c svneol=native#text/plain
src/emu/cpu/z8/z8ops.inc svneol=native#text/plain
src/emu/cpu/z80/tlcs_z80.c svneol=native#text/plain
src/emu/cpu/z80/tmpz84c011.c svneol=native#text/plain
src/emu/cpu/z80/tmpz84c011.h svneol=native#text/plain
src/emu/cpu/z80/z80.c svneol=native#text/plain
src/emu/cpu/z80/z80.h svneol=native#text/plain
src/emu/cpu/z80/z80daisy.c svneol=native#text/plain

1
src/emu/cpu/cpu.mak
View File

@ -2229,6 +2229,7 @@ $(CPUOBJ)/tlcs900/dasm900.o: $(CPUSRC)/tlcs900/dasm900.c
ifneq ($(filter Z80,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/z80
CPUOBJS += $(CPUOBJ)/z80/z80.o $(CPUOBJ)/z80/tlcs_z80.o $(CPUOBJ)/z80/z80daisy.o
CPUOBJS += $(CPUOBJ)/z80/tmpz84c011.o
DASMOBJS += $(CPUOBJ)/z80/z80dasm.o
endif

282
src/emu/cpu/z80/tmpz84c011.c Normal file
View File

@ -0,0 +1,282 @@
#include "tmpz84c011.h"
// how do we actually install default handlers for logging?
/*
READ8_MEMBER(tmpz84c011_device::porta_default_r) { logerror("%s read port A but no handler assigned\n", machine().describe_context()); return 0xff; }
READ8_MEMBER(tmpz84c011_device::portb_default_r) { logerror("%s read port B but no handler assigned\n", machine().describe_context()); return 0xff; }
READ8_MEMBER(tmpz84c011_device::portc_default_r) { logerror("%s read port C but no handler assigned\n", machine().describe_context()); return 0xff; }
READ8_MEMBER(tmpz84c011_device::portd_default_r) { logerror("%s read port D but no handler assigned\n", machine().describe_context()); return 0xff; }
READ8_MEMBER(tmpz84c011_device::porte_default_r) { logerror("%s read port E but no handler assigned\n", machine().describe_context()); return 0xff; }
WRITE8_MEMBER(tmpz84c011_device::porta_default_w) { logerror("%s write %02x to port A but no handler assigned\n", machine().describe_context(), data); }
WRITE8_MEMBER(tmpz84c011_device::portb_default_w) { logerror("%s write %02x to port B but no handler assigned\n", machine().describe_context(), data); }
WRITE8_MEMBER(tmpz84c011_device::portc_default_w) { logerror("%s write %02x to port C but no handler assigned\n", machine().describe_context(), data); }
WRITE8_MEMBER(tmpz84c011_device::portd_default_w) { logerror("%s write %02x to port D but no handler assigned\n", machine().describe_context(), data); }
WRITE8_MEMBER(tmpz84c011_device::porte_default_w) { logerror("%s write %02x to port E but no handler assigned\n", machine().describe_context(), data); }
*/
READ8_MEMBER(tmpz84c011_device::tmpz84c011_pio_r)
{
int portdata = 0xff;
switch (offset)
{
case 0: /* PA_0 */
portdata = m_inports0();
break;
case 1: /* PB_0 */
portdata = m_inports1();
break;
case 2: /* PC_0 */
portdata = m_inports2();
break;
case 3: /* PD_0 */
portdata = m_inports3();
break;
case 4: /* PE_0 */
portdata = m_inports4();
break;
}
return portdata;
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pio_w)
{
switch (offset)
{
case 0: /* PA_0 */
m_outports0(data);
break;
case 1: /* PB_0 */
m_outports1(data);
break;
case 2: /* PC_0 */
m_outports2(data);
break;
case 3: /* PD_0 */
m_outports3(data);
break;
case 4: /* PE_0 */
m_outports4(data);
break;
}
}
/* CPU interface */
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_r)
{
return (tmpz84c011_pio_r(space,0) & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]);
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_r)
{
return (tmpz84c011_pio_r(space,1) & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]);
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_r)
{
return (tmpz84c011_pio_r(space,2) & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]);
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_r)
{
return (tmpz84c011_pio_r(space,3) & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]);
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_r)
{
return (tmpz84c011_pio_r(space,4) & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]);
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_w)
{
m_pio_latch[0] = data;
tmpz84c011_pio_w(space, 0, data);
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_w)
{
m_pio_latch[1] = data;
tmpz84c011_pio_w(space, 1, data);
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_w)
{
m_pio_latch[2] = data;
tmpz84c011_pio_w(space, 2, data);
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_w)
{
m_pio_latch[3] = data;
tmpz84c011_pio_w(space, 3, data);
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_w)
{
m_pio_latch[4] = data;
tmpz84c011_pio_w(space, 4, data);
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_r)
{
return m_pio_dir[0];
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_r)
{
return m_pio_dir[1];
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_r)
{
return m_pio_dir[2];
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_r)
{
return m_pio_dir[3];
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_r)
{
return m_pio_dir[4];
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_w)
{
m_pio_dir[0] = data;
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_w)
{
m_pio_dir[1] = data;
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_w)
{
m_pio_dir[2] = data;
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_w)
{
m_pio_dir[3] = data;
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_w)
{
m_pio_dir[4] = data;
}
static ADDRESS_MAP_START( tmpz84c011_internal_io_map, AS_IO, 8, tmpz84c011_device )
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ctc", z80ctc_device, read, write) AM_MIRROR(0xff00)
AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w) AM_MIRROR(0xff00)
AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w) AM_MIRROR(0xff00)
AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w) AM_MIRROR(0xff00)
AM_RANGE(0x30, 0x30) AM_READWRITE(tmpz84c011_0_pd_r, tmpz84c011_0_pd_w) AM_MIRROR(0xff00)
AM_RANGE(0x40, 0x40) AM_READWRITE(tmpz84c011_0_pe_r, tmpz84c011_0_pe_w) AM_MIRROR(0xff00)
AM_RANGE(0x54, 0x54) AM_READWRITE(tmpz84c011_0_dir_pa_r, tmpz84c011_0_dir_pa_w) AM_MIRROR(0xff00)
AM_RANGE(0x55, 0x55) AM_READWRITE(tmpz84c011_0_dir_pb_r, tmpz84c011_0_dir_pb_w) AM_MIRROR(0xff00)
AM_RANGE(0x56, 0x56) AM_READWRITE(tmpz84c011_0_dir_pc_r, tmpz84c011_0_dir_pc_w) AM_MIRROR(0xff00)
AM_RANGE(0x34, 0x34) AM_READWRITE(tmpz84c011_0_dir_pd_r, tmpz84c011_0_dir_pd_w) AM_MIRROR(0xff00)
AM_RANGE(0x44, 0x44) AM_READWRITE(tmpz84c011_0_dir_pe_r, tmpz84c011_0_dir_pe_w) AM_MIRROR(0xff00)
ADDRESS_MAP_END
tmpz84c011_device::tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: z80_device(mconfig, TMPZ84C011, "TMPZ84C011", tag, owner, clock, "tmpz84c011", __FILE__),
m_io_space_config( "io", ENDIANNESS_LITTLE, 8, 16, 0, ADDRESS_MAP_NAME( tmpz84c011_internal_io_map ) ),
m_outports0(*this),
m_outports1(*this),
m_outports2(*this),
m_outports3(*this),
m_outports4(*this),
m_inports0(*this),
m_inports1(*this),
m_inports2(*this),
m_inports3(*this),
m_inports4(*this),
m_intr_cb(*this),
m_zc0_cb(*this),
m_zc1_cb(*this),
m_zc2_cb(*this)
{
}
WRITE_LINE_MEMBER( tmpz84c011_device::intr_cb_trampoline_w ) { m_intr_cb(state); }
WRITE_LINE_MEMBER( tmpz84c011_device::zc0_cb_trampoline_w ) { m_zc0_cb(state); }
WRITE_LINE_MEMBER( tmpz84c011_device::zc1_cb_trampoline_w ) { m_zc1_cb(state); }
WRITE_LINE_MEMBER( tmpz84c011_device::zc2_cb_trampoline_w ) { m_zc2_cb(state); }
const device_type TMPZ84C011 = &device_creator<tmpz84c011_device>;
static MACHINE_CONFIG_FRAGMENT( tmpz84c011 )
MCFG_DEVICE_ADD("ctc", Z80CTC, DERIVED_CLOCK(1,1) )
MCFG_Z80CTC_INTR_CB(WRITELINE(tmpz84c011_device, intr_cb_trampoline_w))
MCFG_Z80CTC_ZC0_CB(WRITELINE(tmpz84c011_device, zc0_cb_trampoline_w))
MCFG_Z80CTC_ZC1_CB(WRITELINE(tmpz84c011_device, zc1_cb_trampoline_w))
MCFG_Z80CTC_ZC2_CB(WRITELINE(tmpz84c011_device, zc2_cb_trampoline_w))
MACHINE_CONFIG_END
machine_config_constructor tmpz84c011_device::device_mconfig_additions() const
{
return MACHINE_CONFIG_NAME( tmpz84c011 );
}
void tmpz84c011_device::device_start()
{
z80_device::device_start();
m_outports0.resolve_safe();
m_outports1.resolve_safe();
m_outports2.resolve_safe();
m_outports3.resolve_safe();
m_outports4.resolve_safe();
m_inports0.resolve_safe(0);
m_inports1.resolve_safe(0);
m_inports2.resolve_safe(0);
m_inports3.resolve_safe(0);
m_inports4.resolve_safe(0);
m_intr_cb.resolve_safe();
m_zc0_cb.resolve_safe();
m_zc1_cb.resolve_safe();
m_zc2_cb.resolve_safe();
save_item(NAME(m_pio_dir[0]));
save_item(NAME(m_pio_latch[0]));
save_item(NAME(m_pio_dir[1]));
save_item(NAME(m_pio_latch[1]));
save_item(NAME(m_pio_dir[2]));
save_item(NAME(m_pio_latch[2]));
save_item(NAME(m_pio_dir[3]));
save_item(NAME(m_pio_latch[3]));
save_item(NAME(m_pio_dir[4]));
save_item(NAME(m_pio_latch[4]));
}
void tmpz84c011_device::device_reset()
{
z80_device::device_reset();
// initialize TMPZ84C011 PIO
for (int i = 0; i < 5; i++)
{
m_pio_dir[i] = m_pio_latch[i] = 0;
tmpz84c011_pio_w(*m_io, i, 0);
}
}

154
src/emu/cpu/z80/tmpz84c011.h Normal file
View File

@ -0,0 +1,154 @@
#include "emu.h"
#include "z80.h"
#define MCFG_TMPZ84C011_PORTA_READ_CB(_devcb) \
devcb = &tmpz84c011_device::set_inports0_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTB_READ_CB(_devcb) \
devcb = &tmpz84c011_device::set_inports1_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTC_READ_CB(_devcb) \
devcb = &tmpz84c011_device::set_inports2_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTD_READ_CB(_devcb) \
devcb = &tmpz84c011_device::set_inports3_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTE_READ_CB(_devcb) \
devcb = &tmpz84c011_device::set_inports4_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTA_WRITE_CB(_devcb) \
devcb = &tmpz84c011_device::set_outports0_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTB_WRITE_CB(_devcb) \
devcb = &tmpz84c011_device::set_outports1_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTC_WRITE_CB(_devcb) \
devcb = &tmpz84c011_device::set_outports2_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTD_WRITE_CB(_devcb) \
devcb = &tmpz84c011_device::set_outports3_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTE_WRITE_CB(_devcb) \
devcb = &tmpz84c011_device::set_outports4_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_Z80CTC_INTR_CB(_devcb) \
devcb = &tmpz84c011_device::set_intr_callback(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_Z80CTC_ZC0_CB(_devcb) \
devcb = &tmpz84c011_device::set_zc0_callback(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_Z80CTC_ZC1_CB(_devcb) \
devcb = &tmpz84c011_device::set_zc1_callback(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_Z80CTC_ZC2_CB(_devcb) \
devcb = &tmpz84c011_device::set_zc2_callback(*device, DEVCB_##_devcb);
class tmpz84c011_device : public z80_device
{
public:
tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32);
template<class _Object> static devcb_base & set_outports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports0.set_callback(object); }
template<class _Object> static devcb_base & set_outports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports1.set_callback(object); }
template<class _Object> static devcb_base & set_outports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports2.set_callback(object); }
template<class _Object> static devcb_base & set_outports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports3.set_callback(object); }
template<class _Object> static devcb_base & set_outports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports4.set_callback(object); }
template<class _Object> static devcb_base & set_inports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports0.set_callback(object); }
template<class _Object> static devcb_base & set_inports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports1.set_callback(object); }
template<class _Object> static devcb_base & set_inports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports2.set_callback(object); }
template<class _Object> static devcb_base & set_inports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports3.set_callback(object); }
template<class _Object> static devcb_base & set_inports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports4.set_callback(object); }
template<class _Object> static devcb_base &set_intr_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_intr_cb.set_callback(object); }
template<class _Object> static devcb_base &set_zc0_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_zc0_cb.set_callback(object); }
template<class _Object> static devcb_base &set_zc1_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_zc1_cb.set_callback(object); }
template<class _Object> static devcb_base &set_zc2_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_zc2_cb.set_callback(object); }
DECLARE_READ8_MEMBER(tmpz84c011_pio_r);
DECLARE_WRITE8_MEMBER(tmpz84c011_pio_w);
DECLARE_READ8_MEMBER(tmpz84c011_0_pa_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_pb_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_pc_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_pd_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_pe_r);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pa_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pb_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pc_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pd_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pe_w);
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pa_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pb_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pc_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pd_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pe_r);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pa_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pb_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pc_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pd_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pe_w);
DECLARE_READ8_MEMBER(porta_default_r);
DECLARE_READ8_MEMBER(portb_default_r);
DECLARE_READ8_MEMBER(portc_default_r);
DECLARE_READ8_MEMBER(portd_default_r);
DECLARE_READ8_MEMBER(porte_default_r);
DECLARE_WRITE8_MEMBER(porta_default_w);
DECLARE_WRITE8_MEMBER(portb_default_w);
DECLARE_WRITE8_MEMBER(portc_default_w);
DECLARE_WRITE8_MEMBER(portd_default_w);
DECLARE_WRITE8_MEMBER(porte_default_w);
DECLARE_WRITE_LINE_MEMBER(intr_cb_trampoline_w);
DECLARE_WRITE_LINE_MEMBER(zc0_cb_trampoline_w);
DECLARE_WRITE_LINE_MEMBER(zc1_cb_trampoline_w);
DECLARE_WRITE_LINE_MEMBER(zc2_cb_trampoline_w);
protected:
// device-level overrides
virtual machine_config_constructor device_mconfig_additions() const;
virtual void device_start();
virtual void device_reset();
const address_space_config m_io_space_config;
const address_space_config *memory_space_config(address_spacenum spacenum) const
{
switch (spacenum)
{
case AS_IO: return &m_io_space_config;
default: return z80_device::memory_space_config(spacenum);
}
}
UINT8 m_pio_dir[5];
UINT8 m_pio_latch[5];
private:
devcb_write8 m_outports0;
devcb_write8 m_outports1;
devcb_write8 m_outports2;
devcb_write8 m_outports3;
devcb_write8 m_outports4;
devcb_read8 m_inports0;
devcb_read8 m_inports1;
devcb_read8 m_inports2;
devcb_read8 m_inports3;
devcb_read8 m_inports4;
devcb_write_line m_intr_cb; // interrupt callback
devcb_write_line m_zc0_cb; // channel 0 zero crossing callbacks
devcb_write_line m_zc1_cb; // channel 1 zero crossing callbacks
devcb_write_line m_zc2_cb; // channel 2 zero crossing callbacks
};
extern const device_type TMPZ84C011;

245
src/emu/cpu/z80/z80.c
View File

@ -3737,251 +3737,6 @@ nsc800_device::nsc800_device(const machine_config &mconfig, const char *tag, dev
const device_type NSC800 = &device_creator<nsc800_device>;
// how do we actually install default handlers for logging?
/*
READ8_MEMBER(tmpz84c011_device::porta_default_r) { logerror("%s read port A but no handler assigned\n", machine().describe_context()); return 0xff; }
READ8_MEMBER(tmpz84c011_device::portb_default_r) { logerror("%s read port B but no handler assigned\n", machine().describe_context()); return 0xff; }
READ8_MEMBER(tmpz84c011_device::portc_default_r) { logerror("%s read port C but no handler assigned\n", machine().describe_context()); return 0xff; }
READ8_MEMBER(tmpz84c011_device::portd_default_r) { logerror("%s read port D but no handler assigned\n", machine().describe_context()); return 0xff; }
READ8_MEMBER(tmpz84c011_device::porte_default_r) { logerror("%s read port E but no handler assigned\n", machine().describe_context()); return 0xff; }
WRITE8_MEMBER(tmpz84c011_device::porta_default_w) { logerror("%s write %02x to port A but no handler assigned\n", machine().describe_context(), data); }
WRITE8_MEMBER(tmpz84c011_device::portb_default_w) { logerror("%s write %02x to port B but no handler assigned\n", machine().describe_context(), data); }
WRITE8_MEMBER(tmpz84c011_device::portc_default_w) { logerror("%s write %02x to port C but no handler assigned\n", machine().describe_context(), data); }
WRITE8_MEMBER(tmpz84c011_device::portd_default_w) { logerror("%s write %02x to port D but no handler assigned\n", machine().describe_context(), data); }
WRITE8_MEMBER(tmpz84c011_device::porte_default_w) { logerror("%s write %02x to port E but no handler assigned\n", machine().describe_context(), data); }
*/
READ8_MEMBER(tmpz84c011_device::tmpz84c011_pio_r)
{
int portdata = 0xff;
switch (offset)
{
case 0: /* PA_0 */
portdata = m_inports0();
break;
case 1: /* PB_0 */
portdata = m_inports1();
break;
case 2: /* PC_0 */
portdata = m_inports2();
break;
case 3: /* PD_0 */
portdata = m_inports3();
break;
case 4: /* PE_0 */
portdata = m_inports4();
break;
}
return portdata;
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pio_w)
{
switch (offset)
{
case 0: /* PA_0 */
m_outports0(data);
break;
case 1: /* PB_0 */
m_outports1(data);
break;
case 2: /* PC_0 */
m_outports2(data);
break;
case 3: /* PD_0 */
m_outports3(data);
break;
case 4: /* PE_0 */
m_outports4(data);
break;
}
}
/* CPU interface */
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_r)
{
return (tmpz84c011_pio_r(space,0) & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]);
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_r)
{
return (tmpz84c011_pio_r(space,1) & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]);
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_r)
{
return (tmpz84c011_pio_r(space,2) & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]);
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_r)
{
return (tmpz84c011_pio_r(space,3) & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]);
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_r)
{
return (tmpz84c011_pio_r(space,4) & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]);
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_w)
{
m_pio_latch[0] = data;
tmpz84c011_pio_w(space, 0, data);
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_w)
{
m_pio_latch[1] = data;
tmpz84c011_pio_w(space, 1, data);
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_w)
{
m_pio_latch[2] = data;
tmpz84c011_pio_w(space, 2, data);
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_w)
{
m_pio_latch[3] = data;
tmpz84c011_pio_w(space, 3, data);
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_w)
{
m_pio_latch[4] = data;
tmpz84c011_pio_w(space, 4, data);
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_r)
{
return m_pio_dir[0];
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_r)
{
return m_pio_dir[1];
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_r)
{
return m_pio_dir[2];
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_r)
{
return m_pio_dir[3];
}
READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_r)
{
return m_pio_dir[4];
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_w)
{
m_pio_dir[0] = data;
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_w)
{
m_pio_dir[1] = data;
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_w)
{
m_pio_dir[2] = data;
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_w)
{
m_pio_dir[3] = data;
}
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_w)
{
m_pio_dir[4] = data;
}
static ADDRESS_MAP_START( tmpz84c011_internal_io_map, AS_IO, 8, tmpz84c011_device )
AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w) AM_MIRROR(0xff00)
AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w) AM_MIRROR(0xff00)
AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w) AM_MIRROR(0xff00)
AM_RANGE(0x30, 0x30) AM_READWRITE(tmpz84c011_0_pd_r, tmpz84c011_0_pd_w) AM_MIRROR(0xff00)
AM_RANGE(0x40, 0x40) AM_READWRITE(tmpz84c011_0_pe_r, tmpz84c011_0_pe_w) AM_MIRROR(0xff00)
AM_RANGE(0x54, 0x54) AM_READWRITE(tmpz84c011_0_dir_pa_r, tmpz84c011_0_dir_pa_w) AM_MIRROR(0xff00)
AM_RANGE(0x55, 0x55) AM_READWRITE(tmpz84c011_0_dir_pb_r, tmpz84c011_0_dir_pb_w) AM_MIRROR(0xff00)
AM_RANGE(0x56, 0x56) AM_READWRITE(tmpz84c011_0_dir_pc_r, tmpz84c011_0_dir_pc_w) AM_MIRROR(0xff00)
AM_RANGE(0x34, 0x34) AM_READWRITE(tmpz84c011_0_dir_pd_r, tmpz84c011_0_dir_pd_w) AM_MIRROR(0xff00)
AM_RANGE(0x44, 0x44) AM_READWRITE(tmpz84c011_0_dir_pe_r, tmpz84c011_0_dir_pe_w) AM_MIRROR(0xff00)
ADDRESS_MAP_END
tmpz84c011_device::tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: z80_device(mconfig, TMPZ84C011, "TMPZ84C011", tag, owner, clock, "tmpz84c011", __FILE__),
m_io_space_config( "io", ENDIANNESS_LITTLE, 8, 16, 0, ADDRESS_MAP_NAME( tmpz84c011_internal_io_map ) ),
m_outports0(*this),
m_outports1(*this),
m_outports2(*this),
m_outports3(*this),
m_outports4(*this),
m_inports0(*this),
m_inports1(*this),
m_inports2(*this),
m_inports3(*this),
m_inports4(*this)
{
}
const device_type TMPZ84C011 = &device_creator<tmpz84c011_device>;
void tmpz84c011_device::device_start()
{
z80_device::device_start();
m_outports0.resolve_safe();
m_outports1.resolve_safe();
m_outports2.resolve_safe();
m_outports3.resolve_safe();
m_outports4.resolve_safe();
m_inports0.resolve_safe(0);
m_inports1.resolve_safe(0);
m_inports2.resolve_safe(0);
m_inports3.resolve_safe(0);
m_inports4.resolve_safe(0);
save_item(NAME(m_pio_dir[0]));
save_item(NAME(m_pio_latch[0]));
save_item(NAME(m_pio_dir[1]));
save_item(NAME(m_pio_latch[1]));
save_item(NAME(m_pio_dir[2]));
save_item(NAME(m_pio_latch[2]));
save_item(NAME(m_pio_dir[3]));
save_item(NAME(m_pio_latch[3]));
save_item(NAME(m_pio_dir[4]));
save_item(NAME(m_pio_latch[4]));
}
void tmpz84c011_device::device_reset()
{
z80_device::device_reset();
// initialize TMPZ84C011 PIO
for (int i = 0; i < 5; i++)
{
m_pio_dir[i] = m_pio_latch[i] = 0;
tmpz84c011_pio_w(*m_io, i, 0);
}
}
WRITE_LINE_MEMBER( z80_device::irq_line )
{

127
src/emu/cpu/z80/z80.h
View File

@ -340,131 +340,4 @@ extern const device_type TLCS_Z80;
#define MCFG_TMPZ84C011_PORTA_READ_CB(_devcb) \
devcb = &tmpz84c011_device::set_inports0_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTB_READ_CB(_devcb) \
devcb = &tmpz84c011_device::set_inports1_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTC_READ_CB(_devcb) \
devcb = &tmpz84c011_device::set_inports2_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTD_READ_CB(_devcb) \
devcb = &tmpz84c011_device::set_inports3_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTE_READ_CB(_devcb) \
devcb = &tmpz84c011_device::set_inports4_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTA_WRITE_CB(_devcb) \
devcb = &tmpz84c011_device::set_outports0_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTB_WRITE_CB(_devcb) \
devcb = &tmpz84c011_device::set_outports1_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTC_WRITE_CB(_devcb) \
devcb = &tmpz84c011_device::set_outports2_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTD_WRITE_CB(_devcb) \
devcb = &tmpz84c011_device::set_outports3_cb(*device, DEVCB_##_devcb);
#define MCFG_TMPZ84C011_PORTE_WRITE_CB(_devcb) \
devcb = &tmpz84c011_device::set_outports4_cb(*device, DEVCB_##_devcb);
class tmpz84c011_device : public z80_device
{
public:
tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32);
template<class _Object> static devcb_base & set_outports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports0.set_callback(object); }
template<class _Object> static devcb_base & set_outports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports1.set_callback(object); }
template<class _Object> static devcb_base & set_outports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports2.set_callback(object); }
template<class _Object> static devcb_base & set_outports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports3.set_callback(object); }
template<class _Object> static devcb_base & set_outports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports4.set_callback(object); }
template<class _Object> static devcb_base & set_inports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports0.set_callback(object); }
template<class _Object> static devcb_base & set_inports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports1.set_callback(object); }
template<class _Object> static devcb_base & set_inports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports2.set_callback(object); }
template<class _Object> static devcb_base & set_inports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports3.set_callback(object); }
template<class _Object> static devcb_base & set_inports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports4.set_callback(object); }
DECLARE_READ8_MEMBER(tmpz84c011_pio_r);
DECLARE_WRITE8_MEMBER(tmpz84c011_pio_w);
DECLARE_READ8_MEMBER(tmpz84c011_0_pa_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_pb_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_pc_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_pd_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_pe_r);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pa_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pb_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pc_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pd_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pe_w);
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pa_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pb_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pc_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pd_r);
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pe_r);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pa_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pb_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pc_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pd_w);
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pe_w);
DECLARE_READ8_MEMBER(porta_default_r);
DECLARE_READ8_MEMBER(portb_default_r);
DECLARE_READ8_MEMBER(portc_default_r);
DECLARE_READ8_MEMBER(portd_default_r);
DECLARE_READ8_MEMBER(porte_default_r);
DECLARE_WRITE8_MEMBER(porta_default_w);
DECLARE_WRITE8_MEMBER(portb_default_w);
DECLARE_WRITE8_MEMBER(portc_default_w);
DECLARE_WRITE8_MEMBER(portd_default_w);
DECLARE_WRITE8_MEMBER(porte_default_w);
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
const address_space_config m_io_space_config;
const address_space_config *memory_space_config(address_spacenum spacenum) const
{
switch (spacenum)
{
case AS_IO: return &m_io_space_config;
default: return z80_device::memory_space_config(spacenum);
}
}
UINT8 m_pio_dir[5];
UINT8 m_pio_latch[5];
private:
devcb_write8 m_outports0;
devcb_write8 m_outports1;
devcb_write8 m_outports2;
devcb_write8 m_outports3;
devcb_write8 m_outports4;
devcb_read8 m_inports0;
devcb_read8 m_inports1;
devcb_read8 m_inports2;
devcb_read8 m_inports3;
devcb_read8 m_inports4;
};
extern const device_type TMPZ84C011;
#endif /* __Z80_H__ */

12
src/mame/drivers/csplayh5.c
View File

@ -27,8 +27,7 @@
#include "cpu/m68000/m68000.h"
#include "machine/tmp68301.h"
#include "video/v9938.h"
#include "cpu/z80/z80.h"
#include "machine/z80ctc.h"
#include "cpu/z80/tmpz84c011.h"
#include "sound/dac.h"
#include "sound/3812intf.h"
#include "cpu/z80/z80daisy.h"
@ -235,7 +234,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( csplayh5_sound_io_map, AS_IO, 8, csplayh5_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
AM_RANGE(0x80, 0x81) AM_DEVWRITE("ymsnd", ym3812_device, write)
ADDRESS_MAP_END
@ -453,7 +451,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(csplayh5_state::csplayh5_irq)
static const z80_daisy_config daisy_chain_sound[] =
{
{ "ctc" },
{ "audiocpu:ctc" },
{ NULL }
};
@ -483,10 +481,8 @@ static MACHINE_CONFIG_START( csplayh5, csplayh5_state )
MCFG_TMPZ84C011_PORTC_WRITE_CB(WRITE8(csplayh5_state, soundcpu_dac1_w))
MCFG_TMPZ84C011_PORTD_READ_CB(READ8(csplayh5_state, soundcpu_portd_r))
MCFG_TMPZ84C011_PORTE_WRITE_CB(WRITE8(csplayh5_state, soundcpu_porte_w))
MCFG_DEVICE_ADD("ctc", Z80CTC, 8000000)
MCFG_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
MCFG_Z80CTC_ZC0_CB(DEVWRITELINE("ctc", z80ctc_device, trg3))
MCFG_TMPZ84C011_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
MCFG_TMPZ84C011_Z80CTC_ZC0_CB(DEVWRITELINE("audiocpu:ctc", z80ctc_device, trg3))
MCFG_NVRAM_ADD_0FILL("nvram")

9
src/mame/drivers/kenseim.c
View File

@ -139,8 +139,7 @@ GND | 20
// note: I've kept this code out of cps1.c as there is likely to be a substantial amount of game specific code here ones all the extra hardware is emulated
#include "emu.h"
#include "cpu/z80/z80.h"
#include "machine/z80ctc.h"
#include "cpu/z80/tmpz84c011.h"
#include "includes/cps1.h"
#include "kenseim.lh"
#include "machine/mb89363b.h"
@ -460,14 +459,13 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( kenseim_io_map, AS_IO, 8, kenseim_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("gamecpu_ctc", z80ctc_device, read, write)
AM_RANGE(0x20, 0x27) AM_DEVREADWRITE("mb89363b", mb89363b_device, read, write)
ADDRESS_MAP_END
static const z80_daisy_config daisy_chain_gamecpu[] =
{
{ "gamecpu_ctc" },
{ "gamecpu:ctc" },
{ NULL }
};
@ -486,9 +484,8 @@ static MACHINE_CONFIG_DERIVED_CLASS( kenseim, cps1_12MHz, kenseim_state )
MCFG_TMPZ84C011_PORTC_READ_CB(IOPORT("CAB-IN"))
MCFG_TMPZ84C011_PORTD_READ_CB(READ8(kenseim_state, cpu_portd_r))
MCFG_CPU_CONFIG(daisy_chain_gamecpu)
MCFG_TMPZ84C011_Z80CTC_INTR_CB(INPUTLINE("gamecpu", INPUT_LINE_IRQ0))
MCFG_DEVICE_ADD("gamecpu_ctc", Z80CTC, XTAL_16MHz/2) // part of the tmpz84
MCFG_Z80CTC_INTR_CB(INPUTLINE("gamecpu", INPUT_LINE_IRQ0))
MCFG_MB89363B_ADD("mb89363b")
// a,b,c always $80: all ports set as output

48
src/mame/drivers/nbmj9195.c
View File

@ -20,8 +20,7 @@ Notes:
******************************************************************************/
#include "emu.h"
#include "cpu/z80/z80.h"
#include "machine/z80ctc.h"
#include "cpu/z80/tmpz84c011.h"
#include "machine/nvram.h"
#include "includes/nb1413m3.h" // needed for mahjong input controller
#include "sound/3812intf.h"
@ -323,7 +322,7 @@ WRITE8_MEMBER(nbmj9195_state::soundcpu_porte_w)
/* CTC of main cpu, ch0 trigger is vblank */
INTERRUPT_GEN_MEMBER(nbmj9195_state::ctc0_trg1)
{
z80ctc_device *ctc = machine().device<z80ctc_device>("main_ctc");
z80ctc_device *ctc = machine().device<z80ctc_device>("maincpu:ctc");
ctc->trg1(1);
ctc->trg1(0);
}
@ -345,9 +344,6 @@ DRIVER_INIT_MEMBER(nbmj9195_state,nbmj9195)
logerror("DRIVER_INIT( nbmj9195 )\n");
}
static ADDRESS_MAP_START( tmpz84c011_regs, AS_IO, 8, nbmj9195_state )
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("main_ctc", z80ctc_device, read, write)
ADDRESS_MAP_END
static ADDRESS_MAP_START( sailorws_map, AS_PROGRAM, 8, nbmj9195_state )
AM_RANGE(0x0000, 0xefff) AM_ROM
@ -391,7 +387,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( mjuraden_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_0_w)
@ -405,7 +400,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( koinomp_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_0_w)
@ -424,7 +418,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( patimono_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_1_r)
AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_1_w)
@ -442,7 +435,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( mmehyou_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_0_w)
@ -456,7 +448,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( gal10ren_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
@ -474,7 +465,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( renaiclb_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x20, 0x20) AM_WRITE(nbmj9195_sound_w)
AM_RANGE(0x24, 0x24) AM_WRITENOP
@ -492,7 +482,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( mjlaman_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x20, 0x20) AM_WRITE(nbmj9195_sound_w)
AM_RANGE(0x22, 0x22) AM_WRITENOP
@ -510,7 +499,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( mkeibaou_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_0_w)
@ -528,7 +516,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( pachiten_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
@ -546,7 +533,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sailorws_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
@ -564,7 +550,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sailorwr_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
@ -582,7 +567,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( psailor1_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
@ -600,7 +584,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( psailor2_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
@ -618,7 +601,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( otatidai_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
@ -636,7 +618,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( yosimoto_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
@ -654,7 +635,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( yosimotm_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
@ -672,7 +652,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( jituroku_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
@ -690,7 +669,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( ngpgal_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0xa0, 0xa0) AM_WRITE(nbmj9195_sound_w)
AM_RANGE(0xa4, 0xa4) AM_WRITENOP
@ -704,7 +682,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( mjgottsu_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_0_w)
@ -718,7 +695,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( cmehyou_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0xa0, 0xa0) AM_WRITE(nbmj9195_sound_w)
AM_RANGE(0xa8, 0xa8) AM_WRITENOP
@ -732,7 +708,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( mjkoiura_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_0_r)
AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_0_w)
@ -746,7 +721,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( mkoiuraa_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0xa0, 0xa0) AM_WRITE(nbmj9195_sound_w)
AM_RANGE(0xa4, 0xa4) AM_WRITENOP
@ -760,7 +734,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( mscoutm_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x80, 0x80) AM_READ(mscoutm_dipsw_1_r)
AM_RANGE(0x82, 0x82) AM_READ(mscoutm_dipsw_0_r)
@ -780,7 +753,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( imekura_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x80, 0x80) AM_READ(mscoutm_dipsw_1_r)
AM_RANGE(0x82, 0x82) AM_READ(mscoutm_dipsw_0_r)
@ -800,7 +772,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( mjegolf_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
AM_RANGE(0x80, 0x86) AM_WRITENOP // nb22090 param ?
@ -828,7 +799,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sailorws_sound_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("audio_ctc", z80ctc_device, read, write)
AM_RANGE(0x80, 0x81) AM_DEVWRITE("ymsnd", ym3812_device, write)
ADDRESS_MAP_END
@ -849,7 +819,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( shabdama_io_map, AS_IO, 8, nbmj9195_state )
// ADDRESS_MAP_UNMAP_HIGH
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_IMPORT_FROM( tmpz84c011_regs )
// AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
// AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
@ -2812,13 +2781,13 @@ INPUT_PORTS_END
static const z80_daisy_config daisy_chain_main[] =
{
{ "main_ctc" },
{ "maincpu:ctc" },
{ NULL }
};
static const z80_daisy_config daisy_chain_sound[] =
{
{ "audio_ctc" },
{ "audiocpu:ctc" },
{ NULL }
};
@ -2865,18 +2834,15 @@ static MACHINE_CONFIG_START( NBMJDRV1_base, nbmj9195_state )
MCFG_CPU_PROGRAM_MAP(sailorws_map)
MCFG_CPU_IO_MAP(sailorws_io_map)
MCFG_CPU_VBLANK_INT_DRIVER("screen", nbmj9195_state, ctc0_trg1) /* vblank is connect to ctc triggfer */
MCFG_TMPZ84C011_Z80CTC_INTR_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
MCFG_CPU_ADD("audiocpu", TMPZ84C011, 8000000) /* TMPZ84C011, 8.00 MHz */
MCFG_CPU_CONFIG(daisy_chain_sound)
MCFG_CPU_PROGRAM_MAP(sailorws_sound_map)
MCFG_CPU_IO_MAP(sailorws_sound_io_map)
MCFG_TMPZ84C011_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
MCFG_TMPZ84C011_Z80CTC_ZC0_CB(DEVWRITELINE("audiocpu:ctc", z80ctc_device, trg3))
MCFG_DEVICE_ADD("main_ctc", Z80CTC, 12000000/2 /* same as "maincpu" */)
MCFG_Z80CTC_INTR_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
MCFG_DEVICE_ADD("audio_ctc", Z80CTC, 8000000 /* same as "audiocpu" */)
MCFG_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
MCFG_Z80CTC_ZC0_CB(DEVWRITELINE("audio_ctc", z80ctc_device, trg3))
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)

11
src/mame/drivers/niyanpai.c
View File

@ -34,10 +34,9 @@ Memo:
******************************************************************************/
#include "emu.h"
#include "cpu/z80/z80.h"
#include "cpu/z80/tmpz84c011.h"
#include "cpu/m68000/m68000.h"
#include "machine/tmp68301.h"
#include "machine/z80ctc.h"
#include "includes/nb1413m3.h"
#include "sound/dac.h"
#include "sound/3812intf.h"
@ -336,7 +335,6 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( niyanpai_sound_io_map, AS_IO, 8, niyanpai_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
AM_RANGE(0x80, 0x81) AM_DEVWRITE("ymsnd", ym3812_device, write)
ADDRESS_MAP_END
@ -765,7 +763,7 @@ INTERRUPT_GEN_MEMBER(niyanpai_state::niyanpai_interrupt)
static const z80_daisy_config daisy_chain_sound[] =
{
{ "ctc" },
{ "audiocpu:ctc" },
{ NULL }
};
@ -791,10 +789,9 @@ static MACHINE_CONFIG_START( niyanpai, niyanpai_state )
MCFG_TMPZ84C011_PORTB_WRITE_CB(WRITE8(niyanpai_state, cpu_portb_w))
MCFG_TMPZ84C011_PORTC_WRITE_CB(WRITE8(niyanpai_state, cpu_portc_w))
MCFG_TMPZ84C011_PORTE_WRITE_CB(WRITE8(niyanpai_state, cpu_porte_w))
MCFG_TMPZ84C011_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
MCFG_TMPZ84C011_Z80CTC_ZC0_CB(DEVWRITELINE("audiocpu:ctc", z80ctc_device, trg3))
MCFG_DEVICE_ADD("ctc", Z80CTC, 8000000 /* same as "audiocpu" */)
MCFG_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
MCFG_Z80CTC_ZC0_CB(DEVWRITELINE("ctc", z80ctc_device, trg3))
MCFG_NVRAM_ADD_0FILL("nvram")