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xavix - some changes to keep code running better, I think it's trying… (#3180)

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* xavix - some changes to keep code running better, I think it's trying to do a palette writes at 6800/6900 before crashing now (nw)

* new machines marked as NOT WORKING
Play TV Monster Truck [Sean Riddle, Peter Wilhelmsen]

* experiments (nw)

* ram address 0xff (internal ram / zero page ram) is used to bank data reads at 0x8000 (the equiavlent of how the custom ocpods bank code reads there instead)
This commit is contained in:
David Haywood 2018-02-08 21:03:57 +00:00 committed by R. Belmont
parent 15556478e7
commit f2caf3fbb0
6 changed files with 419 additions and 141 deletions
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2
src/devices/cpu/m6502/dxavix.lst
View File

@ -5,7 +5,7 @@ brk_xav_imp ora_idx kil_non slo_idx nop_zpg ora_zpg asl_zpg
bpl_rel ora_idy kil_non slo_idy nop_zpx ora_zpx asl_zpx slo_zpx clc_imp ora_aby nop_imp slo_aby nop_abx ora_abx asl_abx slo_abx bpl_rel ora_idy kil_non slo_idy nop_zpx ora_zpx asl_zpx slo_zpx clc_imp ora_aby nop_imp slo_aby nop_abx ora_abx asl_abx slo_abx
jsr_adr and_idx callf_xa3 rla_idx bit_zpg and_zpg rol_zpg rla_zpg plp_imp and_imm rol_acc anc_imm bit_aba and_aba rol_aba rla_aba jsr_adr and_idx callf_xa3 rla_idx bit_zpg and_zpg rol_zpg rla_zpg plp_imp and_imm rol_acc anc_imm bit_aba and_aba rol_aba rla_aba
bmi_rel and_idy kil_non rla_idy nop_zpx and_zpx rol_zpx rla_zpx sec_imp and_aby nop_imp rla_aby nop_abx and_abx rol_abx rla_abx bmi_rel and_idy kil_non rla_idy nop_zpx and_zpx rol_zpx rla_zpx sec_imp and_aby nop_imp rla_aby nop_abx and_abx rol_abx rla_abx
rti_imp eor_idx kil_non sre_idx nop_zpg eor_zpg lsr_zpg sre_zpg pha_imp eor_imm lsr_acc asr_imm jmp_adr eor_aba lsr_aba sre_aba rti_xav_imp eor_idx kil_non sre_idx nop_zpg eor_zpg lsr_zpg sre_zpg pha_imp eor_imm lsr_acc asr_imm jmp_adr eor_aba lsr_aba sre_aba
bvc_rel eor_idy kil_non sre_idy nop_zpx eor_zpx lsr_zpx sre_zpx cli_imp eor_aby nop_imp sre_aby nop_abx eor_abx lsr_abx sre_abx bvc_rel eor_idy kil_non sre_idy nop_zpx eor_zpx lsr_zpx sre_zpx cli_imp eor_aby nop_imp sre_aby nop_abx eor_abx lsr_abx sre_abx
rts_imp adc_idx kil_non rra_idx nop_zpg adc_zpg ror_zpg rra_zpg pla_imp adc_imm ror_acc arr_imm jmp_ind adc_aba ror_aba rra_aba rts_imp adc_idx kil_non rra_idx nop_zpg adc_zpg ror_zpg rra_zpg pla_imp adc_imm ror_acc arr_imm jmp_ind adc_aba ror_aba rra_aba
bvs_rel adc_idy kil_non rra_idy nop_zpx adc_zpx ror_zpx rra_zpx sei_imp adc_aby nop_imp rra_aby nop_abx adc_abx ror_abx rra_abx bvs_rel adc_idy kil_non rra_idy nop_zpx adc_zpx ror_zpx rra_zpx sei_imp adc_aby nop_imp rra_aby nop_abx adc_abx ror_abx rra_abx

44
src/devices/cpu/m6502/oxavix.lst
View File

@ -3,30 +3,38 @@
# xavix opcodes # xavix opcodes
callf_xa3 callf_xa3
read(SP);
if (PC & 0x8000) // if top bit of PC isn't set we're in the non-banked RAM area, don't store farbank?
{
write(SP, m_farbank);
dec_SP();
}
TMP2 = read_pc(); TMP2 = read_pc();
TMP = read_pc(); TMP = read_pc();
TMP |= (read_pc()<<8); //read(SP);
read(SP);
write(SP, PC>>8); write(SP, PC>>8);
dec_SP(); dec_SP();
write(SP, PC); write(SP, PC);
dec_SP(); dec_SP();
write(SP, m_farbank); TMP = set_h(TMP, read_pc());
dec_SP();
m_farbank=TMP2;
PC = TMP; PC = TMP;
m_farbank=TMP2;
prefetch(); prefetch();
retf_imp retf_imp
read_pc_noinc(); read_pc_noinc();
read(SP); read(SP);
inc_SP(); inc_SP();
TMP2 = read(SP);
inc_SP();
PC = read(SP); PC = read(SP);
inc_SP(); inc_SP();
PC = set_h(PC, read(SP)); PC = set_h(PC, read(SP));
m_farbank = TMP2; if (PC & 0x8000) // if top bit of PC is set then we're jumping back to a banked ROM area, so get farbank? (see 0fdae in rad_ping)
{
inc_SP();
TMP2 = read(SP);
m_farbank = TMP2;
}
read_pc();
prefetch(); prefetch();
brk_xav_imp brk_xav_imp
@ -36,6 +44,8 @@ brk_xav_imp
} else { } else {
read_pc(); read_pc();
} }
write(SP, m_farbank); // maybe
dec_SP();
write(SP, PC >> 8); write(SP, PC >> 8);
dec_SP(); dec_SP();
write(SP, PC); write(SP, PC);
@ -47,11 +57,13 @@ brk_xav_imp
{ {
PC = read_arg(0xfffa); PC = read_arg(0xfffa);
PC = set_h(PC, read_arg(0xfffb)); PC = set_h(PC, read_arg(0xfffb));
m_farbank = 0;
} }
else else
{ {
PC = m_vector_callback(0,1); PC = m_vector_callback(0,1);
PC = set_h(PC, m_vector_callback(0,0)); PC = set_h(PC, m_vector_callback(0,0));
m_farbank = 0;
} }
nmi_state = false; nmi_state = false;
@ -61,11 +73,13 @@ brk_xav_imp
{ {
PC = read_arg(0xfffe); PC = read_arg(0xfffe);
PC = set_h(PC, read_arg(0xffff)); PC = set_h(PC, read_arg(0xffff));
m_farbank = 0;
} }
else else
{ {
PC = m_vector_callback(1,1); PC = m_vector_callback(1,1);
PC = set_h(PC, m_vector_callback(1,0)); PC = set_h(PC, m_vector_callback(1,0));
m_farbank = 0;
} }
if(irq_taken) if(irq_taken)
@ -75,3 +89,17 @@ brk_xav_imp
P |= F_I; // Do *not* move after the prefetch P |= F_I; // Do *not* move after the prefetch
prefetch(); prefetch();
inst_state = -1; inst_state = -1;
rti_xav_imp
read_pc_noinc();
read(SP);
inc_SP();
P = read(SP) | (F_B|F_E);
inc_SP();
PC = read(SP);
inc_SP();
PC = set_h(PC, read(SP));
inc_SP();
TMP2 = read(SP);
m_farbank = TMP2;
prefetch();

10
src/devices/cpu/m6502/xavix.cpp
View File

@ -67,7 +67,10 @@ uint8_t xavix_device::mi_xavix_normal::read(uint16_t adr)
if (adr < 0x8000) if (adr < 0x8000)
return program->read_byte(adr); return program->read_byte(adr);
else else
return program->read_byte(base->adr_with_bank(adr)); {
uint8_t data_bank = program->read_byte(0xff);
return program->read_byte((data_bank << 16) | adr);
}
} }
uint8_t xavix_device::mi_xavix_normal::read_sync(uint16_t adr) uint8_t xavix_device::mi_xavix_normal::read_sync(uint16_t adr)
@ -91,7 +94,10 @@ void xavix_device::mi_xavix_normal::write(uint16_t adr, uint8_t val)
if (adr < 0x8000) if (adr < 0x8000)
program->write_byte(adr, val); program->write_byte(adr, val);
else else
program->write_byte(base->adr_with_bank(adr), val); {
uint8_t data_bank = program->read_byte(0xff);
program->write_byte((data_bank << 16) | adr, val);
}
} }
xavix_device::mi_xavix_nd::mi_xavix_nd(xavix_device *_base) : mi_xavix_normal(_base) xavix_device::mi_xavix_nd::mi_xavix_nd(xavix_device *_base) : mi_xavix_normal(_base)

1
src/devices/cpu/m6502/xavix.h
View File

@ -29,6 +29,7 @@ public:
O(callf_xa3); O(callf_xa3);
O(retf_imp); O(retf_imp);
O(brk_xav_imp); O(brk_xav_imp);
O(rti_xav_imp);
typedef device_delegate<uint8_t (int which, int half)> xavix_interrupt_vector_delegate; typedef device_delegate<uint8_t (int which, int half)> xavix_interrupt_vector_delegate;

500
src/mame/drivers/xavix.cpp
View File

@ -58,7 +58,10 @@ class xavix_state : public driver_device
public: public:
xavix_state(const machine_config &mconfig, device_type type, const char *tag) xavix_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag), : driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu") m_maincpu(*this, "maincpu"),
m_palram1(*this, "palram1"),
m_palram2(*this, "palram2"),
m_palette(*this, "palette")
{ } { }
// devices // devices
@ -71,22 +74,32 @@ public:
DECLARE_WRITE8_MEMBER(xavix_7900_w); DECLARE_WRITE8_MEMBER(xavix_7900_w);
DECLARE_WRITE8_MEMBER(xavix_7980_w); DECLARE_WRITE8_MEMBER(dma_trigger_w);
DECLARE_WRITE8_MEMBER(xavix_7981_w); DECLARE_WRITE8_MEMBER(dmasrc_lo_w);
DECLARE_WRITE8_MEMBER(xavix_7982_w); DECLARE_WRITE8_MEMBER(dmasrc_md_w);
DECLARE_WRITE8_MEMBER(xavix_7983_w); DECLARE_WRITE8_MEMBER(dmasrc_hi_w);
DECLARE_WRITE8_MEMBER(xavix_7984_w); DECLARE_WRITE8_MEMBER(dmadst_lo_w);
DECLARE_WRITE8_MEMBER(xavix_7985_w); DECLARE_WRITE8_MEMBER(dmadst_hi_w);
DECLARE_WRITE8_MEMBER(xavix_7986_w); DECLARE_WRITE8_MEMBER(dmalen_lo_w);
DECLARE_WRITE8_MEMBER(xavix_7987_w); DECLARE_WRITE8_MEMBER(dmalen_hi_w);
DECLARE_READ8_MEMBER(xavix_7980_r); DECLARE_READ8_MEMBER(dma_trigger_r);
DECLARE_READ8_MEMBER(xavix_7a01_r);
DECLARE_WRITE8_MEMBER(xavix_7ff9_w); DECLARE_WRITE8_MEMBER(irq_enable_w);
DECLARE_WRITE8_MEMBER(xavix_7ffa_w); DECLARE_WRITE8_MEMBER(irq_vector0_lo_w);
DECLARE_WRITE8_MEMBER(xavix_7ffb_w); DECLARE_WRITE8_MEMBER(irq_vector0_hi_w);
DECLARE_WRITE8_MEMBER(xavix_7ffe_w); DECLARE_WRITE8_MEMBER(irq_vector1_lo_w);
DECLARE_WRITE8_MEMBER(xavix_7fff_w); DECLARE_WRITE8_MEMBER(irq_vector1_hi_w);
DECLARE_READ8_MEMBER(xavix_75f4_r);
DECLARE_READ8_MEMBER(xavix_75f5_r);
DECLARE_WRITE8_MEMBER(xavix_75f6_w);
DECLARE_WRITE8_MEMBER(xavix_75f7_w);
DECLARE_WRITE8_MEMBER(xavix_75f8_w);
DECLARE_WRITE8_MEMBER(xavix_75f9_w);
DECLARE_WRITE8_MEMBER(xavix_75ff_w);
DECLARE_READ8_MEMBER(xavix_75f9_r);
INTERRUPT_GEN_MEMBER(interrupt); INTERRUPT_GEN_MEMBER(interrupt);
TIMER_DEVICE_CALLBACK_MEMBER(scanline_cb); TIMER_DEVICE_CALLBACK_MEMBER(scanline_cb);
@ -99,43 +112,76 @@ protected:
virtual void video_start() override; virtual void video_start() override;
private: private:
uint8_t m_xavix_7981_data; uint8_t m_dmasrc_lo_data;
uint8_t m_xavix_7982_data; uint8_t m_dmasrc_md_data;
uint8_t m_xavix_7983_data; uint8_t m_dmasrc_hi_data;
uint8_t m_xavix_7984_data; uint8_t m_dmadst_lo_data;
uint8_t m_xavix_7985_data; uint8_t m_dmadst_hi_data;
uint8_t m_xavix_7986_data; uint8_t m_dmalen_lo_data;
uint8_t m_xavix_7987_data; uint8_t m_dmalen_hi_data;
uint8_t m_xavix_7ff9_data; uint8_t m_irq_enable_data;
uint8_t m_xavix_7ffa_data; uint8_t m_irq_vector0_lo_data;
uint8_t m_xavix_7ffb_data; uint8_t m_irq_vector0_hi_data;
uint8_t m_xavix_7ffe_data; uint8_t m_irq_vector1_lo_data;
uint8_t m_xavix_7fff_data; uint8_t m_irq_vector1_hi_data;
uint8_t get_vectors(int which, int half); uint8_t get_vectors(int which, int half);
required_shared_ptr<uint8_t> m_palram1;
required_shared_ptr<uint8_t> m_palram2;
required_device<palette_device> m_palette;
void handle_palette(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
}; };
void xavix_state::video_start() void xavix_state::video_start()
{ {
} }
void xavix_state::handle_palette(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
// Palette (WRONG! it's probably more like the rad_eu3a14.cpp etc. ones)
int offs = 0;
for (int index = 0; index < 256; index++)
{
uint16_t dat = m_palram1[offs];
dat |= m_palram2[offs]<<8;
offs++;
int r = (dat & 0x000f) >> 0;
int g = (dat & 0x00f0) >> 4;
int b = (dat & 0x0f00) >> 8;
int i = (dat & 0xf000) >> 12;
i+=1;
r = (r * i)-1;
g = (g * i)-1;
b = (b * i)-1;
m_palette->set_pen_color(index, r, g, b);
}
}
uint32_t xavix_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect ) uint32_t xavix_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect )
{ {
handle_palette(screen, bitmap, cliprect);
return 0; return 0;
} }
WRITE8_MEMBER(xavix_state::xavix_7980_w) WRITE8_MEMBER(xavix_state::dma_trigger_w)
{ {
logerror("%s: xavix_7980_w %02x (79xx unk trigger for 7981-7987?)\n", machine().describe_context(), data); logerror("%s: dma_trigger_w %02x\n", machine().describe_context(), data);
uint32_t source = (m_xavix_7983_data << 16) | (m_xavix_7982_data<<8) | m_xavix_7981_data; uint32_t source = (m_dmasrc_hi_data << 16) | (m_dmasrc_md_data<<8) | m_dmasrc_lo_data;
uint16_t dest = (m_xavix_7985_data<<8) | m_xavix_7984_data; uint16_t dest = (m_dmadst_hi_data<<8) | m_dmadst_lo_data;
uint16_t len = (m_xavix_7987_data<<8) | m_xavix_7986_data; uint16_t len = (m_dmalen_hi_data<<8) | m_dmalen_lo_data;
// TODO: don't do tag lookups here once satisfied this is correct // TODO: don't do tag lookups here once satisfied this is correct
const uint32_t rgnlen = memregion("bios")->bytes(); const uint32_t rgnlen = memregion("bios")->bytes();
@ -153,90 +199,90 @@ WRITE8_MEMBER(xavix_state::xavix_7980_w)
} }
} }
WRITE8_MEMBER(xavix_state::xavix_7981_w) WRITE8_MEMBER(xavix_state::dmasrc_lo_w)
{ {
logerror("%s: xavix_7981_w %02x (79xx unk triplet byte 1)\n", machine().describe_context(), data); logerror("%s: dmasrc_lo_w %02x\n", machine().describe_context(), data);
m_xavix_7981_data = data; m_dmasrc_lo_data = data;
} }
WRITE8_MEMBER(xavix_state::xavix_7982_w) WRITE8_MEMBER(xavix_state::dmasrc_md_w)
{ {
logerror("%s: xavix_7982_w %02x (79xx unk triplet byte 2)\n", machine().describe_context(), data); logerror("%s: dmasrc_md_w %02x\n", machine().describe_context(), data);
m_xavix_7982_data = data; m_dmasrc_md_data = data;
} }
WRITE8_MEMBER(xavix_state::xavix_7983_w) WRITE8_MEMBER(xavix_state::dmasrc_hi_w)
{ {
logerror("%s: xavix_7983_w %02x (79xx unk triplet byte 3)\n", machine().describe_context(), data); logerror("%s: dmasrc_hi_w %02x\n", machine().describe_context(), data);
m_xavix_7983_data = data; m_dmasrc_hi_data = data;
// this would mean Taito Nostalgia relies on mirroring tho, as it has the high bits set... so could just be wrong // this would mean Taito Nostalgia relies on mirroring tho, as it has the high bits set... so could just be wrong
logerror(" (possible DMA ROM source of %02x%02x%02x)\n", m_xavix_7983_data, m_xavix_7982_data, m_xavix_7981_data); logerror(" (DMA ROM source of %02x%02x%02x)\n", m_dmasrc_hi_data, m_dmasrc_md_data, m_dmasrc_lo_data);
} }
WRITE8_MEMBER(xavix_state::xavix_7984_w) WRITE8_MEMBER(xavix_state::dmadst_lo_w)
{ {
logerror("%s: xavix_7984_w %02x (79xx unk pair 1 byte 1)\n", machine().describe_context(), data); logerror("%s: dmadst_lo_w %02x\n", machine().describe_context(), data);
m_xavix_7984_data = data; m_dmadst_lo_data = data;
} }
WRITE8_MEMBER(xavix_state::xavix_7985_w) WRITE8_MEMBER(xavix_state::dmadst_hi_w)
{ {
logerror("%s: xavix_7985_w %02x (79xx unk pair 1 byte 2)\n", machine().describe_context(), data); logerror("%s: dmadst_hi_w %02x\n", machine().describe_context(), data);
m_xavix_7985_data = data; m_dmadst_hi_data = data;
logerror(" (possible DMA dest of %02x%02x)\n", m_xavix_7985_data, m_xavix_7984_data); logerror(" (DMA dest of %02x%02x)\n", m_dmadst_hi_data, m_dmadst_lo_data);
} }
WRITE8_MEMBER(xavix_state::xavix_7986_w) WRITE8_MEMBER(xavix_state::dmalen_lo_w)
{ {
logerror("%s: xavix_7986_w %02x (79xx unk pair 2 byte 1)\n", machine().describe_context(), data); logerror("%s: dmalen_lo_w %02x\n", machine().describe_context(), data);
m_xavix_7986_data = data; m_dmalen_lo_data = data;
} }
WRITE8_MEMBER(xavix_state::xavix_7987_w) WRITE8_MEMBER(xavix_state::dmalen_hi_w)
{ {
logerror("%s: xavix_7987_w %02x (79xx unk pair 2 byte 2)\n", machine().describe_context(), data); logerror("%s: dmalen_hi_w %02x\n", machine().describe_context(), data);
m_xavix_7987_data = data; m_dmalen_hi_data = data;
logerror(" (possible DMA len of %02x%02x)\n", m_xavix_7987_data, m_xavix_7986_data); logerror(" (DMA len of %02x%02x)\n", m_dmalen_hi_data, m_dmalen_lo_data);
} }
READ8_MEMBER(xavix_state::xavix_7980_r) READ8_MEMBER(xavix_state::dma_trigger_r)
{ {
logerror("%s: xavix_7980_r (79xx unk operation status?)\n", machine().describe_context()); logerror("%s: dma_trigger_r (operation status?)\n", machine().describe_context());
return 0x00; return 0x00;
} }
WRITE8_MEMBER(xavix_state::xavix_7ff9_w) WRITE8_MEMBER(xavix_state::irq_enable_w)
{ {
logerror("%s: xavix_7ff9_w %02x (trigger for 7ffx region?)\n", machine().describe_context(), data); logerror("%s: irq_enable_w %02x\n", machine().describe_context(), data);
m_xavix_7ff9_data = data; m_irq_enable_data = data;
} }
WRITE8_MEMBER(xavix_state::xavix_7ffa_w) WRITE8_MEMBER(xavix_state::irq_vector0_lo_w)
{ {
logerror("%s: xavix_7ffa_w %02x (7ffx pair 1, byte 1?)\n", machine().describe_context(), data); logerror("%s: irq_vector0_lo_w %02x\n", machine().describe_context(), data);
m_xavix_7ffa_data = data; m_irq_vector0_lo_data = data;
} }
WRITE8_MEMBER(xavix_state::xavix_7ffb_w) WRITE8_MEMBER(xavix_state::irq_vector0_hi_w)
{ {
logerror("%s: xavix_7ffb_w %02x (7ffx pair 1, byte 2?)\n", machine().describe_context(), data); logerror("%s: irq_vector0_hi_w %02x\n", machine().describe_context(), data);
m_xavix_7ffb_data = data; m_irq_vector0_hi_data = data;
} }
WRITE8_MEMBER(xavix_state::xavix_7ffe_w) WRITE8_MEMBER(xavix_state::irq_vector1_lo_w)
{ {
logerror("%s: xavix_7ffe_w %02x (7ffx pair 2, byte 1?)\n", machine().describe_context(), data); logerror("%s: irq_vector1_lo_w %02x\n", machine().describe_context(), data);
m_xavix_7ffe_data = data; m_irq_vector1_lo_data = data;
} }
WRITE8_MEMBER(xavix_state::xavix_7fff_w) WRITE8_MEMBER(xavix_state::irq_vector1_hi_w)
{ {
logerror("%s: xavix_7fff_w %02x (7ffx pair 2, byte 2?)\n", machine().describe_context(), data); logerror("%s: irq_vector1_hi_w %02x\n", machine().describe_context(), data);
m_xavix_7fff_data = data; m_irq_vector1_hi_data = data;
} }
@ -249,48 +295,191 @@ WRITE8_MEMBER(xavix_state::xavix_7900_w)
TIMER_DEVICE_CALLBACK_MEMBER(xavix_state::scanline_cb) TIMER_DEVICE_CALLBACK_MEMBER(xavix_state::scanline_cb)
{ {
// int scanline = param; /*
int scanline = param;
if (scanline == 200)
{
if (m_irq_enable_data != 0)
m_maincpu->set_input_line(INPUT_LINE_IRQ0,HOLD_LINE);
}
*/
} }
INTERRUPT_GEN_MEMBER(xavix_state::interrupt) INTERRUPT_GEN_MEMBER(xavix_state::interrupt)
{ {
// if (m_xavix_7ff9_data != 0) // if (m_irq_enable_data != 0)
// m_maincpu->set_input_line(INPUT_LINE_IRQ0,HOLD_LINE); // m_maincpu->set_input_line(INPUT_LINE_IRQ0,HOLD_LINE);
if (m_xavix_7ff9_data != 0) if (m_irq_enable_data != 0)
m_maincpu->set_input_line(INPUT_LINE_NMI,PULSE_LINE); m_maincpu->set_input_line(INPUT_LINE_NMI,PULSE_LINE);
} }
WRITE8_MEMBER(xavix_state::xavix_75f6_w)
{
logerror("%s: xavix_75f6_w %02x\n", machine().describe_context(), data);
}
WRITE8_MEMBER(xavix_state::xavix_75f7_w)
{
logerror("%s: xavix_75f7_w %02x\n", machine().describe_context(), data);
}
WRITE8_MEMBER(xavix_state::xavix_75f8_w)
{
logerror("%s: xavix_75f8_w %02x\n", machine().describe_context(), data);
}
WRITE8_MEMBER(xavix_state::xavix_75f9_w)
{
logerror("%s: xavix_75f9_w %02x\n", machine().describe_context(), data);
}
WRITE8_MEMBER(xavix_state::xavix_75ff_w)
{
logerror("%s: xavix_75ff_w %02x\n", machine().describe_context(), data);
}
READ8_MEMBER(xavix_state::xavix_75f9_r)
{
logerror("%s: xavix_75f9_r\n", machine().describe_context());
return 0x00;
}
READ8_MEMBER(xavix_state::xavix_7a01_r)
{
//logerror("%s: xavix_7a01_r (random status?)\n", machine().describe_context());
/*
rad_mtrk checks for 0x40 at (interrupt code)
008f02: lda $7a01 -- ??
008f05: and #$40
008f07: beq $8f17
(code that leads to a far call screen fade function with a 'jump to self' at the end, no obvious way out)
008f17 - normal flow?
opposite condition to above
018ac5: lda $7a01 -- ??
018ac8: and #$40
018aca: bne $18ac5
there's a write with 0x80 before the 'jump to self'
018aea: lda #$80
018aec: sta $7a01
018aef: jmp $18aef
and 0x02 elsewhere
near end of interrupt function will conditionally change the value stored at 0x33 to 00 or ff depending on this bit
008f24: lda $7a01
008f27: and #$02
008f29: bne $8f3c
(skips over code to store 0x00 at $33)
008f31: lda $7a01
008f34: and #$02
008f36: beq $8f3c
(skips over code to store 0xff at $33)
there's a similar check fo 0x02 that results in a far call
008099: lda $7a01
00809c: and #$02
00809e: beq $80ab
writes 00 04 and 80
*/
return 0x02;
}
READ8_MEMBER(xavix_state::xavix_75f4_r)
{
// used with 75f0
return 0xff;
}
READ8_MEMBER(xavix_state::xavix_75f5_r)
{
// used with 75f1
return 0xff;
}
// DATA reads from 0x8000-0xffff are banked by byte 0xff of 'ram'
static ADDRESS_MAP_START( xavix_map, AS_PROGRAM, 8, xavix_state ) static ADDRESS_MAP_START( xavix_map, AS_PROGRAM, 8, xavix_state )
AM_RANGE(0x000000, 0x0001ff) AM_RAM AM_RANGE(0x000000, 0x0001ff) AM_RAM
AM_RANGE(0x000200, 0x003fff) AM_RAM // ends up jumping to code here? must be a DMA? AM_RANGE(0x000200, 0x003fff) AM_RAM
AM_RANGE(0x006200, 0x0062ff) AM_RAM // cleared to 0x80 // 6xxx ranges could be the video controller
AM_RANGE(0x006900, 0x006900) AM_WRITENOP // startup (taitons1) AM_RANGE(0x006000, 0x0061ff) AM_RAM // taitons1 writes to other areas here, but might already be off the rails
AM_RANGE(0x006200, 0x0062ff) AM_RAM // cleared to 0x80 by both games
AM_RANGE(0x006300, 0x0067ff) AM_RAM // taitons1 writes to other areas here, but might already be off the rails
// could be palettes?
AM_RANGE(0x006800, 0x0068ff) AM_RAM AM_SHARE("palram1") // written with 6900
AM_RANGE(0x006900, 0x0069ff) AM_RAM AM_SHARE("palram2") // startup (taitons1)
AM_RANGE(0x006a00, 0x006a00) AM_WRITENOP
AM_RANGE(0x006a01, 0x006a01) AM_WRITENOP
AM_RANGE(0x006fc0, 0x006fc0) AM_WRITENOP // startup AM_RANGE(0x006fc0, 0x006fc0) AM_WRITENOP // startup
AM_RANGE(0x006fc8, 0x006fc8) AM_WRITENOP
AM_RANGE(0x006fc9, 0x006fc9) AM_WRITENOP
AM_RANGE(0x006fca, 0x006fca) AM_WRITENOP
AM_RANGE(0x006fcb, 0x006fcb) AM_WRITENOP
AM_RANGE(0x006fcc, 0x006fcc) AM_WRITENOP
AM_RANGE(0x006fcd, 0x006fcd) AM_WRITENOP
AM_RANGE(0x006fce, 0x006fce) AM_WRITENOP
AM_RANGE(0x006fcf, 0x006fcf) AM_WRITENOP
//AM_RANGE(0x006fd7, 0x006fd7) AM_READNOP AM_WRITENOP
AM_RANGE(0x006fd8, 0x006fd8) AM_WRITENOP // startup (taitons1) AM_RANGE(0x006fd8, 0x006fd8) AM_WRITENOP // startup (taitons1)
AM_RANGE(0x006fe9, 0x006fe9) AM_WRITENOP // startup //AM_RANGE(0x006fe0, 0x006fe0) AM_READNOP AM_WRITENOP // after writing to 6fe1/6fe2 and 6fe5/6fe6 rad_mtrk writes 0x43/0x44 here then polls on 0x40 (see function call at c273) write values are hardcoded, similar code at 18401
AM_RANGE(0x006fe1, 0x006fe1) AM_WRITENOP
AM_RANGE(0x006fe2, 0x006fe2) AM_WRITENOP
AM_RANGE(0x006fe5, 0x006fe5) AM_WRITENOP
AM_RANGE(0x006fe6, 0x006fe6) AM_WRITENOP
AM_RANGE(0x006ff1, 0x006ff1) AM_WRITENOP // startup (taitons1) // function in rad_mtrk at 0184b7 uses this
AM_RANGE(0x006fe8, 0x006fe8) AM_WRITENOP // cleared in interrupt 0
AM_RANGE(0x006fe9, 0x006fe9) AM_WRITENOP // startup - cleared in interrupt 0
AM_RANGE(0x006fea, 0x006fea) AM_WRITENOP
AM_RANGE(0x006ff8, 0x006ff8) AM_READNOP AM_WRITENOP // startup AM_RANGE(0x006ff0, 0x006ff0) AM_WRITENOP // cleared in interrupt 0
AM_RANGE(0x006ff1, 0x006ff1) AM_WRITENOP // startup - cleared in interrupt 0
AM_RANGE(0x006ff2, 0x006ff2) AM_WRITENOP // set to 07 after clearing above things in interrupt 0
AM_RANGE(0x006ff8, 0x006ff8) AM_RAM // always seems to be a read/store or read/modify/store
//AM_RANGE(0x006ff9, 0x006ff9) AM_READNOP
// 7xxx ranges system controller?
AM_RANGE(0x0075f0, 0x0075f0) AM_RAM // read/written 8 times in a row
AM_RANGE(0x0075f1, 0x0075f1) AM_RAM // read/written 8 times in a row
AM_RANGE(0x0075f4, 0x0075f4) AM_READ(xavix_75f4_r) // related to 75f0 (read after writing there - rad_mtrk)
AM_RANGE(0x0075f5, 0x0075f5) AM_READ(xavix_75f5_r) // related to 75f1 (read after writing there - rad_mtrk)
// taitons1 after 75f7/75f8 // taitons1 after 75f7/75f8
//AM_RANGE(0x0075f6, 0x0075f6) AM_WRITE(xavix_75f6_w) AM_RANGE(0x0075f6, 0x0075f6) AM_WRITE(xavix_75f6_w)
// taitons1 written as a pair // taitons1 written as a pair
//AM_RANGE(0x0075f7, 0x0075f7) AM_WRITE(xavix_75f7_w) AM_RANGE(0x0075f7, 0x0075f7) AM_WRITE(xavix_75f7_w)
//AM_RANGE(0x0075f8, 0x0075f8) AM_WRITE(xavix_75f8_w) AM_RANGE(0x0075f8, 0x0075f8) AM_WRITE(xavix_75f8_w)
// taitons1 written after 75f6, then read // taitons1 written after 75f6, then read
//AM_RANGE(0x0075f9, 0x0075f9) AM_READWRITE(xavix_75f9_r, xavix_75f9_w) //AM_RANGE(0x0075f9, 0x0075f9) AM_READWRITE(xavix_75f9_r, xavix_75f9_w)
// at another time
AM_RANGE(0x0075fd, 0x0075fd) AM_WRITENOP
AM_RANGE(0x0075fe, 0x0075fe) AM_WRITENOP
// taitons1 written other 75xx operations // taitons1 written other 75xx operations
//AM_RANGE(0x0075ff, 0x0075ff) AM_WRITE(xavix_75ff_w) AM_RANGE(0x0075ff, 0x0075ff) AM_WRITE(xavix_75ff_w)
AM_RANGE(0x007810, 0x007810) AM_WRITENOP // startup AM_RANGE(0x007810, 0x007810) AM_WRITENOP // startup
@ -298,33 +487,48 @@ static ADDRESS_MAP_START( xavix_map, AS_PROGRAM, 8, xavix_state )
AM_RANGE(0x007902, 0x007902) AM_WRITENOP // startup AM_RANGE(0x007902, 0x007902) AM_WRITENOP // startup
// DMA trigger for below (written after the others) waits on status of bit 1 in a loop // DMA trigger for below (written after the others) waits on status of bit 1 in a loop
AM_RANGE(0x007980, 0x007980) AM_READWRITE(xavix_7980_r, xavix_7980_w) AM_RANGE(0x007980, 0x007980) AM_READWRITE(dma_trigger_r, dma_trigger_w)
// DMA source // DMA source
AM_RANGE(0x007981, 0x007981) AM_WRITE(xavix_7981_w) AM_RANGE(0x007981, 0x007981) AM_WRITE(dmasrc_lo_w)
AM_RANGE(0x007982, 0x007982) AM_WRITE(xavix_7982_w) AM_RANGE(0x007982, 0x007982) AM_WRITE(dmasrc_md_w)
AM_RANGE(0x007983, 0x007983) AM_WRITE(xavix_7983_w) AM_RANGE(0x007983, 0x007983) AM_WRITE(dmasrc_hi_w)
// DMA dest // DMA dest
AM_RANGE(0x007984, 0x007984) AM_WRITE(xavix_7984_w) AM_RANGE(0x007984, 0x007984) AM_WRITE(dmadst_lo_w)
AM_RANGE(0x007985, 0x007985) AM_WRITE(xavix_7985_w) AM_RANGE(0x007985, 0x007985) AM_WRITE(dmadst_hi_w)
// DMA length // DMA length
AM_RANGE(0x007986, 0x007986) AM_WRITE(xavix_7986_w) AM_RANGE(0x007986, 0x007986) AM_WRITE(dmalen_lo_w)
AM_RANGE(0x007987, 0x007987) AM_WRITE(xavix_7987_w) AM_RANGE(0x007987, 0x007987) AM_WRITE(dmalen_hi_w)
AM_RANGE(0x007a00, 0x007a00) AM_READNOP // startup (taitons1) //AM_RANGE(0x007a00, 0x007a00) AM_READNOP // startup (taitons1)
AM_RANGE(0x007a01, 0x007a01) AM_READNOP // startup (taitons1) AM_RANGE(0x007a01, 0x007a01) AM_READ(xavix_7a01_r) AM_WRITENOP // startup (taitons1)
AM_RANGE(0x007a03, 0x007a03) AM_READNOP AM_WRITENOP // startup //AM_RANGE(0x007a02, 0x007a02) AM_WRITENOP // startup, gets set to 20, 7a00 is then also written with 20
//AM_RANGE(0x007a03, 0x007a03) AM_READNOP AM_WRITENOP // startup (gets set to 84 which is the same as the bits checked on 7a01, possible port direction register?)
AM_RANGE(0x007a80, 0x007a80) AM_WRITENOP
//AM_RANGE(0x007b80, 0x007b80) AM_READNOP
AM_RANGE(0x007b81, 0x007b81) AM_WRITENOP
AM_RANGE(0x007b82, 0x007b82) AM_WRITENOP
AM_RANGE(0x007c02, 0x007c02) AM_WRITENOP // once
AM_RANGE(0x007ff2, 0x007ff2) AM_WRITENOP
AM_RANGE(0x007ff3, 0x007ff3) AM_WRITENOP
AM_RANGE(0x007ff4, 0x007ff4) AM_WRITENOP
//AM_RANGE(0x007ff5, 0x007ff5) AM_READNOP
//AM_RANGE(0x007ff6, 0x007ff6) AM_READNOP
// maybe irq enable, written after below // maybe irq enable, written after below
AM_RANGE(0x007ff9, 0x007ff9) AM_WRITE(xavix_7ff9_w) AM_RANGE(0x007ff9, 0x007ff9) AM_WRITE(irq_enable_w)
// an IRQ vector (nmi?) // an IRQ vector (nmi?)
AM_RANGE(0x007ffa, 0x007ffa) AM_WRITE(xavix_7ffa_w) AM_RANGE(0x007ffa, 0x007ffa) AM_WRITE(irq_vector0_lo_w)
AM_RANGE(0x007ffb, 0x007ffb) AM_WRITE(xavix_7ffb_w) AM_RANGE(0x007ffb, 0x007ffb) AM_WRITE(irq_vector0_hi_w)
// an IRQ vector (irq?) // an IRQ vector (irq?)
AM_RANGE(0x007ffe, 0x007ffe) AM_WRITE(xavix_7ffe_w) AM_RANGE(0x007ffe, 0x007ffe) AM_WRITE(irq_vector1_lo_w)
AM_RANGE(0x007fff, 0x007fff) AM_WRITE(xavix_7fff_w) AM_RANGE(0x007fff, 0x007fff) AM_WRITE(irq_vector1_hi_w)
AM_RANGE(0x008000, 0x1fffff) AM_ROM AM_REGION("bios", 0x008000) AM_RANGE(0x008000, 0x7fffff) AM_ROM AM_REGION("bios", 0x008000) AM_MIRROR(0x800000) // rad_mtrk relies on rom mirroring
ADDRESS_MAP_END ADDRESS_MAP_END
static INPUT_PORTS_START( xavix ) static INPUT_PORTS_START( xavix )
@ -395,8 +599,33 @@ static const gfx_layout charlayout =
8*8*4 8*8*4
}; };
static const gfx_layout char16layout =
{
16,16,
RGN_FRAC(1,1),
4,
{ STEP4(0,1) },
{ 1*4,0*4,3*4,2*4,5*4,4*4,7*4,6*4, 9*4,8*4,11*4,10*4,13*4,12*4,15*4,14*4 },
{ STEP16(0,4*16) },
16*16*4
};
static const gfx_layout charlayout8bpp =
{
8,8,
RGN_FRAC(1,1),
8,
{ STEP8(0,1) },
{ STEP8(0,8) },
{ STEP8(0,8*8) },
8*8*8
};
static GFXDECODE_START( xavix ) static GFXDECODE_START( xavix )
GFXDECODE_ENTRY( "bios", 0, charlayout, 0, 1 ) GFXDECODE_ENTRY( "bios", 0, charlayout, 0, 1 )
GFXDECODE_ENTRY( "bios", 0, char16layout, 0, 1 )
GFXDECODE_ENTRY( "bios", 0, charlayout8bpp, 0, 1 )
GFXDECODE_END GFXDECODE_END
@ -406,21 +635,21 @@ void xavix_state::machine_start()
void xavix_state::machine_reset() void xavix_state::machine_reset()
{ {
m_xavix_7981_data = 0; m_dmasrc_lo_data = 0;
m_xavix_7982_data = 0; m_dmasrc_md_data = 0;
m_xavix_7983_data = 0; m_dmasrc_hi_data = 0;
m_xavix_7984_data = 0; m_dmadst_lo_data = 0;
m_xavix_7985_data = 0; m_dmadst_hi_data = 0;
m_xavix_7986_data = 0; m_dmalen_lo_data = 0;
m_xavix_7987_data = 0; m_dmalen_hi_data = 0;
m_xavix_7ff9_data = 0; m_irq_enable_data = 0;
m_xavix_7ffa_data = 0; m_irq_vector0_lo_data = 0;
m_xavix_7ffb_data = 0; m_irq_vector0_hi_data = 0;
m_xavix_7ffe_data = 0; m_irq_vector1_lo_data = 0;
m_xavix_7fff_data = 0; m_irq_vector1_hi_data = 0;
} }
typedef device_delegate<uint8_t (int which, int half)> xavix_interrupt_vector_delegate; typedef device_delegate<uint8_t (int which, int half)> xavix_interrupt_vector_delegate;
@ -429,19 +658,19 @@ uint8_t xavix_state::get_vectors(int which, int half)
{ {
// logerror("get_vectors %d %d\n", which, half); // logerror("get_vectors %d %d\n", which, half);
if (which == 0) // NMI if (which == 0) // irq?
{ {
if (half == 0) if (half == 0)
return m_xavix_7ffb_data; return m_irq_vector0_hi_data;
else else
return m_xavix_7ffa_data; return m_irq_vector0_lo_data;
} }
else else
{ {
if (half == 0) if (half == 0)
return m_xavix_7fff_data; return m_irq_vector1_hi_data;
else else
return m_xavix_7ffe_data; return m_irq_vector1_lo_data;
} }
} }
@ -467,7 +696,7 @@ MACHINE_CONFIG_START(xavix_state::xavix)
MCFG_GFXDECODE_ADD("gfxdecode", "palette", xavix) MCFG_GFXDECODE_ADD("gfxdecode", "palette", xavix)
MCFG_PALETTE_ADD("palette", 16) MCFG_PALETTE_ADD("palette", 256)
/* sound hardware */ /* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono") MCFG_SPEAKER_STANDARD_MONO("mono")
@ -483,13 +712,29 @@ MACHINE_CONFIG_END
***************************************************************************/ ***************************************************************************/
ROM_START( taitons1 ) ROM_START( taitons1 )
ROM_REGION( 0x200000, "bios", ROMREGION_ERASE00 ) ROM_REGION( 0x800000, "bios", ROMREGION_ERASE00 )
ROM_LOAD( "taitonostalgia1.u3", 0x000000, 0x200000, CRC(25bd8c67) SHA1(a109cd2da6aa4596e3ca3abd1afce2d0001a473f) ) ROM_LOAD( "taitonostalgia1.u3", 0x000000, 0x200000, CRC(25bd8c67) SHA1(a109cd2da6aa4596e3ca3abd1afce2d0001a473f) )
ROM_RELOAD(0x200000,0x200000)
ROM_RELOAD(0x400000,0x200000)
ROM_RELOAD(0x600000,0x200000)
ROM_END ROM_END
ROM_START( rad_ping ) ROM_START( rad_ping )
ROM_REGION( 0x200000, "bios", ROMREGION_ERASE00 ) ROM_REGION( 0x800000, "bios", ROMREGION_ERASE00 )
ROM_LOAD( "pingpong.bin", 0x000000, 0x100000, CRC(629f7f47) SHA1(2bb19fd202f1e6c319d2f7d18adbfed8a7669235) ) ROM_LOAD( "pingpong.bin", 0x000000, 0x100000, CRC(629f7f47) SHA1(2bb19fd202f1e6c319d2f7d18adbfed8a7669235) )
ROM_RELOAD(0x100000,0x100000)
ROM_RELOAD(0x200000,0x100000)
ROM_RELOAD(0x300000,0x100000)
ROM_RELOAD(0x400000,0x100000)
ROM_RELOAD(0x500000,0x100000)
ROM_RELOAD(0x600000,0x100000)
ROM_RELOAD(0x700000,0x100000)
ROM_END
ROM_START( rad_mtrk )
ROM_REGION( 0x800000, "bios", ROMREGION_ERASE00 )
ROM_LOAD( "monstertruck.bin", 0x000000, 0x400000, CRC(dccda0a7) SHA1(7953cf29643672f8367639555b797c20bb533eab) )
ROM_RELOAD(0x400000,0x400000)
ROM_END ROM_END
ROM_START( xavtenni ) ROM_START( xavtenni )
@ -511,12 +756,9 @@ ROM_END
*/ */
CONS( 2004, xavtenni, 0, 0, xavix, xavix, xavix_state, 0, "SSD Company LTD", "XaviX Tennis (XaviXPORT)", MACHINE_IS_SKELETON ) CONS( 2004, xavtenni, 0, 0, xavix, xavix, xavix_state, 0, "SSD Company LTD", "XaviX Tennis (XaviXPORT)", MACHINE_IS_SKELETON )
/* Standalone TV Games /* Standalone TV Games */
These all have jumps to the 3xxx region, which appears to be RAM (or possibly a banked space?) hopefully it's just missing some kind of DMA transfer and
isn't some additional internal ROM.
*/
CONS( 2006, taitons1, 0, 0, xavix, xavix, xavix_state, 0, "Bandai / SSD Company LTD / Taito", "Let's! TV Play Classic - Taito Nostalgia 1", MACHINE_IS_SKELETON ) CONS( 2006, taitons1, 0, 0, xavix, xavix, xavix_state, 0, "Bandai / SSD Company LTD / Taito", "Let's! TV Play Classic - Taito Nostalgia 1", MACHINE_IS_SKELETON )
CONS( 2000, rad_ping, 0, 0, xavix, xavix, xavix_state, 0, "Radica / SSD Company LTD / Simmer Technology", "Play TV Ping Pong", MACHINE_IS_SKELETON ) // "Simmer Technology" is also known as "Hummer Technology Co., Ltd" CONS( 2000, rad_ping, 0, 0, xavix, xavix, xavix_state, 0, "Radica / SSD Company LTD / Simmer Technology", "Play TV Ping Pong", MACHINE_IS_SKELETON ) // "Simmer Technology" is also known as "Hummer Technology Co., Ltd"
CONS( 2003, rad_mtrk, 0, 0, xavix, xavix, xavix_state, 0, "Radica / SSD Company LTD", "Play TV Monster Truck", MACHINE_IS_SKELETON )

1
src/mame/mame.lst
View File

@ -38935,6 +38935,7 @@ xsleenaj // TA-0019 (c) 1986
taitons1 // taitons1 //
xavtenni // xavtenni //
rad_ping // rad_ping //
rad_mtrk //
@source:xbox.cpp @source:xbox.cpp
xbox // xbox //