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srcclean (nw)

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This commit is contained in:
Vas Crabb 2017-06-25 15:16:48 +10:00
parent 4a57052b5f
commit f31e735053
79 changed files with 556 additions and 556 deletions
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2
hash/nes.xml
View File

@ -80938,7 +80938,7 @@ that the real dumps might surface -->
<!-- ONE BUS based systems are famiclones (of plug-and-play type) which are based on the famicom hw but with a slightly more powerful PPU.
As they are standalone machines they're contained in nes_vt.cpp rather than the software lists. The notes below relate to ROMs
extracted from those sets -->
extracted from those sets -->
<!-- The following iNES roms are ripped from mc_dgear, so we don't include them (crc is from headerless file):
* Deformable [b0716cc2]

4
hash/pet_quik.xml
View File

@ -1,7 +1,7 @@
<?xml version="1.0"?>
<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
<softwarelist name="pet_quik" description="Commodore PET quickload">
<!-- https://www.youtube.com/watch?v=OBEfKMFq8lo -->
<software name="npa">
<description>No Pets Allowed</description>
@ -15,7 +15,7 @@
</dataarea>
</part>
</software>
<!-- https://www.youtube.com/watch?v=gYHYplCyrM0 -->
<software name="hardcore">
<description>Hardcore Petting</description>

14
plugins/cheat/cheat_simple.lua
View File

@ -71,13 +71,13 @@ function codefuncs.nes_gg(desc, code)
if #code == 6 then
addr = ((value >> 4) & 7) | ((value >> 8) & 0x78) | ((value >> 12) & 0x80) | ((value << 8) & 0x700) | ((value << 4) & 0x7800)
newval = ((value >> 20) & 7) | (value & 8) | ((value >> 12) & 0x70) | ((value >> 16) & 0x80)
return prepare_rom_cheat(desc, ":nes_slot:cart:prg_rom", addr, newval, 8)
return prepare_rom_cheat(desc, ":nes_slot:cart:prg_rom", addr, newval, 8)
elseif #code == 8 then
addr = ((value >> 12) & 7) | ((value >> 16) & 0x78) | ((value >> 20) & 0x80) | (value & 0x700) | ((value >> 4) & 0x7800)
newval = ((value >> 28) & 7) | (value & 8) | ((value >> 20) & 0x70) | ((value >> 24) & 0x80)
comp = ((value >> 4) & 7) | ((value >> 8) & 8) | ((value << 4) & 0x70) | ((value << 1) & 0x80)
-- assume 8K banks, 32K also common but is an easy multiple of 8K
return prepare_rom_cheat(desc, ":nes_slot:cart:prg_rom", addr, newval, 8, 8192, comp)
return prepare_rom_cheat(desc, ":nes_slot:cart:prg_rom", addr, newval, 8, 8192, comp)
else
error("error game genie cheat incorrect length " .. desc)
end
@ -100,7 +100,7 @@ local function snes_prepare_cheat(desc, addr, val)
local bank = addr >> 16
local offset = addr & 0xffff
if ((bank <= 0x3f) and (offset < 0x2000)) or ((bank & 0xfe) == 0x7e) then
return prepare_ram_cheat(desc, ":maincpu", addr, val, 8)
return prepare_ram_cheat(desc, ":maincpu", addr, val, 8)
end
if (manager:machine().devices[":maincpu"].spaces["program"]:read_u8(0xffd5) & 1) == 1 then --hirom
if (bank & 0x7f) <= 0x3f and offset >= 0x8000 then
@ -125,7 +125,7 @@ local function snes_prepare_cheat(desc, addr, val)
error("error cheat not rom or ram addr " .. desc)
end
end
return prepare_rom_cheat(desc, ":snsslot:cart:rom", addr, val, 8)
return prepare_rom_cheat(desc, ":snsslot:cart:rom", addr, val, 8)
end
function codefuncs.snes_gg(desc, code)
@ -184,7 +184,7 @@ function codefuncs.megadriv_gg(desc, code)
end
local newval = ((value >> 32) & 0xff) | ((value >> 3) & 0x1f00) | ((value << 5) & 0xe000)
local addr = (value & 0xff00ff) | ((value >> 16) & 0xff00)
return prepare_rom_cheat(desc, ":mdslot:cart:rom", addr, newval, 16)
return prepare_rom_cheat(desc, ":mdslot:cart:rom", addr, newval, 16)
end
function codefuncs.megadriv_ar(desc, code)
@ -221,10 +221,10 @@ local function gbgg_ggcodes(desc, code, region)
error("error game genie cheat bad addr " .. desc)
end
if comp == -1 then
return prepare_rom_cheat(desc, region, addr, newval, 8)
return prepare_rom_cheat(desc, region, addr, newval, 8)
else
-- assume 8K banks
return prepare_rom_cheat(desc, region, addr, newval, 8, 8192, comp)
return prepare_rom_cheat(desc, region, addr, newval, 8, 8192, comp)
end
return cheat
end

4
plugins/cheat/init.lua
View File

@ -107,7 +107,7 @@ function cheat.startplugin()
end
end
end
end
end
return newcheats
end
@ -416,7 +416,7 @@ function cheat.startplugin()
return false
end
menu[1] = {"Select cheat to set hotkey", "", "off"}
menu[2] = {"---", "", "off"}
hotkeylist = {}

2
src/devices/bus/centronics/epson_lx810l.h
View File

@ -97,7 +97,7 @@ private:
DECLARE_READ8_MEMBER(an6_r);
DECLARE_READ8_MEMBER(an7_r);
/* GATE ARRAY */
DECLARE_WRITE16_MEMBER(printhead);
DECLARE_WRITE8_MEMBER(pf_stepper);

12
src/devices/bus/coco/coco_dcmodem.cpp
View File

@ -2,12 +2,12 @@
// copyright-holders:Nathan Woods
/***************************************************************************
coco_dcmodem.cpp
coco_dcmodem.cpp
Code for emulating the CoCo Direct Connect Modem PAK
Code for emulating the CoCo Direct Connect Modem PAK
This is just a "skeleton device"; the UART is emulated but pretty much
nothing else
This is just a "skeleton device"; the UART is emulated but pretty much
nothing else
***************************************************************************/
@ -17,7 +17,7 @@
/***************************************************************************
CONSTANTS
CONSTANTS
***************************************************************************/
#define UART_TAG "uart"
@ -78,7 +78,7 @@ namespace
/***************************************************************************
IMPLEMENTATION
IMPLEMENTATION
***************************************************************************/
MACHINE_CONFIG_MEMBER(coco_dc_modem_device::device_add_mconfig)

4
src/devices/bus/coco/coco_multi.cpp
View File

@ -139,7 +139,7 @@ static SLOT_INTERFACE_START(coco_cart_slot1_3)
SLOT_INTERFACE("rs232", COCO_RS232)
SLOT_INTERFACE("dcmodem", COCO_DCMODEM)
SLOT_INTERFACE("orch90", COCO_ORCH90)
SLOT_INTERFACE("ssc", COCO_SSC) MCFG_SLOT_OPTION_CLOCK("ssc", DERIVED_CLOCK(1, 1))
SLOT_INTERFACE("ssc", COCO_SSC) MCFG_SLOT_OPTION_CLOCK("ssc", DERIVED_CLOCK(1, 1))
SLOT_INTERFACE("games_master", COCO_PAK_GMC)
SLOT_INTERFACE("banked_16k", COCO_PAK_BANKED)
SLOT_INTERFACE("pak", COCO_PAK)
@ -150,7 +150,7 @@ static SLOT_INTERFACE_START(coco_cart_slot4)
SLOT_INTERFACE("rs232", COCO_RS232)
SLOT_INTERFACE("dcmodem", COCO_DCMODEM)
SLOT_INTERFACE("orch90", COCO_ORCH90)
SLOT_INTERFACE("ssc", COCO_SSC) MCFG_SLOT_OPTION_CLOCK("ssc", DERIVED_CLOCK(1, 1))
SLOT_INTERFACE("ssc", COCO_SSC) MCFG_SLOT_OPTION_CLOCK("ssc", DERIVED_CLOCK(1, 1))
SLOT_INTERFACE("games_master", COCO_PAK_GMC)
SLOT_INTERFACE("banked_16k", COCO_PAK_BANKED)
SLOT_INTERFACE("pak", COCO_PAK)

4
src/devices/bus/coco/coco_orch90.cpp
View File

@ -79,8 +79,8 @@ namespace
}
private:
WRITE8_MEMBER(write_left) { m_ldac->write(data); }
WRITE8_MEMBER(write_right) { m_rdac->write(data); }
WRITE8_MEMBER(write_left) { m_ldac->write(data); }
WRITE8_MEMBER(write_right) { m_rdac->write(data); }
// internal state
required_device<dac_byte_interface> m_ldac;

10
src/devices/bus/coco/coco_ssc.cpp
View File

@ -1,4 +1,4 @@
// license:BSD-3-Clause
// license:BSD-3-Clause
// copyright-holders:tim lindner
/***************************************************************************
@ -222,9 +222,9 @@ void coco_ssc_device::device_start()
save_item(NAME(m_tms7000_portb));
save_item(NAME(m_tms7000_portc));
save_item(NAME(m_tms7000_portd));
m_tms7000_busy_timer = timer_alloc(BUSY_TIMER_ID);
}
@ -249,7 +249,7 @@ void coco_ssc_device::device_timer(emu_timer &timer, device_timer_id id, int par
{
case BUSY_TIMER_ID:
m_tms7000_busy = false;
m_tms7000_busy_timer->adjust(attotime::never);
m_tms7000_busy_timer->adjust(attotime::never);
break;
default:
@ -453,7 +453,7 @@ WRITE8_MEMBER(coco_ssc_device::ssc_port_c_w)
m_spo->ald_w(space, 0, m_tms7000_portd);
}
if( ((m_tms7000_portc & C_BSY) == 0) && ((data & C_BSY) == C_BSY) )
if( ((m_tms7000_portc & C_BSY) == 0) && ((data & C_BSY) == C_BSY) )
{
m_tms7000_busy_timer->adjust(attotime::from_usec(1800));
}

22
src/devices/bus/coco/cococart.cpp
View File

@ -31,9 +31,9 @@
19 A0 39 A15
20 A1 40 SLENB
Notes:
CTS - ROM read $C000-$FEFF ($FDFF on CoCo 3)
SCS - Spare Chip Select: IO space between $FF40-5F
Notes:
CTS - ROM read $C000-$FEFF ($FDFF on CoCo 3)
SCS - Spare Chip Select: IO space between $FF40-5F
*********************************************************************/
@ -49,7 +49,7 @@
/***************************************************************************
CONSTANTS
CONSTANTS
***************************************************************************/
enum
@ -484,7 +484,7 @@ void device_cococart_interface::interface_pre_start()
//-------------------------------------------------
// scs_read - Signifies a read where the SCS pin
// on the cartridge slot was asserted ($FF40-5F)
// on the cartridge slot was asserted ($FF40-5F)
//-------------------------------------------------
READ8_MEMBER(device_cococart_interface::scs_read)
@ -495,7 +495,7 @@ READ8_MEMBER(device_cococart_interface::scs_read)
//-------------------------------------------------
// scs_write - Signifies a write where the SCS pin
// on the cartridge slot was asserted ($FF40-5F)
// on the cartridge slot was asserted ($FF40-5F)
//-------------------------------------------------
WRITE8_MEMBER(device_cococart_interface::scs_write)
@ -544,7 +544,7 @@ void device_cococart_interface::cart_base_changed(void)
//-------------------------------------------------
// cartridge_space
// cartridge_space
//-------------------------------------------------
address_space &device_cococart_interface::cartridge_space()
@ -554,7 +554,7 @@ address_space &device_cococart_interface::cartridge_space()
//-------------------------------------------------
// install_read_handler
// install_read_handler
//-------------------------------------------------
void device_cococart_interface::install_read_handler(uint16_t addrstart, uint16_t addrend, read8_delegate rhandler)
@ -565,7 +565,7 @@ void device_cococart_interface::install_read_handler(uint16_t addrstart, uint16_
//-------------------------------------------------
// install_write_handler
// install_write_handler
//-------------------------------------------------
void device_cococart_interface::install_write_handler(uint16_t addrstart, uint16_t addrend, write8_delegate whandler)
@ -576,7 +576,7 @@ void device_cococart_interface::install_write_handler(uint16_t addrstart, uint16
//-------------------------------------------------
// install_readwrite_handler
// install_readwrite_handler
//-------------------------------------------------
void device_cococart_interface::install_readwrite_handler(uint16_t addrstart, uint16_t addrend, read8_delegate rhandler, write8_delegate whandler)
@ -588,7 +588,7 @@ void device_cococart_interface::install_readwrite_handler(uint16_t addrstart, ui
//-------------------------------------------------
// set_line_value
// set_line_value
//-------------------------------------------------
void device_cococart_interface::set_line_value(cococart_slot_device::line line, cococart_slot_device::line_value value)

6
src/devices/bus/coco/cococart.h
View File

@ -195,8 +195,8 @@ protected:
void cart_base_changed(void);
// accessors for containers
cococart_slot_device &owning_slot() { assert(m_owning_slot); return *m_owning_slot; }
device_cococart_host_interface &host() { assert(m_host); return *m_host; }
cococart_slot_device &owning_slot() { assert(m_owning_slot); return *m_owning_slot; }
device_cococart_host_interface &host() { assert(m_host); return *m_host; }
// CoCo cartridges can read directly from the address bus. This is used by a number of
// cartridges (e.g. - Orch-90, Multi-Pak interface) for their control registers, independently
@ -233,7 +233,7 @@ private:
/***************************************************************************
COCO CARTRIDGE DEVICES
COCO CARTRIDGE DEVICES
***************************************************************************/
// device type definitions - CoCo FDC

6
src/devices/bus/gameboy/gb_slot.cpp
View File

@ -481,14 +481,14 @@ bool gb_cart_slot_device_base::is_mbc1col_game(const uint8_t *ROM, uint32_t len)
/* Mortal Kombat I & II US */
"MORTALKOMBATI&II",
};
const uint8_t rows = sizeof(internal_names) / sizeof(internal_names[0]);
for (uint8_t i = 0x00; i < rows; ++i) {
if (0 == memcmp(&ROM[0x134], &internal_names[i][0], name_length))
return true;
}
return false;
}

6
src/devices/bus/hp_dio/hp98544.cpp
View File

@ -80,9 +80,9 @@ void dio16_98544_device::device_start()
m_rom = device().machine().root_device().memregion(this->subtag(HP98544_ROM_REGION).c_str())->base();
m_vram.resize(VRAM_SIZE);
m_dio->install_memory(0x200000, 0x2fffff, read16_delegate(FUNC(dio16_98544_device::vram_r), this),
m_dio->install_memory(0x200000, 0x2fffff, read16_delegate(FUNC(dio16_98544_device::vram_r), this),
write16_delegate(FUNC(dio16_98544_device::vram_w), this));
m_dio->install_memory(0x560000, 0x563fff, read16_delegate(FUNC(dio16_98544_device::rom_r), this),
m_dio->install_memory(0x560000, 0x563fff, read16_delegate(FUNC(dio16_98544_device::rom_r), this),
write16_delegate(FUNC(dio16_98544_device::rom_w), this));
}
@ -124,7 +124,7 @@ uint32_t dio16_98544_device::screen_update(screen_device &screen, bitmap_rgb32 &
uint32_t *scanline;
int x, y;
uint32_t pixels;
for (y = 0; y < 768; y++)
{
scanline = &bitmap.pix32(y);

12
src/devices/bus/hp_dio/hp_dio.h
View File

@ -4,11 +4,11 @@
HP DIO and DIO-II bus devices
DIO is 16-bit, essentially the MC68000 bus
DIO-II extends to 32-bit for 68020/030/040 machines
16-bit DIO cards fit and work in either 16 or 32 bit systems, much like 8-bit ISA.
32-bit DIO-II cards only work in 32 bit DIO-II systems.
DIO is 16-bit, essentially the MC68000 bus
DIO-II extends to 32-bit for 68020/030/040 machines
16-bit DIO cards fit and work in either 16 or 32 bit systems, much like 8-bit ISA.
32-bit DIO-II cards only work in 32 bit DIO-II systems.
***************************************************************************/
@ -91,7 +91,7 @@ public:
template <class Object> static devcb_base &set_out_irq6_callback(device_t &device, Object &&cb) { return downcast<dio16_device &>(device).m_out_irq6_cb.set_callback(std::forward<Object>(cb)); }
void install_memory(offs_t start, offs_t end, read16_delegate rhandler, write16_delegate whandler);
// DANGER: these will currently produce different results for a DIO-I card on DIO-I and DIO-II systems
// due to the varying bus widths. Using all install_memory() shields you from this problem.
// either know what you're doing (m_prgwidth is available to cards for this purpose) or

2
src/devices/bus/ieee488/hp9895.h
View File

@ -50,7 +50,7 @@ public:
DECLARE_READ8_MEMBER(switches_r);
DECLARE_READ8_MEMBER(switches2_r);
// PHI register read
// PHI register read
DECLARE_READ8_MEMBER(phi_reg_r);
// Floppy drive interface

2
src/devices/bus/isa/mda.h
View File

@ -30,7 +30,7 @@ public:
DECLARE_WRITE_LINE_MEMBER(hsync_changed);
DECLARE_WRITE_LINE_MEMBER(vsync_changed);
virtual MC6845_UPDATE_ROW( crtc_update_row );
protected:

8
src/devices/bus/x68k/x68k_midi.cpp
View File

@ -2,9 +2,9 @@
// copyright-holders:Barry Rodewald
/*
* x68k_midi.c
*
*
* X68000 MIDI interface - YM3802
*
*
*/
#include "emu.h"
@ -23,7 +23,7 @@ MACHINE_CONFIG_MEMBER( x68k_midi_device::device_add_mconfig )
MCFG_YM3802_IRQ_HANDLER(WRITELINE(x68k_midi_device,irq_w))
MCFG_MIDI_PORT_ADD("mdin", midiin_slot, "midiin")
MCFG_MIDI_PORT_ADD("mdout", midiout_slot, "midiout")
// MCFG_MIDI_PORT_ADD("mdthru", midiout_slot, "midiout")
// MCFG_MIDI_PORT_ADD("mdthru", midiout_slot, "midiout")
// TODO: Add serial data handlers
MACHINE_CONFIG_END
@ -45,7 +45,7 @@ void x68k_midi_device::device_start()
space.install_readwrite_handler(0xeafa00,0xeafa0f,read8_delegate(FUNC(x68k_midi_device::x68k_midi_reg_r),this),write8_delegate(FUNC(x68k_midi_device::x68k_midi_reg_w),this),0x00ff00ff);
}
void x68k_midi_device::device_reset()
void x68k_midi_device::device_reset()
{
}

2
src/devices/bus/x68k/x68k_midi.h
View File

@ -29,7 +29,7 @@ public:
DECLARE_READ8_MEMBER(x68k_midi_reg_r);
DECLARE_WRITE8_MEMBER(x68k_midi_reg_w);
protected:
// device-level overrides
virtual void device_start() override;

4
src/devices/bus/x68k/x68kexp.h
View File

@ -105,10 +105,10 @@ public:
// reset
virtual void x68k_reset_w() { }
void set_vector(uint8_t vector) { m_vector = vector; }
uint8_t vector() { return m_vector; }
protected:
device_x68k_expansion_card_interface(const machine_config &mconfig, device_t &device);

2
src/devices/cpu/clipper/clipper.h
View File

@ -106,7 +106,7 @@ protected:
SSW_P = 0x80000000, // previous mode
};
enum clipper_ssw_id
enum clipper_ssw_id
{
SSW_ID_C400R0 = 0x00000,
SSW_ID_C400R1 = 0x04000,

4
src/devices/cpu/sm510/sm500.h
View File

@ -94,7 +94,7 @@ protected:
virtual void reset_vector() override { do_branch(0, 0xf, 0); }
virtual void wakeup_vector() override { do_branch(0, 0, 0); }
// lcd driver
devcb_write8 m_write_o;
virtual void lcd_update() override;
@ -154,7 +154,7 @@ public:
protected:
sm5a_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, int stack_levels, int o_mask, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data);
virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const u8 *oprom, const u8 *opram, u32 options) override;
virtual void execute_one() override;
virtual int get_trs_field() override { return 1; }

4
src/devices/cpu/sm510/sm500core.cpp
View File

@ -3,7 +3,7 @@
/*
Sharp SM500 MCU core implementation
TODO:
- EXKSA, EXKFA opcodes
- SM500 data book suggests that R1 divider output is selectable, but how?
@ -89,7 +89,7 @@ void sm500_device::device_reset()
{
// common reset
sm510_base_device::device_reset();
// SM500 specific
op_idiv();
m_1s = true;

4
src/devices/cpu/sm510/sm500op.cpp
View File

@ -24,7 +24,7 @@ u8 sm500_device::get_digit()
0xe, 0x0, 0xc, 0x8, 0x2, 0xa, 0xe, 0x2, 0xe, 0xa, 0x0, 0x0, 0x2, 0xa, 0x2, 0x2,
0xb, 0x9, 0x7, 0xf, 0xd, 0xe, 0xe, 0xb, 0xf, 0xf, 0x4, 0x0, 0xd, 0xe, 0x4, 0x0
};
return lut_digits[m_cn << 4 | m_acc] | (~m_cn & m_mx);
}
@ -100,7 +100,7 @@ void sm500_device::op_trs()
u8 su = get_su();
push_stack();
do_branch(get_trs_field(), 0, m_op & 0x3f);
// E flag was set?
if ((m_prev_op & 0xf0) == 0x70)
do_branch(m_cb, su, m_pc & 0x3f);

2
src/devices/cpu/sm510/sm510.h
View File

@ -155,7 +155,7 @@ protected:
address_space_config m_data_config;
address_space *m_program;
address_space *m_data;
virtual void reset_vector() { do_branch(3, 7, 0); }
virtual void wakeup_vector() { do_branch(1, 0, 0); } // after halt

2
src/devices/cpu/sm510/sm510base.cpp
View File

@ -15,7 +15,7 @@
- proper support for LFSR program counter in debugger
- LCD bs pin blink mode via Y register (0.5s off, 0.5s on)
- wake up after CEND doesn't work right
for more, see the *core.cpp file notes
*/

2
src/devices/cpu/sm510/sm511core.cpp
View File

@ -3,7 +3,7 @@
/*
Sharp SM511 MCU core implementation
TODO:
- undocumented/guessed opcodes:
* $01 is guessed as DIV to ACC transfer, unknown which bits

2
src/devices/cpu/sm510/sm590core.cpp
View File

@ -3,7 +3,7 @@
/*
Sharp SM590 MCU core implementation
TODO:
- finish SM590/SM595 emulation (NES/SNES CIC)

2
src/devices/cpu/sm510/sm5acore.cpp
View File

@ -3,7 +3,7 @@
/*
Sharp SM5A MCU core implementation
TODO:
- confirm SM5A mnemonics

34
src/devices/machine/i7220.cpp
View File

@ -2,26 +2,26 @@
// copyright-holders:Sergey Svishchev
/**********************************************************************
Intel 7220 Bubble Memory Controller emulation
Intel 7220 Bubble Memory Controller emulation
References:
- http://www.decadecounter.com/vta/pdf/BPK72UM.pdf
- http://www.decadecounter.com/vta/pdf/7220-1.pdf
- http://www.decadecounter.com/vta/pdf/7242.pdf
- http://www.decadecounter.com/vta/articleview.php?item=359
References:
- http://www.decadecounter.com/vta/pdf/BPK72UM.pdf
- http://www.decadecounter.com/vta/pdf/7220-1.pdf
- http://www.decadecounter.com/vta/pdf/7242.pdf
- http://www.decadecounter.com/vta/articleview.php?item=359
Implemented at least partially
- commands
Read Bubble Data, Write Bubble Data
Initialize, Reset FIFO, Abort, Software Reset
Read FSA Status, MBM Purge
Implemented at least partially
- commands
Read Bubble Data, Write Bubble Data
Initialize, Reset FIFO, Abort, Software Reset
Read FSA Status, MBM Purge
Not implemented
- interrupts
- DMA
- commands
Read Seek, Write Seek, Read Corrected Data, all Bootloop-related
- access to other than 2 FSA channels at once
Not implemented
- interrupts
- DMA
- commands
Read Seek, Write Seek, Read Corrected Data, all Bootloop-related
- access to other than 2 FSA channels at once
**********************************************************************/

14
src/devices/machine/ram.cpp
View File

@ -32,13 +32,13 @@ uint32_t parse_string(const char *s)
unsigned multiple;
} s_suffixes[] =
{
{ "", 1 },
{ "k", 1024 },
{ "kb", 1024 },
{ "kib", 1024 },
{ "m", 1024 * 1024 },
{ "mb", 1024 * 1024 },
{ "mib", 1024 * 1024 }
{ "", 1 },
{ "k", 1024 },
{ "kb", 1024 },
{ "kib", 1024 },
{ "m", 1024 * 1024 },
{ "mb", 1024 * 1024 },
{ "mib", 1024 * 1024 }
};
// parse the string

62
src/devices/machine/sis85c496.cpp
View File

@ -2,14 +2,14 @@
// copyright-holders:R. Belmont, O. Galibert
/***************************************************************************
sis85c496.cpp - SiS 85C496/497 PCI chipset
by R. Belmont (based on i82439hx.cpp/i82439tx.cpp by O. Galibert)
Unlike Intel chipsets, the southbridge is not a PCI device;
it connects via a proprietary bus to the northbridge, and the two
chips appear to software/the BIOS as a single chip. Thus we emulate
them in a single file.
sis85c496.cpp - SiS 85C496/497 PCI chipset
by R. Belmont (based on i82439hx.cpp/i82439tx.cpp by O. Galibert)
Unlike Intel chipsets, the southbridge is not a PCI device;
it connects via a proprietary bus to the northbridge, and the two
chips appear to software/the BIOS as a single chip. Thus we emulate
them in a single file.
***************************************************************************/
#include "emu.h"
@ -19,7 +19,7 @@
DEFINE_DEVICE_TYPE(SIS85C496, sis85c496_host_device, "sis85c496", "SiS 85C496/497 chipset")
DEVICE_ADDRESS_MAP_START(config_map, 32, sis85c496_host_device)
DEVICE_ADDRESS_MAP_START(config_map, 32, sis85c496_host_device)
AM_RANGE(0x40, 0x43) AM_READWRITE8(dram_config_r, dram_config_w, 0x000000ff)
AM_RANGE(0x44, 0x47) AM_READWRITE16(shadow_config_r, shadow_config_w, 0x0000ffff)
AM_RANGE(0x58, 0x5b) AM_READWRITE8(smram_ctrl_r, smram_ctrl_w, 0x00ff0000)
@ -41,7 +41,7 @@ DEVICE_ADDRESS_MAP_START(internal_io_map, 32, sis85c496_host_device)
AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8("pic8259_slave", pic8259_device, read, write, 0xffffffff)
AM_RANGE(0x00c0, 0x00df) AM_READWRITE8(at_dma8237_2_r, at_dma8237_2_w, 0xffffffff);
AM_RANGE(0x00e0, 0x00ef) AM_NOP
AM_INHERIT_FROM(pci_host_device::io_configuration_access_map)
ADDRESS_MAP_END
@ -124,7 +124,7 @@ sis85c496_host_device::sis85c496_host_device(const machine_config &mconfig, cons
m_speaker(*this, "speaker"),
m_ds12885(*this, "rtc"),
m_pc_kbdc(*this, "pc_kbdc"),
m_at_spkrdata(0), m_pit_out2(0), m_dma_channel(0), m_cur_eop(false), m_dma_high_byte(0), m_at_speaker(0), m_refresh(false), m_channel_check(0), m_nmi_enabled(0)
m_at_spkrdata(0), m_pit_out2(0), m_dma_channel(0), m_cur_eop(false), m_dma_high_byte(0), m_at_speaker(0), m_refresh(false), m_channel_check(0), m_nmi_enabled(0)
{
}
@ -141,7 +141,7 @@ void sis85c496_host_device::set_ram_size(int _ram_size)
void sis85c496_host_device::device_start()
{
pci_host_device::device_start();
cpu = machine().device<cpu_device>(cpu_tag);
memory_space = &cpu->space(AS_PROGRAM);
io_space = &cpu->space(AS_IO);
@ -159,7 +159,7 @@ void sis85c496_host_device::device_start()
m_isa_decoder = 0xff;
m_shadctrl = 0;
m_smramctrl = 0;
ram.resize(ram_size/4);
}
@ -171,14 +171,14 @@ void sis85c496_host_device::reset_all_mappings()
void sis85c496_host_device::device_reset()
{
pci_host_device::device_reset();
m_at_spkrdata = 0;
m_pit_out2 = 1;
m_dma_channel = -1;
m_cur_eop = false;
m_nmi_enabled = 0;
m_refresh = false;
m_bios_config = 0x78;
m_dram_config = 0;
m_isa_decoder = 0xff;
@ -194,7 +194,7 @@ void sis85c496_host_device::map_bios(address_space *memory_space, uint32_t start
void sis85c496_host_device::map_shadowram(address_space *memory_space, offs_t addrstart, offs_t addrend, void *baseptr)
{
if (m_shadctrl & 0x100) // write protected?
if (m_shadctrl & 0x100) // write protected?
{
memory_space->install_rom(addrstart, addrend, baseptr);
}
@ -212,7 +212,7 @@ void sis85c496_host_device::map_extra(uint64_t memory_window_start, uint64_t mem
// is SMRAM at e0000? overrides shadow if so
if ((m_smramctrl & 0x16) == 0x16)
{
{
if (m_smramctrl & 0x08)
{
memory_space->install_ram(0x000e0000, 0x000effff, &ram[0x000b0000/4]);
@ -223,7 +223,7 @@ void sis85c496_host_device::map_extra(uint64_t memory_window_start, uint64_t mem
memory_space->install_ram(0x000e0000, 0x000effff, &ram[0x000a0000/4]);
logerror("Sis496: SMRAM at Exxxx, phys Axxxx\n");
}
// map the high BIOS at FFFExxxx if enabled
if (m_bios_config & 0x40)
{
@ -231,7 +231,7 @@ void sis85c496_host_device::map_extra(uint64_t memory_window_start, uint64_t mem
}
}
else
{
{
// does shadow RAM actually require this to be set? can't tell w/Megatouch BIOS.
if (m_bios_config & 0x40)
{
@ -242,16 +242,16 @@ void sis85c496_host_device::map_extra(uint64_t memory_window_start, uint64_t mem
{
map_bios(memory_space, 0x000e0000, 0x000effff);
}
else // at least one 32K block has shadow memory
else // at least one 32K block has shadow memory
{
if (m_shadctrl & 0x20)
{
logerror("SiS496: shadow RAM at e8000\n");
map_shadowram(memory_space, 0x000e8000, 0x000effff, &ram[0x000e8000/4]);
}
if (m_shadctrl & 0x10)
{
{
logerror("SiS496: shadow RAM at e0000\n");
map_shadowram(memory_space, 0x000e0000, 0x000e7fff, &ram[0x000e0000/4]);
}
@ -261,20 +261,20 @@ void sis85c496_host_device::map_extra(uint64_t memory_window_start, uint64_t mem
if (m_bios_config & 0x20)
{
map_bios(memory_space, 0xffff0000, 0xffffffff);
if ((m_shadctrl & 0xc0) == 0)
{
map_bios(memory_space, 0x000f0000, 0x000fffff);
logerror("SiS496: BIOS at Fxxxx\n");
}
else // at least one 32K block has shadow memory
else // at least one 32K block has shadow memory
{
if (m_shadctrl & 0x80)
{
logerror("SiS496: shadow RAM at f8000\n");
map_shadowram(memory_space, 0x000f8000, 0x000fffff, &ram[0x000f8000/4]);
}
if (m_shadctrl & 0x40)
{
logerror("SiS496: shadow RAM at f0000\n");
@ -282,12 +282,12 @@ void sis85c496_host_device::map_extra(uint64_t memory_window_start, uint64_t mem
}
}
}
if (m_shadctrl & 0x08)
{
logerror("SiS496: shadow RAM at d8000\n");
memory_space->install_ram(0x000d8000, 0x000dffff, &ram[0x000d8000/4]);
}
}
if (m_shadctrl & 0x04)
{
logerror("SiS496: shadow RAM at d0000\n");
@ -297,13 +297,13 @@ void sis85c496_host_device::map_extra(uint64_t memory_window_start, uint64_t mem
{
logerror("SiS496: shadow RAM at c8000\n");
memory_space->install_ram(0x000c8000, 0x000cffff, &ram[0x000c8000/4]);
}
}
if (m_shadctrl & 0x01)
{
logerror("SiS496: shadow RAM at d8000\n");
memory_space->install_ram(0x000c0000, 0x000c7fff, &ram[0x000c0000/4]);
}
// is SMRAM enabled at 6xxxx?
if ((m_smramctrl & 0x12) == 0x02)
{
@ -315,7 +315,7 @@ void sis85c496_host_device::map_extra(uint64_t memory_window_start, uint64_t mem
logerror("SiS496: ISA base 640K enabled\n");
memory_space->install_ram(0x00000000, 0x0009ffff, &ram[0x00000000/4]);
}
// 32 megs of RAM (todo: don't hardcode)
memory_space->install_ram(0x00100000, 0x01ffffff, &ram[0x00100000/4]);
}
@ -611,4 +611,4 @@ config_write 00:05.0:80 00000000 @ 000000ff
*/
*/

6
src/devices/machine/sis85c496.h
View File

@ -51,7 +51,7 @@ public:
DECLARE_WRITE16_MEMBER(shadow_config_w) { COMBINE_DATA(&m_shadctrl); logerror("SiS496: %04x to shadow control\n", m_shadctrl); remap_cb(); }
DECLARE_READ8_MEMBER (smram_ctrl_r) { return m_smramctrl; }
DECLARE_WRITE8_MEMBER(smram_ctrl_w) { m_smramctrl = data; remap_cb(); }
virtual void reset_all_mappings() override;
virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
@ -59,7 +59,7 @@ public:
virtual DECLARE_ADDRESS_MAP(config_map, 32) override;
DECLARE_ADDRESS_MAP(internal_io_map, 32);
// southbridge
DECLARE_READ8_MEMBER(at_page8_r);
DECLARE_WRITE8_MEMBER(at_page8_w);
@ -111,7 +111,7 @@ public:
protected:
virtual void device_start() override;
virtual void device_reset() override;
void map_bios(address_space *memory_space, uint32_t start, uint32_t end);
void map_shadowram(address_space *memory_space, offs_t addrstart, offs_t addrend, void *baseptr);

14
src/devices/machine/ym3802.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Barry Rodewald
/*
* ym3802.c - Yamaha MCS MIDI Communication and Service Controller
*
*
* TODO:
* - Receive serial data
* - Transmit Idle detection
@ -32,7 +32,7 @@ ym3802_device::ym3802_device(const machine_config &mconfig, const char *tag, dev
, m_clkf_rate(614400)
{
}
void ym3802_device::device_start()
{
m_irq_handler.resolve_safe();
@ -145,7 +145,7 @@ void ym3802_device::reset_midi_timer()
{
uint64_t rate;
uint8_t divisor = m_reg[REG_TRR] & 0x1f;
if(!(divisor & 0x10))
{
if(divisor & 0x08)
@ -160,7 +160,7 @@ void ym3802_device::reset_midi_timer()
else
rate = m_clkf_rate / (64 << (divisor & 0x07));
}
if(rate != m_prev_rate)
m_midi_timer->adjust(attotime::from_hz(rate),0,attotime::from_hz(rate));
m_prev_rate = rate;
@ -172,7 +172,7 @@ void ym3802_device::set_comms_mode()
uint8_t data_bits = (m_reg[REG_TMR] & 0x20) ? 7 : 8;
parity_t parity;
stop_bits_t stop_bits = (m_reg[REG_TMR] & 0x02) ? STOP_BITS_2 : STOP_BITS_1;
if(!(m_reg[REG_TMR] & 0x10)) // parity enable
parity = PARITY_NONE;
else
@ -183,7 +183,7 @@ void ym3802_device::set_comms_mode()
parity = PARITY_EVEN;
// TODO: 4-bit parity
}
set_data_frame(1, data_bits, parity, stop_bits);
logerror("MIDI comms set to 1 start bit, %i data bits, %s, parity = %i\n",data_bits, (stop_bits == STOP_BITS_2) ? "2 stop bits" : "1 stop bit", parity);
}
@ -261,7 +261,7 @@ WRITE8_MEMBER(ym3802_device::write)
if((data & 0x07) == 2)
{
uint64_t rate = (m_reg[REG_CCR] & 0x02) ? m_clkm_rate / 4 : m_clkm_rate / 8;
// start message to click counter
m_midi_counter_timer->adjust(attotime::from_hz(rate),0,attotime::from_hz(rate));
}

36
src/devices/machine/ym3802.h
View File

@ -27,7 +27,7 @@
#define MCFG_YM3802_TXD_HANDLER(_devcb) \
devcb = &ym3802_device::set_txd_handler(*device, DEVCB_##_devcb);
class ym3802_device : public device_t, public device_serial_interface
{
public:
@ -40,7 +40,7 @@ public:
DECLARE_READ8_MEMBER(read);
DECLARE_WRITE8_MEMBER(write);
uint8_t vector() { return m_vector; }
protected:
@ -55,57 +55,57 @@ private:
REG_RGR, // Register Group / System Control
REG_ISR, // Interrupt Service (read only)
REG_ICR, // Interrupt Clear (write only)
REG_IOR, // Interrupt Vector Offset Request
REG_IMR, // Interrupt Mode Control
REG_IER, // Interrupt Enable Request
REG_UNUSED1,
REG_DMR = 14, // Real Time Message Control
REG_DCR, // Real Time Message Request
REG_DSR, // FIFO IRx Data
REG_DNR, // FIFO IRx Control
REG_RRR = 24, // Rx Rate
REG_RRR = 24, // Rx Rate
REG_RMR, // Rx Mode
REG_AMR, // Address Hunter Maker
REG_ADR, // Address Hunter Device
REG_RSR = 34, // FIFO Rx Buffer Status
REG_RCR, // FIFO Rx Buffer Control
REG_RDR, // FIFO Rx Data
REG_UNUSED2,
REG_TRR = 44, // Tx Rate
REG_TMR, // Tx Mode
REG_UNUSED3,
REG_UNUSED4,
REG_TSR = 54, // FIFO Tx Status
REG_TCR, // FIFO Tx Control
REG_TDR, // FIFO Tx Data
REG_UNUSED5,
REG_FSR = 64, // FSK status
REG_FCR, // FSK control
REG_CCR, // Click Counter Control
REG_CDR, // Click Counter Data (7-bit)
REG_SRR = 74, // Recording Counter current value
REG_SCR, // Sequencer Control
REG_SPR_LOW, // Playback Counter (low 8-bits)
REG_SPR_HIGH, // Playback Counter (high 7-bits)
REG_GTR_LOW = 84, // General Timer (low 8-bits)
REG_GTR_HIGH, // General Timer (high 6-bits)
REG_MTR_LOW, // MIDI Clock Timer (low 8-bits)
REG_MTR_HIGH, // MIDI Clock Timer (high 6-bits)
REG_EDR = 94, // External I/O Direction
REG_EOR, // External I/O Output Data
REG_EIR, // External I/O Input Data
REG_UNUSED7,
REG_MAX = 100
};
@ -136,14 +136,14 @@ private:
void set_comms_mode();
void set_irq(uint8_t irq);
void reset_irq(uint8_t irq);
devcb_write_line m_irq_handler;
devcb_write_line m_txd_handler;
devcb_read_line m_rxd_handler;
emu_timer* m_clock_timer;
emu_timer* m_midi_timer;
emu_timer* m_midi_counter_timer;
std::vector<uint8_t> m_reg;
uint8_t m_wdr;
uint64_t m_prev_rate;
@ -155,13 +155,13 @@ private:
uint8_t m_click_counter;
uint8_t m_click_counter_base;
uint8_t m_vector;
std::queue<uint8_t> m_tx_fifo;
std::queue<uint8_t> m_rx_fifo;
std::queue<uint8_t> m_itx_fifo;
std::queue<uint8_t> m_irx_fifo;
bool m_tx_busy;
uint64_t m_clkm_rate;
uint64_t m_clkf_rate;
};

4
src/emu/debug/debugcpu.cpp
View File

@ -192,7 +192,7 @@ void debugger_cpu::source_script(const char *file)
// close any existing source file
m_source_file.reset();
// open a new one if requested
// open a new one if requested
if (file != nullptr)
{
auto source_file = std::make_unique<std::ifstream>(file, std::ifstream::in);
@ -875,7 +875,7 @@ void debugger_cpu::process_source_file()
// loop until the file is exhausted or until we are executing again
while (m_execution_state == EXECUTION_STATE_STOPPED
&& m_source_file
&& m_source_file
&& std::getline(*m_source_file, buf))
{
// strip out comments (text after '//')

2
src/frontend/mame/ui/viewgfx.cpp
View File

@ -205,7 +205,7 @@ static void ui_gfx_count_devices(running_machine &machine, ui_gfx_state &state)
state.gfxdev[state.gfxset.devcount].palette[slot] = state.palette.interface;
state.gfxdev[state.gfxset.devcount].color_count[slot] = state.palette.interface->entries() / gfx->granularity();
if (!state.gfxdev[state.gfxset.devcount].color_count[slot])
state.gfxdev[state.gfxset.devcount].color_count[slot] = 1;
state.gfxdev[state.gfxset.devcount].color_count[slot] = 1;
}
}
if (++state.gfxset.devcount == MAX_GFX_DECODERS)

16
src/lib/formats/sdf_dsk.cpp
View File

@ -6,7 +6,7 @@
SDF disk images. Format created by Darren Atkinson for use with
his CoCoSDC floppy disk emulator.
http://cocosdc.blogspot.com/p/sd-card-socket-sd-card-socket-is-push.html
*********************************************************************/
@ -47,7 +47,7 @@ int sdf_format::identify(io_generic *io, uint32_t form_factor)
{
return 0;
}
io_generic_read(io, header, 0, HEADER_SIZE);
int tracks = header[4];
@ -64,7 +64,7 @@ int sdf_format::identify(io_generic *io, uint32_t form_factor)
{
return 0;
}
if (size == HEADER_SIZE + heads * tracks * TOTAL_TRACK_SIZE)
{
return 100;
@ -102,14 +102,14 @@ bool sdf_format::load(io_generic *io, uint32_t form_factor, floppy_image *image)
int idam_location[SECTOR_SLOT_COUNT+1];
int dam_location[SECTOR_SLOT_COUNT+1];
raw_track_data.clear();
// Read track
io_generic_read(io, &track_data[0], HEADER_SIZE + ( heads * track + head ) * TOTAL_TRACK_SIZE, TOTAL_TRACK_SIZE);
int sector_count = track_data[0];
if (sector_count > SECTOR_SLOT_COUNT) return false;
// Transfer IDAM and DAM locations to table
for (int i = 0; i < SECTOR_SLOT_COUNT+1; i++)
{
@ -117,7 +117,7 @@ bool sdf_format::load(io_generic *io, uint32_t form_factor, floppy_image *image)
{
idam_location[i] = ((track_data[ 8 * (i+1) + 1] << 8 | track_data[ 8 * (i+1)]) & 0x3FFF) - 4;
dam_location[i] = ((track_data[ 8 * (i+1) + 1 + 2] << 8 | track_data[ 8 * (i+1) + 2]) & 0x3FFF) - 4;
if (idam_location[i] > TOTAL_TRACK_SIZE) return false;
if (dam_location[i] > TOTAL_TRACK_SIZE) return false;
}

24
src/mame/drivers/40love.cpp
View File

@ -846,7 +846,7 @@ static MACHINE_CONFIG_START( undoukai )
MCFG_CPU_PERIODIC_INT_DRIVER(fortyl_state, irq0_line_hold, 2*60) /* source/number of IRQs is unknown */
MCFG_DEVICE_ADD("bmcu", TAITO68705_MCU, 18432000/6)
MCFG_QUANTUM_TIME(attotime::from_hz(6000))
MCFG_MACHINE_START_OVERRIDE(fortyl_state,40love)
MCFG_MACHINE_RESET_OVERRIDE(fortyl_state,40love) /* init machine */
@ -936,10 +936,10 @@ ROM_END
ROM_START( 40lovej )
ROM_REGION( 0x14000, "maincpu", 0 ) /* Z80 main CPU */
ROM_LOAD( "a30_01.70", 0x000000, 0x004000, CRC(1b89829e) SHA1(d875a4e3586fd9fb2e354e4353c9144ad68ce620) )
ROM_LOAD( "a30_02.71", 0x004000, 0x004000, CRC(1468e71e) SHA1(e251ddf42ab51e9c391c213f54b709b71a3f1519) )
ROM_LOAD( "a30_01.70", 0x000000, 0x004000, CRC(1b89829e) SHA1(d875a4e3586fd9fb2e354e4353c9144ad68ce620) )
ROM_LOAD( "a30_02.71", 0x004000, 0x004000, CRC(1468e71e) SHA1(e251ddf42ab51e9c391c213f54b709b71a3f1519) )
ROM_LOAD( "a30_03.72", 0x010000, 0x004000, CRC(dbc0049d) SHA1(1fca22ca0794564bbd1f946afb644fef0342acca) )
ROM_REGION( 0x10000, "audiocpu", ROMREGION_ERASEFF ) /* Z80 sound CPU */
// not in the provided set, identical?
ROM_LOAD( "a30-08.u08", 0x0000, 0x2000, BAD_DUMP CRC(2fc42ee1) SHA1(b56e5f9acbcdc476252e188f41ad7249dba6f8e1) )
@ -954,20 +954,20 @@ ROM_START( 40lovej )
ROM_LOAD( "a30-14" , 0x0000, 0x0800, BAD_DUMP CRC(c4690279) SHA1(60bc77e03b9be434bb97a374a2fedeb8d049a660) )
// ROM_LOAD( "a30_14", 0x000000, 0x000800, BAD_DUMP CRC(a4f770ce) SHA1(868e98528e8824e7329e9a298603e456bbc1f1f0) )
ROM_REGION( 0x8000, "gfx1", 0 )
ROM_LOAD( "a30_04.18", 0x000000, 0x004000, CRC(529a7489) SHA1(cf3fa83f16e2e62c1a4aa74b00080f1e167865a6) )
ROM_LOAD( "a30_05.19", 0x004000, 0x004000, CRC(7017e5f1) SHA1(fc614fd41109a9a6236ed4a331eda74e5d49b946) )
ROM_REGION( 0x8000, "gfx2", 0 )
ROM_LOAD( "a30_06.59", 0x000000, 0x004000, CRC(f744ea8e) SHA1(0bf6deabfac47237347af810332bc3716e3a26f0) )
ROM_LOAD( "a30_07.60", 0x004000, 0x004000, CRC(b2af1359) SHA1(6a21e38cfb65d52b7e1209101f0dd497f9a71f46) )
ROM_REGION( 0x8000, "gfx1", 0 )
ROM_LOAD( "a30_04.18", 0x000000, 0x004000, CRC(529a7489) SHA1(cf3fa83f16e2e62c1a4aa74b00080f1e167865a6) )
ROM_LOAD( "a30_05.19", 0x004000, 0x004000, CRC(7017e5f1) SHA1(fc614fd41109a9a6236ed4a331eda74e5d49b946) )
ROM_REGION( 0x8000, "gfx2", 0 )
ROM_LOAD( "a30_06.59", 0x000000, 0x004000, CRC(f744ea8e) SHA1(0bf6deabfac47237347af810332bc3716e3a26f0) )
ROM_LOAD( "a30_07.60", 0x004000, 0x004000, CRC(b2af1359) SHA1(6a21e38cfb65d52b7e1209101f0dd497f9a71f46) )
ROM_REGION( 0x1000, "proms", 0 )
// not provided
ROM_LOAD( "a30-15.u03", 0x0000, 0x0400, BAD_DUMP CRC(55e38cc7) SHA1(823a6d7f29eadf5d12702d782d4297b0d4c65a0e) ) /* red */
ROM_LOAD( "a30-16.u01", 0x0400, 0x0400, BAD_DUMP CRC(13997e20) SHA1(9fae1cf633409a88263dc66a17b1c2eeccd05f4f) ) /* green */
ROM_LOAD( "a30-17.u02", 0x0800, 0x0400, BAD_DUMP CRC(5031f2f3) SHA1(1836d82fdc9f39cb318a791af2a935c27baabfd7) ) /* blue */
ROM_LOAD( "a30-18.u13", 0x0c00, 0x0400, BAD_DUMP CRC(78697c0f) SHA1(31382ed4c0d44024f7f57a9de6407527f4d5b0d1) ) /* ??? */
ROM_LOAD( "a30-18.u13", 0x0c00, 0x0400, BAD_DUMP CRC(78697c0f) SHA1(31382ed4c0d44024f7f57a9de6407527f4d5b0d1) ) /* ??? */
ROM_END
ROM_START( fieldday )

2
src/mame/drivers/accomm.cpp
View File

@ -672,7 +672,7 @@ static INPUT_PORTS_START( accomm )
PORT_START("LINE2.1")
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L')
PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR(0xa3)
PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR(0xa3) // £
PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')
PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K')

4
src/mame/drivers/coco12.cpp
View File

@ -247,11 +247,11 @@ SLOT_INTERFACE_START( coco_cart )
SLOT_INTERFACE("rs232", COCO_RS232)
SLOT_INTERFACE("dcmodem", COCO_DCMODEM)
SLOT_INTERFACE("orch90", COCO_ORCH90)
SLOT_INTERFACE("ssc", COCO_SSC) MCFG_SLOT_OPTION_CLOCK("ssc", DERIVED_CLOCK(1, 1))
SLOT_INTERFACE("ssc", COCO_SSC) MCFG_SLOT_OPTION_CLOCK("ssc", DERIVED_CLOCK(1, 1))
SLOT_INTERFACE("games_master", COCO_PAK_GMC)
SLOT_INTERFACE("banked_16k", COCO_PAK_BANKED)
SLOT_INTERFACE("pak", COCO_PAK)
SLOT_INTERFACE("multi", COCO_MULTIPAK) MCFG_SLOT_OPTION_CLOCK("multi", DERIVED_CLOCK(1, 1))
SLOT_INTERFACE("multi", COCO_MULTIPAK) MCFG_SLOT_OPTION_CLOCK("multi", DERIVED_CLOCK(1, 1))
SLOT_INTERFACE_END
//-------------------------------------------------

22
src/mame/drivers/cop01.cpp
View File

@ -177,7 +177,7 @@ ADDRESS_MAP_END
* 0x33: - address 1 (source?)
* 0x34: /
* 0x35: - address 2 (adjust value in rom?)
* 0x36: /
* 0x36: /
* 0x37: R reused for ym3526 register set, read protection rom (same as amatelas)
*
* 0x40: counter set, always 1?
@ -194,25 +194,25 @@ READ8_MEMBER(cop01_state::prot_data_r)
{
if(m_prot_command == 0x41)
return (m_audiocpu->total_cycles() / 0x34) & 1; // wrong
if(m_prot_command == 0x37)
{
{
uint16_t prot_offset = (m_prot_reg[1]<<8)|(m_prot_reg[2]);
uint8_t *prot_rom = memregion("prot_data")->base();
// 0x37c are BGMs while 0x34e are SFXs?
// 0x37c are BGMs while 0x34e are SFXs?
uint8_t prot_adj = 0x82; //0xbd
//printf("%02x",(prot_rom[prot_offset] - 0x44) & 0xff);
return prot_rom[prot_offset & 0x1fff] - prot_adj; // minus value correct?
}
if(m_prot_command == 0x92) // affects coin SFX playback
return 1;
if(m_prot_command == 0x94)
return 0;
return 0;
}
@ -224,9 +224,9 @@ WRITE8_MEMBER(cop01_state::prot_address_w)
WRITE8_MEMBER(cop01_state::prot_data_w)
{
if( m_prot_command>=0x32 && m_prot_command<=0x37 )
{
{
m_prot_reg[m_prot_command-0x32] = data;
#if 0
if(m_prot_command == 0x32)
{

24
src/mame/drivers/csplayh5.cpp
View File

@ -18,13 +18,13 @@
http://www.pioneerelectronics.com/ephox/StaticFiles/Manuals/Business/Pio%20V5000-RS232%20-%20CPM.pdf
After returning a correct status code, tmp68301 sends "FSDVD04.MPG00001<CR>" to serial, probably tries
to playback the file ...
- h8 board components:
H8/3002
MN7100 8-bit channel data acquisition system
Fujitsu MD0208
Heatsinked chip (TBD)
IDE and RS232c ports
xtal 27 MHz
- h8 board components:
H8/3002
MN7100 8-bit channel data acquisition system
Fujitsu MD0208
Heatsinked chip (TBD)
IDE and RS232c ports
xtal 27 MHz
***********************************************************************************************************/
@ -85,7 +85,7 @@ public:
DECLARE_READ16_MEMBER(test_r);
DECLARE_WRITE_LINE_MEMBER(ide_irq);
#endif
DECLARE_DRIVER_INIT(mjmania);
DECLARE_DRIVER_INIT(csplayh5);
DECLARE_DRIVER_INIT(fuudol);
@ -158,8 +158,8 @@ static ADDRESS_MAP_START( csplayh5_sub_map, AS_PROGRAM, 16, csplayh5_state )
AM_RANGE(0x000000, 0x01ffff) AM_ROM
AM_RANGE(0x02000a, 0x02000b) AM_READ(test_r)
// AM_RANGE(0x020008, 0x02000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0, write_cs0)
// AM_RANGE(0x020008, 0x02000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0, write_cs0)
AM_RANGE(0x040018, 0x040019) AM_READ(test_r)
AM_RANGE(0x040028, 0x04002f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0, write_cs0) // correct?
AM_RANGE(0x040036, 0x040037) AM_READ(test_r)
@ -426,7 +426,7 @@ static MACHINE_CONFIG_START( csplayh5 )
MCFG_CPU_ADD("subcpu", H83002, DVD_CLOCK/2) /* unknown divider */
MCFG_CPU_PROGRAM_MAP(csplayh5_sub_map)
MCFG_CPU_IO_MAP(csplayh5_sub_io_map)
MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", nullptr, true) // dvd
MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(csplayh5_state, ide_irq))
#endif
@ -477,7 +477,7 @@ void csplayh5_state::general_init(int patchaddress, int patchvalue)
/* patch DVD comms check */
MAINROM[patchaddress] = patchvalue;
#endif
uint8_t *SNDROM = m_region_audiocpu->base();
/* initialize sound rom bank */

68
src/mame/drivers/dbox.cpp
View File

@ -33,21 +33,21 @@
* History of Nokia Multimedia Division
*-------------------------------------
* Luxor AB was a swedish home electronics and computer manufacturer located in Motala from 1923 and aquired
* by Nokia 1985. Luxor designed among other things TV setsm Radios and the famous ABC-80. The Nokia Multimedia
* Division was formed in Linköping as a result of the Luxor aquesition. Their main design was a satellite
* by Nokia 1985. Luxor designed among other things TV setsm Radios and the famous ABC-80. The Nokia Multimedia
* Division was formed in Linköping as a result of the Luxor aquesition. Their main design was a satellite
* receiver, the first satellite in Europee was launched in 1988 and market was growing fast however it took
* a long time, almost 10 years before the breakthrough came for Nokia, a deal with the Kirsch Gruppe was struck and
* in 1996 the 68340 based Dbox-1 was released in Germany. The original design was expensive, so soon a cost reduced
* version based on PPC, the Dbox-2, was released. The boxes sold in millions but the margins were negative or very
* a long time, almost 10 years before the breakthrough came for Nokia, a deal with the Kirsch Gruppe was struck and
* in 1996 the 68340 based Dbox-1 was released in Germany. The original design was expensive, so soon a cost reduced
* version based on PPC, the Dbox-2, was released. The boxes sold in millions but the margins were negative or very
* low at best and the Kirsch Gruppe went bankrupt in 2002 and Nokia decided to shutdown the facility in Linköping.
*
* The heavily subsidiced Dbox was very popular in Holland since Kirsch Gruppe didn't lock use to themselfs. This was
* corrected in a forced firmware upgrade leaving the "customers" in Holland without a working box. Pretty soon a
* shareware software developed by Uli Hermann appeared called DVB98 and later DVB2000 reenabling the boxes in Holland
* shareware software developed by Uli Hermann appeared called DVB98 and later DVB2000 reenabling the boxes in Holland
* and blocking upgrades. Uli's software was by many considered better than the original software.
*
* Misc links about Nokia Multimedia Division and this board:
* http://www.siliconinvestor.com/readmsg.aspx?msgid=5097482
* http://www.siliconinvestor.com/readmsg.aspx?msgid=5097482
* http://www.telecompaper.com/news/beta-research-publishes-dbox-specifications--163443
* https://de.wikipedia.org/wiki/D-box
* http://dvb2000.org/dvb2000/
@ -57,7 +57,7 @@
* - Serial port on the back runs at 19200 at issues modem commands when attached to terminal
* - It is possible to attach a BDM emulator and retrieve the ROM through it.
* - It is possible to flash new firmware by adding jumper XP06 (under the modem board)
* - The bootstrap is based on RTXC 3.2g RTOS
* - The bootstrap is based on RTXC 3.2g RTOS
* - The bootstrap jumps to firmware from 0xb82 to RAM at 0x800000
*
* Identified chips/devices
@ -74,10 +74,10 @@
* LSI L2A0371 Tuner
* 2 x 29F800-90 (2Mb FLASH)
* 2 x 42260-60 (1Mb DRAM)
* Siemens SDA5708 dot matrix display, SPI like connection
* Siemens SDA5708 dot matrix display, SPI like connection
* - http://arduinotehniq.blogspot.se/2015/07/sda5708-display-8-character-7x5-dot.html
* - charset stored at 0x808404 to 0x808780, 7 bytes per character
*
*
*
* Address Map
* --------------------------------------------------------------------------
@ -88,13 +88,13 @@
* 0x00FFF700-0x00FFF721 Serial devices offset to SIM40
* 0x00FFF600-0x00FFF67F Timers offset to SIM40
* 0x00FFF000-0x00FFF07F SIM40 programmed base adress (MCR)
* 0x00700000-0x008fffff RAM
* 0x00000000-0x0001ffff bootstrap
* 0x00700000-0x008fffff RAM
* 0x00000000-0x0001ffff bootstrap
* --------------------------------------------------------------------------
*
* Init sequence
* -------------
* MCR : 0x6301 Timer/wd disabled, show cycles, ext arbit,
* MCR : 0x6301 Timer/wd disabled, show cycles, ext arbit,
* user access to SIM40, IARB = 1
* MBAR : 0x00FFF101 SIM40 base = 0x00fff000
* VBR : 0x008096F8 VBR - Vector Base Register
@ -127,16 +127,16 @@
* Serial port setup
* ------------------
* --- PC < 0x1FFFF so bootstrap code
* SIM40 + 0x0700: 0x00 Serial Module - MCR High Byte
* SIM40 + 0x0700: 0x00 Serial Module - MCR High Byte
* - The serial module is enabled
* - ignore FREEZE
* - The crystal clock is the clear-to-send input capture clock for both channels
* SIM40 + 0x071F: 0xFF Serial Module - OUTPUT PORT (OP)4 BIT RESET - all cleared
* SIM40 + 0x0700: 0x00 Serial Module - MCR High Byte
* SIM40 + 0x0700: 0x00 Serial Module - MCR High Byte
* - The serial module is enabled
* - ignore FREEZE
* - The crystal clock is the clear-to-send input capture clock for both channels
* SIM40 + 0x0701: 0x8A Serial Module - MCR Low Byte
* SIM40 + 0x0701: 0x8A Serial Module - MCR Low Byte
* - The serial control regosters are only accessable from supervisor mode
* - IARB = 0x0A - serial module has priority level 10d
* SIM40 + 0x0704: 0x01 Serial Module - ILR Interrupt Level
@ -165,7 +165,7 @@
* - Enable Receiver
* - Check for charcters in channel A
* SIM40 + 0x0711: btst #0 Serial Module - SRA Status Register A
* --- if there is
* --- if there is
* store all characters in buffer at (A6) 0x88FFD0
* --- setup Channel B (See details as for channel A above)
* SIM40 + 0x071A: 0x20 Serial Module - CRB Command Register B
@ -176,16 +176,16 @@
* SIM40 + 0x071A: 0x41 Serial Module - CRB Command Register B
* - Check for characters in channel B
* SIM40 + 0x0719: btst #0 Serial Module - SRB Status Register B
* --- if there is
* --- if there is
* store all characters in buffer at (A6) 0x88FFD0
* ---
* ---
* - Check bit 0 set on Input Port
* SIM40 + 0x071D: btst #0 Input Port - IP
* --- if bit 0 is set
* 0x00801208: 0x80
* SIM40 + 0x071A: 0x81 Serial Module - CRB Command Register B
* ---
* SIM40 + 0x0720: 0x41 Serial Module - MR2A Mode register 2A
* ---
* SIM40 + 0x0720: 0x41 Serial Module - MR2A Mode register 2A
* SIM40 + 0x071D: 0x03 OPCR Output Port Control Register
* SIM40 + 0x0715: 0x03 IER Interrupt Enable Register
*
@ -205,16 +205,16 @@
* Serial port setup
* ------------------
* --- PC < 0x1FFFF so bootstrap code
* SIM40 + 0x0700: 0x00 Serial Module - MCR High Byte
* SIM40 + 0x0700: 0x00 Serial Module - MCR High Byte
* - The serial module is enabled
* - ignore FREEZE
* - The crystal clock is the clear-to-send input capture clock for both channels
* SIM40 + 0x071F: 0xFF Serial Module - OUTPUT PORT (OP)4 BIT RESET - all cleared
* SIM40 + 0x0700: 0x00 Serial Module - MCR High Byte
* SIM40 + 0x0700: 0x00 Serial Module - MCR High Byte
* - The serial module is enabled
* - ignore FREEZE
* - The crystal clock is the clear-to-send input capture clock for both channels
* SIM40 + 0x0701: 0x8A Serial Module - MCR Low Byte
* SIM40 + 0x0701: 0x8A Serial Module - MCR Low Byte
* - The serial control regosters are only accessable from supervisor mode
* - IARB = 0x0A - serial module has priority level 10d
* SIM40 + 0x0704: 0x01 Serial Module - ILR Interrupt Level
@ -243,7 +243,7 @@
* - Enable Receiver
* - Check for charcters in channel A
* SIM40 + 0x0711: btst #0 Serial Module - SRA Status Register A
* --- if there is
* --- if there is
* store all characters in buffer at (A6) 0x88FFD0
* --- setup Channel B (See details as for channel A above)
* SIM40 + 0x071A: 0x20 Serial Module - CRB Command Register B
@ -254,16 +254,16 @@
* SIM40 + 0x071A: 0x41 Serial Module - CRB Command Register B
* - Check for characters in channel B
* SIM40 + 0x0719: btst #0 Serial Module - SRB Status Register B
* --- if there is
* --- if there is
* store all characters in buffer at (A6) 0x88FFD0
* ---
* ---
* - Check bit 0 set on Input Port
* SIM40 + 0x071D: btst #0 Input Port - IP
* --- if bit 0 is set
* 0x00801208: 0x80
* SIM40 + 0x071A: 0x81 Serial Module - CRB Command Register B
* ---
* SIM40 + 0x0720: 0x41 Serial Module - MR2A Mode register 2A
* ---
* SIM40 + 0x0720: 0x41 Serial Module - MR2A Mode register 2A
* SIM40 + 0x071D: 0x03 OPCR Output Port Control Register
* SIM40 + 0x0715: 0x03 IER Interrupt Enable Register
*
@ -274,16 +274,16 @@
*
* Identified low level drivers in firmware
* ----------------------------------------
* 800420..80046C : Some PORT A serialisation routine for the
* 800420..80046C : Some PORT A serialisation routine for the
* Siemens SDA5708 dot matrix display
*
* Interrupt sources
* ----------------------------------------------------------
* Description Device Lvl IRQ
* /Board Vector
* /Board Vector
* ----------------------------------------------------------
* On board Sources
*
* On board Sources
*
* Off board Sources (other boards)
* ----------------------------------------------------------
*
@ -342,7 +342,7 @@ DRIVER_INIT_MEMBER(dbox_state, dbox)
ROM_START( dbox )
ROM_REGION(0x1000000, "maincpu", 0)
// ROM_LOAD16_WORD( "dvb2000.bin", 0x000000, 0x8b742, CRC(5b21c455) SHA1(1e7654c37dfa65d1b8ac2469cdda82f91b47b3c7) )
// ROM_LOAD16_WORD( "dvb2000.bin", 0x000000, 0x8b742, CRC(5b21c455) SHA1(1e7654c37dfa65d1b8ac2469cdda82f91b47b3c7) )
ROM_LOAD16_WORD( "nokboot.bin", 0x000000, 0x20000, CRC(0ff53e1f) SHA1(52002ee22c032775dac383d408c44abe9244724f) )
ROM_END

16
src/mame/drivers/dragon.cpp
View File

@ -38,14 +38,14 @@ ADDRESS_MAP_END
/* Dragon keyboard
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
PA6: Ent Clr Brk N/c N/c N/c N/c Shift
PA5: X Y Z Up Dwn Lft Rgt Space
PA4: P Q R S T U V W
PA3: H I J K L M N O
PA2: @ A B C D E F G
PA1: 8 9 : ; , - . /
PA0: 0 1 2 3 4 5 6 7
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
PA6: Ent Clr Brk N/c N/c N/c N/c Shift
PA5: X Y Z Up Dwn Lft Rgt Space
PA4: P Q R S T U V W
PA3: H I J K L M N O
PA2: @ A B C D E F G
PA1: 8 9 : ; , - . /
PA0: 0 1 2 3 4 5 6 7
*/
static INPUT_PORTS_START( dragon_keyboard )
PORT_START("row0")

6
src/mame/drivers/eva.cpp
View File

@ -48,7 +48,7 @@ public:
DECLARE_READ8_MEMBER(eva24_read_g);
DECLARE_WRITE8_MEMBER(eva24_write_g);
DECLARE_WRITE8_MEMBER(eva24_write_d);
u8 m_g;
// EVA-11
@ -124,9 +124,9 @@ READ8_MEMBER(eva_state::eva11_read_k)
{
// K84: TMS5100 CTL81(O30)
u8 ctl = BITSWAP8(m_tms5100->ctl_r(space, 0),7,6,5,4,3,0,1,2) & 0xc;
// TODO: sensors
return ctl;
}

2
src/mame/drivers/ez2d.cpp
View File

@ -110,7 +110,7 @@ ROM_START( ez2d2m )
ROM_REGION( 0x10000, "vbios", 0 ) // video card BIOS, not dumped but downloaded from internet
ROM_LOAD( "62090211.rom", 0x000000, 0x00b000, CRC(5669135b) SHA1(b704ce0d20b71e40563d12bcc45bd1240227be74) )
DISK_REGION( "ide:0:hdd:image" )
DISK_REGION( "ide:0:hdd:image" )
DISK_IMAGE( "ez2d2m", 0, SHA1(431f0bef3b81f83dad3818bca8994faa8ce9d5b7) )
ROM_END

6
src/mame/drivers/goupil.cpp
View File

@ -1,5 +1,5 @@
// license:BSD-3-Clause
// copyright-holders:Jean-François DEL NERO
// copyright-holders:Jean-François DEL NERO
/***************************************************************************
SMT Goupil G1 & G2 driver
@ -17,7 +17,7 @@
-> The internal G1 Basic is working (-> 6800 0xC3 illegal opcode emulation needed).
02/04/2016
Jean-François DEL NERO
Jean-François DEL NERO
****************************************************************************/
@ -598,7 +598,7 @@ static MACHINE_CONFIG_START( goupil_g2 )
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("2K") // visu24x80 2K ram
MCFG_SCREEN_ADD("screen" ,RASTER)
MCFG_SCREEN_REFRESH_RATE(50)
MCFG_SCREEN_NO_PALETTE

172
src/mame/drivers/gridcomp.cpp
View File

@ -2,63 +2,63 @@
// copyright-holders:Sergey Svishchev
/***************************************************************************
drivers/gridcomp.cpp
drivers/gridcomp.cpp
Driver file for GRiD Compass series
Driver file for GRiD Compass series
US patent 4,571,456 describes model 1101:
US patent 4,571,456 describes model 1101:
- 15 MHz XTAL, produces
- 5 MHz system clock for CPU, FPU, OSP
- 7.5 MHz pixel clock
- Intel 8086 - CPU
- Intel 8087 - FPU
- Intel 80130 - Operating System Processor, equivalent of:
- 8259 PIC
- 8254 PIT
- Texas Instruments TMS9914 GPIB controller
- Intel 7220 Bubble Memory Controller
- 7110 Magnetic Bubble Memory modules and support chips
- (unknown) - EAROM for machine ID
- (unknown) - Real-Time Clock
- (custom DMA logic)
- Intel 8741 - keyboard MCU
- Intel 8274 - UART
- Intel 8255 - modem interface
- 2x DAC0832LCN - DAC
- MK5089N - DTMF generator
- ...
- 15 MHz XTAL, produces
- 5 MHz system clock for CPU, FPU, OSP
- 7.5 MHz pixel clock
- Intel 8086 - CPU
- Intel 8087 - FPU
- Intel 80130 - Operating System Processor, equivalent of:
- 8259 PIC
- 8254 PIT
- Texas Instruments TMS9914 GPIB controller
- Intel 7220 Bubble Memory Controller
- 7110 Magnetic Bubble Memory modules and support chips
- (unknown) - EAROM for machine ID
- (unknown) - Real-Time Clock
- (custom DMA logic)
- Intel 8741 - keyboard MCU
- Intel 8274 - UART
- Intel 8255 - modem interface
- 2x DAC0832LCN - DAC
- MK5089N - DTMF generator
- ...
to do:
to do:
- confirm differences between models except screen size
- Compass 110x do not have GRiDROM slots.
- Compass II (112x, 113x) have 4 of them.
- keyboard: decode and add the rest of keycodes
- EAROM, RTC
- serial port, modem (incl. DTMF generator)
- TMS9914 chip driver (incl. DMA)
- GPIB storage devices (floppy, hard disk)
- confirm differences between models except screen size
- Compass 110x do not have GRiDROM slots.
- Compass II (112x, 113x) have 4 of them.
- keyboard: decode and add the rest of keycodes
- EAROM, RTC
- serial port, modem (incl. DTMF generator)
- TMS9914 chip driver (incl. DMA)
- GPIB storage devices (floppy, hard disk)
missing dumps:
missing dumps:
- BIOS from models other than 1139 (CCOS and MS-DOS variants)
- GRiDROM's
- keyboard MCU
- external floppy and hard disk (2101, 2102)
- BIOS from models other than 1139 (CCOS and MS-DOS variants)
- GRiDROM's
- keyboard MCU
- external floppy and hard disk (2101, 2102)
to boot CCOS 3.0.1:
- pad binary image (not .imd) to 384K
- attach it as -memcard
- use grid1129 with 'patched' ROM
- start with -debug and add breakpoints:
to boot CCOS 3.0.1:
- pad binary image (not .imd) to 384K
- attach it as -memcard
- use grid1129 with 'patched' ROM
- start with -debug and add breakpoints:
# bubble memory driver
bp ff27a,1,{ax=ax*2;go}
# boot loader
bp 20618,1,{temp0=214A8;do w@(temp0+7)=120;do w@(temp0+9)=121;go}
# CCOS kernel
bp 0661a,1,{temp0=0f964;do w@(temp0+7)=120;do w@(temp0+9)=121;go}
# bubble memory driver
bp ff27a,1,{ax=ax*2;go}
# boot loader
bp 20618,1,{temp0=214A8;do w@(temp0+7)=120;do w@(temp0+9)=121;go}
# CCOS kernel
bp 0661a,1,{temp0=0f964;do w@(temp0+7)=120;do w@(temp0+9)=121;go}
***************************************************************************/
@ -309,9 +309,9 @@ IRQ_CALLBACK_MEMBER(gridcomp_state::irq_callback)
static ADDRESS_MAP_START( grid1101_map, AS_PROGRAM, 16, gridcomp_state )
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0xdfe80, 0xdfe83) AM_DEVREADWRITE8("i7220", i7220_device, read, write, 0x00ff)
AM_RANGE(0xdfea0, 0xdfeaf) AM_UNMAP // ??
AM_RANGE(0xdfec0, 0xdfecf) AM_DEVREADWRITE8("modem", i8255_device, read, write, 0x00ff) // incl. DTMF generator
AM_RANGE(0xdff40, 0xdff5f) AM_NOP // ?? machine ID EAROM, RTC
AM_RANGE(0xdfea0, 0xdfeaf) AM_UNMAP // ??
AM_RANGE(0xdfec0, 0xdfecf) AM_DEVREADWRITE8("modem", i8255_device, read, write, 0x00ff) // incl. DTMF generator
AM_RANGE(0xdff40, 0xdff5f) AM_NOP // ?? machine ID EAROM, RTC
AM_RANGE(0xdff80, 0xdff8f) AM_READWRITE(grid_gpib_r, grid_gpib_w) // TMS9914
AM_RANGE(0xdffc0, 0xdffcf) AM_READWRITE(grid_keyb_r, grid_keyb_w) // Intel 8741 MCU
AM_RANGE(0xfc000, 0xfffff) AM_ROM AM_REGION("user1", 0)
@ -319,15 +319,15 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( grid1121_map, AS_PROGRAM, 16, gridcomp_state )
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x90000, 0x97fff) AM_UNMAP // ?? ROM slot
AM_RANGE(0x90000, 0x97fff) AM_UNMAP // ?? ROM slot
AM_RANGE(0x9ff00, 0x9ff0f) AM_UNMAP // AM_READ(grid_9ff0_r) // ?? ROM?
AM_RANGE(0xc0000, 0xcffff) AM_UNMAP // ?? ROM slot -- signature expected: 0x4554, 0x5048
AM_RANGE(0xdfe00, 0xdfe1f) AM_UNMAP // AM_DEVREADWRITE8("uart8274", i8274_new_device, ba_cd_r, ba_cd_w, 0x00ff)
AM_RANGE(0xdfe40, 0xdfe4f) AM_UNMAP // ?? diagnostic 8274
AM_RANGE(0xdfe40, 0xdfe4f) AM_UNMAP // ?? diagnostic 8274
AM_RANGE(0xdfe80, 0xdfe83) AM_DEVREADWRITE8("i7220", i7220_device, read, write, 0x00ff)
AM_RANGE(0xdfea0, 0xdfeaf) AM_UNMAP // ??
AM_RANGE(0xdfec0, 0xdfecf) AM_DEVREADWRITE8("modem", i8255_device, read, write, 0x00ff) // incl. DTMF generator
AM_RANGE(0xdff40, 0xdff5f) AM_NOP // ?? machine ID EAROM, RTC
AM_RANGE(0xdfea0, 0xdfeaf) AM_UNMAP // ??
AM_RANGE(0xdfec0, 0xdfecf) AM_DEVREADWRITE8("modem", i8255_device, read, write, 0x00ff) // incl. DTMF generator
AM_RANGE(0xdff40, 0xdff5f) AM_NOP // ?? machine ID EAROM, RTC
AM_RANGE(0xdff80, 0xdff8f) AM_READWRITE(grid_gpib_r, grid_gpib_w) // TMS9914
AM_RANGE(0xdffc0, 0xdffcf) AM_READWRITE(grid_keyb_r, grid_keyb_w) // Intel 8741 MCU
AM_RANGE(0xfc000, 0xfffff) AM_ROM AM_REGION("user1", 0)
@ -341,14 +341,14 @@ static INPUT_PORTS_START( gridcomp )
INPUT_PORTS_END
/*
* IRQ0 serial
* IRQ1 bubble
* IRQ2 modem
* IRQ3 system tick || vert sync
* IRQ4 keyboard
* IRQ5 gpib
* IRQ6 8087
* IRQ7 ring
* IRQ0 serial
* IRQ1 bubble
* IRQ2 modem
* IRQ3 system tick || vert sync
* IRQ4 keyboard
* IRQ5 gpib
* IRQ6 8087
* IRQ7 ring
*/
static MACHINE_CONFIG_START( grid1101 )
MCFG_CPU_ADD("maincpu", I8086, XTAL_15MHz / 3)
@ -467,12 +467,12 @@ ROM_START( grid1129 )
ROM_FILL(0x24,1,0x2)
ROM_FILL(0xbc,1,0x98)
ROM_FILL(0xbd,1,0x2)
ROM_FILL(0x14e,1,0xc1) //
ROM_FILL(0x14f,1,0x2) //
ROM_FILL(0x15a,1,0xc2) //
ROM_FILL(0x15b,1,0x2) //
ROM_FILL(0x17b,1,0x45) //
ROM_FILL(0x17c,1,0x3) //
ROM_FILL(0x14e,1,0xc1) //
ROM_FILL(0x14f,1,0x2) //
ROM_FILL(0x15a,1,0xc2) //
ROM_FILL(0x15b,1,0x2) //
ROM_FILL(0x17b,1,0x45) //
ROM_FILL(0x17c,1,0x3) //
ROM_FILL(0x28c,1,0x98)
ROM_FILL(0x28d,1,0x2)
ROM_FILL(0x28f,1,0x98)
@ -509,18 +509,18 @@ ROM_START( grid1129 )
ROM_FILL(0xe51,1,0x2)
ROM_FILL(0xfa6,1,0x98)
ROM_FILL(0xfa7,1,0x2)
ROM_FILL(0x15fe,1,0xce) //
ROM_FILL(0x15ff,1,0x2) //
ROM_FILL(0x1628,1,0xd0) //
ROM_FILL(0x1629,1,0x2) //
ROM_FILL(0x15fe,1,0xce) //
ROM_FILL(0x15ff,1,0x2) //
ROM_FILL(0x1628,1,0xd0) //
ROM_FILL(0x1629,1,0x2) //
ROM_FILL(0x1700,1,0x98)
ROM_FILL(0x1701,1,0x2)
ROM_FILL(0x1833,1,0xd6) //
ROM_FILL(0x1834,1,0x2) //
ROM_FILL(0x184a,1,0xd6) //
ROM_FILL(0x184b,1,0x2) //
ROM_FILL(0x1a2e,1,0xd6) //
ROM_FILL(0x1a2f,1,0x2) //
ROM_FILL(0x1833,1,0xd6) //
ROM_FILL(0x1834,1,0x2) //
ROM_FILL(0x184a,1,0xd6) //
ROM_FILL(0x184b,1,0x2) //
ROM_FILL(0x1a2e,1,0xd6) //
ROM_FILL(0x1a2f,1,0x2) //
ROM_FILL(0x19c2,1,0x98)
ROM_FILL(0x19c3,1,0x2)
ROM_FILL(0x1ee0,1,0x98)
@ -545,12 +545,12 @@ ROM_START( grid1129 )
ROM_FILL(0x295d,1,0x2)
ROM_FILL(0x2a5e,1,0x98)
ROM_FILL(0x2a5f,1,0x2)
ROM_FILL(0x315c,1,0xc9) //
ROM_FILL(0x315d,1,0x2) //
ROM_FILL(0x3160,1,0xce) //
ROM_FILL(0x3161,1,0x2) //
ROM_FILL(0x3164,1,0xcf) //
ROM_FILL(0x3165,1,0x2) //
ROM_FILL(0x315c,1,0xc9) //
ROM_FILL(0x315d,1,0x2) //
ROM_FILL(0x3160,1,0xce) //
ROM_FILL(0x3161,1,0x2) //
ROM_FILL(0x3164,1,0xcf) //
ROM_FILL(0x3165,1,0x2) //
ROM_END
ROM_START( grid1131 )

12
src/mame/drivers/hh_sm510.cpp
View File

@ -430,7 +430,7 @@ MACHINE_CONFIG_END
Konami Gradius
* PCB label BH004
* Sharp SM511 under epoxy (die label KMS73B, KMS774)
Known in Japan as Nemesis.
***************************************************************************/
@ -557,14 +557,14 @@ MACHINE_CONFIG_END
Nintendo Game & Watch: Mickey Mouse (model MC-25), Egg (model EG-26)
* Sharp SM5A label ?
MC-25 and EG-26 are the same game, it's assumed that the latter was for
regions where Nintendo wasn't able to license from Disney.
In 1984, Elektronika(USSR) released a clone, Nu, Pogodi! This was followed
by several other games that were the same under the hood, only differing
in graphics.
***************************************************************************/
class mc25_state : public hh_sm510_state
@ -838,7 +838,7 @@ MACHINE_CONFIG_END
Nintendo Game & Watch: Donkey Kong Jr. (model DJ-101)
* Sharp SM510 label DJ-101 52ZA (no decap)
This is the new wide screen version, there's also a tabletop version that
plays more like the arcade game.
@ -907,7 +907,7 @@ MACHINE_CONFIG_END
Nintendo Game & Watch: Mario's Cement Factory (model ML-102)
* Sharp SM510 label ML-102 298D (die label CMS54C, KMS577)
This is the new wide screen version, there's also a tabletop version.
***************************************************************************/

72
src/mame/drivers/hp9845.cpp
View File

@ -226,7 +226,7 @@ static INPUT_PORTS_START(hp9845_base)
PORT_BIT(BIT_MASK(4) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_DEL_PAD) PORT_CHAR(UCHAR_MAMEKEY(DEL_PAD)) PORT_NAME("Keypad .") // KP .
PORT_BIT(BIT_MASK(5) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_0_PAD) PORT_CHAR(UCHAR_MAMEKEY(0_PAD)) PORT_NAME("Keypad 0") // KP 0
PORT_BIT(BIT_MASK(6) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER_PAD) PORT_CHAR(UCHAR_MAMEKEY(ENTER_PAD)) PORT_NAME("Execute") // Execute
PORT_BIT(BIT_MASK(7) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_NAME("Cont") PORT_CHAR(13) // Cont
PORT_BIT(BIT_MASK(7) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_NAME("Cont") PORT_CHAR(13) // Cont
PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT)) // Right
PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ') // Space
PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?') // /
@ -262,7 +262,7 @@ static INPUT_PORTS_START(hp9845_base)
PORT_BIT(BIT_MASK(6) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_NAME("Keypad =") // KP =
PORT_BIT(BIT_MASK(7) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_NAME("Pause") // Pause
PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP)) // Up
PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_NAME("Store") // Store
PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_NAME("Store") // Store
PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':') // :
PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K') // K
PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H') // H
@ -354,51 +354,51 @@ static INPUT_PORTS_START(hp9845_base)
PORT_BIT(BIT_MASK(30) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#') // 3
PORT_BIT(BIT_MASK(31) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!') // 1
PORT_START("SHIFTLOCK");
PORT_BIT(BIT_MASK(0) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE PORT_NAME("Shift lock") PORT_CHANGED_MEMBER(DEVICE_SELF, hp9845_base_state, togglekey_changed, 0) // Shift lock
PORT_START("SHIFTLOCK");
PORT_BIT(BIT_MASK(0) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE PORT_NAME("Shift lock") PORT_CHANGED_MEMBER(DEVICE_SELF, hp9845_base_state, togglekey_changed, 0) // Shift lock
INPUT_PORTS_END
/*
German keyboard layout
German keyboard layout
Remarks:
- Most keys including umlauts map correctly to the German keyboard layout of the 9845 without special configuration,
provided that the German keyboard firmware ROM is used on the 9845
- '#' maps positionally correct to Shift+3
- AltGr modifier on the Germany PC keyboard for 9845 shifted keycodes 23=| and 5=@ need to get assigned dynamically
- ~{}\'` are not available on the German 9845 keyboard, ^ is available via keypad only
Remarks:
- Most keys including umlauts map correctly to the German keyboard layout of the 9845 without special configuration,
provided that the German keyboard firmware ROM is used on the 9845
- '#' maps positionally correct to Shift+3
- AltGr modifier on the Germany PC keyboard for 9845 shifted keycodes 23=| and 5=@ need to get assigned dynamically
- ~{}\'` are not available on the German 9845 keyboard, ^ is available via keypad only
*/
static INPUT_PORTS_START(hp9845_base_de)
PORT_INCLUDE(hp9845_base)
PORT_MODIFY("KEY0")
PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('-') PORT_CHAR('_') // - _
PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR(';') // , ;
PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR(':') // . :
PORT_BIT(BIT_MASK(31) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('y') PORT_CHAR('Y') // Y
PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('-') PORT_CHAR('_') // - _
PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR(';') // , ;
PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR(':') // . :
PORT_BIT(BIT_MASK(31) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('y') PORT_CHAR('Y') // Y
PORT_MODIFY("KEY1")
PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(0x00f6) PORT_CHAR(0x00d6) // Ö
PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(0x00e4) PORT_CHAR(0x00c4) // Ä
PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(0x00f6) PORT_CHAR(0x00d6) // Ö
PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(0x00e4) PORT_CHAR(0x00c4) // Ä
PORT_MODIFY("KEY2")
PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR('<') PORT_CHAR('>') // < >
PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('+') PORT_CHAR('*') // + *
PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('z') PORT_CHAR('Z') // Z
PORT_BIT(BIT_MASK(23) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8) // Backspace
PORT_BIT(BIT_MASK(24) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_TILDE) PORT_CHAR(']') PORT_CHAR('@') // ] @
PORT_BIT(BIT_MASK(25) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('[') PORT_CHAR('|') // [ |
PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR(0x00fc) PORT_CHAR(0x00dc) // Ü
PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR('<') PORT_CHAR('>') // < >
PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('+') PORT_CHAR('*') // + *
PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('z') PORT_CHAR('Z') // Z
PORT_BIT(BIT_MASK(23) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8) // Backspace
PORT_BIT(BIT_MASK(24) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_TILDE) PORT_CHAR(']') PORT_CHAR('@') // ] @
PORT_BIT(BIT_MASK(25) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('[') PORT_CHAR('|') // [ |
PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR(0x00fc) PORT_CHAR(0x00dc) // Ü
PORT_MODIFY("KEY3")
PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR('=') // 0 =
PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(') // 8 (
PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&') // 6 &
PORT_BIT(BIT_MASK(14) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"') // 2 "
PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR(0x00df) PORT_CHAR('?') // ß ?
PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')') // 9 )
PORT_BIT(BIT_MASK(28) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('/') // 7 /
PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR('=') // 0 =
PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(') // 8 (
PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&') // 6 &
PORT_BIT(BIT_MASK(14) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"') // 2 "
PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR(0x00df) PORT_CHAR('?') // ß ?
PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')') // 9 )
PORT_BIT(BIT_MASK(28) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('/') // 7 /
INPUT_PORTS_END
// *******************
@ -415,7 +415,7 @@ hp9845_base_state::hp9845_base_state(const machine_config &mconfig, device_type
m_io_key1(*this , "KEY1"),
m_io_key2(*this , "KEY2"),
m_io_key3(*this , "KEY3"),
m_io_shiftlock(*this, "SHIFTLOCK"),
m_io_shiftlock(*this, "SHIFTLOCK"),
m_t14(*this , "t14"),
m_t15(*this , "t15"),
m_beeper(*this , "beeper"),
@ -789,21 +789,21 @@ INPUT_CHANGED_MEMBER(hp9845_base_state::togglekey_changed)
{
uintptr_t togglekey = (uintptr_t)param;
switch (togglekey) {
case 0: // Shift lock
case 0: // Shift lock
{
bool state = m_io_shiftlock->read();
popmessage("SHIFT LOCK %s", state ? "ON" : "OFF");
output().set_value("shift_lock_led" , state);
}
break;
case 1: // Prt all
case 1: // Prt all
{
bool state = BIT(m_io_key0->read(), 1);
popmessage("PRT ALL %s", state ? "ON" : "OFF");
output().set_value("prt_all_led" , state);
}
break;
case 2: // Auto st
case 2: // Auto st
{
bool state = BIT(m_io_key0->read(), 17);
popmessage("AUTO ST %s", state ? "ON" : "OFF");
@ -4003,7 +4003,7 @@ ROM_START( hp9845t_de )
ROM_LOAD("9845-PPU-Color-Enhanced-Graphics-Ger.bin", 0, 0x10000, CRC(a7ef79ee) SHA1(637742ed8fc8201a8e7bac62654f21c5409dfb76))
ROM_END
// YEAR NAME PARENT COMPAT MACHINE INPUT STATE INIT COMPANY FULLNAME FLAGS
// YEAR NAME PARENT COMPAT MACHINE INPUT STATE INIT COMPANY FULLNAME FLAGS
COMP( 1977, hp9845a, 0, 0, hp9845a, hp9845, hp9845_state, 0, "Hewlett-Packard", "9845A", MACHINE_IS_SKELETON | MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
COMP( 1977, hp9845s, hp9845a, 0, hp9845a, hp9845, hp9845_state, 0, "Hewlett-Packard", "9845S", MACHINE_IS_SKELETON | MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
COMP( 1979, hp9835a, 0, 0, hp9835a, hp9845, hp9845_state, 0, "Hewlett-Packard", "9835A", MACHINE_IS_SKELETON | MACHINE_NOT_WORKING | MACHINE_NO_SOUND )

42
src/mame/drivers/hp9k_3xx.cpp
View File

@ -4,7 +4,7 @@
hp9k3xx.c: preliminary driver for HP9000 300 Series (aka HP9000/3xx)
By R. Belmont
TODO: Add DIO/DIO-II slot capability and modularize the video cards
Currently supporting:
@ -26,10 +26,10 @@
340:
MC68030 CPU @ 16.67 MHz w/built-in MMU
MC68881 FPU
370:
MC68030 CPU @ 33 MHz w/built-in MMU
MC68881 FPU
MC68030 CPU @ 33 MHz w/built-in MMU
MC68881 FPU
380:
MC68040 CPU @ 25 MHz w/built-in MMU and FPU
@ -91,14 +91,14 @@ public:
DECLARE_WRITE16_MEMBER(buserror16_w);
DECLARE_READ32_MEMBER(buserror_r);
DECLARE_WRITE32_MEMBER(buserror_w);
DECLARE_WRITE32_MEMBER(led_w)
{
DECLARE_WRITE32_MEMBER(led_w)
{
if (mem_mask != 0x000000ff)
{
return;
}
#if 0
printf("LED: %02x (", data&0xff);
printf("LED: %02x (", data&0xff);
for (int i = 7; i >= 0; i--)
{
if (data & (1 << i))
@ -326,7 +326,7 @@ static MACHINE_CONFIG_START( hp9k310 )
MCFG_CPU_ADD(IOCPU_TAG, I8042, 5000000)
MCFG_CPU_PROGRAM_MAP(iocpu_map)
MCFG_DEVICE_ADD(PTM6840_TAG, PTM6840, 250000) // from oscillator module next to the 6840
MCFG_PTM6840_EXTERNAL_CLOCKS(250000.0f, 250000.0f, 250000.0f)
@ -340,10 +340,10 @@ static MACHINE_CONFIG_START( hp9k320 )
/* basic machine hardware */
MCFG_CPU_ADD(MAINCPU_TAG, M68020FPU, 16670000)
MCFG_CPU_PROGRAM_MAP(hp9k320_map)
MCFG_CPU_ADD(IOCPU_TAG, I8042, 5000000)
MCFG_CPU_PROGRAM_MAP(iocpu_map)
MCFG_DEVICE_ADD(PTM6840_TAG, PTM6840, 250000) // from oscillator module next to the 6840
MCFG_PTM6840_EXTERNAL_CLOCKS(250000.0f, 250000.0f, 250000.0f)
@ -363,7 +363,7 @@ static MACHINE_CONFIG_START( hp9k332 )
/* basic machine hardware */
MCFG_CPU_ADD(MAINCPU_TAG, M68020PMMU, 16670000)
MCFG_CPU_PROGRAM_MAP(hp9k332_map)
MCFG_CPU_ADD(IOCPU_TAG, I8042, 5000000)
MCFG_CPU_PROGRAM_MAP(iocpu_map)
@ -422,7 +422,7 @@ ROM_START( hp9k320 )
ROM_LOAD16_BYTE( "5061-6541.bin", 0x008000, 0x004000, CRC(39d32998) SHA1(6de1bda75187b0878c03c074942b807cf2924f0e) )
ROM_REGION( 0x800, IOCPU_TAG, 0 )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_END
ROM_START( hp9k330 )
@ -431,19 +431,19 @@ ROM_START( hp9k330 )
ROM_LOAD16_BYTE( "1818-4417.bin", 0x000001, 0x010000, CRC(374d49db) SHA1(a12cbf6c151e2f421da4571000b5dffa3ef403b3) )
ROM_REGION( 0x800, IOCPU_TAG, 0 )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_END
ROM_START( hp9k332 )
ROM_REGION( 0x20000, MAINCPU_TAG, 0 )
ROM_LOAD16_BYTE( "1818-4796.bin", 0x000000, 0x010000, CRC(8a7642da) SHA1(7ba12adcea85916d18b021255391bec806c32e94) )
ROM_LOAD16_BYTE( "1818-4797.bin", 0x000001, 0x010000, CRC(98129eb1) SHA1(f3451a854060f1be1bee9f17c5c198b4b1cd61ac) )
ROM_LOAD16_BYTE( "1818-4796.bin", 0x000000, 0x010000, CRC(8a7642da) SHA1(7ba12adcea85916d18b021255391bec806c32e94) )
ROM_LOAD16_BYTE( "1818-4797.bin", 0x000001, 0x010000, CRC(98129eb1) SHA1(f3451a854060f1be1bee9f17c5c198b4b1cd61ac) )
ROM_REGION( 0x800, IOCPU_TAG, 0 )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_REGION( 0x4000, "graphics", ROMREGION_ERASEFF | ROMREGION_BE | ROMREGION_32BIT )
ROM_LOAD16_BYTE( "5180-0471.bin", 0x000001, 0x002000, CRC(7256af2e) SHA1(584e8d4dcae8c898c1438125dc9c4709631b32f7) )
ROM_LOAD16_BYTE( "5180-0471.bin", 0x000001, 0x002000, CRC(7256af2e) SHA1(584e8d4dcae8c898c1438125dc9c4709631b32f7) )
ROM_END
ROM_START( hp9k340 )
@ -452,7 +452,7 @@ ROM_START( hp9k340 )
ROM_LOAD16_BYTE( "1818-4417.bin", 0x000001, 0x010000, CRC(374d49db) SHA1(a12cbf6c151e2f421da4571000b5dffa3ef403b3) )
ROM_REGION( 0x800, IOCPU_TAG, 0 )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_END
ROM_START( hp9k370 )
@ -461,7 +461,7 @@ ROM_START( hp9k370 )
ROM_LOAD16_BYTE( "1818-4417.bin", 0x000001, 0x010000, CRC(374d49db) SHA1(a12cbf6c151e2f421da4571000b5dffa3ef403b3) )
ROM_REGION( 0x800, IOCPU_TAG, 0 )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_END
ROM_START( hp9k380 )
@ -469,7 +469,7 @@ ROM_START( hp9k380 )
ROM_LOAD16_WORD_SWAP( "1818-5062_98754_9000-380_27c210.bin", 0x000000, 0x020000, CRC(500a0797) SHA1(4c0a3929e45202a2689e353657e5c4b58ff9a1fd) )
ROM_REGION( 0x800, IOCPU_TAG, 0 )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_END
ROM_START( hp9k382 )
@ -477,7 +477,7 @@ ROM_START( hp9k382 )
ROM_LOAD16_WORD_SWAP( "1818-5468_27c1024.bin", 0x000000, 0x020000, CRC(d1d9ef13) SHA1(6bbb17b9adad402fbc516dc2f3143e9c38ceef8e) )
ROM_REGION( 0x800, IOCPU_TAG, 0 )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_LOAD( "1820-4874.bin", 0x000000, 0x000800, CRC(e929044a) SHA1(90849a10bdb8c6e38e73ce027c9c0ad8b3956b1b) )
ROM_REGION( 0x2000, "unknown", ROMREGION_ERASEFF | ROMREGION_BE | ROMREGION_32BIT )
ROM_LOAD( "1818-5282_8ce61e951207_28c64.bin", 0x000000, 0x002000, CRC(740442f3) SHA1(ab65bd4eec1024afb97fc2dd3bd3f017e90f49ae) )

2
src/mame/drivers/interpro.cpp
View File

@ -102,7 +102,7 @@ READ8_MEMBER(interpro_state::idprom_r)
0x02, // 2800 series
// 0x00, // 2500 series
0x00, 0x00,
0x00, 0x00,
0x00, // board type, 0x80 = MPCB, 0x00 = MSMT
// for the system boards, these bytes contain cpu clock speed (as femtoseconds per cycle, big-endian)

6
src/mame/drivers/magicard.cpp
View File

@ -216,7 +216,7 @@
E = P0030SG / CD40106BCN
F = 74HCU04D
G = 74HC74D
*******************************************************************************
BIG DEAL BELGIEN Version 5.04
@ -287,7 +287,7 @@
Xtal 1: 30.000 MHz.
Xtal 2: 8.000 MHz.
Xtal 3: 19.660 MHz.
A = LT 0030 / LTC695CN / U18708
B = NEC Japan / D43256BGU-70LL / 0008XD041
C = MX B9819 / 29F1610MC-12C3 / M25685 / TAIWAN
@ -366,7 +366,7 @@
Xtal 1: 30.000 MHz.
Xtal 2: 8.000 MHz.
Xtal 3: 19.660 MHz.
A = LT 0030 / LTC695CN / U18708
B = NEC Japan / D43256BGU-70LL / 0008XD041
C = MX B9819 / 29F1610MC-12C3 / M25685 / TAIWAN

2
src/mame/drivers/mtouchxl.cpp
View File

@ -250,7 +250,7 @@ static MACHINE_CONFIG_START( at486 )
/* Security key */
MCFG_DS1205_ADD("multikey")
#ifdef REAL_PCI_CHIPSET
/* PCI root */
MCFG_PCI_ROOT_ADD( ":pci")

2
src/mame/drivers/nes_vt.cpp
View File

@ -1030,7 +1030,7 @@ CONS( 200?, dgun2500, 0, 0, nes_vt, nes_vt, nes_vt_state, 0, "dreamGEAR",
CONS( 2012, dgun2561, 0, 0, nes_vt, nes_vt, nes_vt_state, 0, "dreamGEAR", "dreamGEAR My Arcade Portable Gaming System (DGUN-2561)", MACHINE_NOT_WORKING )
CONS( 200?, lexcyber, 0, 0, nes_vt_xx, nes_vt, nes_vt_state, 0, "Lexibook", "Lexibook Compact Cyber Arcade", MACHINE_NOT_WORKING )
// these seem to have custom CPU opcodes? looks similar to the above, has many of the same games, but isn't 100% valid 6502
// these seem to have custom CPU opcodes? looks similar to the above, has many of the same games, but isn't 100% valid 6502
// (no visible tiles in ROM using standard decodes tho, might need moving out of here)
CONS( 200?, ii8in1, 0, 0, nes_vt, nes_vt, nes_vt_state, 0, "Intec", "InterAct 8-in-1", MACHINE_NOT_WORKING )
CONS( 200?, ii32in1, 0, 0, nes_vt, nes_vt, nes_vt_state, 0, "Intec", "InterAct 32-in-1", MACHINE_NOT_WORKING )

6
src/mame/drivers/pitnrun.cpp
View File

@ -316,7 +316,7 @@ static MACHINE_CONFIG_START( pitnrun )
MCFG_AY8910_PORT_B_READ_CB(DEVREAD8("soundlatch", generic_latch_8_device, read))
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( pitnrun_mcu, pitnrun )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(pitnrun_map_mcu)
@ -416,8 +416,8 @@ ROM_START( jumpkun )
ROM_REGION( 0x6000, "gfx1", 0 )
ROM_LOAD( "OBJ1.1K.2764", 0x00000, 0x02000, CRC(8929abfd) SHA1(978994af5816c20a8cd520263d04d1cc1e4df576) )
ROM_LOAD( "OBJ2.1M.2764", 0x02000, 0x02000, CRC(c7bf5819) SHA1(15d8e1dd1c0911785237e9063a75a42a2dc1bd50) )
ROM_LOAD( "OBJ3.1N.2764", 0x04000, 0x02000, CRC(5eeec986) SHA1(e58a0b98b90a1dd3971ed305100337aa2e5ec450) )
ROM_LOAD( "OBJ3.1N.2764", 0x04000, 0x02000, CRC(5eeec986) SHA1(e58a0b98b90a1dd3971ed305100337aa2e5ec450) )
ROM_REGION( 0x4000, "gfx2", 0 )
ROM_LOAD( "CHR1.6D.2764", 0x00000, 0x02000, CRC(3c93d4ee) SHA1(003121c49bccbb95efb137e6d92d26eea1957fbd) )
ROM_LOAD( "CHR2.6F.2764", 0x02000, 0x02000, CRC(154fad33) SHA1(7eddc794bd547053f185bb79a8220907bab13d85) )

88
src/mame/drivers/ron.cpp
View File

@ -2,16 +2,16 @@
// copyright-holders:Angelo Salese
/***************************************************************************
Ron II Mah-Jongg (c) 1981 Sanritsu
Ron II Mah-Jongg (c) 1981 Sanritsu
TODO:
- colors;
- dip switches;
TODO:
- colors;
- dip switches;
============================================================================
Debug cheats:
0x8580-d player-1 tiles
0x8680-d player-2 tiles
0x8580-d player-1 tiles
0x8680-d player-2 tiles
***************************************************************************/
@ -33,12 +33,12 @@ class ron_state : public driver_device
{
public:
ron_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_audiocpu(*this, "audiocpu"),
m_ay(*this, "aysnd"),
m_ay(*this, "aysnd"),
m_gfxdecode(*this, "gfxdecode"),
m_vram(*this, "vram"),
m_vram(*this, "vram"),
m_cram(*this, "cram"),
m_mj_ports1(*this, { "PL1_1", "PL1_2", "PL1_3", "PL1_4","PL1_5", "PL1_6", "PL1_7", "PL1_8" }),
m_mj_ports2(*this, { "PL2_1", "PL2_2", "PL2_3", "PL2_4","PL2_5", "PL2_6", "PL2_7", "PL2_8" }),
@ -46,14 +46,14 @@ public:
m_in1(*this, "IN1"),
m_in2(*this, "IN2"),
m_in3(*this, "IN3")
{
{
}
// screen updates
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
DECLARE_PALETTE_INIT(ron);
INTERRUPT_GEN_MEMBER(vblank_irq);
DECLARE_WRITE8_MEMBER(output_w);
DECLARE_READ8_MEMBER(p1_mux_r);
DECLARE_READ8_MEMBER(p2_mux_r);
@ -109,7 +109,7 @@ uint32_t ron_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap,
for (x=0;x<32;x++)
{
uint16_t tile = m_cram[count];
gfx->opaque(bitmap,cliprect,tile,0,0,0,x*8,y*8);
count++;
@ -118,26 +118,26 @@ uint32_t ron_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap,
gfx = m_gfxdecode->gfx(1);
count = 0;
for (y=0;y<32;y++)
{
for (x=0;x<32;x++)
{
uint16_t tile = m_vram[count];
gfx->transpen(bitmap,cliprect,tile,0,0,0,x*8,y*8,0);
count++;
}
}
return 0;
}
WRITE8_MEMBER(ron_state::output_w)
{
m_nmi_enable = (data & 0x10) == 0x10;
if(data & 0xef)
printf("%02x\n",data);
}
@ -145,7 +145,7 @@ WRITE8_MEMBER(ron_state::output_w)
uint8_t ron_state::read_mux(bool which,bool side)
{
uint8_t base_port = which == true ? 4 : 0;
//uint8_t i,res;
// printf("%02x\n", m_mux_data);
@ -154,7 +154,7 @@ uint8_t ron_state::read_mux(bool which,bool side)
for(uint8_t i=0;i<4;i++)
{
if((~m_mux_data) & (1 << i))
return (side == true ? m_mj_ports2[i+base_port] : m_mj_ports1[i+base_port])->read();
return (side == true ? m_mj_ports2[i+base_port] : m_mj_ports1[i+base_port])->read();
}
// TODO: check me
@ -171,9 +171,9 @@ READ8_MEMBER(ron_state::p1_mux_r)
READ8_MEMBER(ron_state::p2_mux_r)
{
uint8_t res = (offset == 0 ? m_in2 : m_in3)->read();
res &= 0xec;
return (read_mux(offset,true) & 0x13) | res;
}
@ -212,7 +212,7 @@ static ADDRESS_MAP_START( ron_audio_map, AS_PROGRAM, 8, ron_state)
ADDRESS_MAP_END
static ADDRESS_MAP_START( ron_audio_io, AS_IO, 8, ron_state)
ADDRESS_MAP_END
static INPUT_PORTS_START( ron )
@ -229,7 +229,7 @@ static INPUT_PORTS_START( ron )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("IN1")
PORT_DIPNAME( 0x04, 0x04, "IN1" )
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
@ -249,7 +249,7 @@ static INPUT_PORTS_START( ron )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("IN2")
PORT_DIPNAME( 0x04, 0x04, "2P Coinage" ) // how many credits per 2p mode
@ -282,7 +282,7 @@ static INPUT_PORTS_START( ron )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("PL1_1")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(1)
@ -319,10 +319,10 @@ static INPUT_PORTS_START( ron )
PORT_START("PL1_7")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(1)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("PL1_8")
PORT_BIT( 0x03, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("PL2_1")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2)
@ -337,22 +337,22 @@ static INPUT_PORTS_START( ron )
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(2)
PORT_START("PL2_4")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(2)
PORT_START("PL2_5")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_M ) PORT_PLAYER(2)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2)
PORT_START("PL2_6")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_N ) PORT_PLAYER(2)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(2)
PORT_START("PL2_7")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_CHI ) PORT_PLAYER(2)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
@ -434,7 +434,7 @@ WRITE8_MEMBER(ron_state::audio_p1_w)
//printf("p1 %02x %d\n",data,m_ay_address_sel);
//machine().debug_break();
if(m_ay_address_sel == true)
m_ay->address_w(space, 0, data);
else
@ -448,7 +448,7 @@ WRITE8_MEMBER(ron_state::audio_p2_w)
// p2 3f
if(data == 0xff)
m_ay_address_sel = false;
// p2 5f
// p2 3f
// p2 3f
@ -456,9 +456,9 @@ WRITE8_MEMBER(ron_state::audio_p2_w)
m_ay_address_sel = true;
m_prev_p2 = data;
//printf("p2 %02x\n",data);
// machine().debug_break();
// machine().debug_break();
}
READ_LINE_MEMBER(ron_state::audio_T1_r )
@ -522,11 +522,11 @@ ROM_START( ron2 )
ROM_LOAD( "r0__3.9l", 0x002000, 0x001000, CRC(6a8c1ef0) SHA1(9300a54102ca096fbf3d5056ede782fba0f5f970) )
ROM_LOAD( "r0__4.9n", 0x003000, 0x001000, CRC(86340522) SHA1(0175dda90e9e4798e9f2ab7a0ab97aa397ca18b8) )
ROM_LOAD( "r0__5.8h", 0x004000, 0x001000, CRC(3a28ad40) SHA1(872ced2d7515850cd86b84c81b14f200093746ad) )
ROM_REGION( 0x10000, "audiocpu", ROMREGION_ERASE00 )
ROM_LOAD( "r0_mu.4a", 0x0000, 0x000800, CRC(3491d8d5) SHA1(0aa0581350f4b3b81f3fa1f7c55a9bfb1f2c5f3b) )
ROM_LOAD( "r0_v0.4c", 0x0800, 0x000800, CRC(4160eb7f) SHA1(1756937378cbabb2229129b794d8c5d955252ed4) )
ROM_REGION( 0x0800, "gfx1", ROMREGION_ERASE00 )
ROM_LOAD( "r0__b.4k", 0x0000, 0x0800, CRC(8a61cdde) SHA1(0a38573ed644f1ed897443187f5cb61a6eb499b2) )
@ -534,16 +534,16 @@ ROM_START( ron2 )
ROM_LOAD( "r0_a1.4n", 0x0000, 0x0800, CRC(2d6276f4) SHA1(432b7fe0a1f1e9fdc9e276bcf27f74a5aec6c940) )
ROM_LOAD( "r0_a2.4l", 0x0800, 0x0800, CRC(2fe4a54f) SHA1(bb1d109851677ede58f875eff2588f60f979864e) )
ROM_REGION( 0x040, "unk_proms", ROMREGION_ERASE00 ) // unknown, near sound roms
ROM_LOAD( "82s123_1.6b", 0x000, 0x020, CRC(bd9bb647) SHA1(aad83eb295107cdc7ee96d78e81b0621ac351398) )
ROM_LOAD( "82s123_2.6c", 0x020, 0x020, CRC(439109d6) SHA1(f0d79048bb27a63c641296b3b1b81f513df9b33d) )
ROM_REGION( 0x040, "unk_proms", ROMREGION_ERASE00 ) // unknown, near sound roms
ROM_LOAD( "82s123_1.6b", 0x000, 0x020, CRC(bd9bb647) SHA1(aad83eb295107cdc7ee96d78e81b0621ac351398) )
ROM_LOAD( "82s123_2.6c", 0x020, 0x020, CRC(439109d6) SHA1(f0d79048bb27a63c641296b3b1b81f513df9b33d) )
ROM_REGION( 0x020, "color_prom", ROMREGION_ERASE00 )
ROM_LOAD( "82s123_5.1n", 0x000, 0x020, CRC(869784fa) SHA1(4bd0f26961d0bb54edb5eab5708d34468721d4c4) )
ROM_LOAD( "82s123_5.1n", 0x000, 0x020, CRC(869784fa) SHA1(4bd0f26961d0bb54edb5eab5708d34468721d4c4) )
ROM_REGION( 0x200, "clut_proms", ROMREGION_ERASE00 )
ROM_LOAD( "82s129_3.2n", 0x000, 0x100, CRC(018ab2a0) SHA1(039c574d8fd3c1a8e9eca6a7c79fe92e8496b157) )
ROM_LOAD( "82s129_4.2m", 0x100, 0x100, CRC(f3c05d59) SHA1(bd48963aa9f2bedaa0c1fd031d7c93089161d1d9) )
ROM_LOAD( "82s129_3.2n", 0x000, 0x100, CRC(018ab2a0) SHA1(039c574d8fd3c1a8e9eca6a7c79fe92e8496b157) )
ROM_LOAD( "82s129_4.2m", 0x100, 0x100, CRC(f3c05d59) SHA1(bd48963aa9f2bedaa0c1fd031d7c93089161d1d9) )
ROM_END
GAME( 1981, ron2, 0, ron, ron, ron_state, 0, ROT270, "Sanritsu", "Ron II Mah-Jongg", MACHINE_NOT_WORKING | MACHINE_WRONG_COLORS )

6
src/mame/drivers/royalmah.cpp
View File

@ -616,7 +616,7 @@ static ADDRESS_MAP_START( seljan_iomap, AS_IO, 8, royalmah_state )
AM_RANGE( 0x0011, 0x0011 ) AM_MIRROR(0x7f00) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
AM_RANGE( 0x0012, 0x0012 ) AM_MIRROR(0x7f00) AM_READ_PORT("DSW2") AM_DEVWRITE("crtc", mc6845_device, address_w)
AM_RANGE( 0x0013, 0x0013 ) AM_MIRROR(0x7f00) AM_READ_PORT("DSW3") AM_DEVWRITE("crtc", mc6845_device, register_w)
// TODO: following actually starts at 0x8000, needs custom 6845 routine because it uses start address register.
AM_RANGE( 0x7e00, 0xffff ) AM_RAM AM_SHARE("videoram")
ADDRESS_MAP_END
@ -3494,7 +3494,7 @@ static MACHINE_CONFIG_DERIVED( janyoup2, ippatsu )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_CLOCK(XTAL_18_432MHz/4) // unknown divider
MCFG_CPU_IO_MAP(janyoup2_iomap)
MCFG_MC6845_ADD("crtc", H46505, "screen", XTAL_18_432MHz/12) // unknown divider
MCFG_MC6845_SHOW_BORDER_AREA(false)
MCFG_MC6845_CHAR_WIDTH(4)
@ -3799,7 +3799,7 @@ ROM_START( seljan ) // Z80A + HD46505SP + AY891X (a sticker covers the chip type
ROM_LOAD( "3", 0x4000, 0x2000, CRC(6c0dfd50) SHA1(1f91ff0ef2f24414888ae8e5ebac72a5bb48780b) )
ROM_LOAD( "5", 0x6000, 0x2000, CRC(22eb98ee) SHA1(aae0ba5098852e6fef3dd7cc97dfad97ca444bb7) )
ROM_LOAD( "4", 0x8000, 0x1000, CRC(d41e2a10) SHA1(9c24f89ba877ab599ea89961b5e705fa770867be) )
ROM_REGION( 0x0020, "proms", 0 )
ROM_LOAD( "82s123_1", 0x0000, 0x0020, CRC(f1df0310) SHA1(cc7dd39a0aa10b57039143e587eee02cf5dd2e5c) )
ROM_END

12
src/mame/drivers/socrates.cpp
View File

@ -578,10 +578,10 @@ logerror("write to i/o 0x60 of %x\n",data);
/* stuff below belongs in video/socrates.c */
/* graphics section:
0x20 - W - lsb offset of screen display
0x21 - W - msb offset of screen display
resulting screen line is one of 512 total offsets on 128-byte boundaries in the whole 64k ram
*/
0x20 - W - lsb offset of screen display
0x21 - W - msb offset of screen display
resulting screen line is one of 512 total offsets on 128-byte boundaries in the whole 64k ram
*/
WRITE8_MEMBER(socrates_state::socrates_scroll_w)
{
if (offset == 0)
@ -966,7 +966,7 @@ static ADDRESS_MAP_START(z80_io, AS_IO, 8, socrates_state )
0xC0 produces a DMC wave read from an unknown address at around 342hz
<todo: test the others, maybe take samples?>
*/
AM_RANGE(0x20, 0x21) AM_READWRITE(read_f3, socrates_scroll_w) AM_MIRROR (0xe)
AM_RANGE(0x20, 0x21) AM_READWRITE(read_f3, socrates_scroll_w) AM_MIRROR (0xe)
AM_RANGE(0x30, 0x30) AM_READWRITE(read_f3, kbmcu_strobe) AM_MIRROR (0xf) /* resets the keyboard IR decoder MCU */
AM_RANGE(0x40, 0x40) AM_READWRITE(status_and_speech, speech_command ) AM_MIRROR(0xf) /* reads status register for vblank/hblank/speech, also reads and writes speech module */
AM_RANGE(0x50, 0x50) AM_READWRITE(socrates_keyboard_low_r, socrates_keyboard_clear) AM_MIRROR(0xE) /* Keyboard keycode low, latched on keypress, can be unlatched by writing anything here */
@ -1382,7 +1382,7 @@ static MACHINE_CONFIG_DERIVED( socrates_pal, socrates )
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_REFRESH_RATE(50)
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) // not accurate
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) // not accurate
MCFG_SCREEN_SIZE(264, 238) // technically the screen size is 256x228 but super painter abuses what I suspect is a hardware bug to display repeated pixels of the very last pixel beyond this horizontal space, well into hblank
MCFG_SCREEN_VISIBLE_AREA(0, 263, 0, 229) // the last few rows are usually cut off by the screen bottom but are indeed displayed if you mess with v-hold
MCFG_SCREEN_UPDATE_DRIVER(socrates_state, screen_update_socrates)

10
src/mame/drivers/spirit76.cpp
View File

@ -47,7 +47,7 @@ private:
static ADDRESS_MAP_START( maincpu_map, AS_PROGRAM, 8, spirit76_state )
ADDRESS_MAP_UNMAP_HIGH
// ADDRESS_MAP_GLOBAL_MASK(0xfff) // this could most likely go in once the memory map is sorted
// ADDRESS_MAP_GLOBAL_MASK(0xfff) // this could most likely go in once the memory map is sorted
AM_RANGE(0x0000, 0x00ff) AM_RAM // 2x 2112
AM_RANGE(0x2200, 0x2203) AM_DEVREADWRITE("pia", pia6821_device, read, write) // 6820
AM_RANGE(0x2400, 0x2400) AM_READ(unk_r)
@ -130,10 +130,10 @@ static MACHINE_CONFIG_START( spirit76 )
MCFG_PIA_WRITEPB_HANDLER(WRITE8(spirit76_state, portb_w))
MCFG_PIA_READPA_HANDLER(READ8(spirit76_state, porta_r))
MCFG_PIA_READPB_HANDLER(READ8(spirit76_state, portb_r))
// MCFG_PIA_CA2_HANDLER(WRITELINE(spirit76_state, pia22_ca2_w))
// MCFG_PIA_CB2_HANDLER(WRITELINE(spirit76_state, pia22_cb2_w))
// MCFG_PIA_IRQA_HANDLER(INPUTLINE("maincpu", M6800_IRQ_LINE))
// MCFG_PIA_IRQB_HANDLER(INPUTLINE("maincpu", M6800_IRQ_LINE))
// MCFG_PIA_CA2_HANDLER(WRITELINE(spirit76_state, pia22_ca2_w))
// MCFG_PIA_CB2_HANDLER(WRITELINE(spirit76_state, pia22_cb2_w))
// MCFG_PIA_IRQA_HANDLER(INPUTLINE("maincpu", M6800_IRQ_LINE))
// MCFG_PIA_IRQB_HANDLER(INPUTLINE("maincpu", M6800_IRQ_LINE))
/* sound hardware */
MCFG_FRAGMENT_ADD( genpin_audio )

28
src/mame/drivers/superqix.cpp
View File

@ -748,7 +748,7 @@ Seems to act like an older version of hotsmash mcu code, the quadrature code is
0x10 - protection scramble; immediately latch the current command (0x10) (or another byte if you write one VERY fast) and do some rotates and scrambling of the value an XORing it against the prior value, and return it. This is affected by the carry flag if something else set it.
**************************************************************************/
/*
* This wrapper routine is necessary because the dial is not connected to an
* hardware counter as usual, but the DIR and CLOCK inputs are directly
@ -799,17 +799,17 @@ WRITE8_MEMBER(hotsmash_state::hotsmash_68705_portC_w)
// maybe on the RISING edge of the latch bit, the semaphores are updated, like TaitoSJ?
/*if (BIT(changed_m_portC_out, 3) && BIT(m_portC_out, 3))
{
switch (m_portC_out & 0x07)
{
case 0x03:
m_Z80HasWritten = 0;
break;
case 0x05:
m_MCUHasWritten = 1;
break;
default:
break;
}
switch (m_portC_out & 0x07)
{
case 0x03:
m_Z80HasWritten = 0;
break;
case 0x05:
m_MCUHasWritten = 1;
break;
default:
break;
}
}*/
// on the falling edge of the latch bit, update port A and (if applicable) m_portB_out latches
if (BIT(changed_m_portC_out, 3) && !BIT(m_portC_out, 3))
@ -852,7 +852,7 @@ WRITE8_MEMBER(hotsmash_state::hotsmash_Z80_mcu_w)
{
m_fromZ80 = data;
//if ((m_fromZ80 != 0x04) && (m_fromZ80 != 0x08))
// logerror("%04x: z80 write to MCU %02x; Z80HasWritten: %d (and will be 1 after this); MCUHasWritten: %d\n",space.device().safe_pc(),m_fromZ80, m_Z80HasWritten, m_MCUHasWritten);
// logerror("%04x: z80 write to MCU %02x; Z80HasWritten: %d (and will be 1 after this); MCUHasWritten: %d\n",space.device().safe_pc(),m_fromZ80, m_Z80HasWritten, m_MCUHasWritten);
m_Z80HasWritten = 1; // set the semaphore, and assert interrupt on the mcu
machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(250)); //boost the interleave temporarily, or the game will crash.
m_mcu->set_input_line(M68705_IRQ_LINE, ASSERT_LINE);
@ -863,7 +863,7 @@ READ8_MEMBER(hotsmash_state::hotsmash_Z80_mcu_r)
if(!machine().side_effect_disabled())
{
//if ((m_fromZ80 != 0x04) && (m_fromZ80 != 0x08))
// logerror("%04x: z80 read from MCU %02x; Z80HasWritten: %d; MCUHasWritten: %d (and will be 0 after this)\n",space.device().safe_pc(),m_fromMCU, m_Z80HasWritten, m_MCUHasWritten);
// logerror("%04x: z80 read from MCU %02x; Z80HasWritten: %d; MCUHasWritten: %d (and will be 0 after this)\n",space.device().safe_pc(),m_fromMCU, m_Z80HasWritten, m_MCUHasWritten);
m_MCUHasWritten = 0;
}
// return the last value the 68705 wrote, but do not mark that we've read it

18
src/mame/drivers/terracre.cpp
View File

@ -100,7 +100,7 @@ AT-2
0000 3000 414e 4b41 4b45 5544 4f4e
0000 2000 0e0e 4b49 5455 4e45 0e0e
0000 1000 0e4b 414b 4553 4f42 410e
2079 0001 0004 4ed0 2079 0001 0008
2079 0001 0004 4ed0 2079 0001 0008
4ed0 7c
*/
@ -120,7 +120,7 @@ static const uint16_t mAmazonProtData[] =
};
/*
0000 5000 5341 4b45 5349 4755 5245
0000 5000 5341 4b45 5349 4755 5245
0000 4000 0e4b 4154 5544 4f4e 0e0e
0000 3000 414e 4b41 4b45 5544 4f4e
0000 2000 0e0e 4b49 5455 4e45 0e0e
@ -176,7 +176,7 @@ READ8_MEMBER(terracre_state::soundlatch_clear_r)
return 0;
}
// 1412M2
// 1412M2
READ16_MEMBER(terracre_state::amazon_protection_r)
{
if(m_mAmazonProtCmd == 0x37)
@ -185,14 +185,14 @@ READ16_MEMBER(terracre_state::amazon_protection_r)
//its usage is more variable in mightguy for whatever reason.
uint16_t prot_offset = (m_mAmazonProtReg[1]<<8)|(m_mAmazonProtReg[2]);
uint8_t *prot_rom = memregion("prot_data")->base();
//printf("Mode %02x:%04x %04x R -> %02x (fixed %02x)\n",m_mAmazonProtReg[0],prot_offset,(m_mAmazonProtReg[3]<<8)|(m_mAmazonProtReg[4]),prot_rom[prot_offset],(prot_rom[prot_offset] - 0x44) & 0xff);
return prot_rom[prot_offset & 0x1fff] - 0x44;
}
popmessage("unknown prot cmd R %02x",m_mAmazonProtCmd);
return 0;
}
@ -209,13 +209,13 @@ WRITE16_MEMBER(terracre_state::amazon_protection_w)
if( m_mAmazonProtCmd>=0x32 && m_mAmazonProtCmd<=0x37 )
{
m_mAmazonProtReg[m_mAmazonProtCmd-0x32] = data;
#if 0
if(m_mAmazonProtCmd == 0x32)
{
for(int i=0;i<6;i++)
printf("%02x ",m_mAmazonProtReg[i]);
printf("\n");
}
#endif
@ -636,7 +636,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( amazon_1412m2, amazon_base )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(amazon_1412m2_map)
// TODO: install 1412m2 here
MACHINE_CONFIG_END

2
src/mame/drivers/viper.cpp
View File

@ -2289,7 +2289,7 @@ WRITE_LINE_MEMBER(viper_state::voodoo_vblank)
{
// FIXME: The driver seems to hang using the voodoo vblank signa
//if (state)
// mpc8240_interrupt(MPC8240_IRQ0);
// mpc8240_interrupt(MPC8240_IRQ0);
//mpc8240_interrupt(MPC8240_IRQ3);
}

2
src/mame/includes/coco.h
View File

@ -54,7 +54,7 @@ SLOT_INTERFACE_EXTERN( coco_cart );
#define DWSOCK_TAG "dwsock"
#define VHD0_TAG "vhd0"
#define VHD1_TAG "vhd1"
#define FLOATING_TAG "floating"
#define FLOATING_TAG "floating"
// inputs
#define CTRL_SEL_TAG "ctrl_sel"

6
src/mame/includes/cop01.h
View File

@ -35,9 +35,9 @@ public:
/* sound-related */
int m_pulse;
int m_timer; // kludge for ym3526 in mightguy
uint8_t m_prot_command;
uint8_t m_prot_reg[6];
uint8_t m_prot_command;
uint8_t m_prot_reg[6];
/* devices */
required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_audiocpu;

6
src/mame/includes/interpro.h
View File

@ -123,7 +123,7 @@ public:
enum sreg_status_mask
{
STATUS_YELLOW_ZONE = 0x0001,
STATUS_YELLOW_ZONE = 0x0001,
STATUS_SRNMI = 0x0002,
STATUS_PWRLOSS = 0x0004,
STATUS_RED_ZONE = 0x0008,
@ -141,11 +141,11 @@ public:
CTRL1_ETHDTR = 0x0020,
CTRL1_ETHRMOD = 0x0040,
CTRL1_CLIPRESET = 0x0040,
CTRL1_FIFOACTIVE = 0x0080
CTRL1_FIFOACTIVE = 0x0080
};
DECLARE_READ16_MEMBER(sreg_ctrl1_r) { return m_sreg_ctrl1; }
DECLARE_WRITE16_MEMBER(sreg_ctrl1_w);
enum sreg_ctrl2_mask
{
CTRL2_PWRUP = 0x0001,

2
src/mame/includes/megadriv.h
View File

@ -32,7 +32,7 @@ MACHINE_CONFIG_EXTERN( megadriv_timers );
MACHINE_CONFIG_EXTERN( md_ntsc );
MACHINE_CONFIG_EXTERN( md_pal );
MACHINE_CONFIG_EXTERN( md_bootleg ); // for topshoot.c & hshavoc.c
MACHINE_CONFIG_EXTERN( dcat16_megadriv );
MACHINE_CONFIG_EXTERN( dcat16_megadriv );
struct genesis_z80_vars
{

8
src/mame/layout/interpro.lay
View File

@ -4,7 +4,7 @@ license:CC0
copyright-holders:Patrick Mackinlay
Intergraph InterPro 2x00 layout.
For now, this is only used to display the (internal) diagnostic 7-segment LED. In the future, it
For now, this is only used to display the (internal) diagnostic 7-segment LED. In the future, it
should be expanded to handle the monitor(s), system unit power/disk lights, and keyboard.
-->
<mamelayout version="2">
@ -18,8 +18,8 @@ should be expanded to handle the monitor(s), system unit power/disk lights, and
<bezel name="digit0" element="digit">
<bounds x="850" y="0" width="40" height="50" />
</bezel>
<screen index="0">
<bounds x="0" y="0" width="800" height="600" />
</screen>
<screen index="0">
<bounds x="0" y="0" width="800" height="600" />
</screen>
</view>
</mamelayout>

4
src/mame/machine/coco.cpp
View File

@ -145,8 +145,8 @@ void coco_state::device_start()
// cart slot
m_cococart->set_cart_base_update(cococart_base_update_delegate(&coco_state::update_cart_base, this));
m_cococart->set_line_delay(cococart_slot_device::line::NMI, 12); // 12 allowed one more instruction to finished after the line is pulled
m_cococart->set_line_delay(cococart_slot_device::line::HALT, 6); // 6 allowed one more instruction to finished after the line is pulled
m_cococart->set_line_delay(cococart_slot_device::line::NMI, 12); // 12 allowed one more instruction to finished after the line is pulled
m_cococart->set_line_delay(cococart_slot_device::line::HALT, 6); // 6 allowed one more instruction to finished after the line is pulled
// save state support
save_item(NAME(m_dac_output));

8
src/mame/machine/coco12.cpp
View File

@ -32,10 +32,10 @@ void coco12_state::configure_sam()
uint8_t *rom = memregion(MAINCPU_TAG)->base();
uint8_t *cart_rom = cococart().get_cart_base();
m_sam->configure_bank(0, ram().pointer(), ram().size(), false); // $0000-$7FFF
m_sam->configure_bank(1, &rom[0x0000], 0x2000, true); // $8000-$9FFF
m_sam->configure_bank(2, &rom[0x2000], 0x2000, true); // $A000-$BFFF
m_sam->configure_bank(3, cart_rom, 0x4000, true); // $C000-$FEFF
m_sam->configure_bank(0, ram().pointer(), ram().size(), false); // $0000-$7FFF
m_sam->configure_bank(1, &rom[0x0000], 0x2000, true); // $8000-$9FFF
m_sam->configure_bank(2, &rom[0x2000], 0x2000, true); // $A000-$BFFF
m_sam->configure_bank(3, cart_rom, 0x4000, true); // $C000-$FEFF
// $FF00-$FF1F
m_sam->configure_bank(4, read8_delegate(FUNC(coco12_state::ff00_read), this), write8_delegate(FUNC(coco12_state::ff00_write), this));

4
src/mame/machine/gridkeyb.cpp
View File

@ -4,9 +4,9 @@
GRiD Compass keyboard HLE, derived from generic_keyboard
Keycodes from "6 - Interceptor, CCProm, Utils, OS - Sysgen/UTILS/DVLEXEC.PLM"
Keycodes from "6 - Interceptor, CCProm, Utils, OS - Sysgen/UTILS/DVLEXEC.PLM"
Multiple shift key combos not simulated yet.
Multiple shift key combos not simulated yet.
***************************************************************************/

22
src/mame/machine/interpro_ioga.h
View File

@ -152,7 +152,7 @@ public:
DECLARE_WRITE32_MEMBER(timer2_w) { write_timer(2, data, IOGA_TIMER_2); }
DECLARE_WRITE32_MEMBER(timer3_w) { write_timer(3, data, IOGA_TIMER_3); }
enum hwicr_mask
enum hwicr_mask
{
IRQ_PENDING = 0x0100,
IRQ_ENABLE_EXTERNAL = 0x0200,
@ -168,7 +168,7 @@ public:
DECLARE_READ8_MEMBER(softint_r) { return m_softint; }
DECLARE_WRITE8_MEMBER(softint_w);
enum nmictrl_mask
enum nmictrl_mask
{
NMI_ALL = 0x01,
NMI_ENABLE1 = 0x02,
@ -184,16 +184,16 @@ public:
DECLARE_READ16_MEMBER(softint_vector_r) { return m_swicr[offset]; }
DECLARE_WRITE16_MEMBER(softint_vector_w);
enum dma_ctrl_mask
enum dma_ctrl_mask
{
DMA_CTRL_TCZERO = 0x00000001, // transfer count zero
DMA_CTRL_BERR = 0x00400000, // bus error
DMA_CTRL_BUSY = 0x02000000, // set until arbiter grants bus access
DMA_CTRL_TCZERO = 0x00000001, // transfer count zero
DMA_CTRL_BERR = 0x00400000, // bus error
DMA_CTRL_BUSY = 0x02000000, // set until arbiter grants bus access
DMA_CTRL_WRITE = 0x40000000, // indicates memory to device transfer
DMA_CTRL_FORCED = 0x60000000,
DMA_CTRL_WRITE = 0x40000000, // indicates memory to device transfer
DMA_CTRL_FORCED = 0x60000000,
DMA_CTRL_WMASK = 0xfd000e00 // writable fields
DMA_CTRL_WMASK = 0xfd000e00 // writable fields
};
DECLARE_READ32_MEMBER(dma_plotter_r) { return dma_r(space, offset, mem_mask, IOGA_DMA_PLOTTER); }
DECLARE_WRITE32_MEMBER(dma_plotter_w) { dma_w(space, offset, data, mem_mask, IOGA_DMA_PLOTTER); }
@ -210,7 +210,7 @@ public:
DECLARE_READ32_MEMBER(error_address_r) { return m_error_address; }
enum error_businfo_mask
enum error_businfo_mask
{
BINFO_CT = 0x003f,
BINFO_TAG = 0x01c0,
@ -220,7 +220,7 @@ public:
BINFO_SNAPOK = 0x4000,
BINFO_MSBE = 0x8000
};
enum error_businfo_bg
enum error_businfo_bg
{
BINFO_BG_IOD = 0x0200,
BINFO_BG_ICAMMU = 0x0400,

4
src/mame/machine/interpro_mcga.cpp
View File

@ -83,7 +83,7 @@ WRITE16_MEMBER(interpro_mcga_device::control_w)
if (data & CONTROL_ENMMBE)
m_error |= ERROR_VALID;
//else
// m_error &= ~ERROR_VALID;
// m_error &= ~ERROR_VALID;
}
WRITE16_MEMBER(interpro_fmcc_device::control_w)
@ -94,5 +94,5 @@ WRITE16_MEMBER(interpro_fmcc_device::control_w)
if (data & CONTROL_ENMMBE)
m_error |= ERROR_VALID;
//else
// m_error &= ~ERROR_VALID;
// m_error &= ~ERROR_VALID;
}

12
src/mame/machine/interpro_mcga.h
View File

@ -16,7 +16,7 @@ public:
DECLARE_READ16_MEMBER(reg00_r) { return m_reg[0]; }
DECLARE_WRITE16_MEMBER(reg00_w) { m_reg[0] = data; }
enum control_mask
enum control_mask
{
CONTROL_OPTMASK = 0x0003,
CONTROL_CBITFRCRD = 0x0004,
@ -32,7 +32,7 @@ public:
DECLARE_READ16_MEMBER(control_r) { return m_control; }
virtual DECLARE_WRITE16_MEMBER(control_w);
enum error_mask
enum error_mask
{
ERROR_SYND = 0x00ff,
ERROR_MMBE = 0x0100,
@ -51,7 +51,7 @@ public:
DECLARE_READ16_MEMBER(reg30_r) { return m_reg[2]; }
DECLARE_WRITE16_MEMBER(reg30_w) { m_reg[2] = data; }
enum memsize_mask
enum memsize_mask
{
MEMSIZE_ADDR = 0x007f
};
@ -80,7 +80,7 @@ public:
virtual DECLARE_ADDRESS_MAP(map, 32) override;
enum control_mask
enum control_mask
{
CONTROL_CBITFRCRD = 0x0004,
CONTROL_CBITFRCSUB = 0x0008,
@ -98,7 +98,7 @@ public:
};
DECLARE_WRITE16_MEMBER(control_w) override;
enum error_mask
enum error_mask
{
ERROR_SYND = 0x00ff,
ERROR_MMBE = 0x0100,
@ -107,7 +107,7 @@ public:
ERROR_VALID = 0x8000
};
enum error_control_mask
enum error_control_mask
{
ERROR_CONTROL_CYCLE = 0x003f,
ERROR_CONTROL_TAG = 0x01c0

10
src/mame/machine/interpro_sga.h
View File

@ -20,7 +20,7 @@ public:
DECLARE_READ32_MEMBER(gcsr_r) { return m_gcsr; }
DECLARE_WRITE32_MEMBER(gcsr_w) { m_gcsr = data; }
enum ipoll_mask
enum ipoll_mask
{
IPOLL_ATTN = 0x000000ff,
IPOLL_DMAEND = 0x00000700,
@ -34,7 +34,7 @@ public:
DECLARE_READ32_MEMBER(ipoll_r) { return m_ipoll; }
DECLARE_WRITE32_MEMBER(ipoll_w) { m_ipoll = data; }
enum imask_mask
enum imask_mask
{
IMASK_DMAENDCH1 = 0x00000200,
IMASK_NOGRANT = 0x00001000,
@ -51,7 +51,7 @@ public:
DECLARE_READ32_MEMBER(range_end_r) { return m_range_end; }
DECLARE_WRITE32_MEMBER(range_end_w) { m_range_end = data; }
enum cttag_mask
enum cttag_mask
{
CTTAG_TAG = 0x00000007,
CTTAG_CYCLE = 0x000001f8,
@ -63,14 +63,14 @@ public:
DECLARE_READ32_MEMBER(address_r) { return m_address; }
DECLARE_WRITE32_MEMBER(address_w) { m_address = data; }
enum dmacsr_mask
enum dmacsr_mask
{
DMACSR_CH1ENABLE = 0x00000080
};
DECLARE_READ32_MEMBER(dmacsr_r) { return m_dmacsr; }
DECLARE_WRITE32_MEMBER(dmacsr_w) { m_dmacsr = data; }
enum edmacsr_mask
enum edmacsr_mask
{
EDMACSR_CH1RDONLY = 0x00000010
};

4
src/mame/machine/megadriv.cpp
View File

@ -953,8 +953,8 @@ MACHINE_CONFIG_START( dcat16_megadriv )
MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(md_cons_state, screen_vblank_console))
// has SD card slot instead?
// MCFG_MD_CARTRIDGE_ADD("mdslot", md_cart, nullptr)
// MCFG_SOFTWARE_LIST_ADD("cart_list","megadriv")
// MCFG_MD_CARTRIDGE_ADD("mdslot", md_cart, nullptr)
// MCFG_SOFTWARE_LIST_ADD("cart_list","megadriv")
MACHINE_CONFIG_END
/************ PAL hardware has a different master clock *************/

24
src/mame/mame.lst
View File

@ -81,7 +81,7 @@ casanova //
@source:40love.cpp
40love // A30 (c) 1984 Taito
40lovej // A30 (c) 1984 Taito
40lovej // A30 (c) 1984 Taito
fieldday // A23 (c) 1984 Taito
undoukai // A17 (c) 1984 Taito
@ -10695,7 +10695,7 @@ dblcrown // (c) 1994 Excellent System
dblewing // MBE (c) 1993 Mitchell
@source:dbox.cpp
dbox // (c) 1996 Nokia Multimedia
dbox // (c) 1996 Nokia Multimedia
@source:dbz.cpp
dbz // (c) 1993 Banpresto
@ -11084,7 +11084,7 @@ cbnj // 27 Bump 'n' Jump
cbtime // 26 1982.08 Hamburger/Burger Time
cburnrub // 27 1982.11 Burnin' Rubber
cburnrub2 // 27
cburnrubj //
cburnrubj //
cdiscon1 // 19 1982.04 Disco No.1
cdsteljn // 14 1981.06 DS Telejan
cexplore // 18 1982.02 Explorer
@ -11093,14 +11093,14 @@ cfghtice // 40 1984.04 Fighting Ice Hockey
cfishing // 25 1982.10 Fishing
cflyball // 35 1983.?? Flying Ball/Bampoline
cgraplop // 28 1982.11 Cluster Buster / Graplop
cgraplopj //
cgraplopj //
cgraplop2 // 28
chamburger // 26 1982.08 Hamburger (Japan)
chwy // 01 1980.12 Highway Chase
clapapa // 29 1982.11 La-Pa-Pa
clapapa2 // 29 Rootin' Tootin' // this one doesn't display lapapa anywhere
clocknch // 11 1981.04 Lock'n'Chase
clocknchj //
clocknchj //
cluckypo // 15 1981.?? Lucky Poker
cmanhat // 03 1981.01 Manhattan
cmissnx // 21 1982.04 Mission-X/Zoar
@ -13097,8 +13097,8 @@ turpins // (c) 1981 bootleg
turtles // (c) 1981 Stern
uniwars // (c) Irem
uniwarsa // (c) Karateco
victoryc // (c) Comsoft
victorycb // (c) Comsoft (bootleg)
victoryc // (c) Comsoft
victorycb // (c) Comsoft (bootleg)
warofbug // (c) 1981 Armenia
warofbugg // German Version
warofbugu // (c) 1981 Armenia
@ -14806,7 +14806,7 @@ hp9816 //
hp9k310 //
hp9k320 //
hp9k330 //
hp9k332 //
hp9k332 //
hp9k340 //
hp9k370 //
hp9k380 //
@ -20155,7 +20155,7 @@ segacd2 // 1993 Sega Sega CD 2 (USA)
wmega // 1992 Sega Wondermega (Japan)
wmegam2 // 1993 Victor Wondermega M2 (Japan)
xeye // 1993 JVC X'eye (USA)
dcat16 //
dcat16 //
@source:megadrvb.cpp
aladmdb // MegaDrive-based hack
@ -31106,7 +31106,7 @@ pitagjr // Pitagorin Junior
@source:pitnrun.cpp
pitnrun // PR (c) 1984 Taito Corporation
pitnruna // PR (c) 1984 Taito Corporation
jumpkun // prototype
jumpkun // prototype
@source:pk8000.cpp
hobby //
@ -31498,7 +31498,7 @@ powerins // (c) 1993 Atlus (USA)
powerinsa // (c) 1993 Atlus (bootleg of USA version)
powerinsb // (c) 1993 Atlus (bootleg of USA version)
powerinsj // (c) 1993 Atlus (Japan)
powerinsp // prototype
powerinsp // prototype
@source:pp01.cpp
pp01 //
@ -32218,7 +32218,7 @@ rollace2 // (c) 1983 Williams
rotaryf //
@source:ron.cpp
ron2 // (c) 1981 Sanritsu
ron2 // (c) 1981 Sanritsu
@source:roul.cpp
roul // (c) 1990

2
src/mame/video/pitnrun.cpp
View File

@ -68,7 +68,7 @@ WRITE8_MEMBER(pitnrun_state::scroll_w)
m_scroll = (m_scroll & (0xff<<((offset)?0:8))) |( data<<((offset)?8:0));
m_bg->set_scrollx(0, m_scroll);
}
WRITE8_MEMBER(pitnrun_state::scroll_y_w)
{
m_bg->set_scrolly(0, data);

2
src/osd/modules/debugger/win/consolewininfo.cpp
View File

@ -180,7 +180,7 @@ void consolewin_info::update_menu()
// not working properly, removed for now until investigation can be done
//if (get_softlist_info(&img))
// AppendMenu(devicesubmenu, MF_STRING, new_item + DEVOPTION_ITEM, TEXT("Mount Item..."));
// AppendMenu(devicesubmenu, MF_STRING, new_item + DEVOPTION_ITEM, TEXT("Mount Item..."));
AppendMenu(devicesubmenu, MF_STRING, new_item + DEVOPTION_OPEN, TEXT("Mount File..."));