From f3509306c0d65d7cc2b89c1bc2da0e44e980935d Mon Sep 17 00:00:00 2001 From: angelosa Date: Sun, 20 Aug 2023 17:08:11 +0200 Subject: [PATCH] video/mb86292.cpp: add base CRTC --- src/devices/machine/8042kbdc.cpp | 2 + src/devices/video/mb86292.cpp | 452 ++++++++++++++++++++-------- src/devices/video/mb86292.h | 11 +- src/devices/video/pc_vga_matrox.cpp | 5 +- src/mame/pc/pcipc.cpp | 7 +- 5 files changed, 339 insertions(+), 138 deletions(-) diff --git a/src/devices/machine/8042kbdc.cpp b/src/devices/machine/8042kbdc.cpp index c1891a89f86..1c1d471083a 100644 --- a/src/devices/machine/8042kbdc.cpp +++ b/src/devices/machine/8042kbdc.cpp @@ -393,6 +393,8 @@ void kbdc8042_device::data_w(offs_t offset, uint8_t data) m_mouse.from_transmit = 0; m_mouse.to_transmit = 0; m_mouse.reporting = false; + m_mouse.reporting = true; + m_mouse.on = true; if (m_mouse.on) { mouse_enqueue(0xfa); diff --git a/src/devices/video/mb86292.cpp b/src/devices/video/mb86292.cpp index 8556e352029..94e79d26a57 100644 --- a/src/devices/video/mb86292.cpp +++ b/src/devices/video/mb86292.cpp @@ -6,14 +6,33 @@ #include "screen.h" -//#define LOG_CONFIG (1U << 1) +#define LOG_WARN (1U << 1) +#define LOG_REGS (1U << 2) +#define LOG_CRTC (1U << 3) -#define VERBOSE (LOG_GENERAL) +#define VERBOSE (LOG_GENERAL | LOG_WARN | LOG_REGS | LOG_CRTC) +//#define LOG_OUTPUT_FUNC osd_printf_info #include "logmacro.h" -//MB86290 / MB86290A +#define LOGWARN(...) LOGMASKED(LOG_WARN, __VA_ARGS__) +#define LOGREGS(...) LOGMASKED(LOG_REGS, __VA_ARGS__) +#define LOGCRTC(...) LOGMASKED(LOG_CRTC, __VA_ARGS__) + +//DEFINE_DEVICE_TYPE(MB86290A, mb86290a_device, "mb86290a", "Fujitsu MB86290A \"Cremson\" Graphics Controller") //DEFINE_DEVICE_TYPE(MB86291, mb86291_device, "mb86291", "Fujitsu MB86291 \"Scarlet\" Graphics Controller") DEFINE_DEVICE_TYPE(MB86292, mb86292_device, "mb86292", "Fujitsu MB86292 \"Orchid\" Graphics Controller") +//DEFINE_DEVICE_TYPE(MB86293, mb86293_device, "mb86293", "Fujitsu MB86293 \"Coral LQ\" Graphics Controller") +//DEFINE_DEVICE_TYPE(MB86294, mb86294_device, "mb86294", "Fujitsu MB86294 \"Coral LB\" Graphics Controller") +//DEFINE_DEVICE_TYPE(MB86294S, mb86294s_device, "mb86294s", "Fujitsu MB86294S \"Coral LB\" Graphics Controller") +// PCI, to move in sub-file +//DEFINE_DEVICE_TYPE(MB86295S, mb86295s_device, "mb86295s", "Fujitsu MB86295S \"Coral P\" Graphics Controller") +// set_ids(0x10cf2019, , 0x038000, ); +// INTA# +//DEFINE_DEVICE_TYPE(MB86296S, mb86296s_device, "mb86296s", "Fujitsu MB86296S \"Coral PA\" Graphics Controller") +// set_ids(0x10cf201e, , 0x038000, ); +//DEFINE_DEVICE_TYPE(MB86297A, mb86297a_device, "mb86297a", "Fujitsu MB86297A \"Carmine\" Graphics Controller") +// set_ids(0x10cf202b, , 0x038000, ); + mb86292_device::mb86292_device(machine_config const &mconfig, device_type type, char const *tag, device_t *owner, u32 clock) : device_t(mconfig, type, tag, owner, clock) @@ -30,154 +49,325 @@ mb86292_device::mb86292_device(machine_config const &mconfig, char const *tag, d void mb86292_device::device_start() { + save_item(NAME(m_dce)); + save_item(STRUCT_MEMBER(m_crtc, hdp)); + save_item(STRUCT_MEMBER(m_crtc, hdb)); + save_item(STRUCT_MEMBER(m_crtc, hsp)); + save_item(STRUCT_MEMBER(m_crtc, hsw)); + save_item(STRUCT_MEMBER(m_crtc, vtr)); + save_item(STRUCT_MEMBER(m_crtc, vsp)); + save_item(STRUCT_MEMBER(m_crtc, vdp)); + save_item(STRUCT_MEMBER(m_crtc, vsw)); } void mb86292_device::device_reset() { + m_dce = 0; } void mb86292_device::vregs_map(address_map &map) { // 0x1fc0000 Host interface HostBase -// map(0x00000, 0x00003) DTC DMA Transfer Count -// map(0x00004, 0x00004) DSU DMA Set Up -// map(0x00005, 0x00005) DRM DMA Request Mask -// map(0x00006, 0x00006) DST DMA STatus -// map(0x00008, 0x00008) DTS DMA Transfer Stop -// map(0x00009, 0x00009) LTS display [List] Transfer Stop -// map(0x00010, 0x00010) LSTA display List Transfer STAtus -// map(0x00018, 0x00018) DRQ DMA ReQuest -// map(0x00020, 0x00023) IST Interrupt STatus -// map(0x00024, 0x00027) MASK Interrupt MASK -// map(0x0002c, 0x0002c) SRST Software ReSeT -// map(0x00040, 0x00043) LSA display List Source Address -// map(0x00044, 0x00047) LCO display List COunt -// map(0x00048, 0x00048) LREQ display List transfer REQuest -// map(0x0fffc, 0x0ffff) MMR Memory I/F Mode Register +// map(0x00000, 0x00003) DTC DMA Transfer Count +// map(0x00004, 0x00004) DSU DMA Set Up +// map(0x00005, 0x00005) DRM DMA Request Mask +// map(0x00006, 0x00006) DST DMA STatus +// map(0x00008, 0x00008) DTS DMA Transfer Stop +// map(0x00009, 0x00009) LTS display [List] Transfer Stop +// map(0x00010, 0x00010) LSTA display List Transfer STAtus +// map(0x00018, 0x00018) DRQ DMA ReQuest +// map(0x00020, 0x00023) IST Interrupt STatus +// map(0x00024, 0x00027) MASK Interrupt MASK +// map(0x0002c, 0x0002c) SRST Software ReSeT +// map(0x00040, 0x00043) LSA display List Source Address +// map(0x00044, 0x00047) LCO display List COunt +// map(0x00048, 0x00048) LREQ display List transfer REQuest +// map(0x0fffc, 0x0ffff) MMR Memory I/F Mode Register // 0x1fd0000 Display engine DisplayBase -// map(0x10000, 0x10001) DCM Display Control Mode -// map(0x10002, 0x10003) DCE Display Controller Enable -// map(0x10006, 0x10007) HTP Horizontal Total Pixels -// map(0x10008, 0x10009) HDP Horizontal Display Period -// map(0x1000a, 0x1000b) HDB Horizontal Display Boundary -// map(0x1000c, 0x1000d) HSP Horizontal Sync pulse Position -// map(0x1000e, 0x1000e) HSW Horizontal Sync pulse Width -// map(0x1000f, 0x1000f) VSW Vertical Sync pulse Width -// map(0x10012, 0x10013) VTR Vertical Total Rasters -// map(0x10014, 0x10015) VSP Vertical Sync pulse Position -// map(0x10016, 0x10017) VDP Vertical Display Period -// map(0x10018, 0x10019) WX Window position X -// map(0x1001a, 0x1001b) WX Window position Y -// map(0x1001c, 0x1001d) WW Window Width -// map(0x1001e, 0x1001f) WH Window Height -// map(0x10020, 0x10023) CM C[onsole] layer Mode -// map(0x10024, 0x10027) COA C layer Origin Address -// map(0x10028, 0x1002b) CDA C layer Display Address -// map(0x1002c, 0x1002d) CDX C layer Display position X -// map(0x1002e, 0x1002f) CDY C layer Display position Y -// map(0x10030, 0x10033) WM W[indow] layer Mode -// map(0x10034, 0x10037) WOA W layer Origin Address -// map(0x10038, 0x1003b) WDA W layer Display Address -// map(0x10040, 0x10043) MLM M[iddle] L[eft] layer Mode -// map(0x10044, 0x10047) MLOA0 ML Origin Address 0 -// map(0x10048, 0x1004b) MLDA0 ML Display Address 0 -// map(0x1004c, 0x1004f) MLOA1 ML Origin Address 1 -// map(0x10050, 0x10053) MLDA1 ML Display Address 1 -// map(0x10054, 0x10055) MLDX ML Display position X -// map(0x10056, 0x10057) MLDY ML Display position Y -// map(0x10058, 0x1005b) MRM M[iddle] R[ight] layer Mode -// map(0x1005c, 0x1005f) MROA0 MR Origin Address 0 -// map(0x10060, 0x10063) MRDA0 MR Display Address 0 -// map(0x10064, 0x1004f) MROA1 MR Origin Address 1 -// map(0x10068, 0x10053) MRDA1 MR Display Address 1 -// map(0x1006c, 0x1006d) MRDX MR Display position X -// map(0x1006e, 0x1006f) MRDY MR Display position Y -// map(0x10070, 0x10073) BLM B[ase] L[eft] layer Mode -// map(0x10074, 0x10077) BLOA0 BL Origin Address 0 -// map(0x10078, 0x1007b) BLDA0 BL Display Address 0 -// map(0x1007c, 0x1007f) BLOA1 BL Origin Address 1 -// map(0x10080, 0x10083) BLDA1 BL Display Address 1 -// map(0x10084, 0x10085) BLDX BL Display position X -// map(0x10086, 0x10087) BLDY BL Display position Y -// map(0x10088, 0x1008b) BRM B[ase] R[ight] layer Mode -// map(0x1008c, 0x1008f) BROA0 BR Origin Address 0 -// map(0x10090, 0x10093) BRDA0 BR Display Address 0 -// map(0x10094, 0x10097) BROA1 BR Origin Address 1 -// map(0x10098, 0x1009b) BRDA1 BR Display Address 1 -// map(0x1009c, 0x1009d) BRDX BR Display position X -// map(0x1009e, 0x1009f) BRDY BR Display position Y -// map(0x100a0, 0x100a1) CUTC Cursor Transparent Control -// map(0x100a2, 0x100a2) CPM Cursor Priority Mode -// map(0x100a4, 0x100a7) CUOA0 CUrsor 0 Origin Address -// map(0x100a8, 0x100a9) CUX0 CUrsor 0 X position -// map(0x100aa, 0x100ab) CUY0 CUrsor 0 Y position -// map(0x100ac, 0x100af) CUOA1 CUrsor 1 Origin Address -// map(0x100b0, 0x100b1) CUX1 CUrsor 1 X position -// map(0x100b2, 0x100b3) CUY1 CUrsor 1 Y position -// map(0x100b4, 0x100b5) BRATIO Blend RATIO -// map(0x100b6, 0x100b7) BMODE Blend MODE -// map(0x100bc, 0x100bd) CTC C layer Transparent Control -// map(0x100c0, 0x100c1) MRTC MR layer Transparent Control -// map(0x100c2, 0x100c3) MLTC ML layer Transparent Control -// map(0x10400, 0x107ff) CPAL C layer PALette -// map(0x10800, 0x10bff) MBPAL M & B layer PALette +// map(0x10000, 0x10001) DCM Display Control Mode + // DCE Display Controller Enable + map(0x10002, 0x10003).lrw16( + NAME([this] (offs_t offset) { + return m_dce; + }), + NAME([this] (offs_t offset, u16 data, u16 mem_mask) { + COMBINE_DATA(&m_dce); + LOGREGS("DCE %04x & %04x\n", data, mem_mask); + }) + ); + // HTP Horizontal Total Pixels + map(0x10006, 0x10007).lrw16( + NAME([this] (offs_t offset) { + return m_crtc.htp; + }), + NAME([this] (offs_t offset, u16 data, u16 mem_mask) { + COMBINE_DATA(&m_crtc.htp); + m_crtc.htp &= 0xfff; + LOGCRTC("HTP %04x & %04x -> %d\n", data, mem_mask, m_crtc.htp + 1); + reconfigure_screen(); + }) + ); + // HDP Horizontal Display Period + map(0x10008, 0x10009).lrw16( + NAME([this] (offs_t offset) { + return m_crtc.hdp; + }), + NAME([this] (offs_t offset, u16 data, u16 mem_mask) { + COMBINE_DATA(&m_crtc.hdp); + m_crtc.hdp &= 0xfff; + LOGCRTC("HDP %04x & %04x -> %d\n", data, mem_mask, m_crtc.hdp + 1); + reconfigure_screen(); + }) + ); + // HDB Horizontal Display Boundary + map(0x1000a, 0x1000b).lrw16( + NAME([this] (offs_t offset) { + return m_crtc.hdb; + }), + NAME([this] (offs_t offset, u16 data, u16 mem_mask) { + COMBINE_DATA(&m_crtc.hdb); + m_crtc.hdb &= 0xfff; + LOGCRTC("HDB %04x & %04x -> %d\n", data, mem_mask, m_crtc.hdb + 1); + reconfigure_screen(); + }) + ); + // HSP Horizontal Sync pulse Position + map(0x1000c, 0x1000d).lrw16( + NAME([this] (offs_t offset) { + return m_crtc.hsp; + }), + NAME([this] (offs_t offset, u16 data, u16 mem_mask) { + COMBINE_DATA(&m_crtc.hsp); + m_crtc.hsp &= 0xfff; + LOGCRTC("HSP %04x & %04x -> %d\n", data, mem_mask, m_crtc.hsp + 1); + reconfigure_screen(); + }) + ); + // HSW Horizontal Sync pulse Width + map(0x1000e, 0x1000e).lrw8( + NAME([this] (offs_t offset) { + return m_crtc.hsw; + }), + NAME([this] (offs_t offset, u8 data) { + m_crtc.hsw = (data & 0x3f); + LOGCRTC("HSW %04x -> %d\n", data, m_crtc.hsw + 1); + reconfigure_screen(); + }) + ); + // VSW Vertical Sync pulse Width + map(0x1000f, 0x1000f).lrw8( + NAME([this] (offs_t offset) { + return m_crtc.vsw; + }), + NAME([this] (offs_t offset, u8 data) { + m_crtc.vsw = (data & 0x3f); + LOGCRTC("VSW %04x -> %d\n", data, m_crtc.vsw + 1); + reconfigure_screen(); + }) + ); + // VTR Vertical Total Rasters + map(0x10012, 0x10013).lrw16( + NAME([this] (offs_t offset) { + return m_crtc.vtr; + }), + NAME([this] (offs_t offset, u16 data, u16 mem_mask) { + COMBINE_DATA(&m_crtc.vtr); + m_crtc.vtr &= 0xfff; + // actually +1.5 & +3 for interlace mode fields + LOGCRTC("VTR %04x & %04x -> %d\n", data, mem_mask, m_crtc.vtr + 1); + reconfigure_screen(); + }) + ); + // VSP Vertical Sync pulse Position + map(0x10014, 0x10015).lrw16( + NAME([this] (offs_t offset) { + return m_crtc.vsp; + }), + NAME([this] (offs_t offset, u16 data, u16 mem_mask) { + COMBINE_DATA(&m_crtc.vsp); + m_crtc.vsp &= 0xfff; + LOGCRTC("VSP %04x & %04x -> %d\n", data, mem_mask, m_crtc.vsp + 1); + reconfigure_screen(); + }) + ); + // VDP Vertical Display Period + map(0x10016, 0x10017).lrw16( + NAME([this] (offs_t offset) { + return m_crtc.vdp; + }), + NAME([this] (offs_t offset, u16 data, u16 mem_mask) { + COMBINE_DATA(&m_crtc.vdp); + m_crtc.vdp &= 0xfff; + LOGCRTC("VDP %04x & %04x -> %d\n", data, mem_mask, m_crtc.vdp + 1); + reconfigure_screen(); + }) + ); +// map(0x10018, 0x10019) WX Window position X +// map(0x1001a, 0x1001b) WX Window position Y +// map(0x1001c, 0x1001d) WW Window Width +// map(0x1001e, 0x1001f) WH Window Height +// map(0x10020, 0x10023) CM C[onsole] layer Mode +// map(0x10024, 0x10027) COA C layer Origin Address +// map(0x10028, 0x1002b) CDA C layer Display Address +// map(0x1002c, 0x1002d) CDX C layer Display position X +// map(0x1002e, 0x1002f) CDY C layer Display position Y +// map(0x10030, 0x10033) WM W[indow] layer Mode +// map(0x10034, 0x10037) WOA W layer Origin Address +// map(0x10038, 0x1003b) WDA W layer Display Address +// map(0x10040, 0x10043) MLM M[iddle] L[eft] layer Mode +// map(0x10044, 0x10047) MLOA0 ML Origin Address 0 +// map(0x10048, 0x1004b) MLDA0 ML Display Address 0 +// map(0x1004c, 0x1004f) MLOA1 ML Origin Address 1 +// map(0x10050, 0x10053) MLDA1 ML Display Address 1 +// map(0x10054, 0x10055) MLDX ML Display position X +// map(0x10056, 0x10057) MLDY ML Display position Y +// map(0x10058, 0x1005b) MRM M[iddle] R[ight] layer Mode +// map(0x1005c, 0x1005f) MROA0 MR Origin Address 0 +// map(0x10060, 0x10063) MRDA0 MR Display Address 0 +// map(0x10064, 0x10067) MROA1 MR Origin Address 1 +// map(0x10068, 0x1006b) MRDA1 MR Display Address 1 +// map(0x1006c, 0x1006d) MRDX MR Display position X +// map(0x1006e, 0x1006f) MRDY MR Display position Y +// map(0x10070, 0x10073) BLM B[ase] L[eft] layer Mode +// map(0x10074, 0x10077) BLOA0 BL Origin Address 0 +// map(0x10078, 0x1007b) BLDA0 BL Display Address 0 +// map(0x1007c, 0x1007f) BLOA1 BL Origin Address 1 +// map(0x10080, 0x10083) BLDA1 BL Display Address 1 +// map(0x10084, 0x10085) BLDX BL Display position X +// map(0x10086, 0x10087) BLDY BL Display position Y +// map(0x10088, 0x1008b) BRM B[ase] R[ight] layer Mode +// map(0x1008c, 0x1008f) BROA0 BR Origin Address 0 +// map(0x10090, 0x10093) BRDA0 BR Display Address 0 +// map(0x10094, 0x10097) BROA1 BR Origin Address 1 +// map(0x10098, 0x1009b) BRDA1 BR Display Address 1 +// map(0x1009c, 0x1009d) BRDX BR Display position X +// map(0x1009e, 0x1009f) BRDY BR Display position Y +// map(0x100a0, 0x100a1) CUTC Cursor Transparent Control +// map(0x100a2, 0x100a2) CPM Cursor Priority Mode +// map(0x100a4, 0x100a7) CUOA0 CUrsor 0 Origin Address +// map(0x100a8, 0x100a9) CUX0 CUrsor 0 X position +// map(0x100aa, 0x100ab) CUY0 CUrsor 0 Y position +// map(0x100ac, 0x100af) CUOA1 CUrsor 1 Origin Address +// map(0x100b0, 0x100b1) CUX1 CUrsor 1 X position +// map(0x100b2, 0x100b3) CUY1 CUrsor 1 Y position +// map(0x100b4, 0x100b5) BRATIO Blend RATIO +// map(0x100b6, 0x100b7) BMODE Blend MODE +// map(0x100bc, 0x100bd) CTC C layer Transparent Control +// map(0x100c0, 0x100c1) MRTC MR layer Transparent Control +// map(0x100c2, 0x100c3) MLTC ML layer Transparent Control +// map(0x10400, 0x107ff) CPAL C layer PALette +// map(0x10800, 0x10bff) MBPAL M & B layer PALette // 0x1fd8000 Video capture CaptureBase -// map(0x18000, 0x18003) VCM Video Capture Mode -// map(0x18004, 0x18007) CSC Capture SCale -// map(0x18008, 0x1800b) VCS Video Capture Status -// map(0x18010, 0x18013) CBM video Capture Buffer Mode -// map(0x18014, 0x18017) CBOA video Capture Buffer Origin Address -// map(0x18018, 0x1801b) CBLA video Capture Buffer Limit Address -// map(0x1801c, 0x1801d) CIHSTR Capture Image Horizontal STaRt -// map(0x1801e, 0x1801f) CIVSTR Capture Image Vertical STaRt -// map(0x18020, 0x18021) CIHEND Capture Image Horizontal END -// map(0x18022, 0x18023) CIVEND Capture Image Vertical END -// map(0x18028, 0x1802b) CHP Capture Horizontal Pixel -// map(0x1802c, 0x1802f) CVP Capture Vertical Pixel -// map(0x1c000, 0x1c003) CDCN Capture Data Count NTSC -// map(0x1c004, 0x1c007) CDCP Capture Data Count PAL +// map(0x18000, 0x18003) VCM Video Capture Mode +// map(0x18004, 0x18007) CSC Capture SCale +// map(0x18008, 0x1800b) VCS Video Capture Status +// map(0x18010, 0x18013) CBM video Capture Buffer Mode +// map(0x18014, 0x18017) CBOA video Capture Buffer Origin Address +// map(0x18018, 0x1801b) CBLA video Capture Buffer Limit Address +// map(0x1801c, 0x1801d) CIHSTR Capture Image Horizontal STaRt +// map(0x1801e, 0x1801f) CIVSTR Capture Image Vertical STaRt +// map(0x18020, 0x18021) CIHEND Capture Image Horizontal END +// map(0x18022, 0x18023) CIVEND Capture Image Vertical END +// map(0x18028, 0x1802b) CHP Capture Horizontal Pixel +// map(0x1802c, 0x1802f) CVP Capture Vertical Pixel +// map(0x1c000, 0x1c003) CDCN Capture Data Count NTSC +// map(0x1c004, 0x1c007) CDCP Capture Data Count PAL // 0x1fe0000 Internal texture memory TextureBase -// map(0x20000, ...) +// map(0x20000, ...) // 0x1ff0000 Drawing engine DrawBase -// map(0x30400, 0x30403) CTR ConTrol Register -// map(0x30404, 0x30407) IFSR Input FIFO Status Register (CTR bits 14-12 alias) -// map(0x30408, 0x3040b) IFCNT Input FIFO CouNTer (CTR bits 19-15 alias) -// map(0x3040c, 0x3040f) SST Setup engine STatus (CTR bits 9-8 alias) -// map(0x30410, 0x30413) DST DDA STatus (CTR bits 5-4 alias) -// map(0x30414, 0x30417) PST Pixel engine STatus (CTR bits 1-0 alias) -// map(0x30418, 0x3041b) EST Error STatus (CTR bits 24-22 alias) -// map(0x30420, 0x30423) MDR0 MoDe Register 0 (miscellaneous) -// map(0x30424, 0x30427) MDR1 MoDe Register 1 (line) -// map(0x30428, 0x3042b) MDR2 MoDe Register 2 (polygon) -// map(0x3042c, 0x3042f) MDR3 MoDe Register 3 (texture) -// map(0x30430, 0x30433) MDR4 MoDe Register 4 (BitBLT) -// map(0x30440, 0x30443) FBR Frame Buffer Register base address -// map(0x30444, 0x30447) XRES X RESoultion -// map(0x30448, 0x3044b) ZBR Z-Buffer Register base address -// map(0x3044c, 0x3044f) TBR Texture memory Base address -// map(0x30450, 0x30453) PFBR 2d Polygon Flag Buffer base address -// map(0x30454, 0x30457) CXMIN Clip X MINimum -// map(0x30458, 0x3045b) CXMAX Clip X MAXimum -// map(0x3045c, 0x3045f) CYMIN Clip Y MINimum -// map(0x30460, 0x30463) CYMAX Clip Y MAXimum -// map(0x30464, 0x30467) TXS TeXture Size -// map(0x30468, 0x3046b) TIle Size -// map(0x3046c, 0x3046f) TOA Texture buffer Offset Address -// map(0x30480, 0x30483) FC Foreground Color -// map(0x30484, 0x30487) BC Background Color -// map(0x30488, 0x3048b) ALF ALpha Factor -// map(0x3048c, 0x3048f) BLP Broken Line Pattern -// map(0x303e0?, 0x303e3?) BLPO Broken Line Pattern Offset <- assume doc mistake, 0x490 seems more realistic -// map(0x30494, 0x30497) TBC Texture Border Color -// Other stuff in the area are apparently r/o copies of the drawing engine internals. +// map(0x30400, 0x30403) CTR ConTrol Register +// map(0x30404, 0x30407) IFSR Input FIFO Status Register (CTR bits 14-12 alias) +// map(0x30408, 0x3040b) IFCNT Input FIFO CouNTer (CTR bits 19-15 alias) +// map(0x3040c, 0x3040f) SST Setup engine STatus (CTR bits 9-8 alias) +// map(0x30410, 0x30413) DST DDA STatus (CTR bits 5-4 alias) +// map(0x30414, 0x30417) PST Pixel engine STatus (CTR bits 1-0 alias) +// map(0x30418, 0x3041b) EST Error STatus (CTR bits 24-22 alias) +// map(0x30420, 0x30423) MDR0 MoDe Register 0 (miscellaneous) +// map(0x30424, 0x30427) MDR1 MoDe Register 1 (line) +// map(0x30428, 0x3042b) MDR2 MoDe Register 2 (polygon) +// map(0x3042c, 0x3042f) MDR3 MoDe Register 3 (texture) +// map(0x30430, 0x30433) MDR4 MoDe Register 4 (BitBLT) +// map(0x30440, 0x30443) FBR Frame Buffer Register base address +// map(0x30444, 0x30447) XRES X RESoultion +// map(0x30448, 0x3044b) ZBR Z-Buffer Register base address +// map(0x3044c, 0x3044f) TBR Texture memory Base address +// map(0x30450, 0x30453) PFBR 2d Polygon Flag Buffer base address +// map(0x30454, 0x30457) CXMIN Clip X MINimum +// map(0x30458, 0x3045b) CXMAX Clip X MAXimum +// map(0x3045c, 0x3045f) CYMIN Clip Y MINimum +// map(0x30460, 0x30463) CYMAX Clip Y MAXimum +// map(0x30464, 0x30467) TXS TeXture Size +// map(0x30468, 0x3046b) TIle Size +// map(0x3046c, 0x3046f) TOA Texture buffer Offset Address +// map(0x30480, 0x30483) FC Foreground Color +// map(0x30484, 0x30487) BC Background Color +// map(0x30488, 0x3048b) ALF ALpha Factor +// map(0x3048c, 0x3048f) BLP Broken Line Pattern +// map(0x303e0?, 0x303e3?) BLPO Broken Line Pattern Offset <- assume doc mistake, 0x490 seems more realistic +// map(0x30494, 0x30497) TBC Texture Border Color +// Other stuff in the area are apparently r/o copies of the drawing engine internals. // 0x1ff8000 Geometry engine GeometryBase -// map(0x38000, ...) +// map(0x38000, 0x38000) GCTR Geometry ConTrol Register +// map(0x38040, 0x38043) GMDR0 Geometry MoDe Register 0 (vertex) +// map(0x38044, 0x38047) GMDR1 Geometry MoDe Register 1 (line) +// map(0x38048, 0x3804b) GMDR2 Geometry MoDe Register 2 (triangle) +// map(0x38400, 0x38403) DFIFOG Display List FIFO for Geometry +} + +void mb86292_device::reconfigure_screen() +{ + const u16 hdb = m_crtc.hdb + 1; + const u16 hdp = m_crtc.hdp + 1; + const u16 hsp = m_crtc.hsp + 1; + const u16 hse = hsp + m_crtc.hsw + 1; + const u16 htp = m_crtc.htp + 1; + // 0 < m_crtc.hdb <= m_crtc.hdp < m_crtc.hsp < (m_crtc.hsp + m_crtc.hsw + 1) < m_crtc.htp + std::array horiz_assert = { + 0 < hdb, + hdb <= hdp, + hdp < hsp, + hsp < hse, + hse < htp + }; + if (!std::all_of(horiz_assert.begin(), horiz_assert.end(), [](bool res) { return res; })) + { + LOGCRTC("\tScreen off (H)\n"); + return; + } + const u16 vdp = m_crtc.vdp + 1; + const u16 vsp = m_crtc.vsp + 1; + const u16 vse = (vsp + m_crtc.vsw + 1); + const u16 vtr = m_crtc.vtr + 1; + // 0 < m_crtc.vdp < m_crtc.vsp < (m_crtc.vsp + m_crtc.vsw + 1) < m_crtc.vtr + std::array vert_assert = { + 0 < vdp, + vdp <= vsp, + vsp < vse, + vse < vtr + }; + if (!std::all_of(vert_assert.begin(), vert_assert.end(), [](bool res) { return res; })) + { + LOGCRTC("\tScreen off (V)\n"); + return; + } + // TODO: refresh rate, interlace, sync + // Supported resolutions: + // 1024x768, 1024x600, 800x600, 854x480, 640x480, 480x234, 400x234, 320x234 + LOGCRTC("\tSetting screen to %d x %d (total: %d x %d)\n", hdp, vdp, htp, vtr); + rectangle visarea(0, hdp - 1, 0, vdp - 1); + screen().configure(htp, vtr, visarea, screen().frame_period().attoseconds()); } u32 mb86292_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, rectangle const &cliprect) { + if (!BIT(m_dce, 15) || ((m_dce & 0x0f) == 0)) + { + bitmap.fill(rgb_t::black(), cliprect); + return 0; + } + // mariojjl / mmaruchan has two RGB555 charsets at $36d80 & $150600 (pitch=128) // pingu has one at $96000 // all Medalusion games also loads up a display list at $780000, which references above and diff --git a/src/devices/video/mb86292.h b/src/devices/video/mb86292.h index b164f291fb3..1be508a14c4 100644 --- a/src/devices/video/mb86292.h +++ b/src/devices/video/mb86292.h @@ -8,7 +8,7 @@ #include "machine/ram.h" class mb86292_device : public device_t, - public device_video_interface + public device_video_interface { public: mb86292_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); @@ -30,6 +30,15 @@ protected: required_device m_screen; required_device m_vram; + + void reconfigure_screen(); +private: + u16 m_dce = 0; + struct { + u16 htp = 0, hdp = 0, hdb = 0, hsp = 0; + u16 vtr = 0, vsp = 0, vdp = 0; + u8 hsw = 0, vsw = 0; + } m_crtc; }; DECLARE_DEVICE_TYPE(MB86292, mb86292_device) diff --git a/src/devices/video/pc_vga_matrox.cpp b/src/devices/video/pc_vga_matrox.cpp index a5fe8bca111..ed2217abd45 100644 --- a/src/devices/video/pc_vga_matrox.cpp +++ b/src/devices/video/pc_vga_matrox.cpp @@ -481,7 +481,7 @@ void matrox_vga_device::recompute_params() // TODO: stub, derives from RAMDAC PLLs (MGA2064W has usual rates of 220 MHz) case 2: default: - xtal = XTAL(50'000'000).value(); + xtal = XTAL(50'000'000 / 2).value(); break; } @@ -501,7 +501,8 @@ uint16_t matrox_vga_device::offset() uint32_t matrox_vga_device::start_addr() { // TODO: fails VBEtest scrolling tests -// if (m_mgamode) + if (m_mgamode) + popmessage("%08x", vga.crtc.start_addr); // return (vga.crtc.start_addr << 4); return svga_device::start_addr(); diff --git a/src/mame/pc/pcipc.cpp b/src/mame/pc/pcipc.cpp index f72b2b8a77d..ded0345e729 100644 --- a/src/mame/pc/pcipc.cpp +++ b/src/mame/pc/pcipc.cpp @@ -611,7 +611,9 @@ void pcipc_state::pcipctx(machine_config &config) void pcipc_state::pcinv3(machine_config &config) { pcipc_state::pcipc(config); - RIVA128(config.replace(), "pci:12.0", 0); +// RIVA128(config.replace(), "pci:12.0", 0); + MGA2064W(config.replace(), "pci:12.0", 0); + } void pcipc_state::pciagp(machine_config &config) @@ -684,9 +686,6 @@ ROM_START(pcipctx) ROM_REGION32_LE(0x40000, "pci:07.0", 0) /* PC bios */ ROM_SYSTEM_BIOS(0, "ga586t2", "Gigabyte GA-586T2") // ITE 8679 I/O ROMX_LOAD("gb_ga586t2.bin", 0x20000, 0x20000, CRC(3a50a6e1) SHA1(dea859b4f1492d0d08aacd260ed1e83e00ebac08), ROM_BIOS(0)) - - ROM_REGION(0x8000,"ibm_vga", 0) - ROM_LOAD("ibm-vga.bin", 0x00000, 0x8000, BAD_DUMP CRC(74e3fadb) SHA1(dce6491424f1726203776dfae9a967a98a4ba7b5) ) ROM_END ROM_START(pcinv3)