Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-05-10 16:21:42 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

mb86233.c: Modernized cpu core (nw)

Browse Source
This commit is contained in:
Wilbert Pol 2013-08-20 20:19:52 +00:00
parent 72129f3d1f
commit f38babb223
7 changed files with 437 additions and 436 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

628
src/emu/cpu/mb86233/mb86233.c
View File

File diff suppressed because it is too large Load Diff

105
src/emu/cpu/mb86233/mb86233.h
View File

@ -38,20 +38,105 @@ enum
MB86233_R15
};
/***************************************************************************
STRUCTURES
***************************************************************************/
typedef int (*mb86233_fifo_read_func)(device_t *device, UINT32 *data);
typedef void (*mb86233_fifo_write_func)(device_t *device, UINT32 data);
#define MCFG_MB86233_FIFO_READ_CB(_devcb) mb86233_cpu_device::set_fifo_read_cb(*device, DEVCB2_##_devcb);
#define MCFG_MB86233_FIFO_READ_OK_CB(_devcb) mb86233_cpu_device::set_fifo_read_ok_cb(*device, DEVCB2_##_devcb);
#define MCFG_MB86233_FIFO_WRITE_CB(_devcb) mb86233_cpu_device::set_fifo_write_cb(*device, DEVCB2_##_devcb);
#define MCFG_MB86233_TABLE_REGION(_region) mb86233_cpu_device::set_tablergn(*device, _region);
struct mb86233_cpu_core
class mb86233_cpu_device : public cpu_device
{
mb86233_fifo_read_func fifo_read_cb;
mb86233_fifo_write_func fifo_write_cb;
const char *tablergn;
public:
// construction/destruction
mb86233_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// static configuration helpers
template<class _Object> static devcb2_base &set_fifo_read_cb(device_t &device, _Object object) { return downcast<mb86233_cpu_device &>(device).m_fifo_read_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_fifo_read_ok_cb(device_t &device, _Object object) { return downcast<mb86233_cpu_device &>(device).m_fifo_read_ok_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_fifo_write_cb(device_t &device, _Object object) { return downcast<mb86233_cpu_device &>(device).m_fifo_write_cb.set_callback(object); }
static void set_tablergn(device_t &device, const char *tablergn) { downcast<mb86233_cpu_device &>(device).m_tablergn = tablergn; }
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const { return 1; }
virtual UINT32 execute_max_cycles() const { return 2; }
virtual UINT32 execute_input_lines() const { return 0; }
virtual void execute_run();
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ); }
// device_state_interface overrides
void state_string_export(const device_state_entry &entry, astring &string);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 4; }
virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
private:
address_space_config m_program_config;
address_space_config m_data_config;
union MB86233_REG
{
INT32 i;
UINT32 u;
float f;
};
UINT16 m_pc;
MB86233_REG m_a;
MB86233_REG m_b;
MB86233_REG m_d;
MB86233_REG m_p;
UINT16 m_reps;
UINT16 m_pcs[4];
UINT8 m_pcsp;
UINT32 m_eb;
UINT32 m_shift;
UINT32 m_repcnt;
UINT16 m_sr;
UINT32 m_gpr[16];
UINT32 m_extport[0x30];
address_space *m_program;
direct_read_data *m_direct;
int m_icount;
/* FIFO */
int m_fifo_wait;
devcb2_read32 m_fifo_read_cb;
devcb2_read_line m_fifo_read_ok_cb;
devcb2_write32 m_fifo_write_cb;
const char *m_tablergn;
/* internal RAM */
UINT32 m_RAM[2 * 0x200];
UINT32 *m_ARAM, *m_BRAM;
UINT32 *m_Tables;
void FLAGSF( float v );
void FLAGSI( UINT32 v );
int COND( UINT32 cond );
void ALU( UINT32 alu);
UINT32 ScaleExp(unsigned int v,int scale);
UINT32 GETEXTERNAL( UINT32 EB, UINT32 offset );
void SETEXTERNAL( UINT32 EB, UINT32 offset, UINT32 value );
UINT32 GETREGS( UINT32 reg, int source );
void SETREGS( UINT32 reg, UINT32 val );
UINT32 INDIRECT( UINT32 reg, int source );
};
DECLARE_LEGACY_CPU_DEVICE(MB86233, mb86233);
extern const device_type MB86233;
#endif /* __MB86233_H__ */

5
src/mame/drivers/model1.c
View File

@ -1594,8 +1594,11 @@ static MACHINE_CONFIG_START( model1_vr, model1_state )
MCFG_CPU_PROGRAM_MAP(model1_snd)
MCFG_CPU_ADD("tgp", MB86233, 16000000)
MCFG_CPU_CONFIG(model1_vr_tgp_config)
MCFG_CPU_PROGRAM_MAP(model1_vr_tgp_map)
MCFG_MB86233_FIFO_READ_CB(READ32(model1_state,copro_fifoin_pop))
MCFG_MB86233_FIFO_READ_OK_CB(READLINE(model1_state,copro_fifoin_pop_ok))
MCFG_MB86233_FIFO_WRITE_CB(WRITE32(model1_state,copro_fifoout_push))
MCFG_MB86233_TABLE_REGION("user5")
MCFG_MACHINE_START_OVERRIDE(model1_state,model1)
MCFG_MACHINE_RESET_OVERRIDE(model1_state,model1_vr)

66
src/mame/drivers/model2.c
View File

@ -147,6 +147,32 @@ static int copro_fifoin_pop(device_t *device, UINT32 *result)
return 1;
}
READ_LINE_MEMBER(model2_state::copro_tgp_fifoin_pop_ok)
{
if (m_copro_fifoin_num == 0)
{
return CLEAR_LINE;
}
return ASSERT_LINE;
}
READ32_MEMBER(model2_state::copro_tgp_fifoin_pop)
{
UINT32 r = m_copro_fifoin_data[m_copro_fifoin_rpos++];
if (m_copro_fifoin_rpos == COPRO_FIFOIN_SIZE)
{
m_copro_fifoin_rpos = 0;
}
m_copro_fifoin_num--;
return r;
}
static void copro_fifoin_push(device_t *device, UINT32 data)
{
model2_state *state = device->machine().driver_data<model2_state>();
@ -256,6 +282,25 @@ static void copro_fifoout_push(device_t *device, UINT32 data)
}
}
WRITE32_MEMBER(model2_state::copro_tgp_fifoout_push)
{
if (m_copro_fifoout_num == COPRO_FIFOOUT_SIZE)
{
fatalerror("Copro FIFOOUT overflow (at %08X)\n", m_tgp->pc());
return;
}
// logerror("COPRO FIFOOUT PUSH %08X, %f, %d\n", data, *(float*)&data,m_copro_fifoout_num);
m_copro_fifoout_data[m_copro_fifoout_wpos++] = data;
if (m_copro_fifoout_wpos == COPRO_FIFOOUT_SIZE)
{
m_copro_fifoout_wpos = 0;
}
m_copro_fifoout_num++;
}
/* Timers - these count down at 25 MHz and pull IRQ2 when they hit 0 */
READ32_MEMBER(model2_state::timers_r)
{
@ -1951,15 +1996,6 @@ ADDRESS_MAP_END
/*****************************************************************************/
static const mb86233_cpu_core tgp_config =
{
copro_fifoin_pop,
copro_fifoout_push,
"user5",
};
/* original Model 2 */
static MACHINE_CONFIG_START( model2o, model2_state )
MCFG_CPU_ADD("maincpu", I960, 25000000)
@ -1970,8 +2006,12 @@ static MACHINE_CONFIG_START( model2o, model2_state )
MCFG_CPU_PROGRAM_MAP(model1_snd)
MCFG_CPU_ADD("tgp", MB86233, 16000000)
MCFG_CPU_CONFIG(tgp_config)
MCFG_CPU_PROGRAM_MAP(copro_tgp_map)
MCFG_MB86233_FIFO_READ_CB(READ32(model2_state,copro_tgp_fifoin_pop))
MCFG_MB86233_FIFO_READ_OK_CB(READLINE(model2_state,copro_tgp_fifoin_pop_ok))
MCFG_MB86233_FIFO_WRITE_CB(WRITE32(model2_state,copro_tgp_fifoout_push))
MCFG_MB86233_TABLE_REGION("user5")
MCFG_MACHINE_START_OVERRIDE(model2_state,model2)
MCFG_MACHINE_RESET_OVERRIDE(model2_state,model2o)
@ -2029,8 +2069,12 @@ static MACHINE_CONFIG_START( model2a, model2_state )
MCFG_CPU_PROGRAM_MAP(model2_snd)
MCFG_CPU_ADD("tgp", MB86233, 16000000)
MCFG_CPU_CONFIG(tgp_config)
MCFG_CPU_PROGRAM_MAP(copro_tgp_map)
MCFG_MB86233_FIFO_READ_CB(READ32(model2_state,copro_tgp_fifoin_pop))
MCFG_MB86233_FIFO_READ_OK_CB(READLINE(model2_state,copro_tgp_fifoin_pop_ok))
MCFG_MB86233_FIFO_WRITE_CB(WRITE32(model2_state,copro_tgp_fifoout_push))
MCFG_MB86233_TABLE_REGION("user5")
MCFG_MACHINE_START_OVERRIDE(model2_state,model2)
MCFG_MACHINE_RESET_OVERRIDE(model2_state,model2)

6
src/mame/includes/model1.h
View File

@ -16,6 +16,7 @@ public:
m_multipcm_1(*this, "sega1"),
m_multipcm_2(*this, "sega2"),
m_dsbz80(*this, DSBZ80_TAG),
m_tgp(*this, "tgp"),
m_mr2(*this, "mr2"),
m_mr(*this, "mr"),
m_display_list0(*this, "display_list0"),
@ -27,6 +28,7 @@ public:
required_device<multipcm_device> m_multipcm_1;
required_device<multipcm_device> m_multipcm_2;
optional_device<dsbz80_device> m_dsbz80; // Digital Sound Board
optional_device<mb86233_cpu_device> m_tgp;
required_shared_ptr<UINT16> m_mr2;
required_shared_ptr<UINT16> m_mr;
@ -148,12 +150,14 @@ public:
void irq_raise(int level);
void irq_init();
IRQ_CALLBACK_MEMBER(irq_callback);
DECLARE_READ_LINE_MEMBER(copro_fifoin_pop_ok);
DECLARE_READ32_MEMBER(copro_fifoin_pop);
DECLARE_WRITE32_MEMBER(copro_fifoout_push);
};
/*----------- defined in machine/model1.c -----------*/
extern const mb86233_cpu_core model1_vr_tgp_config;
ADDRESS_MAP_EXTERN( model1_vr_tgp_map, 32 );
void model1_vr_tgp_reset( running_machine &machine );

3
src/mame/includes/model2.h
View File

@ -189,6 +189,9 @@ public:
TIMER_DEVICE_CALLBACK_MEMBER(model2c_interrupt);
void model2_exit();
DECLARE_WRITE_LINE_MEMBER(scsp_irq);
DECLARE_READ_LINE_MEMBER(copro_tgp_fifoin_pop_ok);
DECLARE_READ32_MEMBER(copro_tgp_fifoin_pop);
DECLARE_WRITE32_MEMBER(copro_tgp_fifoout_push);
};
/*----------- defined in video/model2.c -----------*/

60
src/mame/machine/model1.c
View File

@ -2047,30 +2047,31 @@ void model1_vr_tgp_reset( running_machine &machine )
}
/* FIFO */
static int copro_fifoin_pop(device_t *device, UINT32 *result)
READ_LINE_MEMBER(model1_state::copro_fifoin_pop_ok)
{
model1_state *state = device->machine().driver_data<model1_state>();
UINT32 r;
if (state->m_copro_fifoin_num == 0)
if (m_copro_fifoin_num == 0)
{
return 0;
return CLEAR_LINE;
}
r = state->m_copro_fifoin_data[state->m_copro_fifoin_rpos++];
if (state->m_copro_fifoin_rpos == FIFO_SIZE)
{
state->m_copro_fifoin_rpos = 0;
}
state->m_copro_fifoin_num--;
*result = r;
return 1;
return ASSERT_LINE;
}
READ32_MEMBER(model1_state::copro_fifoin_pop)
{
UINT32 r = m_copro_fifoin_data[m_copro_fifoin_rpos++];
if (m_copro_fifoin_rpos == FIFO_SIZE)
{
m_copro_fifoin_rpos = 0;
}
m_copro_fifoin_num--;
return r;
}
static void copro_fifoin_push(address_space &space, UINT32 data)
{
model1_state *state = space.machine().driver_data<model1_state>();
@ -2117,23 +2118,22 @@ static UINT32 copro_fifoout_pop(address_space &space)
return r;
}
static void copro_fifoout_push(device_t *device, UINT32 data)
WRITE32_MEMBER(model1_state::copro_fifoout_push)
{
model1_state *state = device->machine().driver_data<model1_state>();
if (state->m_copro_fifoout_num == FIFO_SIZE)
if (m_copro_fifoout_num == FIFO_SIZE)
{
fatalerror("Copro FIFOOUT overflow (at %08X)\n", device->safe_pc());
fatalerror("Copro FIFOOUT overflow (at %08X)\n", m_tgp->pc());
return;
}
state->m_copro_fifoout_data[state->m_copro_fifoout_wpos++] = data;
m_copro_fifoout_data[m_copro_fifoout_wpos++] = data;
if (state->m_copro_fifoout_wpos == FIFO_SIZE)
if (m_copro_fifoout_wpos == FIFO_SIZE)
{
state->m_copro_fifoout_wpos = 0;
m_copro_fifoout_wpos = 0;
}
state->m_copro_fifoout_num++;
m_copro_fifoout_num++;
}
READ32_MEMBER(model1_state::copro_ram_r)
@ -2222,14 +2222,6 @@ WRITE16_MEMBER(model1_state::model1_vr_tgp_w)
m_vr_w = (m_vr_w & 0xffff0000) | data;
}
/* TGP config */
const mb86233_cpu_core model1_vr_tgp_config =
{
copro_fifoin_pop,
copro_fifoout_push,
"user5"
};
/* TGP memory map */
ADDRESS_MAP_START( model1_vr_tgp_map, AS_PROGRAM, 32, model1_state )
AM_RANGE(0x00000000, 0x000007ff) AM_RAM AM_REGION("tgp", 0)