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taito/cchance.cpp, taito/tnzs.cpp: Cleaned out crud.

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* Reduced duplication in address maps.
* Got rid of bankdev.
* Got rid of inaccessible RAM hiding under sprite chip (it used to use
  shares, but now allocates its own memory).
* Got rid of unnecessary I/O ports in cchance.
This commit is contained in:
Vas Crabb 2023-03-20 05:54:44 +11:00
parent f5f7689a20
commit f38ddbdc5f
4 changed files with 102 additions and 119 deletions
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12
src/mame/taito/cchance.cpp
View File

@ -95,12 +95,12 @@ void cchance_state::main_map(address_map &map)
{
map(0x0000, 0x7fff).rom();
map(0xa000, 0xafff).ram().rw(m_spritegen, FUNC(x1_001_device::spritecodelow_r8), FUNC(x1_001_device::spritecodelow_w8));
map(0xb000, 0xbfff).ram().rw(m_spritegen, FUNC(x1_001_device::spritecodehigh_r8), FUNC(x1_001_device::spritecodehigh_w8));
map(0xa000, 0xafff).rw(m_spritegen, FUNC(x1_001_device::spritecodelow_r8), FUNC(x1_001_device::spritecodelow_w8));
map(0xb000, 0xbfff).rw(m_spritegen, FUNC(x1_001_device::spritecodehigh_r8), FUNC(x1_001_device::spritecodehigh_w8));
map(0xc000, 0xdfff).ram();
map(0xe000, 0xe2ff).ram().rw(m_spritegen, FUNC(x1_001_device::spriteylow_r8), FUNC(x1_001_device::spriteylow_w8));
map(0xe000, 0xe2ff).rw(m_spritegen, FUNC(x1_001_device::spriteylow_r8), FUNC(x1_001_device::spriteylow_w8));
map(0xe300, 0xe303).ram().mirror(0xfc).w(m_spritegen, FUNC(x1_001_device::spritectrl_w8)); // control registers (0x80 mirror used by Arkanoid 2)
map(0xe800, 0xe800).w(m_spritegen, FUNC(x1_001_device::spritebgflag_w8)); // enable / disable background transparency
@ -184,12 +184,6 @@ static INPUT_PORTS_START( cchance )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
// These ports are required in tnzs_state
PORT_START("IN1")
PORT_START("IN2")
PORT_START("DSWA")
PORT_START("DSWB")
INPUT_PORTS_END
static const gfx_layout cchance_layout =

98
src/mame/taito/tnzs.cpp
View File

@ -762,47 +762,36 @@ void kageki_state::csport_w(uint8_t data)
}
}
void tnzs_base_state::main_map(address_map &map)
void tnzs_base_state::prompal_main_map(address_map &map)
{
map(0x0000, 0x7fff).rom();
map(0x8000, 0xbfff).m(m_mainbank, FUNC(address_map_bank_device::amap8));
map(0xc000, 0xcfff).ram().rw(m_spritegen, FUNC(x1_001_device::spritecodelow_r8), FUNC(x1_001_device::spritecodelow_w8));
map(0xd000, 0xdfff).ram().rw(m_spritegen, FUNC(x1_001_device::spritecodehigh_r8), FUNC(x1_001_device::spritecodehigh_w8));
map(0xe000, 0xefff).ram().share("share1");
map(0xf000, 0xf2ff).ram().rw(m_spritegen, FUNC(x1_001_device::spriteylow_r8), FUNC(x1_001_device::spriteylow_w8));
map(0xf300, 0xf303).mirror(0xfc).w(m_spritegen, FUNC(x1_001_device::spritectrl_w8)); /* control registers (0x80 mirror used by Arkanoid 2) */
map(0xf400, 0xf400).w(m_spritegen, FUNC(x1_001_device::spritebgflag_w8)); /* enable / disable background transparency */
map(0x8000, 0xbfff).bankr(m_mainrombank);
map(0x8000, 0xbfff).view(m_ramromview);
m_ramromview[0](0x8000, 0xbfff).bankrw(m_mainrambank);
map(0xc000, 0xcfff).rw(m_spritegen, FUNC(x1_001_device::spritecodelow_r8), FUNC(x1_001_device::spritecodelow_w8));
map(0xd000, 0xdfff).rw(m_spritegen, FUNC(x1_001_device::spritecodehigh_r8), FUNC(x1_001_device::spritecodehigh_w8));
map(0xe000, 0xefff).ram().share("share1"); // WORK RAM (shared by the 2 Z80's)
map(0xf000, 0xf2ff).rw(m_spritegen, FUNC(x1_001_device::spriteylow_r8), FUNC(x1_001_device::spriteylow_w8));
map(0xf300, 0xf303).mirror(0xfc).w(m_spritegen, FUNC(x1_001_device::spritectrl_w8)); // control registers (0x80 mirror used by Arkanoid 2)
map(0xf400, 0xf400).w(m_spritegen, FUNC(x1_001_device::spritebgflag_w8)); // enable / disable background transparency
map(0xf600, 0xf600).nopr().w(FUNC(tnzs_base_state::ramrom_bankswitch_w));
// arknoid2, extrmatn, plumppop and drtoppel have PROMs instead of RAM
// drtoppel and kabukiz write here anyway!
map(0xf800, 0xfbff).nopw();
}
void tnzs_base_state::rampal_main_map(address_map &map)
{
prompal_main_map(map);
map(0xf800, 0xfbff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
}
void extrmatn_state::prompal_main_map(address_map &map)
{
main_map(map);
/* arknoid2, extrmatn, plumppop and drtoppel have PROMs instead of RAM */
/* drtoppel writes here anyway! (maybe leftover from tests during development) */
map(0xf800, 0xfbff).nopw();
}
void tnzsb_state::tnzsb_main_map(address_map &map)
{
map(0x0000, 0x7fff).rom();
map(0x8000, 0xbfff).m(m_mainbank, FUNC(address_map_bank_device::amap8));
map(0xc000, 0xcfff).ram().rw(m_spritegen, FUNC(x1_001_device::spritecodelow_r8), FUNC(x1_001_device::spritecodelow_w8));
map(0xd000, 0xdfff).ram().rw(m_spritegen, FUNC(x1_001_device::spritecodehigh_r8), FUNC(x1_001_device::spritecodehigh_w8));
map(0xe000, 0xefff).ram().share("share1");
map(0xf000, 0xf2ff).ram().rw(m_spritegen, FUNC(x1_001_device::spriteylow_r8), FUNC(x1_001_device::spriteylow_w8));
map(0xf300, 0xf303).mirror(0xfc).w(m_spritegen, FUNC(x1_001_device::spritectrl_w8)); /* control registers (0x80 mirror used by Arkanoid 2) */
map(0xf400, 0xf400).w(m_spritegen, FUNC(x1_001_device::spritebgflag_w8)); /* enable / disable background transparency */
map(0xf600, 0xf600).w(FUNC(tnzsb_state::ramrom_bankswitch_w));
/* kabukiz still writes here but it's not used (it's palette RAM in type1 map) */
map(0xf800, 0xfbff).nopw();
}
void tnzs_base_state::base_sub_map(address_map &map)
{
map(0x0000, 0x7fff).rom();
map(0x8000, 0x9fff).bankr("subbank");
map(0x8000, 0x9fff).bankr(m_subbank);
map(0xa000, 0xa000).w(FUNC(tnzs_base_state::bankswitch1_w));
map(0xb000, 0xb001).rw("ymsnd", FUNC(ym2203_device::read), FUNC(ym2203_device::write));
map(0xd000, 0xdfff).ram();
@ -812,6 +801,7 @@ void tnzs_base_state::base_sub_map(address_map &map)
void tnzs_mcu_state::tnzs_sub_map(address_map &map)
{
base_sub_map(map);
map(0xc000, 0xc001).rw(FUNC(tnzs_mcu_state::mcu_r), FUNC(tnzs_mcu_state::mcu_w)); /* not present in insectx */
map(0xa000, 0xa000).w(FUNC(tnzs_mcu_state::bankswitch1_w));
map(0xf000, 0xf003).r(FUNC(tnzs_mcu_state::analog_r)); /* paddles in arkanoid2/plumppop. The ports are */
@ -822,12 +812,14 @@ void tnzs_mcu_state::tnzs_sub_map(address_map &map)
void arknoid2_state::arknoid2_sub_map(address_map &map)
{
tnzs_sub_map(map);
map(0xc000, 0xc001).rw(FUNC(arknoid2_state::mcu_r), FUNC(arknoid2_state::mcu_w));
}
void kageki_state::kageki_sub_map(address_map &map)
{
base_sub_map(map);
map(0xc000, 0xc000).portr("IN0");
map(0xc001, 0xc001).portr("IN1");
map(0xc002, 0xc002).portr("IN2");
@ -836,17 +828,18 @@ void kageki_state::kageki_sub_map(address_map &map)
void insectx_state::insectx_sub_map(address_map &map)
{
base_sub_map(map);
map(0xc000, 0xc000).portr("IN0");
map(0xc001, 0xc001).portr("IN1");
map(0xc002, 0xc002).portr("IN2");
}
/* the later board is different, it has a third CPU (and of course no mcu) */
// the later board is different, it has a third CPU (and of course no MCU)
void tnzsb_state::tnzsb_base_sub_map(address_map &map)
{
map(0x0000, 0x7fff).rom();
map(0x8000, 0x9fff).bankr("subbank");
map(0x8000, 0x9fff).bankr(m_subbank);
map(0xa000, 0xa000).w(FUNC(tnzsb_state::bankswitch1_w));
map(0xb002, 0xb002).portr("DSWA");
map(0xb003, 0xb003).portr("DSWB");
@ -861,12 +854,14 @@ void tnzsb_state::tnzsb_base_sub_map(address_map &map)
void tnzsb_state::tnzsb_sub_map(address_map &map)
{
tnzsb_base_sub_map(map);
map(0xf000, 0xf3ff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
}
void kabukiz_state::kabukiz_sub_map(address_map &map)
{
tnzsb_base_sub_map(map);
map(0xf800, 0xfbff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
}
@ -879,7 +874,7 @@ void tnzsb_state::tnzsb_cpu2_map(address_map &map)
void kabukiz_state::kabukiz_cpu2_map(address_map &map)
{
map(0x0000, 0x7fff).rom();
map(0x8000, 0xbfff).bankr("audiobank");
map(0x8000, 0xbfff).bankr(m_audiobank);
map(0xe000, 0xffff).ram();
}
@ -892,22 +887,15 @@ void tnzsb_state::tnzsb_io_map(address_map &map)
void jpopnics_state::jpopnics_main_map(address_map &map)
{
map(0x0000, 0x7fff).rom();
map(0x8000, 0xbfff).m(m_mainbank, FUNC(address_map_bank_device::amap8));
map(0xc000, 0xcfff).ram().rw(m_spritegen, FUNC(x1_001_device::spritecodelow_r8), FUNC(x1_001_device::spritecodelow_w8));
map(0xd000, 0xdfff).ram().rw(m_spritegen, FUNC(x1_001_device::spritecodehigh_r8), FUNC(x1_001_device::spritecodehigh_w8));
map(0xe000, 0xefff).ram().share("share1"); /* WORK RAM (shared by the 2 z80's) */
map(0xf000, 0xf2ff).ram().rw(m_spritegen, FUNC(x1_001_device::spriteylow_r8), FUNC(x1_001_device::spriteylow_w8));
map(0xf300, 0xf303).mirror(0xfc).w(m_spritegen, FUNC(x1_001_device::spritectrl_w8)); /* control registers (0x80 mirror used by Arkanoid 2) */
map(0xf400, 0xf400).w(m_spritegen, FUNC(x1_001_device::spritebgflag_w8)); /* enable / disable background transparency */
map(0xf600, 0xf600).nopr().w(FUNC(jpopnics_state::ramrom_bankswitch_w));
map(0xf800, 0xffff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
prompal_main_map(map);
map(0xf800, 0xffff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette"); // larger palette
}
void jpopnics_state::jpopnics_sub_map(address_map &map)
{
map(0x0000, 0x7fff).rom();
map(0x8000, 0x9fff).bankr("subbank");
map(0x8000, 0x9fff).bankr(m_subbank);
map(0xa000, 0xa000).w(FUNC(jpopnics_state::subbankswitch_w));
map(0xb000, 0xb001).rw("ymsnd", FUNC(ym2151_device::read), FUNC(ym2151_device::write));
@ -922,18 +910,6 @@ void jpopnics_state::jpopnics_sub_map(address_map &map)
map(0xf000, 0xf003).r(m_upd4701, FUNC(upd4701_device::read_xy));
}
/* RAM/ROM bank that maps at 0x8000-0xbfff on maincpu */
void tnzs_base_state::mainbank_map(address_map &map)
{
map(0x00000, 0x07fff).ram(); // instead of the first two banks of ROM being repeated redundantly the hardware maps RAM here
map(0x08000, 0x1ffff).rom().region(":maincpu", 0x8000);
}
void tnzs_base_state::tnzs_mainbank(machine_config &config)
{
ADDRESS_MAP_BANK(config, "mainbank").set_map(&tnzs_base_state::mainbank_map).set_options(ENDIANNESS_LITTLE, 8, 17, 0x4000);
}
static INPUT_PORTS_START( common_in2 )
PORT_START("IN2")
@ -1554,15 +1530,13 @@ void tnzs_base_state::tnzs_base(machine_config &config)
{
/* basic machine hardware */
Z80(config, m_maincpu, XTAL(12'000'000)/2); /* 6.0 MHz ??? - Main board Crystal is 12MHz, verified on insectx, kageki, tnzsb */
m_maincpu->set_addrmap(AS_PROGRAM, &tnzs_base_state::main_map);
m_maincpu->set_addrmap(AS_PROGRAM, &tnzs_base_state::rampal_main_map);
m_maincpu->set_vblank_int("screen", FUNC(tnzs_base_state::irq0_line_hold));
Z80(config, m_subcpu, XTAL(12'000'000)/2); /* 6.0 MHz ??? - Main board Crystal is 12MHz, verified on insectx, kageki, tnzsb */
m_subcpu->set_addrmap(AS_PROGRAM, &tnzs_base_state::base_sub_map);
m_subcpu->set_vblank_int("screen", FUNC(tnzs_base_state::irq0_line_hold));
tnzs_mainbank(config);
config.set_perfect_quantum(m_maincpu);
/* video hardware */
@ -1686,7 +1660,7 @@ void tnzsb_state::tnzsb(machine_config &config)
tnzs_base(config);
/* basic machine hardware */
m_maincpu->set_addrmap(AS_PROGRAM, &tnzsb_state::tnzsb_main_map);
m_maincpu->set_addrmap(AS_PROGRAM, &tnzsb_state::prompal_main_map);
m_subcpu->set_addrmap(AS_PROGRAM, &tnzsb_state::tnzsb_sub_map);
Z80(config, m_audiocpu, XTAL(12'000'000)/2); /* verified on pcb */

92
src/mame/taito/tnzs.h
View File

@ -6,7 +6,6 @@
#pragma once
#include "cpu/mcs48/mcs48.h"
#include "machine/bankdev.h"
#include "machine/gen_latch.h"
#include "machine/upd4701.h"
#include "sound/dac.h"
@ -46,27 +45,35 @@ protected:
tnzs_base_state(const machine_config &mconfig, device_type type, const char *tag)
: tnzs_video_state_base(mconfig, type, tag)
, m_subcpu(*this, "sub")
, m_mainbank(*this, "mainbank")
, m_subbank(*this, "subbank")
, m_mainrombank(*this, "rombank")
, m_mainrambank(*this, "rambank")
, m_bankedram(*this, "bankedram", 0x8000, ENDIANNESS_LITTLE)
, m_ramromview(*this, "ramrom")
{ }
void tnzs_base(machine_config &config);
void tnzs_mainbank(machine_config &config);
void tnzs_base(machine_config &config) ATTR_COLD;
virtual void machine_start() override;
virtual void machine_start() override ATTR_COLD;
virtual void bankswitch1_w(uint8_t data);
void ramrom_bankswitch_w(uint8_t data);
void base_sub_map(address_map &map);
void main_map(address_map &map);
void mainbank_map(address_map &map);
void prompal_main_map(address_map &map) ATTR_COLD;
void rampal_main_map(address_map &map) ATTR_COLD;
void base_sub_map(address_map &map) ATTR_COLD;
// devices
required_device<cpu_device> m_subcpu;
required_device<address_map_bank_device> m_mainbank;
required_memory_bank m_subbank;
private:
required_memory_bank m_mainrombank;
required_memory_bank m_mainrambank;
memory_share_creator<uint8_t> m_bankedram;
memory_view m_ramromview;
};
@ -84,7 +91,7 @@ public:
, m_lockout_level(lockout_level)
{ }
void tnzs(machine_config &config);
void tnzs(machine_config &config) ATTR_COLD;
protected:
virtual void bankswitch1_w(uint8_t data) override;
@ -96,7 +103,7 @@ protected:
uint8_t analog_r(offs_t offset);
void tnzs_sub_map(address_map &map);
void tnzs_sub_map(address_map &map) ATTR_COLD;
required_device<upi41_cpu_device> m_mcu;
optional_device<upd4701_device> m_upd4701;
@ -124,11 +131,8 @@ public:
: tnzs_mcu_state(mconfig, type, tag, false)
{ }
void extrmatn(machine_config &config);
void plumppop(machine_config &config);
protected:
void prompal_main_map(address_map &map);
void extrmatn(machine_config &config) ATTR_COLD;
void plumppop(machine_config &config) ATTR_COLD;
};
class arknoid2_state : public extrmatn_state
@ -143,11 +147,11 @@ public:
, m_in2(*this, "IN2")
{ }
void arknoid2(machine_config &config);
void arknoid2(machine_config &config) ATTR_COLD;
private:
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void machine_start() override ATTR_COLD;
virtual void machine_reset() override ATTR_COLD;
virtual void bankswitch1_w(uint8_t data) override;
@ -155,7 +159,9 @@ private:
void mcu_w(offs_t offset, uint8_t data);
INTERRUPT_GEN_MEMBER(mcu_interrupt);
void arknoid2_sub_map(address_map &map);
void arknoid2_sub_map(address_map &map) ATTR_COLD;
void mcu_reset();
required_ioport m_coin1;
required_ioport m_coin2;
@ -163,8 +169,6 @@ private:
required_ioport m_in1;
required_ioport m_in2;
void mcu_reset();
int m_mcu_initializing = 0;
int m_mcu_coinage_init = 0;
int m_mcu_command = 0;
@ -190,13 +194,13 @@ public:
, m_csport_sel(0)
{ }
void kageki(machine_config &config);
void kageki(machine_config &config) ATTR_COLD;
void init_kageki();
void init_kageki() ATTR_COLD;
protected:
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void machine_start() override ATTR_COLD;
virtual void machine_reset() override ATTR_COLD;
private:
static constexpr unsigned MAX_SAMPLES = 0x2f;
@ -206,18 +210,16 @@ private:
uint8_t csport_r();
void csport_w(uint8_t data);
DECLARE_MACHINE_RESET(kageki);
SAMPLES_START_CB_MEMBER(init_samples);
void kageki_sub_map(address_map &map);
void kageki_sub_map(address_map &map) ATTR_COLD;
required_device<samples_device> m_samples;
required_ioport m_dswa;
required_ioport m_dswb;
/* sound-related */
// sound-related
std::unique_ptr<int16_t[]> m_sampledata[MAX_SAMPLES];
int m_samplesize[MAX_SAMPLES]{};
@ -232,13 +234,14 @@ public:
, m_upd4701(*this, "upd4701")
{ }
void jpopnics(machine_config &config);
void jpopnics(machine_config &config) ATTR_COLD;
private:
void subbankswitch_w(uint8_t data);
void jpopnics_main_map(address_map &map);
void jpopnics_sub_map(address_map &map);
void jpopnics_main_map(address_map &map) ATTR_COLD;
void jpopnics_sub_map(address_map &map) ATTR_COLD;
required_device<upd4701_device> m_upd4701;
};
@ -249,11 +252,11 @@ public:
: tnzs_base_state(mconfig, type, tag)
{ }
void insectx(machine_config &config);
void insectx(machine_config &config) ATTR_COLD;
private:
virtual void bankswitch1_w(uint8_t data) override;
void insectx_sub_map(address_map &map);
void insectx_sub_map(address_map &map) ATTR_COLD;
};
class tnzsb_state : public tnzs_base_state
@ -265,7 +268,7 @@ public:
, m_soundlatch(*this, "soundlatch")
{ }
void tnzsb(machine_config &config);
void tnzsb(machine_config &config) ATTR_COLD;
protected:
DECLARE_WRITE_LINE_MEMBER(ym2203_irqhandler);
@ -274,11 +277,10 @@ protected:
virtual void bankswitch1_w(uint8_t data) override;
void tnzsb_base_sub_map(address_map &map);
void tnzsb_cpu2_map(address_map &map);
void tnzsb_io_map(address_map &map);
void tnzsb_main_map(address_map &map);
void tnzsb_sub_map(address_map &map);
void tnzsb_base_sub_map(address_map &map) ATTR_COLD;
void tnzsb_sub_map(address_map &map) ATTR_COLD;
void tnzsb_cpu2_map(address_map &map) ATTR_COLD;
void tnzsb_io_map(address_map &map) ATTR_COLD;
required_device<cpu_device> m_audiocpu;
required_device<generic_latch_8_device> m_soundlatch;
@ -292,16 +294,16 @@ public:
, m_audiobank(*this, "audiobank")
{ }
void kabukiz(machine_config &config);
void kabukiz(machine_config &config) ATTR_COLD;
protected:
virtual void machine_start() override;
virtual void machine_start() override ATTR_COLD;
private:
void sound_bank_w(uint8_t data);
void kabukiz_cpu2_map(address_map &map);
void kabukiz_sub_map(address_map &map);
void kabukiz_cpu2_map(address_map &map) ATTR_COLD;
void kabukiz_sub_map(address_map &map) ATTR_COLD;
required_memory_bank m_audiobank;
};

19
src/mame/taito/tnzs_m.cpp
View File

@ -348,10 +348,16 @@ void tnzs_base_state::machine_start()
{
tnzs_video_state_base::machine_start();
uint8_t *sub = memregion("sub")->base();
uint8_t *const main = memregion("maincpu")->base();
m_mainrombank->configure_entries(0, 8, &main[0], 0x4000);
m_mainrombank->set_entry(2);
m_mainbank->set_bank(2);
m_mainrambank->configure_entries(0, 2, &m_bankedram[0], 0x4000);
m_mainrambank->set_entry(0);
m_ramromview.disable();
uint8_t *const sub = memregion("sub")->base();
m_subbank->configure_entries(0, 4, &sub[0x08000], 0x2000);
m_subbank->set_entry(0);
}
@ -399,7 +405,14 @@ void tnzs_base_state::ramrom_bankswitch_w(uint8_t data)
m_subcpu->set_input_line(INPUT_LINE_RESET, BIT(data, 4) ? CLEAR_LINE : ASSERT_LINE);
// bits 0-2 select RAM/ROM bank
m_mainbank->set_bank(data & 0x07);
m_mainrombank->set_entry(data & 0x07);
m_mainrambank->set_entry(data & 0x01);
// instead of the first two banks of ROM being repeated redundantly the hardware maps RAM here
if (data & 0x06)
m_ramromview.disable();
else
m_ramromview.select(0);
}
void arknoid2_state::bankswitch1_w(uint8_t data)