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(nw) dms86 : added devices but commented out as not working
This commit is contained in:
Robbbert
parent
d9eaaf2151
commit
f3a161d3f4
@ -7,16 +7,21 @@
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11/01/2010 Skeleton driver.
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Monitor commands:
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A
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A Display incoming terminal data in hex
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B boot to HiNet
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C copy memory
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D dump memory to screen
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F fill memory
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G go (eg G address [breakpoint])
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I in port
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L memory test
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M memory test
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O out port (e.g. O 84 77)
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P
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P set segment
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S write a byte to memory
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T
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T type ascii string into the address set by D or S
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X display registers
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? help
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: load intel hex format file
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Note that bit 3 of port 82 is tested at boot. If low, the computer bypasses
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@ -26,73 +31,68 @@ the monitor and goes straight to "Joining HiNet".
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#include "emu.h"
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#include "cpu/i86/i86.h"
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#include "machine/z80ctc.h"
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#include "machine/z80sio.h"
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#include "machine/clock.h"
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#include "bus/rs232/rs232.h"
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#include "machine/terminal.h"
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#define TERMINAL_TAG "terminal"
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class dms86_state : public driver_device
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{
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public:
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dms86_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_terminal(*this, TERMINAL_TAG)
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{
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}
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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{ }
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DECLARE_READ16_MEMBER( dms86_82_r );
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DECLARE_READ16_MEMBER( dms86_84_r );
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DECLARE_READ16_MEMBER( dms86_86_r );
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DECLARE_READ16_MEMBER( dms86_9a_r );
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DECLARE_READ16_MEMBER( port82_r );
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DECLARE_READ16_MEMBER( port9a_r );
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DECLARE_READ16_MEMBER( port9c_r );
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void kbd_put(u8 data);
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protected:
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required_device<cpu_device> m_maincpu;
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required_device<generic_terminal_device> m_terminal;
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uint8_t *m_ram;
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uint8_t m_term_data;
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private:
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u8 m_term_data;
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virtual void machine_reset() override;
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required_device<cpu_device> m_maincpu;
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};
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READ16_MEMBER( dms86_state::dms86_82_r )
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READ16_MEMBER( dms86_state::port82_r )
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{
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// HiNet / Monitor switch
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return 0xff;
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return 8;
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}
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READ16_MEMBER( dms86_state::dms86_84_r )
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READ16_MEMBER( dms86_state::port9a_r )
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{
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return m_term_data ? 0x40 : 0;
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}
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READ16_MEMBER( dms86_state::port9c_r )
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{
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uint8_t ret = m_term_data;
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m_term_data = 0;
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return ret;
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}
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READ16_MEMBER( dms86_state::dms86_86_r )
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{
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return 4 | (m_term_data ? 1 : 0);
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}
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READ16_MEMBER( dms86_state::dms86_9a_r )
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{
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return 0;
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}
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static ADDRESS_MAP_START(dms86_mem, AS_PROGRAM, 16, dms86_state)
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static ADDRESS_MAP_START(mem_map, AS_PROGRAM, 16, dms86_state)
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ADDRESS_MAP_UNMAP_HIGH
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AM_RANGE(0x00000, 0x1ffff) AM_RAM
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AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION("user1",0)
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AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION("roms",0)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(dms86_io, AS_IO, 16, dms86_state)
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static ADDRESS_MAP_START(io_map, AS_IO, 16, dms86_state)
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ADDRESS_MAP_UNMAP_HIGH
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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AM_RANGE(0x82, 0x83) AM_READ(dms86_82_r)
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AM_RANGE(0x84, 0x85) AM_READ(dms86_84_r) AM_DEVWRITE8(TERMINAL_TAG, generic_terminal_device, write, 0xff)
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AM_RANGE(0x86, 0x87) AM_READ(dms86_86_r)
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AM_RANGE(0x9A, 0x9B) AM_READ(dms86_9a_r)
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AM_RANGE(0x9c, 0x9d) AM_DEVWRITE8(TERMINAL_TAG, generic_terminal_device, write, 0xff)
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AM_RANGE(0x82, 0x83) AM_READ(port82_r)
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//AM_RANGE(0x80, 0x87) AM_DEVREADWRITE8("sio1", z80sio_device, ba_cd_r, ba_cd_w, 0x00ff)
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AM_RANGE(0x88, 0x8f) AM_DEVREADWRITE8("ctc", z80ctc_device, read, write, 0x00ff)
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AM_RANGE(0x90, 0x97) AM_DEVREADWRITE8("sio2", z80sio_device, ba_cd_r, ba_cd_w, 0x00ff)
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AM_RANGE(0x9A, 0x9B) AM_READ(port9a_r) // parallel SASI port
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AM_RANGE(0x9c, 0x9d) AM_READ(port9c_r) AM_DEVWRITE8("terminal", generic_terminal_device, write, 0xff)
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ADDRESS_MAP_END
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/* Input ports */
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@ -111,18 +111,45 @@ void dms86_state::kbd_put(u8 data)
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static MACHINE_CONFIG_START( dms86 )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu",I8086, XTAL_9_8304MHz)
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MCFG_CPU_PROGRAM_MAP(dms86_mem)
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MCFG_CPU_IO_MAP(dms86_io)
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MCFG_CPU_ADD("maincpu", I8086, XTAL_14_7456MHz / 3) // according to the manual... hmm
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MCFG_CPU_PROGRAM_MAP(mem_map)
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MCFG_CPU_IO_MAP(io_map)
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// According to the manual the clock is 14,765,600 / 4 but that couldn't possibly work.
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// By maths, clock should be 9600*32*4*16 = 19,660,800 but not working either
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// So, commented out because it makes the whole thing crawl, only get 18% on my machine
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//MCFG_DEVICE_ADD("ctc_clock", CLOCK, 19660800) //XTAL_14_7456MHz / 4)
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//MCFG_CLOCK_SIGNAL_HANDLER(DEVWRITELINE("ctc" ,z80ctc_device, trg0))
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//MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("ctc" ,z80ctc_device, trg1))
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//MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("ctc" ,z80ctc_device, trg2))
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MCFG_DEVICE_ADD(TERMINAL_TAG, GENERIC_TERMINAL, 0)
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MCFG_DEVICE_ADD("ctc", Z80CTC, XTAL_14_7456MHz / 3)
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//MCFG_Z80CTC_INTR_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0)) // frame rate interrupt to maincpu
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MCFG_Z80CTC_ZC0_CB(DEVWRITELINE("sio1", z80sio_device, rxtxcb_w)) // SIO1 Ch B
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MCFG_Z80CTC_ZC1_CB(DEVWRITELINE("sio1", z80sio_device, txca_w)) // SIO1 Ch A
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MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("sio1" ,z80sio_device, rxca_w))
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MCFG_Z80CTC_ZC2_CB(DEVWRITELINE("sio2", z80sio_device, rxtxcb_w)) // SIO2
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MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("sio2" ,z80sio_device, rxca_w))
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MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("sio2" ,z80sio_device, rxca_w))
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MCFG_DEVICE_ADD("sio1", Z80SIO, XTAL_14_7456MHz / 3)
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MCFG_Z80SIO_OUT_TXDB_CB(DEVWRITELINE("rs232", rs232_port_device, write_txd))
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MCFG_Z80SIO_OUT_DTRB_CB(DEVWRITELINE("rs232", rs232_port_device, write_dtr))
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MCFG_Z80SIO_OUT_RTSB_CB(DEVWRITELINE("rs232", rs232_port_device, write_rts))
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MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, nullptr)
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MCFG_RS232_RXD_HANDLER(DEVWRITELINE("sio1", z80sio_device, rxb_w))
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MCFG_RS232_DCD_HANDLER(DEVWRITELINE("sio1", z80sio_device, dcdb_w))
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MCFG_RS232_CTS_HANDLER(DEVWRITELINE("sio1", z80sio_device, ctsb_w)) MCFG_DEVCB_INVERT
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MCFG_DEVICE_ADD("sio2", Z80SIO, XTAL_14_7456MHz / 3)
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MCFG_DEVICE_ADD("terminal", GENERIC_TERMINAL, 0)
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MCFG_GENERIC_TERMINAL_KEYBOARD_CB(PUT(dms86_state, kbd_put))
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MACHINE_CONFIG_END
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/* ROM definition */
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ROM_START( dms86 )
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ROM_REGION( 0x2000, "user1", ROMREGION_ERASEFF )
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ROM_REGION( 0x2000, "roms", ROMREGION_ERASEFF )
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ROM_LOAD16_BYTE( "hns-86_54-8678.bin", 0x0000, 0x1000, CRC(95f58e1c) SHA1(6fc8f087f0c887d8b429612cd035c6c1faab570c))
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ROM_LOAD16_BYTE( "hns-86_54-8677.bin", 0x0001, 0x1000, CRC(78fad756) SHA1(ddcbff1569ec6975b8489935cdcfa80eba413502))
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ROM_END
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@ -152,7 +152,7 @@ static ADDRESS_MAP_START( hpz80unk_io, AS_IO, 8, hpz80unk_state )
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AM_RANGE(0x04, 0x04) AM_READWRITE(port04_r,port04_w) // uart2 data
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AM_RANGE(0x0d, 0x0d) AM_READ(port0d_r) // uart3 status
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AM_RANGE(0x0e, 0x0e) AM_WRITE(port0e_w) // uart3 data
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AM_RANGE(0x1d, 0x1e) // top of memory is written here, little-endian
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AM_RANGE(0x1d, 0x1e) // top of memory is written here, big-endian
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AM_RANGE(0x1f, 0x1f) AM_READ_PORT("DSW") // select which uarts to use
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AM_RANGE(0xfc, 0xfc) AM_READ(portfc_r)
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ADDRESS_MAP_END
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