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- h6280.c: Modernized the H6280 core.

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- c6280.c: Modernized the C2680 sound core.

(nw) fixed ssem compile issue
This commit is contained in:
Ryan Holtz 2012-12-23 07:15:04 +00:00
parent 4eaee5d7d0
commit f4b7f17a41
35 changed files with 1079 additions and 962 deletions
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757
src/emu/cpu/h6280/h6280.c
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@ -112,424 +112,589 @@
#include "debugger.h"
#include "h6280.h"
static void set_irq_line(h6280_Regs* cpustate, int irqline, int state);
//static void set_irq_line(h6280_Regs* cpustate, int irqline, int state);
/* include the macros */
#include "h6280ops.h"
//**************************************************************************
// DEVICE INTERFACE
//**************************************************************************
INLINE h6280_Regs *get_safe_token(device_t *device)
const device_type H6280 = &device_creator<h6280_device>;
//-------------------------------------------------
// h6280_device - constructor
//-------------------------------------------------
h6280_device::h6280_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: cpu_device(mconfig, H6280, "H6280", tag, owner, clock),
m_program_config("program", ENDIANNESS_LITTLE, 8, 21),
m_io_config("io", ENDIANNESS_LITTLE, 8, 2)
{
assert(device != NULL);
assert(device->type() == H6280);
return (h6280_Regs *)downcast<legacy_cpu_device *>(device)->token();
// build the opcode table
for (int op = 0; op < 256; op++)
m_opcode[op] = s_opcodetable[op];
}
/* include the opcode macros, functions and function pointer tables */
#include "tblh6280.c"
/*****************************************************************************/
static CPU_INIT( h6280 )
const h6280_device::ophandler h6280_device::s_opcodetable[256] =
{
h6280_Regs* cpustate = get_safe_token(device);
&h6280_device::op_000, &h6280_device::op_001, &h6280_device::op_002, &h6280_device::op_003, &h6280_device::op_004, &h6280_device::op_005, &h6280_device::op_006, &h6280_device::op_007,
&h6280_device::op_008, &h6280_device::op_009, &h6280_device::op_00a, &h6280_device::op_00b, &h6280_device::op_00c, &h6280_device::op_00d, &h6280_device::op_00e, &h6280_device::op_00f,
&h6280_device::op_010, &h6280_device::op_011, &h6280_device::op_012, &h6280_device::op_013, &h6280_device::op_014, &h6280_device::op_015, &h6280_device::op_016, &h6280_device::op_017,
&h6280_device::op_018, &h6280_device::op_019, &h6280_device::op_01a, &h6280_device::op_01b, &h6280_device::op_01c, &h6280_device::op_01d, &h6280_device::op_01e, &h6280_device::op_01f,
&h6280_device::op_020, &h6280_device::op_021, &h6280_device::op_022, &h6280_device::op_023, &h6280_device::op_024, &h6280_device::op_025, &h6280_device::op_026, &h6280_device::op_027,
&h6280_device::op_028, &h6280_device::op_029, &h6280_device::op_02a, &h6280_device::op_02b, &h6280_device::op_02c, &h6280_device::op_02d, &h6280_device::op_02e, &h6280_device::op_02f,
&h6280_device::op_030, &h6280_device::op_031, &h6280_device::op_032, &h6280_device::op_033, &h6280_device::op_034, &h6280_device::op_035, &h6280_device::op_036, &h6280_device::op_037,
&h6280_device::op_038, &h6280_device::op_039, &h6280_device::op_03a, &h6280_device::op_03b, &h6280_device::op_03c, &h6280_device::op_03d, &h6280_device::op_03e, &h6280_device::op_03f,
&h6280_device::op_040, &h6280_device::op_041, &h6280_device::op_042, &h6280_device::op_043, &h6280_device::op_044, &h6280_device::op_045, &h6280_device::op_046, &h6280_device::op_047,
&h6280_device::op_048, &h6280_device::op_049, &h6280_device::op_04a, &h6280_device::op_04b, &h6280_device::op_04c, &h6280_device::op_04d, &h6280_device::op_04e, &h6280_device::op_04f,
&h6280_device::op_050, &h6280_device::op_051, &h6280_device::op_052, &h6280_device::op_053, &h6280_device::op_054, &h6280_device::op_055, &h6280_device::op_056, &h6280_device::op_057,
&h6280_device::op_058, &h6280_device::op_059, &h6280_device::op_05a, &h6280_device::op_05b, &h6280_device::op_05c, &h6280_device::op_05d, &h6280_device::op_05e, &h6280_device::op_05f,
&h6280_device::op_060, &h6280_device::op_061, &h6280_device::op_062, &h6280_device::op_063, &h6280_device::op_064, &h6280_device::op_065, &h6280_device::op_066, &h6280_device::op_067,
&h6280_device::op_068, &h6280_device::op_069, &h6280_device::op_06a, &h6280_device::op_06b, &h6280_device::op_06c, &h6280_device::op_06d, &h6280_device::op_06e, &h6280_device::op_06f,
&h6280_device::op_070, &h6280_device::op_071, &h6280_device::op_072, &h6280_device::op_073, &h6280_device::op_074, &h6280_device::op_075, &h6280_device::op_076, &h6280_device::op_077,
&h6280_device::op_078, &h6280_device::op_079, &h6280_device::op_07a, &h6280_device::op_07b, &h6280_device::op_07c, &h6280_device::op_07d, &h6280_device::op_07e, &h6280_device::op_07f,
&h6280_device::op_080, &h6280_device::op_081, &h6280_device::op_082, &h6280_device::op_083, &h6280_device::op_084, &h6280_device::op_085, &h6280_device::op_086, &h6280_device::op_087,
&h6280_device::op_088, &h6280_device::op_089, &h6280_device::op_08a, &h6280_device::op_08b, &h6280_device::op_08c, &h6280_device::op_08d, &h6280_device::op_08e, &h6280_device::op_08f,
&h6280_device::op_090, &h6280_device::op_091, &h6280_device::op_092, &h6280_device::op_093, &h6280_device::op_094, &h6280_device::op_095, &h6280_device::op_096, &h6280_device::op_097,
&h6280_device::op_098, &h6280_device::op_099, &h6280_device::op_09a, &h6280_device::op_09b, &h6280_device::op_09c, &h6280_device::op_09d, &h6280_device::op_09e, &h6280_device::op_09f,
&h6280_device::op_0a0, &h6280_device::op_0a1, &h6280_device::op_0a2, &h6280_device::op_0a3, &h6280_device::op_0a4, &h6280_device::op_0a5, &h6280_device::op_0a6, &h6280_device::op_0a7,
&h6280_device::op_0a8, &h6280_device::op_0a9, &h6280_device::op_0aa, &h6280_device::op_0ab, &h6280_device::op_0ac, &h6280_device::op_0ad, &h6280_device::op_0ae, &h6280_device::op_0af,
&h6280_device::op_0b0, &h6280_device::op_0b1, &h6280_device::op_0b2, &h6280_device::op_0b3, &h6280_device::op_0b4, &h6280_device::op_0b5, &h6280_device::op_0b6, &h6280_device::op_0b7,
&h6280_device::op_0b8, &h6280_device::op_0b9, &h6280_device::op_0ba, &h6280_device::op_0bb, &h6280_device::op_0bc, &h6280_device::op_0bd, &h6280_device::op_0be, &h6280_device::op_0bf,
&h6280_device::op_0c0, &h6280_device::op_0c1, &h6280_device::op_0c2, &h6280_device::op_0c3, &h6280_device::op_0c4, &h6280_device::op_0c5, &h6280_device::op_0c6, &h6280_device::op_0c7,
&h6280_device::op_0c8, &h6280_device::op_0c9, &h6280_device::op_0ca, &h6280_device::op_0cb, &h6280_device::op_0cc, &h6280_device::op_0cd, &h6280_device::op_0ce, &h6280_device::op_0cf,
&h6280_device::op_0d0, &h6280_device::op_0d1, &h6280_device::op_0d2, &h6280_device::op_0d3, &h6280_device::op_0d4, &h6280_device::op_0d5, &h6280_device::op_0d6, &h6280_device::op_0d7,
&h6280_device::op_0d8, &h6280_device::op_0d9, &h6280_device::op_0da, &h6280_device::op_0db, &h6280_device::op_0dc, &h6280_device::op_0dd, &h6280_device::op_0de, &h6280_device::op_0df,
&h6280_device::op_0e0, &h6280_device::op_0e1, &h6280_device::op_0e2, &h6280_device::op_0e3, &h6280_device::op_0e4, &h6280_device::op_0e5, &h6280_device::op_0e6, &h6280_device::op_0e7,
&h6280_device::op_0e8, &h6280_device::op_0e9, &h6280_device::op_0ea, &h6280_device::op_0eb, &h6280_device::op_0ec, &h6280_device::op_0ed, &h6280_device::op_0ee, &h6280_device::op_0ef,
&h6280_device::op_0f0, &h6280_device::op_0f1, &h6280_device::op_0f2, &h6280_device::op_0f3, &h6280_device::op_0f4, &h6280_device::op_0f5, &h6280_device::op_0f6, &h6280_device::op_0f7,
&h6280_device::op_0f8, &h6280_device::op_0f9, &h6280_device::op_0fa, &h6280_device::op_0fb, &h6280_device::op_0fc, &h6280_device::op_0fd, &h6280_device::op_0fe, &h6280_device::op_0ff
};
device->save_item(NAME(cpustate->ppc.w.l));
device->save_item(NAME(cpustate->pc.w.l));
device->save_item(NAME(cpustate->sp.w.l));
device->save_item(NAME(cpustate->zp.w.l));
device->save_item(NAME(cpustate->ea.w.l));
device->save_item(NAME(cpustate->a));
device->save_item(NAME(cpustate->x));
device->save_item(NAME(cpustate->y));
device->save_item(NAME(cpustate->p));
device->save_item(NAME(cpustate->mmr));
device->save_item(NAME(cpustate->irq_mask));
device->save_item(NAME(cpustate->timer_status));
device->save_item(NAME(cpustate->timer_ack));
device->save_item(NAME(cpustate->clocks_per_cycle));
device->save_item(NAME(cpustate->timer_value));
device->save_item(NAME(cpustate->timer_load));
device->save_item(NAME(cpustate->nmi_state));
device->save_item(NAME(cpustate->irq_state[0]));
device->save_item(NAME(cpustate->irq_state[1]));
device->save_item(NAME(cpustate->irq_state[2]));
device->save_item(NAME(cpustate->irq_pending));
void h6280_device::device_start()
{
// register our state for the debugger
state_add(STATE_GENPC, "GENPC", m_pc.w.l).noshow();
state_add(STATE_GENFLAGS, "GENFLAGS", m_p).callimport().callexport().formatstr("%8s").noshow();
state_add(H6280_PC, "PC:", m_pc.d).mask(0xffff);
state_add(H6280_S, "S:", m_sp.b.l).mask(0xff);
state_add(H6280_P, "P:", m_p).mask(0xff);
state_add(H6280_A, "A:", m_a).mask(0xff);
state_add(H6280_X, "X:", m_x).mask(0xff);
state_add(H6280_Y, "Y:", m_y).mask(0xff);
state_add(H6280_IRQ_MASK, "IM:", m_irq_mask).mask(0xff);
state_add(H6280_TIMER_STATE,"TMR:", m_timer_status).mask(0xff);
state_add(H6280_NMI_STATE, "NMI:", m_nmi_state).mask(0xf);
state_add(H6280_IRQ1_STATE, "IRQ1:", m_irq_state[0]).mask(0xf);
state_add(H6280_IRQ2_STATE, "IRQ2:", m_irq_state[1]).mask(0xf);
state_add(H6280_IRQT_STATE, "IRQT:", m_irq_state[2]).mask(0xf);
state_add(H6280_M1, "M1:", m_mmr[0]).mask(0xff);
state_add(H6280_M2, "M2:", m_mmr[1]).mask(0xff);
state_add(H6280_M3, "M3:", m_mmr[2]).mask(0xff);
state_add(H6280_M4, "M4:", m_mmr[3]).mask(0xff);
state_add(H6280_M5, "M5:", m_mmr[4]).mask(0xff);
state_add(H6280_M6, "M6:", m_mmr[5]).mask(0xff);
state_add(H6280_M7, "M7:", m_mmr[6]).mask(0xff);
state_add(H6280_M8, "M8:", m_mmr[7]).mask(0xff);
save_item(NAME(m_ppc.w.l));
save_item(NAME(m_pc.w.l));
save_item(NAME(m_sp.w.l));
save_item(NAME(m_zp.w.l));
save_item(NAME(m_ea.w.l));
save_item(NAME(m_a));
save_item(NAME(m_x));
save_item(NAME(m_y));
save_item(NAME(m_p));
save_item(NAME(m_mmr));
save_item(NAME(m_irq_mask));
save_item(NAME(m_timer_status));
save_item(NAME(m_timer_ack));
save_item(NAME(m_clocks_per_cycle));
save_item(NAME(m_timer_value));
save_item(NAME(m_timer_load));
save_item(NAME(m_nmi_state));
save_item(NAME(m_irq_state[0]));
save_item(NAME(m_irq_state[1]));
save_item(NAME(m_irq_state[2]));
save_item(NAME(m_irq_pending));
#if LAZY_FLAGS
device->save_item(NAME(cpustate->NZ));
save_item(NAME(m_nz));
#endif
device->save_item(NAME(cpustate->io_buffer));
save_item(NAME(m_io_buffer));
cpustate->irq_callback = irqcallback;
cpustate->device = device;
cpustate->program = &device->space(AS_PROGRAM);
cpustate->direct = &cpustate->program->direct();
cpustate->io = &device->space(AS_IO);
// set our instruction counter
m_icountptr = &m_icount;
}
static CPU_RESET( h6280 )
void h6280_device::device_reset()
{
h6280_Regs* cpustate = get_safe_token(device);
device_irq_acknowledge_callback save_irqcallback;
int i;
/* wipe out the h6280 structure */
save_irqcallback = cpustate->irq_callback;
memset(cpustate, 0, sizeof(h6280_Regs));
cpustate->irq_callback = save_irqcallback;
cpustate->device = device;
cpustate->program = &device->space(AS_PROGRAM);
cpustate->direct = &cpustate->program->direct();
cpustate->io = &device->space(AS_IO);
m_ppc.d = 0;
m_pc.d = 0;
m_zp.d = 0;
m_ea.d = 0;
m_a = 0;
m_x = 0;
m_y = 0;
m_p = 0;
memset(m_mmr, 0, sizeof(UINT8) * 8);
m_irq_mask = 0;
m_timer_ack = 0;
m_timer_value = 0;
#if LAZY_FLAGS
m_nz = 0;
#endif
m_io_buffer = 0;
m_program = &space(AS_PROGRAM);
m_direct = &m_program->direct();
m_io = &space(AS_IO);
/* set I and B flags */
P = _fI | _fB;
/* stack starts at 0x01ff */
cpustate->sp.d = 0x1ff;
m_sp.d = 0x1ff;
/* read the reset vector into PC */
PCL = RDMEM(cpustate, H6280_RESET_VEC);
PCH = RDMEM(cpustate, (H6280_RESET_VEC+1));
PCL = program_read8(H6280_RESET_VEC);
PCH = program_read8(H6280_RESET_VEC + 1);
/* CPU starts in low speed mode */
cpustate->clocks_per_cycle = 4;
m_clocks_per_cycle = 4;
/* timer off by default */
cpustate->timer_status=0;
cpustate->timer_load = 128 * 1024;
m_timer_status = 0;
m_timer_load = 128 * 1024;
/* clear pending interrupts */
for (i = 0; i < 3; i++)
cpustate->irq_state[i] = CLEAR_LINE;
cpustate->nmi_state = CLEAR_LINE;
for (int i = 0; i < 3; i++)
{
m_irq_state[i] = CLEAR_LINE;
}
m_nmi_state = CLEAR_LINE;
cpustate->irq_pending = 0;
m_irq_pending = 0;
}
static CPU_EXIT( h6280 )
void h6280_device::device_stop()
{
/* nothing */
}
static CPU_EXECUTE( h6280 )
//-------------------------------------------------
// memory_space_config - return the configuration
// of the specified address space, or NULL if
// the space doesn't exist
//-------------------------------------------------
const address_space_config *h6280_device::memory_space_config(address_spacenum spacenum) const
{
if (spacenum == AS_PROGRAM)
{
return &m_program_config;
}
else if (spacenum == AS_IO)
{
return &m_io_config;
}
return NULL;
}
//-------------------------------------------------
// state_string_export - export state as a string
// for the debugger
//-------------------------------------------------
void h6280_device::state_string_export(const device_state_entry &entry, astring &string)
{
switch (entry.index())
{
case STATE_GENFLAGS:
string.printf("%c%c%c%c%c%c%c%c",
(m_p & 0x80) ? 'N':'.',
(m_p & 0x40) ? 'V':'.',
(m_p & 0x20) ? 'R':'.',
(m_p & 0x10) ? 'B':'.',
(m_p & 0x08) ? 'D':'.',
(m_p & 0x04) ? 'I':'.',
(m_p & 0x02) ? 'Z':'.',
(m_p & 0x01) ? 'C':'.');
break;
}
}
//-------------------------------------------------
// disasm_min_opcode_bytes - return the length
// of the shortest instruction, in bytes
//-------------------------------------------------
UINT32 h6280_device::disasm_min_opcode_bytes() const
{
return 1;
}
//-------------------------------------------------
// disasm_max_opcode_bytes - return the length
// of the longest instruction, in bytes
//-------------------------------------------------
UINT32 h6280_device::disasm_max_opcode_bytes() const
{
return 7;
}
//-------------------------------------------------
// disasm_disassemble - call the disassembly
// helper function
//-------------------------------------------------
offs_t h6280_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
{
extern CPU_DISASSEMBLE( h6280 );
return disassemble(buffer, pc, oprom, opram, 0);
}
//-------------------------------------------------
// execute_min_cycles - return minimum number of
// cycles it takes for one instruction to execute
//-------------------------------------------------
UINT32 h6280_device::execute_min_cycles() const
{
return 2;
}
//-------------------------------------------------
// execute_max_cycles - return maximum number of
// cycles it takes for one instruction to execute
//-------------------------------------------------
UINT32 h6280_device::execute_max_cycles() const
{
return 17 + 6*65536;
}
//-------------------------------------------------
// execute_input_lines - return the number of
// input/interrupt lines
//-------------------------------------------------
UINT32 h6280_device::execute_input_lines() const
{
return 4;
}
//-------------------------------------------------
// execute_set_input - act on a changed input/
// interrupt line
//-------------------------------------------------
void h6280_device::execute_set_input(int inputnum, int state)
{
switch(inputnum)
{
case H6280_IRQ1_STATE:
case 0:
set_irq_line(0, state);
break;
case H6280_IRQ2_STATE:
case 1:
set_irq_line(1, state);
break;
case H6280_IRQT_STATE:
case 2:
set_irq_line(2, state);
break;
case H6280_NMI_STATE:
case INPUT_LINE_NMI:
set_irq_line(INPUT_LINE_NMI, state);
break;
}
}
/***************************************************************
* program_read8 read memory
***************************************************************/
UINT8 h6280_device::program_read8(offs_t addr)
{
CHECK_VDC_VCE_PENALTY(addr);
return m_program->read_byte(TRANSLATED(addr));
}
/***************************************************************
* program_write8 write memory
***************************************************************/
void h6280_device::program_write8(offs_t addr, UINT8 data)
{
CHECK_VDC_VCE_PENALTY(addr);
m_program->write_byte(TRANSLATED(addr), data);
}
/***************************************************************
* program_read8z read memory - zero page
***************************************************************/
UINT8 h6280_device::program_read8z(offs_t addr)
{
return m_program->read_byte((m_mmr[1] << 13) | (addr & 0x1fff));
}
/***************************************************************
* program_write8z write memory - zero page
***************************************************************/
void h6280_device::program_write8z(offs_t addr, UINT8 data)
{
m_program->write_byte((m_mmr[1] << 13) | (addr & 0x1fff), data);
}
/***************************************************************
* program_read16 read word from memory
***************************************************************/
UINT16 h6280_device::program_read16(offs_t addr)
{
return m_program->read_byte(TRANSLATED(addr));
(m_program->read_byte(TRANSLATED(addr + 1)) << 8);
}
/***************************************************************
* program_read16z read a word from a zero page address
***************************************************************/
UINT16 h6280_device::program_read16z(offs_t addr)
{
if ((addr & 0xff) == 0xff)
{
return m_program->read_byte((m_mmr[1] << 13) | (addr & 0x1fff)) |
(m_program->read_byte((m_mmr[1] << 13) | ((addr - 0xff) & 0x1fff)) << 8);
}
else
{
return m_program->read_byte((m_mmr[1] << 13) | (addr & 0x1fff)) |
(m_program->read_byte((m_mmr[1] << 13) | ((addr + 1) & 0x1fff)) << 8);
}
}
/***************************************************************
* push a register onto the stack
***************************************************************/
void h6280_device::push(UINT8 value)
{
m_program->write_byte((m_mmr[1] << 13) | m_sp.d, value);
S--;
}
/***************************************************************
* pull a register from the stack
***************************************************************/
void h6280_device::pull(UINT8 &value)
{
S++;
value = m_program->read_byte((m_mmr[1] << 13) | m_sp.d);
}
/***************************************************************
* read_opcode read an opcode
***************************************************************/
UINT8 h6280_device::read_opcode()
{
return m_direct->read_decrypted_byte(TRANSLATED(PCW));
}
/***************************************************************
* read_opcode_arg read an opcode argument
***************************************************************/
UINT8 h6280_device::read_opcode_arg()
{
return m_direct->read_raw_byte(TRANSLATED(PCW));
}
//-------------------------------------------------
// execute_run - execute a timeslice's worth of
// opcodes
//-------------------------------------------------
void h6280_device::execute_run()
{
int in;
h6280_Regs* cpustate = get_safe_token(device);
if ( cpustate->irq_pending == 2 ) {
cpustate->irq_pending--;
if (m_irq_pending == 2)
{
m_irq_pending--;
}
/* Execute instructions */
do
{
cpustate->ppc = cpustate->pc;
m_ppc = m_pc;
debugger_instruction_hook(device, PCW);
debugger_instruction_hook(this, PCW);
/* Execute 1 instruction */
in=RDOP();
in = read_opcode();
PCW++;
insnh6280[in](cpustate);
(this->*m_opcode[in])();
if ( cpustate->irq_pending ) {
if ( cpustate->irq_pending == 1 ) {
if ( !(P & _fI) ) {
cpustate->irq_pending--;
if (m_irq_pending)
{
if (m_irq_pending == 1)
{
if (!(P & _fI))
{
m_irq_pending--;
CHECK_AND_TAKE_IRQ_LINES;
}
} else {
cpustate->irq_pending--;
}
else
{
m_irq_pending--;
}
}
/* Check internal timer */
if(cpustate->timer_status)
if (m_timer_status)
{
if(cpustate->timer_value<=0)
if (m_timer_value<=0)
{
if ( ! cpustate->irq_pending )
cpustate->irq_pending = 1;
while( cpustate->timer_value <= 0 )
cpustate->timer_value += cpustate->timer_load;
set_irq_line(cpustate, 2,ASSERT_LINE);
if (!m_irq_pending)
{
m_irq_pending = 1;
}
while (m_timer_value <= 0)
{
m_timer_value += m_timer_load;
}
set_irq_line(2, ASSERT_LINE);
}
}
} while (cpustate->ICount > 0);
} while (m_icount > 0);
}
/*****************************************************************************/
static void set_irq_line(h6280_Regs* cpustate, int irqline, int state)
//**************************************************************************
// IRQ HANDLING
//**************************************************************************
void h6280_device::set_irq_line(int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if ( state != ASSERT_LINE ) return;
cpustate->nmi_state = state;
if (state != ASSERT_LINE)
return;
m_nmi_state = state;
CHECK_IRQ_LINES;
}
else if (irqline < 3)
{
/* If the state has not changed, just return */
if ( cpustate->irq_state[irqline] == state )
if (m_irq_state[irqline] == state)
return;
cpustate->irq_state[irqline] = state;
m_irq_state[irqline] = state;
CHECK_IRQ_LINES;
}
}
//**************************************************************************
// REGISTER HANDLING
//**************************************************************************
/*****************************************************************************/
READ8_HANDLER( h6280_irq_status_r )
READ8_MEMBER( h6280_device::irq_status_r )
{
int status;
h6280_Regs *cpustate = get_safe_token(&space.device());
switch (offset&3)
switch (offset & 3)
{
default: return cpustate->io_buffer;
default:
return m_io_buffer;
case 3:
{
status=0;
if(cpustate->irq_state[1]!=CLEAR_LINE) status|=1; /* IRQ 2 */
if(cpustate->irq_state[0]!=CLEAR_LINE) status|=2; /* IRQ 1 */
if(cpustate->irq_state[2]!=CLEAR_LINE) status|=4; /* TIMER */
return status|(cpustate->io_buffer&(~H6280_IRQ_MASK));
status = 0;
if (m_irq_state[1] != CLEAR_LINE)
status |= 1; /* IRQ 2 */
if (m_irq_state[0] != CLEAR_LINE)
status |= 2; /* IRQ 1 */
if (m_irq_state[2] != CLEAR_LINE)
status |= 4; /* TIMER */
return status | (m_io_buffer & (~H6280_IRQ_MASK));
}
case 2: return cpustate->irq_mask|(cpustate->io_buffer&(~H6280_IRQ_MASK));
case 2:
return m_irq_mask | (m_io_buffer & (~H6280_IRQ_MASK));
}
}
WRITE8_HANDLER( h6280_irq_status_w )
WRITE8_MEMBER( h6280_device::irq_status_w )
{
h6280_Regs *cpustate = get_safe_token(&space.device());
cpustate->io_buffer=data;
switch (offset&3)
m_io_buffer = data;
switch (offset & 3)
{
default:cpustate->io_buffer=data;break;
default:
m_io_buffer = data;
break;
case 2: /* Write irq mask */
cpustate->irq_mask=data&0x7;
m_irq_mask = data & 0x7;
CHECK_IRQ_LINES;
break;
case 3: /* Timer irq ack */
set_irq_line(cpustate, 2, CLEAR_LINE);
set_irq_line(2, CLEAR_LINE);
break;
}
}
READ8_HANDLER( h6280_timer_r )
READ8_MEMBER( h6280_device::timer_r )
{
/* only returns countdown */
h6280_Regs *cpustate = get_safe_token(&space.device());
return ((cpustate->timer_value >> 10)&0x7F)|(cpustate->io_buffer&0x80);
return ((m_timer_value >> 10) & 0x7F) | (m_io_buffer & 0x80);
}
WRITE8_HANDLER( h6280_timer_w )
WRITE8_MEMBER( h6280_device::timer_w )
{
h6280_Regs *cpustate = get_safe_token(&space.device());
cpustate->io_buffer=data;
switch (offset & 1) {
m_io_buffer = data;
switch (offset & 1)
{
case 0: /* Counter preload */
cpustate->timer_load=cpustate->timer_value=((data&127)+1)*1024;
m_timer_load = m_timer_value = ((data & 127) + 1) * 1024;
return;
case 1: /* Counter enable */
if(data&1)
if (data & 1)
{ /* stop -> start causes reload */
if(cpustate->timer_status==0) cpustate->timer_value=cpustate->timer_load;
if(m_timer_status == 0)
m_timer_value = m_timer_load;
}
cpustate->timer_status=data&1;
m_timer_status = data & 1;
return;
}
}
static CPU_TRANSLATE( h6280 )
bool h6280_device::memory_translate(address_spacenum spacenum, int intention, offs_t &address)
{
h6280_Regs* cpustate = get_safe_token(device);
if (space == AS_PROGRAM)
*address = TRANSLATED(*address);
if (spacenum == AS_PROGRAM)
address = TRANSLATED(address);
return TRUE;
}
UINT8 h6280io_get_buffer(device_t *device)
UINT8 h6280_device::io_get_buffer()
{
h6280_Regs* cpustate = get_safe_token(device);
return cpustate->io_buffer;
}
void h6280io_set_buffer(device_t *device, UINT8 data)
{
h6280_Regs* cpustate = get_safe_token(device);
cpustate->io_buffer=data;
return m_io_buffer;
}
/*****************************************************************************/
/**************************************************************************
* Generic set_info
**************************************************************************/
static CPU_SET_INFO( h6280 )
void h6280_device::io_set_buffer(UINT8 data)
{
h6280_Regs* cpustate = get_safe_token(device);
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(cpustate, 0, info->i); break;
case CPUINFO_INT_INPUT_STATE + 1: set_irq_line(cpustate, 1, info->i); break;
case CPUINFO_INT_INPUT_STATE + 2: set_irq_line(cpustate, 2, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + H6280_PC: PCW = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + H6280_S: S = info->i; break;
case CPUINFO_INT_REGISTER + H6280_P: P = info->i; break;
case CPUINFO_INT_REGISTER + H6280_A: A = info->i; break;
case CPUINFO_INT_REGISTER + H6280_X: X = info->i; break;
case CPUINFO_INT_REGISTER + H6280_Y: Y = info->i; break;
case CPUINFO_INT_REGISTER + H6280_IRQ_MASK: cpustate->irq_mask = info->i; CHECK_IRQ_LINES; break;
case CPUINFO_INT_REGISTER + H6280_TIMER_STATE: cpustate->timer_status = info->i; break;
case CPUINFO_INT_REGISTER + H6280_NMI_STATE: set_irq_line( cpustate, INPUT_LINE_NMI, info->i ); break;
case CPUINFO_INT_REGISTER + H6280_IRQ1_STATE: set_irq_line( cpustate, 0, info->i ); break;
case CPUINFO_INT_REGISTER + H6280_IRQ2_STATE: set_irq_line( cpustate, 1, info->i ); break;
case CPUINFO_INT_REGISTER + H6280_IRQT_STATE: set_irq_line( cpustate, 2, info->i ); break;
case CPUINFO_INT_REGISTER + H6280_M1: cpustate->mmr[0] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M2: cpustate->mmr[1] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M3: cpustate->mmr[2] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M4: cpustate->mmr[3] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M5: cpustate->mmr[4] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M6: cpustate->mmr[5] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M7: cpustate->mmr[6] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M8: cpustate->mmr[7] = info->i; break;
}
m_io_buffer = data;
}
/**************************************************************************
* Generic get_info
**************************************************************************/
CPU_GET_INFO( h6280 )
{
h6280_Regs* cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(h6280_Regs); break;
case CPUINFO_INT_INPUT_LINES: info->i = 3; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 7; break;
case CPUINFO_INT_MIN_CYCLES: info->i = 2; break;
case CPUINFO_INT_MAX_CYCLES: info->i = 17 + 6*65536; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 21; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
case CPUINFO_INT_LOGADDR_WIDTH_PROGRAM: info->i = 16; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 2; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + 0: info->i = cpustate->irq_state[0]; break;
case CPUINFO_INT_INPUT_STATE + 1: info->i = cpustate->irq_state[1]; break;
case CPUINFO_INT_INPUT_STATE + 2: info->i = cpustate->irq_state[2]; break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->nmi_state; break;
case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->ppc.d; break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + H6280_PC: info->i = PCD; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + H6280_S: info->i = S; break;
case CPUINFO_INT_REGISTER + H6280_P: info->i = P; break;
case CPUINFO_INT_REGISTER + H6280_A: info->i = A; break;
case CPUINFO_INT_REGISTER + H6280_X: info->i = X; break;
case CPUINFO_INT_REGISTER + H6280_Y: info->i = Y; break;
case CPUINFO_INT_REGISTER + H6280_IRQ_MASK: info->i = cpustate->irq_mask; break;
case CPUINFO_INT_REGISTER + H6280_TIMER_STATE: info->i = cpustate->timer_status; break;
case CPUINFO_INT_REGISTER + H6280_NMI_STATE: info->i = cpustate->nmi_state; break;
case CPUINFO_INT_REGISTER + H6280_IRQ1_STATE: info->i = cpustate->irq_state[0]; break;
case CPUINFO_INT_REGISTER + H6280_IRQ2_STATE: info->i = cpustate->irq_state[1]; break;
case CPUINFO_INT_REGISTER + H6280_IRQT_STATE: info->i = cpustate->irq_state[2]; break;
case CPUINFO_INT_REGISTER + H6280_M1: info->i = cpustate->mmr[0]; break;
case CPUINFO_INT_REGISTER + H6280_M2: info->i = cpustate->mmr[1]; break;
case CPUINFO_INT_REGISTER + H6280_M3: info->i = cpustate->mmr[2]; break;
case CPUINFO_INT_REGISTER + H6280_M4: info->i = cpustate->mmr[3]; break;
case CPUINFO_INT_REGISTER + H6280_M5: info->i = cpustate->mmr[4]; break;
case CPUINFO_INT_REGISTER + H6280_M6: info->i = cpustate->mmr[5]; break;
case CPUINFO_INT_REGISTER + H6280_M7: info->i = cpustate->mmr[6]; break;
case CPUINFO_INT_REGISTER + H6280_M8: info->i = cpustate->mmr[7]; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(h6280); break;
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h6280); break;
case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(h6280); break;
case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(h6280); break;
case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(h6280); break;
case CPUINFO_FCT_BURN: info->burn = NULL; break;
case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(h6280);break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->ICount; break;
case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(h6280); break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "HuC6280"); break;
case CPUINFO_STR_FAMILY: strcpy(info->s, "Hudsonsoft 6280"); break;
case CPUINFO_STR_VERSION: strcpy(info->s, "1.11"); break;
case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Bryan McPhail, mish@tendril.co.uk"); break;
case CPUINFO_STR_FLAGS:
sprintf(info->s, "%c%c%c%c%c%c%c%c",
cpustate->p & 0x80 ? 'N':'.',
cpustate->p & 0x40 ? 'V':'.',
cpustate->p & 0x20 ? 'R':'.',
cpustate->p & 0x10 ? 'B':'.',
cpustate->p & 0x08 ? 'D':'.',
cpustate->p & 0x04 ? 'I':'.',
cpustate->p & 0x02 ? 'Z':'.',
cpustate->p & 0x01 ? 'C':'.');
break;
case CPUINFO_STR_REGISTER + H6280_PC: sprintf(info->s, "PC:%04X", cpustate->pc.d); break;
case CPUINFO_STR_REGISTER + H6280_S: sprintf(info->s, "S:%02X", cpustate->sp.b.l); break;
case CPUINFO_STR_REGISTER + H6280_P: sprintf(info->s, "P:%02X", cpustate->p); break;
case CPUINFO_STR_REGISTER + H6280_A: sprintf(info->s, "A:%02X", cpustate->a); break;
case CPUINFO_STR_REGISTER + H6280_X: sprintf(info->s, "X:%02X", cpustate->x); break;
case CPUINFO_STR_REGISTER + H6280_Y: sprintf(info->s, "Y:%02X", cpustate->y); break;
case CPUINFO_STR_REGISTER + H6280_IRQ_MASK: sprintf(info->s, "IM:%02X", cpustate->irq_mask);break;
case CPUINFO_STR_REGISTER + H6280_TIMER_STATE: sprintf(info->s, "TMR:%02X", cpustate->timer_status); break;
case CPUINFO_STR_REGISTER + H6280_NMI_STATE: sprintf(info->s, "NMI:%X", cpustate->nmi_state); break;
case CPUINFO_STR_REGISTER + H6280_IRQ1_STATE: sprintf(info->s, "IRQ1:%X", cpustate->irq_state[0]); break;
case CPUINFO_STR_REGISTER + H6280_IRQ2_STATE: sprintf(info->s, "IRQ2:%X", cpustate->irq_state[1]); break;
case CPUINFO_STR_REGISTER + H6280_IRQT_STATE: sprintf(info->s, "IRQT:%X", cpustate->irq_state[2]); break;
case CPUINFO_STR_REGISTER + H6280_M1: sprintf(info->s, "M1:%02X", cpustate->mmr[0]); break;
case CPUINFO_STR_REGISTER + H6280_M2: sprintf(info->s, "M2:%02X", cpustate->mmr[1]); break;
case CPUINFO_STR_REGISTER + H6280_M3: sprintf(info->s, "M3:%02X", cpustate->mmr[2]); break;
case CPUINFO_STR_REGISTER + H6280_M4: sprintf(info->s, "M4:%02X", cpustate->mmr[3]); break;
case CPUINFO_STR_REGISTER + H6280_M5: sprintf(info->s, "M5:%02X", cpustate->mmr[4]); break;
case CPUINFO_STR_REGISTER + H6280_M6: sprintf(info->s, "M6:%02X", cpustate->mmr[5]); break;
case CPUINFO_STR_REGISTER + H6280_M7: sprintf(info->s, "M7:%02X", cpustate->mmr[6]); break;
case CPUINFO_STR_REGISTER + H6280_M8: sprintf(info->s, "M8:%02X", cpustate->mmr[7]); break;
}
}
DEFINE_LEGACY_CPU_DEVICE(H6280, h6280);

181
src/emu/cpu/h6280/h6280.h
View File

@ -15,18 +15,36 @@
#ifndef __H6280_H__
#define __H6280_H__
#define LAZY_FLAGS 0
/***************************************************************************
REGISTER ENUMERATION
***************************************************************************/
enum
{
H6280_PC=1, H6280_S, H6280_P, H6280_A, H6280_X, H6280_Y,
H6280_IRQ_MASK, H6280_TIMER_STATE,
H6280_NMI_STATE, H6280_IRQ1_STATE, H6280_IRQ2_STATE, H6280_IRQT_STATE,
H6280_M1, H6280_M2, H6280_M3, H6280_M4,
H6280_M5, H6280_M6, H6280_M7, H6280_M8
H6280_PC = 1,
H6280_S,
H6280_P,
H6280_A,
H6280_X,
H6280_Y,
H6280_IRQ_MASK,
H6280_TIMER_STATE,
H6280_NMI_STATE,
H6280_IRQ1_STATE,
H6280_IRQ2_STATE,
H6280_IRQT_STATE,
H6280_M1,
H6280_M2,
H6280_M3,
H6280_M4,
H6280_M5,
H6280_M6,
H6280_M7,
H6280_M8
};
#define LAZY_FLAGS 0
#define H6280_RESET_VEC 0xfffe
#define H6280_NMI_VEC 0xfffc
#define H6280_TIMER_VEC 0xfffa
@ -34,56 +52,121 @@ enum
#define H6280_IRQ2_VEC 0xfff6 /* Aka BRK vector */
/****************************************************************************
* The 6280 registers.
****************************************************************************/
struct h6280_Regs
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
// ======================> h6280_device
// Used by core CPU interface
class h6280_device : public cpu_device
{
int ICount;
public:
// construction/destruction
h6280_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
PAIR ppc; /* previous program counter */
PAIR pc; /* program counter */
PAIR sp; /* stack pointer (always 100 - 1FF) */
PAIR zp; /* zero page address */
PAIR ea; /* effective address */
UINT8 a; /* Accumulator */
UINT8 x; /* X index register */
UINT8 y; /* Y index register */
UINT8 p; /* Processor status */
UINT8 mmr[8]; /* Hu6280 memory mapper registers */
UINT8 irq_mask; /* interrupt enable/disable */
UINT8 timer_status; /* timer status */
UINT8 timer_ack; /* timer acknowledge */
UINT8 clocks_per_cycle; /* 4 = low speed mode, 1 = high speed mode */
INT32 timer_value; /* timer interrupt */
INT32 timer_load; /* reload value */
UINT8 nmi_state;
UINT8 irq_state[3];
UINT8 irq_pending;
device_irq_acknowledge_callback irq_callback;
legacy_cpu_device *device;
address_space *program;
direct_read_data *direct;
address_space *io;
// public interfaces
void set_irq_line(int irqline, int state);
DECLARE_READ8_MEMBER( irq_status_r );
DECLARE_WRITE8_MEMBER( irq_status_w );
DECLARE_READ8_MEMBER( timer_r );
DECLARE_WRITE8_MEMBER( timer_w );
/* functions for use by the PSG and joypad port only! */
UINT8 io_get_buffer();
void io_set_buffer(UINT8);
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
virtual void device_stop();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const;
virtual UINT32 execute_max_cycles() const;
virtual UINT32 execute_input_lines() const;
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
virtual bool memory_translate(address_spacenum spacenum, int intention, offs_t &address);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const;
virtual UINT32 disasm_max_opcode_bytes() const;
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
// device_state_interface overrides
virtual void state_string_export(const device_state_entry &entry, astring &string);
// opcode accessors
UINT8 program_read8(offs_t addr);
void program_write8(offs_t addr, UINT8 data);
UINT8 program_read8z(offs_t addr);
void program_write8z(offs_t addr, UINT8 data);
UINT16 program_read16(offs_t addr);
UINT16 program_read16z(offs_t addr);
void push(UINT8 value);
void pull(UINT8 &value);
UINT8 read_opcode();
UINT8 read_opcode_arg();
// include the macros
#include "h6280ops.h"
// include the opcode macros and functions
#include "tblh6280.c"
// address spaces
const address_space_config m_program_config;
const address_space_config m_io_config;
// CPU registers
PAIR m_ppc; /* previous program counter */
PAIR m_pc; /* program counter */
PAIR m_sp; /* stack pointer (always 100 - 1FF) */
PAIR m_zp; /* zero page address */
PAIR m_ea; /* effective address */
UINT8 m_a; /* Accumulator */
UINT8 m_x; /* X index register */
UINT8 m_y; /* Y index register */
UINT8 m_p; /* Processor status */
UINT8 m_mmr[8]; /* Hu6280 memory mapper registers */
UINT8 m_irq_mask; /* interrupt enable/disable */
UINT8 m_timer_status; /* timer status */
UINT8 m_timer_ack; /* timer acknowledge */
UINT8 m_clocks_per_cycle; /* 4 = low speed mode, 1 = high speed mode */
INT32 m_timer_value; /* timer interrupt */
INT32 m_timer_load; /* reload value */
UINT8 m_nmi_state;
UINT8 m_irq_state[3];
UINT8 m_irq_pending;
#if LAZY_FLAGS
INT32 NZ; /* last value (lazy N and Z flag) */
INT32 m_nz; /* last value (lazy N and Z flag) */
#endif
UINT8 io_buffer; /* last value written to the PSG, timer, and interrupt pages */
UINT8 m_io_buffer; /* last value written to the PSG, timer, and interrupt pages */
// other internal states
int m_icount;
// address spaces
address_space *m_program;
address_space *m_io;
direct_read_data *m_direct;
typedef void (h6280_device::*ophandler)();
ophandler m_opcode[256];
static const ophandler s_opcodetable[256];
};
extern const device_type H6280;
DECLARE_LEGACY_CPU_DEVICE(H6280, h6280);
DECLARE_READ8_HANDLER( h6280_irq_status_r );
DECLARE_WRITE8_HANDLER( h6280_irq_status_w );
DECLARE_READ8_HANDLER( h6280_timer_r );
DECLARE_WRITE8_HANDLER( h6280_timer_w );
/* functions for use by the PSG and joypad port only! */
UINT8 h6280io_get_buffer(device_t*);
void h6280io_set_buffer(device_t*, UINT8);
CPU_DISASSEMBLE( h6280 );

406
src/emu/cpu/h6280/h6280ops.h
View File

@ -21,22 +21,22 @@
#define _fN 0x80
/* some shortcuts for improved readability */
#define A cpustate->a
#define X cpustate->x
#define Y cpustate->y
#define P cpustate->p
#define S cpustate->sp.b.l
#define A m_a
#define X m_x
#define Y m_y
#define P m_p
#define S m_sp.b.l
#define TRANSLATED(addr) ((cpustate->mmr[(addr)>>13&7] << 13) | ((addr)&0x1fff))
#define H6280_CYCLES(cyc) \
{ \
cpustate->ICount -= ((cyc) * cpustate->clocks_per_cycle); \
cpustate->timer_value -= ((cyc) * cpustate->clocks_per_cycle); \
#define TRANSLATED(addr) ((m_mmr[(addr) >> 13 & 7] << 13) | ((addr) & 0x1fff))
#define H6280_CYCLES(cyc) \
{ \
m_icount -= ((cyc) * m_clocks_per_cycle); \
m_timer_value -= ((cyc) * m_clocks_per_cycle); \
}
#if LAZY_FLAGS
#define NZ cpustate->NZ
#define NZ m_NZ
#define SET_NZ(n) \
P &= ~_fT; \
NZ = ((n & _fN) << 8) | n
@ -50,20 +50,20 @@
#endif
#define EAL cpustate->ea.b.l
#define EAH cpustate->ea.b.h
#define EAW cpustate->ea.w.l
#define EAD cpustate->ea.d
#define EAL m_ea.b.l
#define EAH m_ea.b.h
#define EAW m_ea.w.l
#define EAD m_ea.d
#define ZPL cpustate->zp.b.l
#define ZPH cpustate->zp.b.h
#define ZPW cpustate->zp.w.l
#define ZPD cpustate->zp.d
#define ZPL m_zp.b.l
#define ZPH m_zp.b.h
#define ZPW m_zp.w.l
#define ZPD m_zp.d
#define PCL cpustate->pc.b.l
#define PCH cpustate->pc.b.h
#define PCW cpustate->pc.w.l
#define PCD cpustate->pc.d
#define PCL m_pc.b.l
#define PCH m_pc.b.h
#define PCW m_pc.w.l
#define PCD m_pc.d
#define CLEAR_T \
P &= ~_fT;
@ -71,44 +71,44 @@
#define DO_INTERRUPT(vector) \
{ \
H6280_CYCLES(7); /* 7 cycles for an int */ \
PUSH(PCH); \
PUSH(PCL); \
COMPOSE_P(0,_fB); \
PUSH(P); \
push(PCH); \
push(PCL); \
COMPOSE_P(0, _fB); \
push(P); \
P = (P & ~_fD) | _fI; /* knock out D and set I flag */ \
PCL = RDMEM(cpustate, vector); \
PCH = RDMEM(cpustate, (vector+1)); \
PCL = program_read8(vector); \
PCH = program_read8(vector + 1); \
}
#define CHECK_AND_TAKE_IRQ_LINES \
if ( cpustate->nmi_state != CLEAR_LINE ) { \
cpustate->nmi_state = CLEAR_LINE; \
DO_INTERRUPT(H6280_NMI_VEC); \
} \
else if( !(P & _fI) ) \
{ \
if ( cpustate->irq_state[2] != CLEAR_LINE && \
!(cpustate->irq_mask & 0x4) ) \
{ \
DO_INTERRUPT(H6280_TIMER_VEC); \
} else \
if ( cpustate->irq_state[0] != CLEAR_LINE && \
!(cpustate->irq_mask & 0x2) ) \
{ \
DO_INTERRUPT(H6280_IRQ1_VEC); \
(*cpustate->irq_callback)(cpustate->device, 0); \
} else \
if ( cpustate->irq_state[1] != CLEAR_LINE && \
!(cpustate->irq_mask & 0x1) ) \
{ \
DO_INTERRUPT(H6280_IRQ2_VEC); \
(*cpustate->irq_callback)(cpustate->device, 1); \
} \
#define CHECK_AND_TAKE_IRQ_LINES \
if ( m_nmi_state != CLEAR_LINE ) { \
m_nmi_state = CLEAR_LINE; \
DO_INTERRUPT(H6280_NMI_VEC); \
} \
else if( !(P & _fI) ) \
{ \
if ( m_irq_state[2] != CLEAR_LINE && \
!(m_irq_mask & 0x4) ) \
{ \
DO_INTERRUPT(H6280_TIMER_VEC); \
} else \
if ( m_irq_state[0] != CLEAR_LINE && \
!(m_irq_mask & 0x2) ) \
{ \
DO_INTERRUPT(H6280_IRQ1_VEC); \
standard_irq_callback(0); \
} else \
if ( m_irq_state[1] != CLEAR_LINE && \
!(m_irq_mask & 0x1) ) \
{ \
DO_INTERRUPT(H6280_IRQ2_VEC); \
standard_irq_callback(1); \
} \
}
#define CHECK_IRQ_LINES \
if ( ! cpustate->irq_pending ) \
cpustate->irq_pending = 2;
#define CHECK_IRQ_LINES \
if (!m_irq_pending) \
m_irq_pending = 2;
/***************************************************************
* CHECK_VDC_VCE_PENALTY
@ -120,74 +120,6 @@
H6280_CYCLES(1); \
}
/***************************************************************
* RDMEM read memory
***************************************************************/
INLINE UINT8 RDMEM(h6280_Regs* cpustate, offs_t addr) {
CHECK_VDC_VCE_PENALTY(addr);
return cpustate->program->read_byte(TRANSLATED(addr));
}
/***************************************************************
* WRMEM write memory
***************************************************************/
INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
CHECK_VDC_VCE_PENALTY(addr);
cpustate->program->write_byte(TRANSLATED(addr),data);
}
/***************************************************************
* RDMEMZ read memory - zero page
***************************************************************/
#define RDMEMZ(addr) \
cpustate->program->read_byte((cpustate->mmr[1] << 13) | ((addr)&0x1fff));
/***************************************************************
* WRMEMZ write memory - zero page
***************************************************************/
#define WRMEMZ(addr,data) \
cpustate->program->write_byte((cpustate->mmr[1] << 13) | ((addr)&0x1fff),data);
/***************************************************************
* RDMEMW read word from memory
***************************************************************/
#define RDMEMW(addr) \
cpustate->program->read_byte(TRANSLATED(addr)) \
| ( cpustate->program->read_byte(TRANSLATED(addr+1)) << 8 )
/***************************************************************
* RDZPWORD read a word from a zero page address
***************************************************************/
#define RDZPWORD(addr) \
((addr&0xff)==0xff) ? \
cpustate->program->read_byte((cpustate->mmr[1] << 13) | ((addr)&0x1fff)) \
+(cpustate->program->read_byte((cpustate->mmr[1] << 13) | ((addr-0xff)&0x1fff))<<8) : \
cpustate->program->read_byte((cpustate->mmr[1] << 13) | ((addr)&0x1fff)) \
+(cpustate->program->read_byte((cpustate->mmr[1] << 13) | ((addr+1)&0x1fff))<<8)
/***************************************************************
* push a register onto the stack
***************************************************************/
#define PUSH(Rg) cpustate->program->write_byte((cpustate->mmr[1] << 13) | cpustate->sp.d,Rg); S--
/***************************************************************
* pull a register from the stack
***************************************************************/
#define PULL(Rg) S++; Rg = cpustate->program->read_byte((cpustate->mmr[1] << 13) | cpustate->sp.d)
/***************************************************************
* RDOP read an opcode
***************************************************************/
#define RDOP() \
cpustate->direct->read_decrypted_byte(TRANSLATED(PCW))
/***************************************************************
* RDOPARG read an opcode argument
***************************************************************/
#define RDOPARG() \
cpustate->direct->read_raw_byte(TRANSLATED(PCW))
/***************************************************************
* BRA branch relative
***************************************************************/
@ -196,7 +128,7 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
if (cond) \
{ \
H6280_CYCLES(4); \
tmp = RDOPARG(); \
tmp = read_opcode_arg(); \
PCW++; \
EAW = PCW + (signed char)tmp; \
PCD = EAD; \
@ -217,7 +149,7 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
* EA = zero page address
***************************************************************/
#define EA_ZPG \
ZPL = RDOPARG(); \
ZPL = read_opcode_arg(); \
PCW++; \
EAD = ZPD
@ -232,7 +164,7 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
* EA = zero page address + X
***************************************************************/
#define EA_ZPX \
ZPL = RDOPARG() + X; \
ZPL = read_opcode_arg() + X; \
PCW++; \
EAD = ZPD
@ -240,7 +172,7 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
* EA = zero page address + Y
***************************************************************/
#define EA_ZPY \
ZPL = RDOPARG() + Y; \
ZPL = read_opcode_arg() + Y; \
PCW++; \
EAD = ZPD
@ -248,9 +180,9 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
* EA = absolute address
***************************************************************/
#define EA_ABS \
EAL = RDOPARG(); \
EAL = read_opcode_arg(); \
PCW++; \
EAH = RDOPARG(); \
EAH = read_opcode_arg(); \
PCW++
/***************************************************************
@ -271,25 +203,25 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
* EA = zero page indirect (65c02 pre indexed w/o X)
***************************************************************/
#define EA_ZPI \
ZPL = RDOPARG(); \
ZPL = read_opcode_arg(); \
PCW++; \
EAD = RDZPWORD(ZPD)
EAD = program_read16z(ZPD);
/***************************************************************
* EA = zero page + X indirect (pre indexed)
***************************************************************/
#define EA_IDX \
ZPL = RDOPARG() + X; \
ZPL = read_opcode_arg() + X; \
PCW++; \
EAD = RDZPWORD(ZPD);
EAD = program_read16z(ZPD);
/***************************************************************
* EA = zero page indirect + Y (post indexed)
***************************************************************/
#define EA_IDY \
ZPL = RDOPARG(); \
ZPL = read_opcode_arg(); \
PCW++; \
EAD = RDZPWORD(ZPD); \
EAD = program_read16z(ZPD); \
EAW += Y
/***************************************************************
@ -297,9 +229,9 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
***************************************************************/
#define EA_IND \
EA_ABS; \
tmp = RDMEM(cpustate, EAD); \
tmp = program_read8(EAD); \
EAD++; \
EAH = RDMEM(cpustate, EAD); \
EAH = program_read8(EAD); \
EAL = tmp
/***************************************************************
@ -308,42 +240,42 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
#define EA_IAX \
EA_ABS; \
EAD+=X; \
tmp = RDMEM(cpustate, EAD); \
tmp = program_read8(EAD); \
EAD++; \
EAH = RDMEM(cpustate, EAD); \
EAH = program_read8(EAD); \
EAL = tmp
/* read a value into tmp */
#define RD_IMM tmp = RDOPARG(); PCW++
#define RD_IMM2 tmp2 = RDOPARG(); PCW++
#define RD_IMM tmp = read_opcode_arg(); PCW++
#define RD_IMM2 tmp2 = read_opcode_arg(); PCW++
#define RD_ACC tmp = A
#define RD_ZPG EA_ZPG; tmp = RDMEMZ(EAD)
#define RD_ZPX EA_ZPX; tmp = RDMEMZ(EAD)
#define RD_ZPY EA_ZPY; tmp = RDMEMZ(EAD)
#define RD_ABS EA_ABS; tmp = RDMEM(cpustate, EAD)
#define RD_ABX EA_ABX; tmp = RDMEM(cpustate, EAD)
#define RD_ABY EA_ABY; tmp = RDMEM(cpustate, EAD)
#define RD_ZPI EA_ZPI; tmp = RDMEM(cpustate, EAD)
#define RD_IDX EA_IDX; tmp = RDMEM(cpustate, EAD)
#define RD_IDY EA_IDY; tmp = RDMEM(cpustate, EAD)
#define RD_TFL EA_TFLG; tflagtemp = RDMEMZ(EAD)
#define RD_ZPG EA_ZPG; tmp = program_read8z(EAD)
#define RD_ZPX EA_ZPX; tmp = program_read8z(EAD)
#define RD_ZPY EA_ZPY; tmp = program_read8z(EAD)
#define RD_ABS EA_ABS; tmp = program_read8(EAD)
#define RD_ABX EA_ABX; tmp = program_read8(EAD)
#define RD_ABY EA_ABY; tmp = program_read8(EAD)
#define RD_ZPI EA_ZPI; tmp = program_read8(EAD)
#define RD_IDX EA_IDX; tmp = program_read8(EAD)
#define RD_IDY EA_IDY; tmp = program_read8(EAD)
#define RD_TFL EA_TFLG; tflagtemp = program_read8z(EAD)
/* write a value from tmp */
#define WR_ZPG EA_ZPG; WRMEMZ(EAD, tmp)
#define WR_ZPX EA_ZPX; WRMEMZ(EAD, tmp)
#define WR_ZPY EA_ZPY; WRMEMZ(EAD, tmp)
#define WR_ABS EA_ABS; WRMEM(cpustate, EAD, tmp)
#define WR_ABX EA_ABX; WRMEM(cpustate, EAD, tmp)
#define WR_ABY EA_ABY; WRMEM(cpustate, EAD, tmp)
#define WR_ZPI EA_ZPI; WRMEM(cpustate, EAD, tmp)
#define WR_IDX EA_IDX; WRMEM(cpustate, EAD, tmp)
#define WR_IDY EA_IDY; WRMEM(cpustate, EAD, tmp)
#define WR_ZPG EA_ZPG; program_write8z(EAD, tmp)
#define WR_ZPX EA_ZPX; program_write8z(EAD, tmp)
#define WR_ZPY EA_ZPY; program_write8z(EAD, tmp)
#define WR_ABS EA_ABS; program_write8(EAD, tmp)
#define WR_ABX EA_ABX; program_write8(EAD, tmp)
#define WR_ABY EA_ABY; program_write8(EAD, tmp)
#define WR_ZPI EA_ZPI; program_write8(EAD, tmp)
#define WR_IDX EA_IDX; program_write8(EAD, tmp)
#define WR_IDY EA_IDY; program_write8(EAD, tmp)
/* write back a value from tmp to the last EA */
#define WB_ACC A = (UINT8)tmp;
#define WB_EA WRMEM(cpustate, EAD, tmp)
#define WB_EAZ WRMEMZ(EAD, tmp)
#define WB_TFL WRMEMZ(EAD, tflagtemp)
#define WB_EA program_write8(EAD, tmp)
#define WB_EAZ program_write8z(EAD, tmp)
#define WB_TFL program_write8z(EAD, tflagtemp)
/***************************************************************
*
@ -515,8 +447,7 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
/* 6280 ********************************************************
* BIT Bit test
***************************************************************/
#undef BIT
#define BIT \
#define HBIT \
P = (P & ~(_fN|_fV|_fT|_fZ)) \
| ((tmp&0x80) ? _fN:0) \
| ((tmp&0x40) ? _fV:0) \
@ -558,19 +489,19 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
logerror("BRK %04x\n",PCW); \
CLEAR_T; \
PCW++; \
PUSH(PCH); \
PUSH(PCL); \
PUSH(P); \
push(PCH); \
push(PCL); \
push(P); \
P = (P & ~_fD) | _fI; \
PCL = RDMEM(cpustate, H6280_IRQ2_VEC); \
PCH = RDMEM(cpustate, H6280_IRQ2_VEC+1); \
PCL = program_read8(H6280_IRQ2_VEC); \
PCH = program_read8(H6280_IRQ2_VEC+1); \
/* 6280 ********************************************************
* BSR Branch to subroutine
***************************************************************/
#define BSR \
PUSH(PCH); \
PUSH(PCL); \
push(PCH); \
push(PCL); \
H6280_CYCLES(4); /* 4 cycles here, 4 in BRA */ \
BRA(1)
@ -770,8 +701,8 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
#define JSR \
CLEAR_T; \
PCW--; \
PUSH(PCH); \
PUSH(PCL); \
push(PCH); \
push(PCL); \
PCD = EAD; \
/* 6280 ********************************************************
@ -841,7 +772,7 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
***************************************************************/
#define PHA \
CLEAR_T; \
PUSH(A)
push(A)
/* 6280 ********************************************************
* PHP Push processor status (flags)
@ -849,28 +780,28 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
#define PHP \
CLEAR_T; \
COMPOSE_P(0,0); \
PUSH(P)
push(P)
/* 6280 ********************************************************
* PHX Push index X
***************************************************************/
#define PHX \
CLEAR_T; \
PUSH(X)
push(X)
/* 6280 ********************************************************
* PHY Push index Y
***************************************************************/
#define PHY \
CLEAR_T; \
PUSH(Y)
push(Y)
/* 6280 ********************************************************
* PLA Pull accumulator
***************************************************************/
#define PLA \
CLEAR_T; \
PULL(A); \
pull(A); \
SET_NZ(A)
/* 6280 ********************************************************
@ -879,7 +810,7 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
#if LAZY_FLAGS
#define PLP \
PULL(P); \
pull(P); \
P |= _fB; \
NZ = ((P & _fN) << 8) | \
((P & _fZ) ^ _fZ); \
@ -888,7 +819,7 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
#else
#define PLP \
PULL(P); \
pull(P); \
P |= _fB; \
CHECK_IRQ_LINES
#endif
@ -898,7 +829,7 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
***************************************************************/
#define PLX \
CLEAR_T; \
PULL(X); \
pull(X); \
SET_NZ(X)
/* 6280 ********************************************************
@ -906,7 +837,7 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
***************************************************************/
#define PLY \
CLEAR_T; \
PULL(Y); \
pull(Y); \
SET_NZ(Y)
/* 6280 ********************************************************
@ -945,20 +876,20 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
#if LAZY_FLAGS
#define RTI \
PULL(P); \
pull(P); \
P |= _fB; \
NZ = ((P & _fN) << 8) | \
((P & _fZ) ^ _fZ); \
PULL(PCL); \
PULL(PCH); \
pull(PCL); \
pull(PCH); \
CHECK_IRQ_LINES
#else
#define RTI \
PULL(P); \
pull(P); \
P |= _fB; \
PULL(PCL); \
PULL(PCH); \
pull(PCL); \
pull(PCH); \
CHECK_IRQ_LINES
#endif
@ -968,8 +899,8 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
***************************************************************/
#define RTS \
CLEAR_T; \
PULL(PCL); \
PULL(PCH); \
pull(PCL); \
pull(PCH); \
PCW++;
/* 6280 ********************************************************
@ -1110,21 +1041,21 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
***************************************************************/
#define ST0 \
CLEAR_T; \
cpustate->io->write_byte(0x0000,tmp)
m_io->write_byte(0x0000,tmp)
/* 6280 ********************************************************
* ST1 Store at hardware address 2
***************************************************************/
#define ST1 \
CLEAR_T; \
cpustate->io->write_byte(0x0002,tmp)
m_io->write_byte(0x0002,tmp)
/* 6280 ********************************************************
* ST2 Store at hardware address 3
***************************************************************/
#define ST2 \
CLEAR_T; \
cpustate->io->write_byte(0x0003,tmp)
m_io->write_byte(0x0003,tmp)
/* 6280 ********************************************************
* STA Store accumulator
@ -1168,15 +1099,16 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
***************************************************************/
#define TAI \
CLEAR_T; \
from=RDMEMW(PCW); \
to =RDMEMW(PCW+2); \
length=RDMEMW(PCW+4); \
PCW+=6; \
alternate=0; \
from = program_read16(PCW); \
to = program_read16(PCW + 2); \
length = program_read16(PCW + 4); \
PCW += 6; \
alternate = 0; \
if (!length) length = 0x10000; \
H6280_CYCLES( ((6 * length) + 17) ); \
while ((length--) != 0) { \
WRMEM(cpustate, to,RDMEM(cpustate, from+alternate)); \
while ((length--) != 0) \
{ \
program_write8(to, program_read8(from + alternate)); \
to++; \
alternate ^= 1; \
}
@ -1186,14 +1118,14 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
***************************************************************/
#define TAM \
CLEAR_T; \
if (tmp&0x01) cpustate->mmr[0] = A; \
if (tmp&0x02) cpustate->mmr[1] = A; \
if (tmp&0x04) cpustate->mmr[2] = A; \
if (tmp&0x08) cpustate->mmr[3] = A; \
if (tmp&0x10) cpustate->mmr[4] = A; \
if (tmp&0x20) cpustate->mmr[5] = A; \
if (tmp&0x40) cpustate->mmr[6] = A; \
if (tmp&0x80) cpustate->mmr[7] = A
if (tmp&0x01) m_mmr[0] = A; \
if (tmp&0x02) m_mmr[1] = A; \
if (tmp&0x04) m_mmr[2] = A; \
if (tmp&0x08) m_mmr[3] = A; \
if (tmp&0x10) m_mmr[4] = A; \
if (tmp&0x20) m_mmr[5] = A; \
if (tmp&0x40) m_mmr[6] = A; \
if (tmp&0x80) m_mmr[7] = A
/* 6280 ********************************************************
* TAX Transfer accumulator to index X
@ -1216,14 +1148,14 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
***************************************************************/
#define TDD \
CLEAR_T; \
from=RDMEMW(PCW); \
to =RDMEMW(PCW+2); \
length=RDMEMW(PCW+4); \
from = program_read16(PCW); \
to = program_read16(PCW + 2); \
length = program_read16(PCW + 4); \
PCW+=6; \
if (!length) length = 0x10000; \
H6280_CYCLES( ((6 * length) + 17) ); \
while ((length--) != 0) { \
WRMEM(cpustate, to,RDMEM(cpustate, from)); \
program_write8(to, program_read8(from)); \
to--; \
from--; \
}
@ -1233,15 +1165,15 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
***************************************************************/
#define TIA \
CLEAR_T; \
from=RDMEMW(PCW); \
to =RDMEMW(PCW+2); \
length=RDMEMW(PCW+4); \
from = program_read16(PCW); \
to = program_read16(PCW + 2); \
length = program_read16(PCW + 4); \
PCW+=6; \
alternate=0; \
if (!length) length = 0x10000; \
H6280_CYCLES( ((6 * length) + 17) ); \
while ((length--) != 0) { \
WRMEM(cpustate, to+alternate,RDMEM(cpustate, from)); \
program_write8(to + alternate, program_read8(from)); \
from++; \
alternate ^= 1; \
}
@ -1251,14 +1183,14 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
***************************************************************/
#define TII \
CLEAR_T; \
from=RDMEMW(PCW); \
to =RDMEMW(PCW+2); \
length=RDMEMW(PCW+4); \
PCW+=6; \
from = program_read16(PCW); \
to = program_read16(PCW + 2); \
length = program_read16(PCW + 4); \
PCW += 6; \
if (!length) length = 0x10000; \
H6280_CYCLES( ((6 * length) + 17) ); \
while ((length--) != 0) { \
WRMEM(cpustate, to,RDMEM(cpustate, from)); \
program_write8(to, program_read8(from)); \
to++; \
from++; \
}
@ -1268,14 +1200,14 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
***************************************************************/
#define TIN \
CLEAR_T; \
from=RDMEMW(PCW); \
to =RDMEMW(PCW+2); \
length=RDMEMW(PCW+4); \
from = program_read16(PCW); \
to = program_read16(PCW + 2); \
length = program_read16(PCW + 4); \
PCW+=6; \
if (!length) length = 0x10000; \
H6280_CYCLES( ((6 * length) + 17) ); \
while ((length--) != 0) { \
WRMEM(cpustate, to,RDMEM(cpustate, from)); \
program_write8(to, program_read8(from)); \
from++; \
}
@ -1285,14 +1217,14 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
***************************************************************/
#define TMA \
CLEAR_T; \
if (tmp&0x01) A = cpustate->mmr[0]; \
if (tmp&0x02) A = cpustate->mmr[1]; \
if (tmp&0x04) A = cpustate->mmr[2]; \
if (tmp&0x08) A = cpustate->mmr[3]; \
if (tmp&0x10) A = cpustate->mmr[4]; \
if (tmp&0x20) A = cpustate->mmr[5]; \
if (tmp&0x40) A = cpustate->mmr[6]; \
if (tmp&0x80) A = cpustate->mmr[7]
if (tmp&0x01) A = m_mmr[0]; \
if (tmp&0x02) A = m_mmr[1]; \
if (tmp&0x04) A = m_mmr[2]; \
if (tmp&0x08) A = m_mmr[3]; \
if (tmp&0x10) A = m_mmr[4]; \
if (tmp&0x20) A = m_mmr[5]; \
if (tmp&0x40) A = m_mmr[6]; \
if (tmp&0x80) A = m_mmr[7]
/* 6280 ********************************************************
* TRB Test and reset bits
@ -1361,10 +1293,10 @@ INLINE void WRMEM(h6280_Regs* cpustate, offs_t addr, UINT8 data) {
* CSH Set CPU in high speed mode
***************************************************************/
#define CSH \
cpustate->clocks_per_cycle = 1;
m_clocks_per_cycle = 1;
/* 6280 ********************************************************
* CSL Set CPU in low speed mode
***************************************************************/
#define CSL \
cpustate->clocks_per_cycle = 4;
m_clocks_per_cycle = 4;

55
src/emu/cpu/h6280/tblh6280.c
View File

@ -11,7 +11,7 @@
******************************************************************************/
#undef OP
#define OP(nnn) INLINE void h6280##nnn(h6280_Regs* cpustate)
#define OP(nnn) inline void op##nnn()
/*****************************************************************************
*****************************************************************************
@ -93,7 +93,7 @@ OP(_0d3) { int to,from,length; TIN; } // 6*l+17 TIN XFER
OP(_0f3) { int to,from,length,alternate; TAI; } // 6*l+17 TAI XFER
OP(_004) { int tmp; H6280_CYCLES(6); RD_ZPG; TSB; WB_EAZ; } // 6 TSB ZPG
OP(_024) { int tmp; H6280_CYCLES(4); RD_ZPG; BIT; } // 4 BIT ZPG
OP(_024) { int tmp; H6280_CYCLES(4); RD_ZPG; HBIT; } // 4 BIT ZPG
OP(_044) { int tmp; BSR; } // 8 BSR REL
OP(_064) { int tmp; H6280_CYCLES(4); STZ; WR_ZPG; } // 4 STZ ZPG
OP(_084) { int tmp; H6280_CYCLES(4); STY; WR_ZPG; } // 4 STY ZPG
@ -102,7 +102,7 @@ OP(_0c4) { int tmp; H6280_CYCLES(4); RD_ZPG; CPY; } // 4 CPY ZPG
OP(_0e4) { int tmp; H6280_CYCLES(4); RD_ZPG; CPX; } // 4 CPX ZPG
OP(_014) { int tmp; H6280_CYCLES(6); RD_ZPG; TRB; WB_EAZ; } // 6 TRB ZPG
OP(_034) { int tmp; H6280_CYCLES(4); RD_ZPX; BIT; } // 4 BIT ZPX
OP(_034) { int tmp; H6280_CYCLES(4); RD_ZPX; HBIT; } // 4 BIT ZPX
OP(_054) { H6280_CYCLES(3); CSL; } // 3 CSL
OP(_074) { int tmp; H6280_CYCLES(4); STZ; WR_ZPX; } // 4 STZ ZPX
OP(_094) { int tmp; H6280_CYCLES(4); STY; WR_ZPX; } // 4 STY ZPX
@ -137,10 +137,10 @@ OP(_0a6) { int tmp; H6280_CYCLES(4); RD_ZPG; LDX; } // 4 LDX ZPG
OP(_0c6) { int tmp; H6280_CYCLES(6); RD_ZPG; DEC; WB_EAZ; } // 6 DEC ZPG
OP(_0e6) { int tmp; H6280_CYCLES(6); RD_ZPG; INC; WB_EAZ; } // 6 INC ZPG
OP(_016) { int tmp; H6280_CYCLES(6); RD_ZPX; ASL; WB_EAZ } // 6 ASL ZPX
OP(_036) { int tmp; H6280_CYCLES(6); RD_ZPX; ROL; WB_EAZ } // 6 ROL ZPX
OP(_056) { int tmp; H6280_CYCLES(6); RD_ZPX; LSR; WB_EAZ } // 6 LSR ZPX
OP(_076) { int tmp; H6280_CYCLES(6); RD_ZPX; ROR; WB_EAZ } // 6 ROR ZPX
OP(_016) { int tmp; H6280_CYCLES(6); RD_ZPX; ASL; WB_EAZ; } // 6 ASL ZPX
OP(_036) { int tmp; H6280_CYCLES(6); RD_ZPX; ROL; WB_EAZ; } // 6 ROL ZPX
OP(_056) { int tmp; H6280_CYCLES(6); RD_ZPX; LSR; WB_EAZ; } // 6 LSR ZPX
OP(_076) { int tmp; H6280_CYCLES(6); RD_ZPX; ROR; WB_EAZ; } // 6 ROR ZPX
OP(_096) { int tmp; H6280_CYCLES(4); STX; WR_ZPY; } // 4 STX ZPY
OP(_0b6) { int tmp; H6280_CYCLES(4); RD_ZPY; LDX; } // 4 LDX ZPY
OP(_0d6) { int tmp; H6280_CYCLES(6); RD_ZPX; DEC; WB_EAZ; } // 6 DEC ZPX
@ -186,7 +186,7 @@ OP(_009) { int tmp; H6280_CYCLES(2); RD_IMM; ORA; } // 2 ORA IMM
OP(_029) { int tmp; H6280_CYCLES(2); RD_IMM; AND; } // 2 AND IMM
OP(_049) { int tmp; H6280_CYCLES(2); RD_IMM; EOR; } // 2 EOR IMM
OP(_069) { int tmp; H6280_CYCLES(2); RD_IMM; ADC; } // 2 ADC IMM
OP(_089) { int tmp; H6280_CYCLES(2); RD_IMM; BIT; } // 2 BIT IMM
OP(_089) { int tmp; H6280_CYCLES(2); RD_IMM; HBIT; } // 2 BIT IMM
OP(_0a9) { int tmp; H6280_CYCLES(2); RD_IMM; LDA; } // 2 LDA IMM
OP(_0c9) { int tmp; H6280_CYCLES(2); RD_IMM; CMP; } // 2 CMP IMM
OP(_0e9) { int tmp; H6280_CYCLES(2); RD_IMM; SBC; } // 2 SBC IMM
@ -237,7 +237,7 @@ OP(_0db) { H6280_CYCLES(2); NOP; } // 2 NOP
OP(_0fb) { H6280_CYCLES(2); NOP; } // 2 NOP
OP(_00c) { int tmp; H6280_CYCLES(7); RD_ABS; TSB; WB_EA; } // 7 TSB ABS
OP(_02c) { int tmp; H6280_CYCLES(5); RD_ABS; BIT; } // 5 BIT ABS
OP(_02c) { int tmp; H6280_CYCLES(5); RD_ABS; HBIT; } // 5 BIT ABS
OP(_04c) { H6280_CYCLES(4); EA_ABS; JMP; } // 4 JMP ABS
OP(_06c) { int tmp; H6280_CYCLES(7); EA_IND; JMP; } // 7 JMP IND
OP(_08c) { int tmp; H6280_CYCLES(5); STY; WR_ABS; } // 5 STY ABS
@ -246,7 +246,7 @@ OP(_0cc) { int tmp; H6280_CYCLES(5); RD_ABS; CPY; } // 5 CPY ABS
OP(_0ec) { int tmp; H6280_CYCLES(5); RD_ABS; CPX; } // 5 CPX ABS
OP(_01c) { int tmp; H6280_CYCLES(7); RD_ABS; TRB; WB_EA; } // 7 TRB ABS
OP(_03c) { int tmp; H6280_CYCLES(5); RD_ABX; BIT; } // 5 BIT ABX
OP(_03c) { int tmp; H6280_CYCLES(5); RD_ABX; HBIT; } // 5 BIT ABX
OP(_05c) { H6280_CYCLES(2); NOP; } // 2 NOP
OP(_07c) { int tmp; H6280_CYCLES(7); EA_IAX; JMP; } // 7 JMP IAX
OP(_09c) { int tmp; H6280_CYCLES(5); STZ; WR_ABS; } // 5 STZ ABS
@ -307,38 +307,3 @@ OP(_09f) { int tmp; H6280_CYCLES(4); RD_ZPG; BBS(1); } // 6/8 BBS1 ZPG,REL
OP(_0bf) { int tmp; H6280_CYCLES(4); RD_ZPG; BBS(3); } // 6/8 BBS3 ZPG,REL
OP(_0df) { int tmp; H6280_CYCLES(4); RD_ZPG; BBS(5); } // 6/8 BBS5 ZPG,REL
OP(_0ff) { int tmp; H6280_CYCLES(4); RD_ZPG; BBS(7); } // 6/8 BBS7 ZPG,REL
static void (*const insnh6280[0x100])(h6280_Regs* cpustate) = {
h6280_000,h6280_001,h6280_002,h6280_003,h6280_004,h6280_005,h6280_006,h6280_007,
h6280_008,h6280_009,h6280_00a,h6280_00b,h6280_00c,h6280_00d,h6280_00e,h6280_00f,
h6280_010,h6280_011,h6280_012,h6280_013,h6280_014,h6280_015,h6280_016,h6280_017,
h6280_018,h6280_019,h6280_01a,h6280_01b,h6280_01c,h6280_01d,h6280_01e,h6280_01f,
h6280_020,h6280_021,h6280_022,h6280_023,h6280_024,h6280_025,h6280_026,h6280_027,
h6280_028,h6280_029,h6280_02a,h6280_02b,h6280_02c,h6280_02d,h6280_02e,h6280_02f,
h6280_030,h6280_031,h6280_032,h6280_033,h6280_034,h6280_035,h6280_036,h6280_037,
h6280_038,h6280_039,h6280_03a,h6280_03b,h6280_03c,h6280_03d,h6280_03e,h6280_03f,
h6280_040,h6280_041,h6280_042,h6280_043,h6280_044,h6280_045,h6280_046,h6280_047,
h6280_048,h6280_049,h6280_04a,h6280_04b,h6280_04c,h6280_04d,h6280_04e,h6280_04f,
h6280_050,h6280_051,h6280_052,h6280_053,h6280_054,h6280_055,h6280_056,h6280_057,
h6280_058,h6280_059,h6280_05a,h6280_05b,h6280_05c,h6280_05d,h6280_05e,h6280_05f,
h6280_060,h6280_061,h6280_062,h6280_063,h6280_064,h6280_065,h6280_066,h6280_067,
h6280_068,h6280_069,h6280_06a,h6280_06b,h6280_06c,h6280_06d,h6280_06e,h6280_06f,
h6280_070,h6280_071,h6280_072,h6280_073,h6280_074,h6280_075,h6280_076,h6280_077,
h6280_078,h6280_079,h6280_07a,h6280_07b,h6280_07c,h6280_07d,h6280_07e,h6280_07f,
h6280_080,h6280_081,h6280_082,h6280_083,h6280_084,h6280_085,h6280_086,h6280_087,
h6280_088,h6280_089,h6280_08a,h6280_08b,h6280_08c,h6280_08d,h6280_08e,h6280_08f,
h6280_090,h6280_091,h6280_092,h6280_093,h6280_094,h6280_095,h6280_096,h6280_097,
h6280_098,h6280_099,h6280_09a,h6280_09b,h6280_09c,h6280_09d,h6280_09e,h6280_09f,
h6280_0a0,h6280_0a1,h6280_0a2,h6280_0a3,h6280_0a4,h6280_0a5,h6280_0a6,h6280_0a7,
h6280_0a8,h6280_0a9,h6280_0aa,h6280_0ab,h6280_0ac,h6280_0ad,h6280_0ae,h6280_0af,
h6280_0b0,h6280_0b1,h6280_0b2,h6280_0b3,h6280_0b4,h6280_0b5,h6280_0b6,h6280_0b7,
h6280_0b8,h6280_0b9,h6280_0ba,h6280_0bb,h6280_0bc,h6280_0bd,h6280_0be,h6280_0bf,
h6280_0c0,h6280_0c1,h6280_0c2,h6280_0c3,h6280_0c4,h6280_0c5,h6280_0c6,h6280_0c7,
h6280_0c8,h6280_0c9,h6280_0ca,h6280_0cb,h6280_0cc,h6280_0cd,h6280_0ce,h6280_0cf,
h6280_0d0,h6280_0d1,h6280_0d2,h6280_0d3,h6280_0d4,h6280_0d5,h6280_0d6,h6280_0d7,
h6280_0d8,h6280_0d9,h6280_0da,h6280_0db,h6280_0dc,h6280_0dd,h6280_0de,h6280_0df,
h6280_0e0,h6280_0e1,h6280_0e2,h6280_0e3,h6280_0e4,h6280_0e5,h6280_0e6,h6280_0e7,
h6280_0e8,h6280_0e9,h6280_0ea,h6280_0eb,h6280_0ec,h6280_0ed,h6280_0ee,h6280_0ef,
h6280_0f0,h6280_0f1,h6280_0f2,h6280_0f3,h6280_0f4,h6280_0f5,h6280_0f6,h6280_0f7,
h6280_0f8,h6280_0f9,h6280_0fa,h6280_0fb,h6280_0fc,h6280_0fd,h6280_0fe,h6280_0ff
};

52
src/emu/cpu/m6809/m6809.c
View File

@ -337,7 +337,7 @@ const device_type M6809 = &device_creator<m6809_device>;
const device_type M6809E = &device_creator<m6809e_device>;
//-------------------------------------------------
// atmega8_device - constructor
// m6809_base_device - constructor
//-------------------------------------------------
m6809_base_device::m6809_base_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock, const device_type type, int divider)
@ -574,28 +574,6 @@ UINT32 m6809_base_device::disasm_max_opcode_bytes() const
}
//-------------------------------------------------
// execute_clocks_to_cycles - convert the raw
// clock into cycles per second
//-------------------------------------------------
UINT64 m6809_base_device::execute_clocks_to_cycles(UINT64 clocks) const
{
return (clocks + m_clock_divider - 1) / m_clock_divider;
}
//-------------------------------------------------
// execute_cycles_to_clocks - convert a cycle
// count back to raw clocks
//-------------------------------------------------
UINT64 m6809_base_device::execute_cycles_to_clocks(UINT64 cycles) const
{
return cycles * m_clock_divider;
}
//-------------------------------------------------
// disasm_disassemble - call the disassembly
// helper function
@ -607,6 +585,7 @@ offs_t m6809_base_device::disasm_disassemble(char *buffer, offs_t pc, const UINT
return disassemble(buffer, pc, oprom, opram, 0);
}
//**************************************************************************
// IRQ HANDLING
//**************************************************************************
@ -666,6 +645,28 @@ void m6809_base_device::set_irq_line(int irqline, int state)
// CORE EXECUTION LOOP
//**************************************************************************
//-------------------------------------------------
// execute_clocks_to_cycles - convert the raw
// clock into cycles per second
//-------------------------------------------------
UINT64 m6809_base_device::execute_clocks_to_cycles(UINT64 clocks) const
{
return (clocks + m_clock_divider - 1) / m_clock_divider;
}
//-------------------------------------------------
// execute_cycles_to_clocks - convert a cycle
// count back to raw clocks
//-------------------------------------------------
UINT64 m6809_base_device::execute_cycles_to_clocks(UINT64 cycles) const
{
return cycles * m_clock_divider;
}
//-------------------------------------------------
// execute_min_cycles - return minimum number of
// cycles it takes for one instruction to execute
@ -699,6 +700,11 @@ UINT32 m6809_base_device::execute_input_lines() const
}
//-------------------------------------------------
// execute_set_input - act on a changed input/
// interrupt line
//-------------------------------------------------
void m6809_base_device::execute_set_input(int inputnum, int state)
{
switch(inputnum)

8
src/emu/cpu/ssem/ssem.c
View File

@ -74,8 +74,14 @@ inline void ssem_device::program_write32(UINT32 address, UINT32 data)
/*****************************************************************************/
const device_type SSEMCPU = &device_creator<ssem_device>;
//-------------------------------------------------
// ssem_device - constructor
//-------------------------------------------------
ssem_device::ssem_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: cpu_device(mconfig, SSEM, "SSEM", tag, owner, clock),
: cpu_device(mconfig, SSEMCPU, "SSEMCPU", tag, owner, clock),
m_program_config("program", ENDIANNESS_LITTLE, 8, 16),
m_pc(1),
m_shifted_pc(1<<2),

4
src/emu/cpu/ssem/ssem.h
View File

@ -13,8 +13,6 @@
// TYPE DEFINITIONS
//**************************************************************************
class ssem_device;
// ======================> ssem_device
// Used by core CPU interface
@ -68,7 +66,7 @@ public:
};
// device type definition
extern const device_type SSEM;
extern const device_type SSEMCPU;
/***************************************************************************
REGISTER ENUMERATION

384
src/emu/sound/c6280.c
View File

@ -56,256 +56,92 @@
#include "emu.h"
#include "c6280.h"
struct t_channel {
UINT16 frequency;
UINT8 control;
UINT8 balance;
UINT8 waveform[32];
UINT8 index;
INT16 dda;
UINT8 noise_control;
UINT32 noise_counter;
UINT32 counter;
};
struct c6280_t {
sound_stream *stream;
device_t *device;
device_t *cpudevice;
UINT8 select;
UINT8 balance;
UINT8 lfo_frequency;
UINT8 lfo_control;
t_channel channel[8];
INT16 volume_table[32];
UINT32 noise_freq_tab[32];
UINT32 wave_freq_tab[4096];
};
INLINE c6280_t *get_safe_token(device_t *device)
{
assert(device != NULL);
assert(device->type() == C6280);
return (c6280_t *)downcast<c6280_device *>(device)->token();
}
/* only needed for io_buffer */
#include "cpu/h6280/h6280.h"
static void c6280_init(device_t *device, c6280_t *p, double clk, double rate)
{
const c6280_interface *intf = (const c6280_interface *)device->static_config();
int i;
double step;
/* Loudest volume level for table */
double level = 65535.0 / 6.0 / 32.0;
/* Clear context */
memset(p, 0, sizeof(c6280_t));
p->device = device;
p->cpudevice = device->machine().device(intf->cpu);
if (p->cpudevice == NULL)
fatalerror("c6280_init: no CPU found with tag of '%s'\n", device->tag());
/* Make waveform frequency table */
for(i = 0; i < 4096; i += 1)
{
step = ((clk / rate) * 4096) / (i+1);
p->wave_freq_tab[(1 + i) & 0xFFF] = (UINT32)step;
}
/* Make noise frequency table */
for(i = 0; i < 32; i += 1)
{
step = ((clk / rate) * 32) / (i+1);
p->noise_freq_tab[i] = (UINT32)step;
}
/* Make volume table */
/* PSG has 48dB volume range spread over 32 steps */
step = 48.0 / 32.0;
for(i = 0; i < 31; i++)
{
p->volume_table[i] = (UINT16)level;
level /= pow(10.0, step / 20.0);
}
p->volume_table[31] = 0;
}
static void c6280_write(c6280_t *p, int offset, int data)
{
t_channel *q = &p->channel[p->select];
/* Update stream */
p->stream->update();
switch(offset & 0x0F)
{
case 0x00: /* Channel select */
p->select = data & 0x07;
break;
case 0x01: /* Global balance */
p->balance = data;
break;
case 0x02: /* Channel frequency (LSB) */
q->frequency = (q->frequency & 0x0F00) | data;
q->frequency &= 0x0FFF;
break;
case 0x03: /* Channel frequency (MSB) */
q->frequency = (q->frequency & 0x00FF) | (data << 8);
q->frequency &= 0x0FFF;
break;
case 0x04: /* Channel control (key-on, DDA mode, volume) */
/* 1-to-0 transition of DDA bit resets waveform index */
if((q->control & 0x40) && ((data & 0x40) == 0))
{
q->index = 0;
}
q->control = data;
break;
case 0x05: /* Channel balance */
q->balance = data;
break;
case 0x06: /* Channel waveform data */
switch(q->control & 0xC0)
{
case 0x00:
q->waveform[q->index & 0x1F] = data & 0x1F;
q->index = (q->index + 1) & 0x1F;
break;
case 0x40:
break;
case 0x80:
q->waveform[q->index & 0x1F] = data & 0x1F;
q->index = (q->index + 1) & 0x1F;
break;
case 0xC0:
q->dda = data & 0x1F;
break;
}
break;
case 0x07: /* Noise control (enable, frequency) */
q->noise_control = data;
break;
case 0x08: /* LFO frequency */
p->lfo_frequency = data;
break;
case 0x09: /* LFO control (enable, mode) */
p->lfo_control = data;
break;
default:
break;
}
}
static STREAM_UPDATE( c6280_update )
void c6280_device::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)
{
static const int scale_tab[] = {
0x00, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F,
0x10, 0x13, 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F
};
int ch;
int i;
c6280_t *p = (c6280_t *)param;
int lmal = (p->balance >> 4) & 0x0F;
int rmal = (p->balance >> 0) & 0x0F;
int vll, vlr;
int lmal = (m_balance >> 4) & 0x0F;
int rmal = (m_balance >> 0) & 0x0F;
lmal = scale_tab[lmal];
rmal = scale_tab[rmal];
/* Clear buffer */
for(i = 0; i < samples; i++)
for (int i = 0; i < samples; i++)
{
outputs[0][i] = 0;
outputs[1][i] = 0;
}
for(ch = 0; ch < 6; ch++)
for (int ch = 0; ch < 6; ch++)
{
/* Only look at enabled channels */
if(p->channel[ch].control & 0x80)
if(m_channel[ch].m_control & 0x80)
{
int lal = (p->channel[ch].balance >> 4) & 0x0F;
int ral = (p->channel[ch].balance >> 0) & 0x0F;
int al = p->channel[ch].control & 0x1F;
int lal = (m_channel[ch].m_balance >> 4) & 0x0F;
int ral = (m_channel[ch].m_balance >> 0) & 0x0F;
int al = m_channel[ch].m_control & 0x1F;
lal = scale_tab[lal];
ral = scale_tab[ral];
/* Calculate volume just as the patent says */
vll = (0x1F - lal) + (0x1F - al) + (0x1F - lmal);
int vll = (0x1F - lal) + (0x1F - al) + (0x1F - lmal);
if(vll > 0x1F) vll = 0x1F;
vlr = (0x1F - ral) + (0x1F - al) + (0x1F - rmal);
int vlr = (0x1F - ral) + (0x1F - al) + (0x1F - rmal);
if(vlr > 0x1F) vlr = 0x1F;
vll = p->volume_table[vll];
vlr = p->volume_table[vlr];
vll = m_volume_table[vll];
vlr = m_volume_table[vlr];
/* Check channel mode */
if((ch >= 4) && (p->channel[ch].noise_control & 0x80))
if((ch >= 4) && (m_channel[ch].m_noise_control & 0x80))
{
/* Noise mode */
UINT32 step = p->noise_freq_tab[(p->channel[ch].noise_control & 0x1F) ^ 0x1F];
for(i = 0; i < samples; i += 1)
UINT32 step = m_noise_freq_tab[(m_channel[ch].m_noise_control & 0x1F) ^ 0x1F];
for (int i = 0; i < samples; i += 1)
{
static int data = 0;
p->channel[ch].noise_counter += step;
if(p->channel[ch].noise_counter >= 0x800)
m_channel[ch].m_noise_counter += step;
if(m_channel[ch].m_noise_counter >= 0x800)
{
data = (p->device->machine().rand() & 1) ? 0x1F : 0;
data = (machine().rand() & 1) ? 0x1F : 0;
}
p->channel[ch].noise_counter &= 0x7FF;
m_channel[ch].m_noise_counter &= 0x7FF;
outputs[0][i] += (INT16)(vll * (data - 16));
outputs[1][i] += (INT16)(vlr * (data - 16));
}
}
else
if(p->channel[ch].control & 0x40)
if(m_channel[ch].m_control & 0x40)
{
/* DDA mode */
for(i = 0; i < samples; i++)
for (int i = 0; i < samples; i++)
{
outputs[0][i] += (INT16)(vll * (p->channel[ch].dda - 16));
outputs[1][i] += (INT16)(vlr * (p->channel[ch].dda - 16));
outputs[0][i] += (INT16)(vll * (m_channel[ch].m_dda - 16));
outputs[1][i] += (INT16)(vlr * (m_channel[ch].m_dda - 16));
}
}
else
{
/* Waveform mode */
UINT32 step = p->wave_freq_tab[p->channel[ch].frequency];
for(i = 0; i < samples; i += 1)
UINT32 step = m_wave_freq_tab[m_channel[ch].m_frequency];
for (int i = 0; i < samples; i += 1)
{
int offset;
INT16 data;
offset = (p->channel[ch].counter >> 12) & 0x1F;
p->channel[ch].counter += step;
p->channel[ch].counter &= 0x1FFFF;
data = p->channel[ch].waveform[offset];
offset = (m_channel[ch].m_counter >> 12) & 0x1F;
m_channel[ch].m_counter += step;
m_channel[ch].m_counter &= 0x1FFFF;
data = m_channel[ch].m_waveform[offset];
outputs[0][i] += (INT16)(vll * (data - 16));
outputs[1][i] += (INT16)(vlr * (data - 16));
}
@ -319,29 +155,93 @@ static STREAM_UPDATE( c6280_update )
/* MAME specific code */
/*--------------------------------------------------------------------------*/
static DEVICE_START( c6280 )
READ8_MEMBER( c6280_device::c6280_r )
{
int rate = device->clock()/16;
c6280_t *info = get_safe_token(device);
/* Initialize PSG emulator */
c6280_init(device, info, device->clock(), rate);
/* Create stereo stream */
info->stream = device->machine().sound().stream_alloc(*device, 0, 2, rate, info, c6280_update);
return m_cpudevice->io_get_buffer();
}
READ8_DEVICE_HANDLER( c6280_r )
WRITE8_MEMBER( c6280_device::c6280_w )
{
c6280_t *info = get_safe_token(device);
return h6280io_get_buffer(info->cpudevice);
}
m_cpudevice->io_set_buffer(data);
WRITE8_DEVICE_HANDLER( c6280_w )
{
c6280_t *info = get_safe_token(device);
h6280io_set_buffer(info->cpudevice, data);
c6280_write(info, offset, data);
channel *chan = &m_channel[m_select];
/* Update stream */
m_stream->update();
switch(offset & 0x0F)
{
case 0x00: /* Channel select */
m_select = data & 0x07;
break;
case 0x01: /* Global balance */
m_balance = data;
break;
case 0x02: /* Channel frequency (LSB) */
chan->m_frequency = (chan->m_frequency & 0x0F00) | data;
chan->m_frequency &= 0x0FFF;
break;
case 0x03: /* Channel frequency (MSB) */
chan->m_frequency = (chan->m_frequency & 0x00FF) | (data << 8);
chan->m_frequency &= 0x0FFF;
break;
case 0x04: /* Channel control (key-on, DDA mode, volume) */
/* 1-to-0 transition of DDA bit resets waveform index */
if((chan->m_control & 0x40) && ((data & 0x40) == 0))
{
chan->m_index = 0;
}
chan->m_control = data;
break;
case 0x05: /* Channel balance */
chan->m_balance = data;
break;
case 0x06: /* Channel waveform data */
switch(chan->m_control & 0xC0)
{
case 0x00:
chan->m_waveform[chan->m_index & 0x1F] = data & 0x1F;
chan->m_index = (chan->m_index + 1) & 0x1F;
break;
case 0x40:
break;
case 0x80:
chan->m_waveform[chan->m_index & 0x1F] = data & 0x1F;
chan->m_index = (chan->m_index + 1) & 0x1F;
break;
case 0xC0:
chan->m_dda = data & 0x1F;
break;
}
break;
case 0x07: /* Noise control (enable, frequency) */
chan->m_noise_control = data;
break;
case 0x08: /* LFO frequency */
m_lfo_frequency = data;
break;
case 0x09: /* LFO control (enable, mode) */
m_lfo_control = data;
break;
default:
break;
}
}
const device_type C6280 = &device_creator<c6280_device>;
@ -350,7 +250,6 @@ c6280_device::c6280_device(const machine_config &mconfig, const char *tag, devic
: device_t(mconfig, C6280, "HuC6280", tag, owner, clock),
device_sound_interface(mconfig, *this)
{
m_token = global_alloc_clear(c6280_t);
}
//-------------------------------------------------
@ -369,17 +268,50 @@ void c6280_device::device_config_complete()
void c6280_device::device_start()
{
DEVICE_START_NAME( c6280 )(this);
int rate = clock() / 16;
/* Create stereo stream */
m_stream = machine().sound().stream_alloc(*this, 0, 2, rate, this);
const c6280_interface *intf = (const c6280_interface *)static_config();
/* Loudest volume level for table */
double level = 65535.0 / 6.0 / 32.0;
/* Clear context */
m_select = 0;
m_balance = 0;
m_lfo_frequency = 0;
m_lfo_control = 0;
memset(m_channel, 0, sizeof(channel) * 8);
m_cpudevice = machine().device<h6280_device>(intf->cpu);
if (m_cpudevice == NULL)
{
fatalerror("c6280_init: no CPU found with tag of '%s'\n", tag());
}
/* Make waveform frequency table */
for (int i = 0; i < 4096; i += 1)
{
double step = ((clock() / rate) * 4096) / (i + 1);
m_wave_freq_tab[(1 + i) & 0xFFF] = (UINT32)step;
}
/* Make noise frequency table */
for (int i = 0; i < 32; i += 1)
{
double step = ((clock() / rate) * 32) / (i+1);
m_noise_freq_tab[i] = (UINT32)step;
}
/* Make volume table */
/* PSG has 48dB volume range spread over 32 steps */
double step = 48.0 / 32.0;
for (int i = 0; i < 31; i++)
{
m_volume_table[i] = (UINT16)level;
level /= pow(10.0, step / 20.0);
}
m_volume_table[31] = 0;
}
//-------------------------------------------------
// sound_stream_update - handle a stream update
//-------------------------------------------------
void c6280_device::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)
{
// should never get here
fatalerror("sound_stream_update called; not applicable to legacy sound devices\n");
}

39
src/emu/sound/c6280.h
View File

@ -3,26 +3,23 @@
#ifndef __C6280_H__
#define __C6280_H__
#include "devlegcy.h"
#include "cpu/h6280/h6280.h"
struct c6280_interface
{
const char * cpu;
};
/* Function prototypes */
DECLARE_WRITE8_DEVICE_HANDLER( c6280_w );
DECLARE_READ8_DEVICE_HANDLER( c6280_r );
class c6280_device : public device_t,
public device_sound_interface
public device_sound_interface
{
public:
c6280_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
~c6280_device() { global_free(m_token); }
// access to legacy token
void *token() const { assert(m_token != NULL); return m_token; }
// read/write
DECLARE_READ8_MEMBER( c6280_r );
DECLARE_WRITE8_MEMBER( c6280_w );
protected:
// device-level overrides
virtual void device_config_complete();
@ -30,9 +27,31 @@ protected:
// sound stream update overrides
virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
private:
struct channel {
UINT16 m_frequency;
UINT8 m_control;
UINT8 m_balance;
UINT8 m_waveform[32];
UINT8 m_index;
INT16 m_dda;
UINT8 m_noise_control;
UINT32 m_noise_counter;
UINT32 m_counter;
};
// internal state
void *m_token;
sound_stream *m_stream;
h6280_device *m_cpudevice;
UINT8 m_select;
UINT8 m_balance;
UINT8 m_lfo_frequency;
UINT8 m_lfo_control;
channel m_channel[8];
INT16 m_volume_table[32];
UINT32 m_noise_freq_tab[32];
UINT32 m_wave_freq_tab[4096];
};
extern const device_type C6280;

4
src/mame/drivers/actfancr.c
View File

@ -109,7 +109,7 @@ static ADDRESS_MAP_START( triothep_map, AS_PROGRAM, 8, actfancr_state )
AM_RANGE(0x140000, 0x140001) AM_READNOP /* Value doesn't matter */
AM_RANGE(0x1f0000, 0x1f3fff) AM_RAM AM_SHARE("main_ram") /* Main ram */
AM_RANGE(0x1ff000, 0x1ff001) AM_READWRITE(triothep_control_r, triothep_control_select_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("maincpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
/******************************************************************************/
@ -321,7 +321,7 @@ MACHINE_RESET_MEMBER(actfancr_state,triothep)
static MACHINE_CONFIG_START( actfancr, actfancr_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu",H6280,21477200/3) /* Should be accurate */
MCFG_CPU_ADD("maincpu", H6280, 21477200/3) /* Should be accurate */
MCFG_CPU_PROGRAM_MAP(actfan_map)
MCFG_CPU_VBLANK_INT_DRIVER("screen", actfancr_state, irq0_line_hold) /* VBL */

6
src/mame/drivers/battlera.c
View File

@ -72,7 +72,7 @@ static ADDRESS_MAP_START( battlera_map, AS_PROGRAM, 8, battlera_state )
AM_RANGE(0x1fe000, 0x1fe001) AM_READWRITE(HuC6270_register_r, HuC6270_register_w)
AM_RANGE(0x1fe002, 0x1fe003) AM_WRITE(HuC6270_data_w)
AM_RANGE(0x1ff000, 0x1ff001) AM_READWRITE(control_data_r, control_data_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("maincpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
static ADDRESS_MAP_START( battlera_portmap, AS_IO, 8, battlera_state )
@ -110,10 +110,10 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, battlera_state )
AM_RANGE(0x000000, 0x00ffff) AM_ROM
AM_RANGE(0x040000, 0x040001) AM_DEVWRITE_LEGACY("ymsnd", ym2203_w)
AM_RANGE(0x080000, 0x080001) AM_WRITE(battlera_adpcm_data_w)
AM_RANGE(0x1fe800, 0x1fe80f) AM_DEVWRITE_LEGACY("c6280", c6280_w)
AM_RANGE(0x1fe800, 0x1fe80f) AM_DEVWRITE("c6280", c6280_device, c6280_w)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank7") /* Main ram */
AM_RANGE(0x1ff000, 0x1ff001) AM_READ(soundlatch_byte_r) AM_WRITE(battlera_adpcm_reset_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
/******************************************************************************/

6
src/mame/drivers/boogwing.c
View File

@ -136,8 +136,8 @@ static ADDRESS_MAP_START( audio_map, AS_PROGRAM, 8, boogwing_state )
AM_RANGE(0x130000, 0x130001) AM_DEVREADWRITE("oki2", okim6295_device, read, write)
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
@ -333,7 +333,7 @@ static MACHINE_CONFIG_START( boogwing, boogwing_state )
MCFG_CPU_PROGRAM_MAP(boogwing_map)
MCFG_CPU_VBLANK_INT_DRIVER("screen", boogwing_state, irq6_line_hold)
MCFG_CPU_ADD("audiocpu", H6280,32220000/4)
MCFG_CPU_ADD("audiocpu", H6280, 32220000/4)
MCFG_CPU_PROGRAM_MAP(audio_map)
/* video hardware */

4
src/mame/drivers/cbuster.c
View File

@ -135,8 +135,8 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, cbuster_state )
AM_RANGE(0x130000, 0x130001) AM_DEVREADWRITE("oki2", okim6295_device, read, write)
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
/******************************************************************************/

17
src/mame/drivers/cninja.c
View File

@ -107,7 +107,14 @@ WRITE16_MEMBER(cninja_state::cninja_irq_w)
case 1: /* Raster IRQ scanline position, only valid for values between 1 & 239 (0 and 240-256 do NOT generate IRQ's) */
m_scanline = data & 0xff;
if (!BIT(m_irq_mask, 1) && m_scanline > 0 && m_scanline < 240)
if (!
BIT(
m_irq_mask,
1
)
&&
m_scanline > 0 &&
m_scanline < 240)
m_raster_irq_timer->adjust(machine().primary_screen->time_until_pos(m_scanline), m_scanline);
else
m_raster_irq_timer->reset();
@ -303,8 +310,8 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, cninja_state )
AM_RANGE(0x130000, 0x130001) AM_DEVREADWRITE("oki2", okim6295_device, read, write)
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_map_mutantf, AS_PROGRAM, 8, cninja_state )
@ -315,8 +322,8 @@ static ADDRESS_MAP_START( sound_map_mutantf, AS_PROGRAM, 8, cninja_state )
AM_RANGE(0x130000, 0x130001) AM_DEVREADWRITE("oki2", okim6295_device, read, write)
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
static ADDRESS_MAP_START( stoneage_s_map, AS_PROGRAM, 8, cninja_state )

4
src/mame/drivers/darkseal.c
View File

@ -90,8 +90,8 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, darkseal_state )
AM_RANGE(0x130000, 0x130001) AM_DEVREADWRITE("oki2", okim6295_device, read, write)
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
/******************************************************************************/

4
src/mame/drivers/dassault.c
View File

@ -267,8 +267,8 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, dassault_state )
AM_RANGE(0x130000, 0x130001) AM_DEVREADWRITE("oki2", okim6295_device, read, write)
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
/**********************************************************************************/

8
src/mame/drivers/dec0.c
View File

@ -313,7 +313,7 @@ static ADDRESS_MAP_START( robocop_sub_map, AS_PROGRAM, 8, dec0_state )
AM_RANGE(0x000000, 0x00ffff) AM_ROM
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAM /* Main ram */
AM_RANGE(0x1f2000, 0x1f3fff) AM_RAM AM_SHARE("robocop_shared") /* Shared ram */
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("sub", h6280_device, irq_status_w)
ADDRESS_MAP_END
static ADDRESS_MAP_START( hippodrm_sub_map, AS_PROGRAM, 8, dec0_state )
@ -324,7 +324,7 @@ static ADDRESS_MAP_START( hippodrm_sub_map, AS_PROGRAM, 8, dec0_state )
AM_RANGE(0x1a1000, 0x1a17ff) AM_DEVREADWRITE_LEGACY("tilegen3", deco_bac06_pf_data_8bit_swap_r, deco_bac06_pf_data_8bit_swap_w)
AM_RANGE(0x1d0000, 0x1d00ff) AM_READWRITE(hippodrm_prot_r, hippodrm_prot_w)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8") /* Main ram */
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("sub", h6280_device, irq_status_w)
AM_RANGE(0x1ff402, 0x1ff403) AM_READ_PORT("VBLANK")
ADDRESS_MAP_END
@ -564,7 +564,7 @@ static ADDRESS_MAP_START( slyspy_s_map, AS_PROGRAM, 8, dec0_state )
AM_RANGE(0x0e0000, 0x0e0001) AM_DEVREADWRITE("oki", okim6295_device, read, write)
AM_RANGE(0x0f0000, 0x0f0001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
static ADDRESS_MAP_START( midres_s_map, AS_PROGRAM, 8, dec0_state )
@ -574,7 +574,7 @@ static ADDRESS_MAP_START( midres_s_map, AS_PROGRAM, 8, dec0_state )
AM_RANGE(0x130000, 0x130001) AM_DEVREADWRITE("oki", okim6295_device, read, write)
AM_RANGE(0x138000, 0x138001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END

4
src/mame/drivers/deco32.c
View File

@ -1009,8 +1009,8 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, deco32_state )
AM_RANGE(0x130000, 0x130001) AM_DEVREADWRITE("oki2", okim6295_device, read, write)
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
READ8_MEMBER(deco32_state::latch_r)

4
src/mame/drivers/dietgo.c
View File

@ -39,8 +39,8 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, dietgo_state )
AM_RANGE(0x130000, 0x130001) AM_NOP /* This board only has 1 oki chip */
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END

4
src/mame/drivers/funkyjet.c
View File

@ -126,8 +126,8 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, funkyjet_state )
AM_RANGE(0x130000, 0x130001) AM_NOP /* This board only has 1 oki chip */
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
/******************************************************************************/

6
src/mame/drivers/ggconnie.c
View File

@ -139,10 +139,10 @@ static ADDRESS_MAP_START( sgx_mem , AS_PROGRAM, 8, ggconnie_state )
AM_RANGE( 0x1fe008, 0x1fe00f) AM_READWRITE_LEGACY(vpc_r, vpc_w) AM_MIRROR(0x03e0)
AM_RANGE( 0x1fe010, 0x1fe017) AM_READWRITE_LEGACY(vdc_1_r, vdc_1_w) AM_MIRROR(0x03e0)
AM_RANGE( 0x1fe400, 0x1fe7ff) AM_READWRITE_LEGACY(vce_r, vce_w)
AM_RANGE( 0x1fe800, 0x1febff) AM_DEVREADWRITE_LEGACY("c6280", c6280_r, c6280_w)
AM_RANGE( 0x1fec00, 0x1fefff) AM_READWRITE_LEGACY(h6280_timer_r, h6280_timer_w)
AM_RANGE( 0x1fe800, 0x1febff) AM_DEVREADWRITE("c6280", c6280_device, c6280_r, c6280_w)
AM_RANGE( 0x1fec00, 0x1fefff) AM_DEVREADWRITE("maincpu", h6280_device, timer_r, timer_w)
AM_RANGE( 0x1ff000, 0x1ff000) AM_READ_PORT("IN0") AM_WRITE(lamp_w)
AM_RANGE( 0x1ff400, 0x1ff7ff) AM_READWRITE_LEGACY(h6280_irq_status_r, h6280_irq_status_w )
AM_RANGE( 0x1ff400, 0x1ff7ff) AM_DEVREADWRITE("maincpu", h6280_device, irq_status_r, irq_status_w )
ADDRESS_MAP_END
static ADDRESS_MAP_START( sgx_io , AS_IO, 8, ggconnie_state )

4
src/mame/drivers/madmotor.c
View File

@ -74,8 +74,8 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, madmotor_state )
AM_RANGE(0x130000, 0x130001) AM_DEVREADWRITE("oki2", okim6295_device, read, write)
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
/******************************************************************************/

6
src/mame/drivers/paranoia.c
View File

@ -78,10 +78,10 @@ static ADDRESS_MAP_START( pce_mem , AS_PROGRAM, 8, paranoia_state )
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000)
AM_RANGE( 0x1FE000, 0x1FE3FF) AM_READWRITE_LEGACY(vdc_0_r, vdc_0_w )
AM_RANGE( 0x1FE400, 0x1FE7FF) AM_READWRITE_LEGACY(vce_r, vce_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE_LEGACY("c6280", c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_READWRITE_LEGACY(h6280_timer_r, h6280_timer_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE("c6280", c6280_device, c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_DEVREADWRITE("maincpu", h6280_device, timer_r, timer_w )
AM_RANGE( 0x1FF000, 0x1FF3FF) AM_READWRITE(pce_joystick_r, pce_joystick_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_READWRITE_LEGACY(h6280_irq_status_r, h6280_irq_status_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_DEVREADWRITE("maincpu", h6280_device, irq_status_r, irq_status_w )
ADDRESS_MAP_END
static ADDRESS_MAP_START( pce_io , AS_IO, 8, paranoia_state )

6
src/mame/drivers/rohga.c
View File

@ -268,8 +268,8 @@ static ADDRESS_MAP_START( rohga_sound_map, AS_PROGRAM, 8, rohga_state )
AM_RANGE(0x130000, 0x130001) AM_DEVREADWRITE("oki2", okim6295_device, read, write)
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
@ -790,7 +790,7 @@ static MACHINE_CONFIG_START( rohga, rohga_state )
MCFG_CPU_PROGRAM_MAP(rohga_map)
MCFG_CPU_VBLANK_INT_DRIVER("screen", rohga_state, irq6_line_assert)
MCFG_CPU_ADD("audiocpu", H6280,32220000/4/3) /* verified on pcb (8.050Mhz is XIN on pin 10 of H6280 */
MCFG_CPU_ADD("audiocpu", H6280, 32220000/4/3) /* verified on pcb (8.050Mhz is XIN on pin 10 of H6280 */
MCFG_CPU_PROGRAM_MAP(rohga_sound_map)
/* video hardware */

4
src/mame/drivers/supbtime.c
View File

@ -102,8 +102,8 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, supbtime_state )
AM_RANGE(0x130000, 0x130001) AM_NOP /* This board only has 1 oki chip */
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
/******************************************************************************/

6
src/mame/drivers/tourvis.c
View File

@ -282,10 +282,10 @@ static ADDRESS_MAP_START( pce_mem , AS_PROGRAM, 8, tourvision_state )
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000)
AM_RANGE( 0x1FE000, 0x1FE3FF) AM_READWRITE_LEGACY(vdc_0_r, vdc_0_w )
AM_RANGE( 0x1FE400, 0x1FE7FF) AM_READWRITE_LEGACY(vce_r, vce_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE_LEGACY("c6280", c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_READWRITE_LEGACY(h6280_timer_r, h6280_timer_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE("c6280", c6280_device, c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_DEVREADWRITE("maincpu", h6280_device, timer_r, timer_w )
AM_RANGE( 0x1FF000, 0x1FF3FF) AM_READWRITE(pce_joystick_r, pce_joystick_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_READWRITE_LEGACY(h6280_irq_status_r, h6280_irq_status_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_DEVREADWRITE("maincpu", h6280_device, irq_status_r, irq_status_w )
ADDRESS_MAP_END
static ADDRESS_MAP_START( pce_io , AS_IO, 8, tourvision_state )

4
src/mame/drivers/tumblep.c
View File

@ -135,8 +135,8 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, tumblep_state )
AM_RANGE(0x130000, 0x130001) AM_NOP /* This board only has 1 oki chip */
AM_RANGE(0x140000, 0x140001) AM_READ(soundlatch_byte_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8")
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
/******************************************************************************/

6
src/mame/drivers/uapce.c
View File

@ -286,10 +286,10 @@ static ADDRESS_MAP_START( pce_mem , AS_PROGRAM, 8, uapce_state )
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000)
AM_RANGE( 0x1FE000, 0x1FE3FF) AM_READWRITE_LEGACY(vdc_0_r, vdc_0_w )
AM_RANGE( 0x1FE400, 0x1FE7FF) AM_READWRITE_LEGACY(vce_r, vce_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE_LEGACY("c6280", c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_READWRITE_LEGACY(h6280_timer_r, h6280_timer_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE("c6280", c6280_device, c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_DEVREADWRITE("maincpu", h6280_device, timer_r, timer_w )
AM_RANGE( 0x1FF000, 0x1FF3FF) AM_READWRITE(pce_joystick_r, pce_joystick_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_READWRITE_LEGACY(h6280_irq_status_r, h6280_irq_status_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_DEVREADWRITE("maincpu", h6280_device, irq_status_r, irq_status_w )
ADDRESS_MAP_END
static ADDRESS_MAP_START( pce_io , AS_IO, 8, uapce_state )

4
src/mame/drivers/vaportra.c
View File

@ -83,8 +83,8 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, vaportra_state )
AM_RANGE(0x130000, 0x130001) AM_DEVREADWRITE("oki2", okim6295_device, read, write)
AM_RANGE(0x140000, 0x140001) AM_READ(vaportra_soundlatch_r)
AM_RANGE(0x1f0000, 0x1f1fff) AM_RAMBANK("bank8") /* ??? LOOKUP ??? */
AM_RANGE(0x1fec00, 0x1fec01) AM_WRITE_LEGACY(h6280_timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_WRITE_LEGACY(h6280_irq_status_w)
AM_RANGE(0x1fec00, 0x1fec01) AM_DEVWRITE("audiocpu", h6280_device, timer_w)
AM_RANGE(0x1ff400, 0x1ff403) AM_DEVWRITE("audiocpu", h6280_device, irq_status_w)
ADDRESS_MAP_END
/******************************************************************************/

2
src/mame/machine/pcecommn.c
View File

@ -19,7 +19,7 @@
/* todo: how many input ports does the PCE have? */
WRITE8_MEMBER(pce_common_state::pce_joystick_w)
{
h6280io_set_buffer(&space.device(), data);
machine().device<h6280_device>("maincpu")->io_set_buffer(data);
/* bump counter on a low-to-high transition of bit 1 */
if((!m_joystick_data_select) && (data & JOY_CLOCK))
{

24
src/mess/drivers/pce.c
View File

@ -79,10 +79,10 @@ static ADDRESS_MAP_START( pce_mem , AS_PROGRAM, 8, pce_state )
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000) AM_SHARE("user_ram")
AM_RANGE( 0x1FE000, 0x1FE3FF) AM_READWRITE_LEGACY(vdc_0_r, vdc_0_w )
AM_RANGE( 0x1FE400, 0x1FE7FF) AM_READWRITE_LEGACY(vce_r, vce_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE_LEGACY(C6280_TAG, c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_READWRITE_LEGACY(h6280_timer_r, h6280_timer_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE(C6280_TAG, c6280_device, c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_DEVREADWRITE("maincpu", h6280_device, timer_r, timer_w )
AM_RANGE( 0x1FF000, 0x1FF3FF) AM_READWRITE(mess_pce_joystick_r, mess_pce_joystick_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_READWRITE_LEGACY(h6280_irq_status_r, h6280_irq_status_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_DEVREADWRITE("maincpu", h6280_device, irq_status_r, irq_status_w )
AM_RANGE( 0x1FF800, 0x1FFBFF) AM_READWRITE(pce_cd_intf_r, pce_cd_intf_w )
ADDRESS_MAP_END
@ -104,10 +104,10 @@ static ADDRESS_MAP_START( sgx_mem , AS_PROGRAM, 8, pce_state )
AM_RANGE( 0x1FE008, 0x1FE00F) AM_READWRITE_LEGACY(vpc_r, vpc_w ) AM_MIRROR(0x03E0)
AM_RANGE( 0x1FE010, 0x1FE017) AM_READWRITE_LEGACY(vdc_1_r, vdc_1_w ) AM_MIRROR(0x03E0)
AM_RANGE( 0x1FE400, 0x1FE7FF) AM_READWRITE_LEGACY(vce_r, vce_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE_LEGACY(C6280_TAG, c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_READWRITE_LEGACY(h6280_timer_r, h6280_timer_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE(C6280_TAG, c6280_device, c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_DEVREADWRITE("maincpu", h6280_device, timer_r, timer_w )
AM_RANGE( 0x1FF000, 0x1FF3FF) AM_READWRITE(mess_pce_joystick_r, mess_pce_joystick_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_READWRITE_LEGACY(h6280_irq_status_r, h6280_irq_status_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_DEVREADWRITE("maincpu", h6280_device, irq_status_r, irq_status_w )
AM_RANGE( 0x1FF800, 0x1FFBFF) AM_READWRITE(pce_cd_intf_r, pce_cd_intf_w )
ADDRESS_MAP_END
@ -455,10 +455,10 @@ static ADDRESS_MAP_START( pce_mem_new , AS_PROGRAM, 8, pce_state )
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000) AM_SHARE("user_ram")
AM_RANGE( 0x1FE000, 0x1FE3FF) AM_DEVREADWRITE( "huc6270", huc6270_device, read, write )
AM_RANGE( 0x1FE400, 0x1FE7FF) AM_DEVREADWRITE( "huc6260", huc6260_device, read, write )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE_LEGACY( C6280_TAG, c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_READWRITE_LEGACY( h6280_timer_r, h6280_timer_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE( C6280_TAG, c6280_device, c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_DEVREADWRITE( "maincpu", h6280_device, timer_r, timer_w )
AM_RANGE( 0x1FF000, 0x1FF3FF) AM_READWRITE( mess_pce_joystick_r, mess_pce_joystick_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_READWRITE_LEGACY( h6280_irq_status_r, h6280_irq_status_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_DEVREADWRITE( "maincpu", h6280_device, irq_status_r, irq_status_w )
AM_RANGE( 0x1FF800, 0x1FFBFF) AM_READWRITE( pce_cd_intf_r, pce_cd_intf_w )
ADDRESS_MAP_END
@ -481,10 +481,10 @@ static ADDRESS_MAP_START( sgx_mem_new , AS_PROGRAM, 8, pce_state )
AM_RANGE( 0x1FE008, 0x1FE00F) AM_DEVREADWRITE( "huc6202", huc6202_device, read, write ) AM_MIRROR(0x03E0)
AM_RANGE( 0x1FE010, 0x1FE017) AM_DEVREADWRITE( "huc6270_1", huc6270_device, read, write ) AM_MIRROR(0x03E0)
AM_RANGE( 0x1FE400, 0x1FE7FF) AM_DEVREADWRITE( "huc6260", huc6260_device, read, write )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE_LEGACY(C6280_TAG, c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_READWRITE_LEGACY(h6280_timer_r, h6280_timer_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE(C6280_TAG, c6280_device, c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_DEVREADWRITE("maincpu", h6280_device, timer_r, timer_w )
AM_RANGE( 0x1FF000, 0x1FF3FF) AM_READWRITE(mess_pce_joystick_r, mess_pce_joystick_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_READWRITE_LEGACY(h6280_irq_status_r, h6280_irq_status_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_DEVREADWRITE("maincpu", h6280_device, irq_status_r, irq_status_w )
AM_RANGE( 0x1FF800, 0x1FFBFF) AM_READWRITE(pce_cd_intf_r, pce_cd_intf_w )
ADDRESS_MAP_END

7
src/mess/drivers/ssem.c
View File

@ -10,14 +10,15 @@
#include "imagedev/cartslot.h"
#include <stdarg.h>
class ssem_state : public driver_device
{
public:
ssem_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag) ,
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_store(*this, "store"){ }
required_device<ssem_device> m_maincpu;
required_shared_ptr<UINT8> m_store;
UINT8 m_store_line;
virtual void machine_reset();
@ -632,7 +633,7 @@ void ssem_state::machine_reset()
static MACHINE_CONFIG_START( ssem, ssem_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", SSEM, 700)
MCFG_CPU_ADD("maincpu", SSEMCPU, 700)
MCFG_CPU_PROGRAM_MAP(ssem_map)

4
src/mess/drivers/x1twin.c
View File

@ -59,10 +59,10 @@ static ADDRESS_MAP_START( pce_mem , AS_PROGRAM, 8, x1twin_state )
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000)
AM_RANGE( 0x1FE000, 0x1FE3FF) AM_READWRITE( vdc_0_r, vdc_0_w )
AM_RANGE( 0x1FE400, 0x1FE7FF) AM_READWRITE( vce_r, vce_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE( "c6280", c6280_r, c6280_w )
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE( "c6280", c6280_device, c6280_r, c6280_w )
AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_READWRITE( h6280_timer_r, h6280_timer_w )
AM_RANGE( 0x1FF000, 0x1FF3FF) AM_READWRITE( pce_joystick_r, pce_joystick_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_READWRITE( h6280_irq_status_r, h6280_irq_status_w )
AM_RANGE( 0x1FF400, 0x1FF7FF) AM_DEVREADWRITE( "maincpu", h6280_device, irq_status_r, irq_status_w )
ADDRESS_MAP_END
static ADDRESS_MAP_START( pce_io, AS_IO, 8, x1twin_state )

5
src/mess/includes/pce.h
View File

@ -10,6 +10,7 @@
#define PCE_H_
#include "cdrom.h"
#include "cpu/h6280/h6280.h"
#include "sound/msm5205.h"
#include "machine/nvram.h"
#include "video/huc6260.h"
@ -108,12 +109,14 @@ class pce_state : public driver_device
{
public:
pce_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag) ,
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_cd_ram(*this, "cd_ram"),
m_user_ram(*this, "user_ram"),
m_huc6260(*this, "huc6260")
{ }
required_device<h6280_device> m_maincpu;
required_shared_ptr<UINT8> m_cd_ram;
required_shared_ptr<unsigned char> m_user_ram;
optional_device<huc6260_device> m_huc6260;

2
src/mess/machine/pce.c
View File

@ -302,7 +302,7 @@ WRITE8_MEMBER(pce_state::mess_pce_joystick_w)
int joy_i;
UINT8 joy_type = ioport("JOY_TYPE")->read();
h6280io_set_buffer(&space.device(), data);
m_maincpu->io_set_buffer(data);
/* bump counter on a low-to-high transition of bit 1 */
if ((!m_joystick_data_select) && (data & JOY_CLOCK))