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Converted Z80 CTC to a proper device. Updated all drivers.

Browse Source 
Added new item to the interface which is the tag of a CPU
to take the base clock from. Are there any known cases
where the base clock does NOT come from the CPU directly?

Changed Z80 daisy chain interface to simply be a list of
devices in the chain. Interrupt callback functions are now
fetched via the standard device interface and referenced by
the daisy chain code.

Changed Z80 PIO interrupt callback to pass a device instead
of the machine. All device callbacks should provide the
device.
This commit is contained in:
Aaron Giles 2008-09-29 17:20:58 +00:00
parent 3355357ffc
commit f4dc7a2f36
23 changed files with 638 additions and 575 deletions
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8
src/emu/cpu/z180/z180.c
View File

@ -115,7 +115,7 @@ typedef struct {
UINT8 nmi_pending; /* nmi pending */
UINT8 irq_state[3]; /* irq line states (INT0,INT1,INT2) */
UINT8 after_EI; /* are we in the EI shadow? */
const struct z80_irq_daisy_chain *daisy;
z80_daisy_state *daisy;
int (*irq_callback)(int irqline);
} Z180_Regs;
@ -1898,7 +1898,9 @@ static void z180_write_iolines(UINT32 data)
static void z180_init(int index, int clock, const void *config, int (*irqcallback)(int))
{
Z180.daisy = config;
Z180.daisy = NULL;
if (config)
Z180.daisy = z80daisy_init(Machine, config);
Z180.irq_callback = irqcallback;
state_save_register_item("z180", index, Z180.AF.w.l);
@ -1933,7 +1935,7 @@ static void z180_init(int index, int clock, const void *config, int (*irqcallbac
****************************************************************************/
static void z180_reset(void)
{
const struct z80_irq_daisy_chain *save_daisy;
z80_daisy_state *save_daisy;
int (*save_irqcallback)(int);
int i, p;
#if BIG_FLAGS_ARRAY

5
src/emu/cpu/z80/z80.c
View File

@ -127,8 +127,8 @@ typedef struct
UINT8 nmi_pending; /* nmi pending */
UINT8 irq_state; /* irq line state */
UINT8 after_ei; /* are we in the EI shadow? */
const struct z80_irq_daisy_chain *daisy;
int (*irq_callback)(int irqline);
z80_daisy_state *daisy;
} Z80_Regs;
#define CF 0x01
@ -3498,7 +3498,8 @@ static void z80_init(int index, int clock, const void *config, int (*irqcallback
/* Reset registers to their initial values */
memset(&Z80, 0, sizeof(Z80));
Z80.daisy = config;
if (config != NULL)
Z80.daisy = z80daisy_init(Machine, config);
Z80.irq_callback = irqcallback;
IX = IY = 0xffff; /* IX and IY are FFFF after a reset! */
F = ZF; /* Zero flag is set */

62
src/emu/cpu/z80/z80daisy.c
View File

@ -10,21 +10,51 @@
#include "z80daisy.h"
void z80daisy_reset(const struct z80_irq_daisy_chain *daisy)
struct _z80_daisy_state
{
/* loop over all devices and call their reset function */
for ( ; daisy->param != -1; daisy++)
if (daisy->reset)
(*daisy->reset)(daisy->param);
z80_daisy_state * next; /* next device */
const device_config * device; /* associated device */
z80_daisy_irq_state irq_state; /* IRQ state callback */
z80_daisy_irq_ack irq_ack; /* IRQ ack callback */
z80_daisy_irq_reti irq_reti; /* IRQ reti callback */
};
z80_daisy_state *z80daisy_init(running_machine *machine, const z80_daisy_chain *daisy)
{
z80_daisy_state *head = NULL;
z80_daisy_state **tailptr = &head;
/* create a linked list of devices */
for ( ; daisy->devtype != NULL; daisy++)
{
*tailptr = auto_malloc(sizeof(**tailptr));
(*tailptr)->next = NULL;
(*tailptr)->device = devtag_get_device(machine, daisy->devtype, daisy->devname);
(*tailptr)->irq_state = (z80_daisy_irq_state)device_get_info_fct((*tailptr)->device, DEVINFO_FCT_IRQ_STATE);
(*tailptr)->irq_ack = (z80_daisy_irq_ack)device_get_info_fct((*tailptr)->device, DEVINFO_FCT_IRQ_ACK);
(*tailptr)->irq_reti = (z80_daisy_irq_reti)device_get_info_fct((*tailptr)->device, DEVINFO_FCT_IRQ_RETI);
tailptr = &(*tailptr)->next;
}
return head;
}
int z80daisy_update_irq_state(const struct z80_irq_daisy_chain *daisy)
void z80daisy_reset(z80_daisy_state *daisy)
{
/* loop over all devices and call their reset function */
for ( ; daisy != NULL; daisy = daisy->next)
device_reset(daisy->device);
}
int z80daisy_update_irq_state(z80_daisy_state *daisy)
{
/* loop over all devices; dev[0] is highest priority */
for ( ; daisy->param != -1; daisy++)
for ( ; daisy != NULL; daisy = daisy->next)
{
int state = (*daisy->irq_state)(daisy->param);
int state = (*daisy->irq_state)(daisy->device);
/* if this device is asserting the INT line, that's the one we want */
if (state & Z80_DAISY_INT)
@ -39,16 +69,16 @@ int z80daisy_update_irq_state(const struct z80_irq_daisy_chain *daisy)
}
int z80daisy_call_ack_device(const struct z80_irq_daisy_chain *daisy)
int z80daisy_call_ack_device(z80_daisy_state *daisy)
{
/* loop over all devices; dev[0] is the highest priority */
for ( ; daisy->param != -1; daisy++)
for ( ; daisy != NULL; daisy = daisy->next)
{
int state = (*daisy->irq_state)(daisy->param);
int state = (*daisy->irq_state)(daisy->device);
/* if this device is asserting the INT line, that's the one we want */
if (state & Z80_DAISY_INT)
return (*daisy->irq_ack)(daisy->param);
return (*daisy->irq_ack)(daisy->device);
}
logerror("z80daisy_call_ack_device: failed to find an device to ack!\n");
@ -56,17 +86,17 @@ int z80daisy_call_ack_device(const struct z80_irq_daisy_chain *daisy)
}
void z80daisy_call_reti_device(const struct z80_irq_daisy_chain *daisy)
void z80daisy_call_reti_device(z80_daisy_state *daisy)
{
/* loop over all devices; dev[0] is the highest priority */
for ( ; daisy->param != -1; daisy++)
for ( ; daisy != NULL; daisy = daisy->next)
{
int state = (*daisy->irq_state)(daisy->param);
int state = (*daisy->irq_state)(daisy->device);
/* if this device is asserting the IEO line, that's the one we want */
if (state & Z80_DAISY_IEO)
{
(*daisy->irq_reti)(daisy->param);
(*daisy->irq_reti)(daisy->device);
return;
}
}

68
src/emu/cpu/z80/z80daisy.h
View File

@ -6,31 +6,65 @@
***************************************************************************/
#pragma once
#ifndef Z80DAISY_H
#define Z80DAISY_H
#ifndef __Z80DAISY_H__
#define __Z80DAISY_H__
#include "devintrf.h"
/* daisy-chain link */
struct z80_irq_daisy_chain
{
void (*reset)(int); /* reset callback */
int (*irq_state)(int); /* get interrupt state */
int (*irq_ack)(int); /* interrupt acknowledge callback */
void (*irq_reti)(int); /* reti callback */
int param; /* callback parameter (-1 ends list) */
};
/***************************************************************************
CONSTANTS
***************************************************************************/
/* these constants are returned from the irq_state function */
#define Z80_DAISY_INT 0x01 /* interrupt request mask */
#define Z80_DAISY_IEO 0x02 /* interrupt disable mask (IEO) */
/* prototypes */
void z80daisy_reset(const struct z80_irq_daisy_chain *daisy);
int z80daisy_update_irq_state(const struct z80_irq_daisy_chain *chain);
int z80daisy_call_ack_device(const struct z80_irq_daisy_chain *chain);
void z80daisy_call_reti_device(const struct z80_irq_daisy_chain *chain);
enum
{
DEVINFO_FCT_IRQ_STATE = DEVINFO_FCT_DEVICE_SPECIFIC, /* R/O: z80_daisy_irq_state */
DEVINFO_FCT_IRQ_ACK, /* R/O: z80_daisy_irq_ack */
DEVINFO_FCT_IRQ_RETI /* R/O: z80_daisy_irq_reti */
};
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/
/* per-device callback functions */
typedef int (*z80_daisy_irq_state)(const device_config *device);
typedef int (*z80_daisy_irq_ack)(const device_config *device);
typedef int (*z80_daisy_irq_reti)(const device_config *device);
/* opaque internal daisy chain state */
typedef struct _z80_daisy_state z80_daisy_state;
/* daisy chain structure */
typedef struct _z80_daisy_chain z80_daisy_chain;
struct _z80_daisy_chain
{
device_type devtype; /* type of device */
const char * devname; /* name of the device */
};
/***************************************************************************
FUNCTION PROTOTYPES
***************************************************************************/
z80_daisy_state *z80daisy_init(running_machine *machine, const z80_daisy_chain *daisy);
void z80daisy_reset(z80_daisy_state *daisy);
int z80daisy_update_irq_state(z80_daisy_state *chain);
int z80daisy_call_ack_device(z80_daisy_state *chain);
void z80daisy_call_reti_device(z80_daisy_state *chain);
#endif

389
src/emu/machine/z80ctc.c
View File

@ -10,7 +10,6 @@
***************************************************************************/
#include "driver.h"
#include "deprecat.h"
#include "z80ctc.h"
#include "cpu/z80/z80.h"
#include "cpu/z80/z80daisy.h"
@ -73,31 +72,54 @@
TYPE DEFINITIONS
***************************************************************************/
typedef struct _ctc_channel ctc_channel;
struct _ctc_channel
{
write8_device_func zc; /* zero crossing callbacks */
UINT8 notimer; /* no timer masks */
UINT16 mode; /* current mode */
UINT16 tconst; /* time constant */
UINT16 down; /* down counter (clock mode only) */
UINT8 extclk; /* current signal from the external clock */
emu_timer * timer; /* array of active timers */
UINT8 int_state; /* interrupt status (for daisy chain) */
};
typedef struct _z80ctc z80ctc;
struct _z80ctc
{
UINT8 vector; /* interrupt vector */
UINT32 clock; /* system clock */
attotime period16; /* 16/system clock */
attotime period256; /* 256/system clock */
void (*intr)(running_machine *machine, int which); /* interrupt callback */
write8_machine_func zc[4]; /* zero crossing callbacks */
UINT8 notimer; /* no timer masks */
UINT16 mode[4]; /* current mode */
UINT16 tconst[4]; /* time constant */
UINT16 down[4]; /* down counter (clock mode only) */
UINT8 extclk[4]; /* current signal from the external clock */
emu_timer *timer[4]; /* array of active timers */
UINT8 int_state[4]; /* interrupt status (for daisy chain) */
UINT8 vector; /* interrupt vector */
UINT32 clock; /* system clock */
attotime period16; /* 16/system clock */
attotime period256; /* 256/system clock */
void (*intr)(const device_config *device, int which); /* interrupt callback */
ctc_channel channel[4]; /* data for each channel */
};
/***************************************************************************
GLOBAL VARIABLES
FUNCTION PROTOTYPES
***************************************************************************/
static z80ctc ctcs[MAX_CTC];
static int z80ctc_irq_state(const device_config *device);
static int z80ctc_irq_ack(const device_config *device);
static void z80ctc_irq_reti(const device_config *device);
/***************************************************************************
INLINE FUNCTIONS
***************************************************************************/
INLINE z80ctc *get_safe_token(const device_config *device)
{
assert(device != NULL);
assert(device->token != NULL);
assert(device->type == Z80CTC);
return (z80ctc *)device->token;
}
@ -105,39 +127,39 @@ static z80ctc ctcs[MAX_CTC];
INTERNAL STATE MANAGEMENT
***************************************************************************/
static void interrupt_check(running_machine *machine, int which)
static void interrupt_check(const device_config *device)
{
z80ctc *ctc = ctcs + which;
z80ctc *ctc = get_safe_token(device);
/* if we have a callback, update it with the current state */
if (ctc->intr)
(*ctc->intr)(machine, (z80ctc_irq_state(which) & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE);
if (ctc->intr != NULL)
(*ctc->intr)(device, (z80ctc_irq_state(device) & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE);
}
static TIMER_CALLBACK( timercallback )
{
int which = param >> 2;
int ch = param & 3;
z80ctc *ctc = ctcs + which;
const device_config *device = ptr;
z80ctc *ctc = get_safe_token(device);
ctc_channel *channel = &ctc->channel[param];
/* down counter has reached zero - see if we should interrupt */
if ((ctc->mode[ch] & INTERRUPT) == INTERRUPT_ON)
if ((channel->mode & INTERRUPT) == INTERRUPT_ON)
{
ctc->int_state[ch] |= Z80_DAISY_INT;
VPRINTF(("CTC timer ch%d\n", ch));
interrupt_check(machine, which);
channel->int_state |= Z80_DAISY_INT;
VPRINTF(("CTC timer ch%d\n", param));
interrupt_check(device);
}
/* generate the clock pulse */
if (ctc->zc[ch])
if (channel->zc != NULL)
{
(*ctc->zc[ch])(machine,0,1);
(*ctc->zc[ch])(machine,0,0);
(*channel->zc)(device, 0, 1);
(*channel->zc)(device, 0, 0);
}
/* reset the down counter */
ctc->down[ch] = ctc->tconst[ch];
channel->down = channel->tconst;
}
@ -146,75 +168,26 @@ static TIMER_CALLBACK( timercallback )
INITIALIZATION/CONFIGURATION
***************************************************************************/
void z80ctc_init(int which, z80ctc_interface *intf)
attotime z80ctc_getperiod(const device_config *device, int ch)
{
z80ctc *ctc = &ctcs[which];
assert(which < MAX_CTC);
memset(ctc, 0, sizeof(*ctc));
ctc->clock = intf->baseclock;
ctc->period16 = attotime_mul(ATTOTIME_IN_HZ(intf->baseclock), 16);
ctc->period256 = attotime_mul(ATTOTIME_IN_HZ(intf->baseclock), 256);
ctc->notimer = intf->notimer;
ctc->intr = intf->intr;
ctc->timer[0] = timer_alloc(timercallback, NULL);
ctc->timer[1] = timer_alloc(timercallback, NULL);
ctc->timer[2] = timer_alloc(timercallback, NULL);
ctc->timer[3] = timer_alloc(timercallback, NULL);
ctc->zc[0] = intf->zc0;
ctc->zc[1] = intf->zc1;
ctc->zc[2] = intf->zc2;
ctc->zc[3] = 0;
z80ctc_reset(which);
state_save_register_item("z80ctc", which, ctc->vector);
state_save_register_item_array("z80ctc", which, ctc->mode);
state_save_register_item_array("z80ctc", which, ctc->tconst);
state_save_register_item_array("z80ctc", which, ctc->down);
state_save_register_item_array("z80ctc", which, ctc->extclk);
state_save_register_item_array("z80ctc", which, ctc->int_state);
}
void z80ctc_reset(int which)
{
z80ctc *ctc = ctcs + which;
int i;
/* set up defaults */
for (i = 0; i < 4; i++)
{
ctc->mode[i] = RESET_ACTIVE;
ctc->tconst[i] = 0x100;
timer_adjust_oneshot(ctc->timer[i], attotime_never, 0);
ctc->int_state[i] = 0;
}
interrupt_check(Machine, which);
VPRINTF(("CTC Reset\n"));
}
attotime z80ctc_getperiod(int which, int ch)
{
z80ctc *ctc = ctcs + which;
z80ctc *ctc = get_safe_token(device);
ctc_channel *channel = &ctc->channel[ch];
attotime period;
/* if reset active, no period */
if ((ctc->mode[ch] & RESET) == RESET_ACTIVE)
if ((channel->mode & RESET) == RESET_ACTIVE)
return attotime_zero;
/* if counter mode, no real period */
if ((ctc->mode[ch] & MODE) == MODE_COUNTER)
if ((channel->mode & MODE) == MODE_COUNTER)
{
logerror("CTC %d is CounterMode : Can't calculate period\n", ch );
return attotime_zero;
}
/* compute the period */
period = ((ctc->mode[ch] & PRESCALER) == PRESCALER_16) ? ctc->period16 : ctc->period256;
return attotime_mul(period, ctc->tconst[ch]);
period = ((channel->mode & PRESCALER) == PRESCALER_16) ? ctc->period16 : ctc->period256;
return attotime_mul(period, channel->tconst);
}
@ -223,13 +196,15 @@ attotime z80ctc_getperiod(int which, int ch)
WRITE HANDLERS
***************************************************************************/
void z80ctc_w(int which, int ch, UINT8 data)
WRITE8_DEVICE_HANDLER( z80ctc_w )
{
z80ctc *ctc = ctcs + which;
z80ctc *ctc = get_safe_token(device);
int ch = offset & 3;
ctc_channel *channel = &ctc->channel[ch];
int mode;
/* get the current mode */
mode = ctc->mode[ch];
mode = channel->mode;
/* if we're waiting for a time constant, this is it */
if ((mode & CONSTANT) == CONSTANT_LOAD)
@ -237,13 +212,13 @@ void z80ctc_w(int which, int ch, UINT8 data)
VPRINTF(("CTC ch.%d constant = %02x\n", ch, data));
/* set the time constant (0 -> 0x100) */
ctc->tconst[ch] = data ? data : 0x100;
channel->tconst = data ? data : 0x100;
/* clear the internal mode -- we're no longer waiting */
ctc->mode[ch] &= ~CONSTANT;
channel->mode &= ~CONSTANT;
/* also clear the reset, since the constant gets it going again */
ctc->mode[ch] &= ~RESET;
channel->mode &= ~RESET;
/* if we're in timer mode.... */
if ((mode & MODE) == MODE_TIMER)
@ -251,24 +226,24 @@ void z80ctc_w(int which, int ch, UINT8 data)
/* if we're triggering on the time constant, reset the down counter now */
if ((mode & TRIGGER) == TRIGGER_AUTO)
{
if (!(ctc->notimer & (1<<ch)))
if (!channel->notimer)
{
attotime period = ((mode & PRESCALER) == PRESCALER_16) ? ctc->period16 : ctc->period256;
period = attotime_mul(period, ctc->tconst[ch]);
period = attotime_mul(period, channel->tconst);
timer_adjust_periodic(ctc->timer[ch], period, (which << 2) + ch, period);
timer_adjust_periodic(channel->timer, period, ch, period);
}
else
timer_adjust_oneshot(ctc->timer[ch], attotime_never, 0);
timer_adjust_oneshot(channel->timer, attotime_never, 0);
}
/* else set the bit indicating that we're waiting for the appropriate trigger */
else
ctc->mode[ch] |= WAITING_FOR_TRIG;
channel->mode |= WAITING_FOR_TRIG;
}
/* also set the down counter in case we're clocking externally */
ctc->down[ch] = ctc->tconst[ch];
channel->down = channel->tconst;
/* all done here */
return;
@ -292,13 +267,13 @@ void z80ctc_w(int which, int ch, UINT8 data)
if ((data & CONTROL) == CONTROL_WORD)
{
/* set the new mode */
ctc->mode[ch] = data;
channel->mode = data;
VPRINTF(("CTC ch.%d mode = %02x\n", ch, data));
/* if we're being reset, clear out any pending timers for this channel */
if ((data & RESET) == RESET_ACTIVE)
{
timer_adjust_oneshot(ctc->timer[ch], attotime_never, 0);
timer_adjust_oneshot(channel->timer, attotime_never, 0);
/* note that we don't clear the interrupt state here! */
}
@ -307,104 +282,99 @@ void z80ctc_w(int which, int ch, UINT8 data)
}
}
WRITE8_HANDLER( z80ctc_0_w ) { z80ctc_w(0, offset, data); }
WRITE8_HANDLER( z80ctc_1_w ) { z80ctc_w(1, offset, data); }
/***************************************************************************
READ HANDLERS
***************************************************************************/
UINT8 z80ctc_r(int which, int ch)
READ8_DEVICE_HANDLER( z80ctc_r )
{
z80ctc *ctc = ctcs + which;
z80ctc *ctc = get_safe_token(device);
int ch = offset & 3;
ctc_channel *channel = &ctc->channel[ch];
/* if we're in counter mode, just return the count */
if ((ctc->mode[ch] & MODE) == MODE_COUNTER || (ctc->mode[ch] & WAITING_FOR_TRIG))
return ctc->down[ch];
if ((channel->mode & MODE) == MODE_COUNTER || (channel->mode & WAITING_FOR_TRIG))
return channel->down;
/* else compute the down counter value */
else
{
attotime period = ((ctc->mode[ch] & PRESCALER) == PRESCALER_16) ? ctc->period16 : ctc->period256;
attotime period = ((channel->mode & PRESCALER) == PRESCALER_16) ? ctc->period16 : ctc->period256;
VPRINTF(("CTC clock %f\n",ATTOSECONDS_TO_HZ(period.attoseconds)));
if (ctc->timer[ch])
return ((int)(attotime_to_double(timer_timeleft(ctc->timer[ch])) * attotime_to_double(period)) + 1) & 0xff;
if (channel->timer != NULL)
return ((int)(attotime_to_double(timer_timeleft(channel->timer)) * attotime_to_double(period)) + 1) & 0xff;
else
return 0;
}
}
READ8_HANDLER( z80ctc_0_r ) { return z80ctc_r(0, offset); }
READ8_HANDLER( z80ctc_1_r ) { return z80ctc_r(1, offset); }
/***************************************************************************
EXTERNAL TRIGGERS
***************************************************************************/
void z80ctc_trg_w(running_machine *machine, int which, int ch, UINT8 data)
void z80ctc_trg_w(const device_config *device, int ch, UINT8 data)
{
z80ctc *ctc = ctcs + which;
z80ctc *ctc = get_safe_token(device);
ctc_channel *channel = &ctc->channel[ch];
/* normalize data */
data = data ? 1 : 0;
/* see if the trigger value has changed */
if (data != ctc->extclk[ch])
if (data != channel->extclk)
{
ctc->extclk[ch] = data;
channel->extclk = data;
/* see if this is the active edge of the trigger */
if (((ctc->mode[ch] & EDGE) == EDGE_RISING && data) || ((ctc->mode[ch] & EDGE) == EDGE_FALLING && !data))
if (((channel->mode & EDGE) == EDGE_RISING && data) || ((channel->mode & EDGE) == EDGE_FALLING && !data))
{
/* if we're waiting for a trigger, start the timer */
if ((ctc->mode[ch] & WAITING_FOR_TRIG) && (ctc->mode[ch] & MODE) == MODE_TIMER)
if ((channel->mode & WAITING_FOR_TRIG) && (channel->mode & MODE) == MODE_TIMER)
{
if (!(ctc->notimer & (1<<ch)))
if (!channel->notimer)
{
attotime period = ((ctc->mode[ch] & PRESCALER) == PRESCALER_16) ? ctc->period16 : ctc->period256;
period = attotime_mul(period, ctc->tconst[ch]);
attotime period = ((channel->mode & PRESCALER) == PRESCALER_16) ? ctc->period16 : ctc->period256;
period = attotime_mul(period, channel->tconst);
VPRINTF(("CTC period %s\n", attotime_string(period, 9)));
timer_adjust_periodic(ctc->timer[ch], period, (which << 2) + ch, period);
timer_adjust_periodic(channel->timer, period, ch, period);
}
else
{
VPRINTF(("CTC disabled\n"));
timer_adjust_oneshot(ctc->timer[ch], attotime_never, 0);
timer_adjust_oneshot(channel->timer, attotime_never, 0);
}
}
/* we're no longer waiting */
ctc->mode[ch] &= ~WAITING_FOR_TRIG;
channel->mode &= ~WAITING_FOR_TRIG;
/* if we're clocking externally, decrement the count */
if ((ctc->mode[ch] & MODE) == MODE_COUNTER)
if ((channel->mode & MODE) == MODE_COUNTER)
{
ctc->down[ch]--;
channel->down--;
/* if we hit zero, do the same thing as for a timer interrupt */
if (!ctc->down[ch])
timercallback(machine, NULL, (which << 2) + ch);
if (!channel->down)
{
void *ptr = (void *)device;
timercallback(device->machine, ptr, ch);
}
}
}
}
}
WRITE8_HANDLER( z80ctc_0_trg0_w ) { z80ctc_trg_w(machine, 0, 0, data); }
WRITE8_HANDLER( z80ctc_0_trg1_w ) { z80ctc_trg_w(machine, 0, 1, data); }
WRITE8_HANDLER( z80ctc_0_trg2_w ) { z80ctc_trg_w(machine, 0, 2, data); }
WRITE8_HANDLER( z80ctc_0_trg3_w ) { z80ctc_trg_w(machine, 0, 3, data); }
WRITE8_HANDLER( z80ctc_1_trg0_w ) { z80ctc_trg_w(machine, 1, 0, data); }
WRITE8_HANDLER( z80ctc_1_trg1_w ) { z80ctc_trg_w(machine, 1, 1, data); }
WRITE8_HANDLER( z80ctc_1_trg2_w ) { z80ctc_trg_w(machine, 1, 2, data); }
WRITE8_HANDLER( z80ctc_1_trg3_w ) { z80ctc_trg_w(machine, 1, 3, data); }
WRITE8_DEVICE_HANDLER( z80ctc_trg0_w ) { z80ctc_trg_w(device, 0, data); }
WRITE8_DEVICE_HANDLER( z80ctc_trg1_w ) { z80ctc_trg_w(device, 1, data); }
WRITE8_DEVICE_HANDLER( z80ctc_trg2_w ) { z80ctc_trg_w(device, 2, data); }
WRITE8_DEVICE_HANDLER( z80ctc_trg3_w ) { z80ctc_trg_w(device, 3, data); }
@ -412,72 +382,183 @@ WRITE8_HANDLER( z80ctc_1_trg3_w ) { z80ctc_trg_w(machine, 1, 3, data); }
DAISY CHAIN INTERFACE
***************************************************************************/
int z80ctc_irq_state(int which)
static int z80ctc_irq_state(const device_config *device)
{
z80ctc *ctc = ctcs + which;
z80ctc *ctc = get_safe_token(device);
int state = 0;
int ch;
VPRINTF(("CTC IRQ state = %d%d%d%d\n", ctc->int_state[0], ctc->int_state[1], ctc->int_state[2], ctc->int_state[3]));
VPRINTF(("CTC IRQ state = %d%d%d%d\n", ctc->channel[0].int_state, ctc->channel[1].int_state, ctc->channel[2].int_state, ctc->channel[3].int_state));
/* loop over all channels */
for (ch = 0; ch < 4; ch++)
{
ctc_channel *channel = &ctc->channel[ch];
/* if we're servicing a request, don't indicate more interrupts */
if (ctc->int_state[ch] & Z80_DAISY_IEO)
if (channel->int_state & Z80_DAISY_IEO)
{
state |= Z80_DAISY_IEO;
break;
}
state |= ctc->int_state[ch];
state |= channel->int_state;
}
return state;
}
int z80ctc_irq_ack(int which)
static int z80ctc_irq_ack(const device_config *device)
{
z80ctc *ctc = ctcs + which;
z80ctc *ctc = get_safe_token(device);
int ch;
/* loop over all channels */
for (ch = 0; ch < 4; ch++)
{
ctc_channel *channel = &ctc->channel[ch];
/* find the first channel with an interrupt requested */
if (ctc->int_state[ch] & Z80_DAISY_INT)
if (channel->int_state & Z80_DAISY_INT)
{
VPRINTF(("CTC IRQAck ch%d\n", ch));
/* clear interrupt, switch to the IEO state, and update the IRQs */
ctc->int_state[ch] = Z80_DAISY_IEO;
interrupt_check(Machine, which);
channel->int_state = Z80_DAISY_IEO;
interrupt_check(device);
return ctc->vector + ch * 2;
}
}
logerror("z80ctc_irq_ack: failed to find an interrupt to ack!\n");
return ctc->vector;
}
void z80ctc_irq_reti(int which)
static void z80ctc_irq_reti(const device_config *device)
{
z80ctc *ctc = ctcs + which;
z80ctc *ctc = get_safe_token(device);
int ch;
/* loop over all channels */
for (ch = 0; ch < 4; ch++)
{
ctc_channel *channel = &ctc->channel[ch];
/* find the first channel with an IEO pending */
if (ctc->int_state[ch] & Z80_DAISY_IEO)
if (channel->int_state & Z80_DAISY_IEO)
{
VPRINTF(("CTC IRQReti ch%d\n", ch));
/* clear the IEO state and update the IRQs */
ctc->int_state[ch] &= ~Z80_DAISY_IEO;
interrupt_check(Machine, which);
channel->int_state &= ~Z80_DAISY_IEO;
interrupt_check(device);
return;
}
}
logerror("z80ctc_irq_reti: failed to find an interrupt to clear IEO on!\n");
}
static DEVICE_START( z80ctc )
{
const z80ctc_interface *intf = device->static_config;
z80ctc *ctc = get_safe_token(device);
char unique_tag[30];
int cpunum = -1;
int ch;
if (intf->cpu != NULL)
cpunum = mame_find_cpu_index(device->machine, intf->cpu);
if (cpunum != -1)
ctc->clock = device->machine->config->cpu[cpunum].clock;
else
ctc->clock = intf->baseclock;
ctc->period16 = attotime_mul(ATTOTIME_IN_HZ(ctc->clock), 16);
ctc->period256 = attotime_mul(ATTOTIME_IN_HZ(ctc->clock), 256);
for (ch = 0; ch < 4; ch++)
{
ctc_channel *channel = &ctc->channel[ch];
void *ptr = (void *)device;
channel->notimer = (intf->notimer >> ch) & 1;
channel->timer = timer_alloc(timercallback, ptr);
}
ctc->intr = intf->intr;
ctc->channel[0].zc = intf->zc0;
ctc->channel[1].zc = intf->zc1;
ctc->channel[2].zc = intf->zc2;
ctc->channel[3].zc = NULL;
/* register for save states */
state_save_combine_module_and_tag(unique_tag, "z80ctc", device->tag);
state_save_register_item(unique_tag, 0, ctc->vector);
for (ch = 0; ch < 4; ch++)
{
ctc_channel *channel = &ctc->channel[ch];
state_save_register_item(unique_tag, ch, channel->mode);
state_save_register_item(unique_tag, ch, channel->tconst);
state_save_register_item(unique_tag, ch, channel->down);
state_save_register_item(unique_tag, ch, channel->extclk);
state_save_register_item(unique_tag, ch, channel->int_state);
}
return DEVICE_START_OK;
}
static DEVICE_RESET( z80ctc )
{
z80ctc *ctc = get_safe_token(device);
int ch;
/* set up defaults */
for (ch = 0; ch < 4; ch++)
{
ctc_channel *channel = &ctc->channel[ch];
channel->mode = RESET_ACTIVE;
channel->tconst = 0x100;
timer_adjust_oneshot(channel->timer, attotime_never, 0);
channel->int_state = 0;
}
interrupt_check(device);
VPRINTF(("CTC Reset\n"));
}
static DEVICE_SET_INFO( z80ctc )
{
switch (state)
{
/* no parameters to set */
}
}
DEVICE_GET_INFO( z80ctc )
{
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case DEVINFO_INT_TOKEN_BYTES: info->i = sizeof(z80ctc); break;
case DEVINFO_INT_INLINE_CONFIG_BYTES: info->i = 0; break;
case DEVINFO_INT_CLASS: info->i = DEVICE_CLASS_PERIPHERAL; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case DEVINFO_FCT_SET_INFO: info->set_info = DEVICE_SET_INFO_NAME(z80ctc); break;
case DEVINFO_FCT_START: info->start = DEVICE_START_NAME(z80ctc);break;
case DEVINFO_FCT_STOP: /* Nothing */ break;
case DEVINFO_FCT_RESET: info->reset = DEVICE_RESET_NAME(z80ctc);break;
case DEVINFO_FCT_IRQ_STATE: info->f = (genf *)z80ctc_irq_state; break;
case DEVINFO_FCT_IRQ_ACK: info->f = (genf *)z80ctc_irq_ack; break;
case DEVINFO_FCT_IRQ_RETI: info->f = (genf *)z80ctc_irq_reti; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case DEVINFO_STR_NAME: info->s = "Zilog Z80 CTC"; break;
case DEVINFO_STR_FAMILY: info->s = "Z80"; break;
case DEVINFO_STR_VERSION: info->s = "1.0"; break;
case DEVINFO_STR_SOURCE_FILE: info->s = __FILE__; break;
case DEVINFO_STR_CREDITS: info->s = "Copyright Nicola Salmoria and the MAME Team"; break;
}
}

84
src/emu/machine/z80ctc.h
View File

@ -7,12 +7,14 @@
***************************************************************************/
#ifndef __Z80CTC_H__
#define __Z80CTC_H__
/***************************************************************************
CONSTANTS
***************************************************************************/
#define MAX_CTC 2
#define NOTIMER_0 (1<<0)
#define NOTIMER_1 (1<<1)
#define NOTIMER_2 (1<<2)
@ -24,15 +26,30 @@
TYPE DEFINITIONS
***************************************************************************/
typedef struct
typedef struct _z80ctc_interface z80ctc_interface;
struct _z80ctc_interface
{
int baseclock; /* timer clock */
int notimer; /* timer disablers */
void (*intr)(running_machine *machine, int which); /* callback when change interrupt status */
write8_machine_func zc0; /* ZC/TO0 callback */
write8_machine_func zc1; /* ZC/TO1 callback */
write8_machine_func zc2; /* ZC/TO2 callback */
} z80ctc_interface;
const char *cpu; /* CPU whose clock we use for our base */
int baseclock; /* timer clock */
int notimer; /* timer disablers */
void (*intr)(const device_config *device, int which); /* callback when change interrupt status */
write8_device_func zc0; /* ZC/TO0 callback */
write8_device_func zc1; /* ZC/TO1 callback */
write8_device_func zc2; /* ZC/TO2 callback */
};
/***************************************************************************
DEVICE CONFIGURATION MACROS
***************************************************************************/
#define MDRV_Z80CTC_ADD(_tag, _intrf) \
MDRV_DEVICE_ADD(_tag, Z80CTC) \
MDRV_DEVICE_CONFIG(_intrf)
#define MDRV_Z80CTC_REMOVE(_tag) \
MDRV_DEVICE_REMOVE(_tag, Z80CTC)
@ -40,29 +57,17 @@ typedef struct
INITIALIZATION/CONFIGURATION
***************************************************************************/
void z80ctc_init(int which, z80ctc_interface *intf);
void z80ctc_reset(int which);
attotime z80ctc_getperiod (int which, int ch);
void z80ctc_reset(const device_config *device);
attotime z80ctc_getperiod(const device_config *device, int ch);
/***************************************************************************
WRITE HANDLERS
READ/WRITE HANDLERS
***************************************************************************/
void z80ctc_w(int which, int ch, UINT8 data);
WRITE8_HANDLER( z80ctc_0_w );
WRITE8_HANDLER( z80ctc_1_w );
/***************************************************************************
READ HANDLERS
***************************************************************************/
UINT8 z80ctc_r(int which, int ch);
READ8_HANDLER( z80ctc_0_r );
READ8_HANDLER( z80ctc_1_r );
WRITE8_DEVICE_HANDLER( z80ctc_w );
READ8_DEVICE_HANDLER( z80ctc_r );
@ -70,22 +75,17 @@ READ8_HANDLER( z80ctc_1_r );
EXTERNAL TRIGGERS
***************************************************************************/
void z80ctc_trg_w(running_machine *machine, int which, int trg, UINT8 data);
WRITE8_HANDLER( z80ctc_0_trg0_w );
WRITE8_HANDLER( z80ctc_0_trg1_w );
WRITE8_HANDLER( z80ctc_0_trg2_w );
WRITE8_HANDLER( z80ctc_0_trg3_w );
WRITE8_HANDLER( z80ctc_1_trg0_w );
WRITE8_HANDLER( z80ctc_1_trg1_w );
WRITE8_HANDLER( z80ctc_1_trg2_w );
WRITE8_HANDLER( z80ctc_1_trg3_w );
void z80ctc_trg_w(const device_config *device, int trg, UINT8 data);
WRITE8_DEVICE_HANDLER( z80ctc_trg0_w );
WRITE8_DEVICE_HANDLER( z80ctc_trg1_w );
WRITE8_DEVICE_HANDLER( z80ctc_trg2_w );
WRITE8_DEVICE_HANDLER( z80ctc_trg3_w );
/***************************************************************************
DAISY CHAIN INTERFACE
***************************************************************************/
/* ----- device interface ----- */
int z80ctc_irq_state(int which);
int z80ctc_irq_ack(int which);
void z80ctc_irq_reti(int which);
#define Z80CTC DEVICE_GET_INFO_NAME(z80ctc)
DEVICE_GET_INFO( z80ctc );
#endif

30
src/emu/machine/z80pio.c
View File

@ -53,10 +53,11 @@
TYPE DEFINITIONS
***************************************************************************/
typedef struct _z80pio z80pio_t;
struct _z80pio
{
UINT8 vector[2]; /* interrupt vector */
void (*intr)(running_machine *, int which); /* interrupt callbacks */
void (*intr)(const device_config *, int which); /* interrupt callbacks */
void (*rdyr[2])(int data); /* RDY active callback */
read8_device_func port_read[2]; /* port read callbacks */
write8_device_func port_write[2]; /* port write callbacks */
@ -70,7 +71,17 @@ struct _z80pio
UINT8 strobe[2]; /* strobe inputs */
UINT8 int_state[2]; /* interrupt status (daisy chain) */
};
typedef struct _z80pio z80pio_t;
/***************************************************************************
FUNCTION PROTOTYPES
***************************************************************************/
static int z80pio_irq_state(const device_config *device);
static int z80pio_irq_ack(const device_config *device);
static void z80pio_irq_reti(const device_config *device);
/***************************************************************************
@ -108,7 +119,7 @@ INLINE void interrupt_check(const device_config *device)
/* if we have a callback, update it with the current state */
if (z80pio->intr)
z80pio->intr(device->machine, (z80pio_irq_state(device) & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE);
z80pio->intr(device, (z80pio_irq_state(device) & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE);
}
@ -442,7 +453,7 @@ void z80pio_bstb_w(const device_config *device, int state) { z80pio_update_strob
DAISY CHAIN INTERFACE
***************************************************************************/
int z80pio_irq_state(const device_config *device)
static int z80pio_irq_state(const device_config *device)
{
z80pio_t *z80pio = get_safe_token( device );
int state = 0;
@ -463,7 +474,7 @@ int z80pio_irq_state(const device_config *device)
}
int z80pio_irq_ack(const device_config *device)
static int z80pio_irq_ack(const device_config *device)
{
z80pio_t *z80pio = get_safe_token( device );
int ch;
@ -485,7 +496,7 @@ int z80pio_irq_ack(const device_config *device)
}
void z80pio_irq_reti(const device_config *device)
static void z80pio_irq_reti(const device_config *device)
{
z80pio_t *z80pio = get_safe_token( device );
int ch;
@ -604,10 +615,13 @@ DEVICE_GET_INFO( z80pio )
case DEVINFO_FCT_START: info->start = DEVICE_START_NAME(z80pio);break;
case DEVINFO_FCT_STOP: /* Nothing */ break;
case DEVINFO_FCT_RESET: info->reset = DEVICE_RESET_NAME(z80pio);break;
case DEVINFO_FCT_IRQ_STATE: info->f = (genf *)z80pio_irq_state; break;
case DEVINFO_FCT_IRQ_ACK: info->f = (genf *)z80pio_irq_ack; break;
case DEVINFO_FCT_IRQ_RETI: info->f = (genf *)z80pio_irq_reti; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case DEVINFO_STR_NAME: info->s = "Zilog Z80PIO"; break;
case DEVINFO_STR_FAMILY: info->s = "Z80PIO"; break;
case DEVINFO_STR_NAME: info->s = "Zilog Z80 PIO"; break;
case DEVINFO_STR_FAMILY: info->s = "Z80"; break;
case DEVINFO_STR_VERSION: info->s = "1.0"; break;
case DEVINFO_STR_SOURCE_FILE: info->s = __FILE__; break;
case DEVINFO_STR_CREDITS: info->s = "Copyright Nicola Salmoria and the MAME Team"; break;

18
src/emu/machine/z80pio.h
View File

@ -7,17 +7,18 @@
***************************************************************************/
#ifndef __Z80PIO_H_
#define __Z80PIO_H_
#ifndef __Z80PIO_H__
#define __Z80PIO_H__
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/
typedef struct _z80pio_interface z80pio_interface;
struct _z80pio_interface
{
void (*intr)(running_machine *machine, int which); /* callback when change interrupt status */
void (*intr)(const device_config *device, int which); /* callback when change interrupt status */
read8_device_func portAread; /* port A read callback */
read8_device_func portBread; /* port B read callback */
write8_device_func portAwrite; /* port A write callback */
@ -25,7 +26,7 @@ struct _z80pio_interface
void (*rdyA)(int data); /* portA ready active callback (do not support yet)*/
void (*rdyB)(int data); /* portB ready active callback (do not support yet)*/
};
typedef struct _z80pio_interface z80pio_interface;
/***************************************************************************
@ -80,15 +81,6 @@ void z80pio_astb_w(const device_config *device, int state);
void z80pio_bstb_w(const device_config *device, int state);
/***************************************************************************
DAISY CHAIN INTERFACE
***************************************************************************/
int z80pio_irq_state(const device_config *device);
int z80pio_irq_ack(const device_config *device);
void z80pio_irq_reti(const device_config *device);
/***************************************************************************
READ/WRITE HANDLERS
***************************************************************************/

23
src/mame/audio/cchasm.c
View File

@ -13,6 +13,7 @@
#include "sound/dac.h"
static int sound_flags;
static const device_config *ctc;
READ8_HANDLER( cchasm_snd_io_r )
{
@ -36,7 +37,7 @@ READ8_HANDLER( cchasm_snd_io_r )
case 0x41:
sound_flags &= ~0x80;
z80ctc_0_trg2_w (machine, 0, 0);
z80ctc_trg2_w(ctc, 0, 0);
return soundlatch2_r (machine, offset);
default:
logerror("Read from unmapped internal IO device at 0x%x\n", offset + 0x6000);
@ -75,7 +76,7 @@ WRITE8_HANDLER( cchasm_snd_io_w )
break;
case 0x61:
z80ctc_0_trg0_w (machine, 0, 0);
z80ctc_trg0_w(ctc, 0, 0);
break;
default:
@ -98,7 +99,7 @@ WRITE16_HANDLER( cchasm_io_w )
case 1:
sound_flags |= 0x80;
soundlatch2_w (machine, offset, data);
z80ctc_0_trg2_w (machine, 0, 1);
z80ctc_trg2_w (ctc, 0, 1);
cpunum_set_input_line(machine, 1, INPUT_LINE_NMI, PULSE_LINE);
break;
case 2:
@ -131,12 +132,12 @@ READ16_HANDLER( cchasm_io_r )
static int channel_active[2];
static int output[2];
static void ctc_interrupt (running_machine *machine, int state)
static void ctc_interrupt (const device_config *device, int state)
{
cpunum_set_input_line(machine, 1, 0, state);
cpunum_set_input_line(device->machine, 1, 0, state);
}
static WRITE8_HANDLER( ctc_timer_1_w )
static WRITE8_DEVICE_HANDLER( ctc_timer_1_w )
{
if (data) /* rising edge */
{
@ -146,7 +147,7 @@ static WRITE8_HANDLER( ctc_timer_1_w )
}
}
static WRITE8_HANDLER( ctc_timer_2_w )
static WRITE8_DEVICE_HANDLER( ctc_timer_2_w )
{
if (data) /* rising edge */
{
@ -156,8 +157,9 @@ static WRITE8_HANDLER( ctc_timer_2_w )
}
}
static z80ctc_interface ctc_intf =
z80ctc_interface cchasm_ctc_intf =
{
"audio", /* clock from the audio CPU */
0, /* clock (filled in from the CPU 0 clock */
0, /* timer disables */
ctc_interrupt, /* interrupt handler */
@ -169,7 +171,7 @@ static z80ctc_interface ctc_intf =
static TIMER_CALLBACK( cchasm_sh_update )
{
if ((input_port_read(machine, "IN3") & 0x70) != 0x70)
z80ctc_0_trg0_w (machine, 0, 1);
z80ctc_trg0_w (ctc, 0, 1);
}
SOUND_START( cchasm )
@ -177,8 +179,7 @@ SOUND_START( cchasm )
sound_flags = 0;
output[0] = 0; output[1] = 0;
ctc_intf.baseclock = cpunum_get_clock(1);
z80ctc_init (0, &ctc_intf);
ctc = devtag_get_device(machine, Z80CTC, "ctc");
timer_pulse(video_screen_get_frame_period(machine->primary_screen), NULL, 0, cchasm_sh_update);
}

21
src/mame/audio/cinemat.c
View File

@ -1490,14 +1490,15 @@ static const ay8910_interface demon_ay8910_interface_3 =
};
static void ctc_interrupt(running_machine *machine, int state)
static void ctc_interrupt(const device_config *device, int state)
{
cpunum_set_input_line(machine, 1, 0, state);
cpunum_set_input_line(device->machine, 1, 0, state);
}
static z80ctc_interface demon_z80ctc_interface =
{
"audio", /* clocked from the audio CPU */
0, /* clock (filled in from the CPU clock) */
0, /* timer disables */
ctc_interrupt, /* interrupt handler */
@ -1512,10 +1513,6 @@ static MACHINE_RESET( demon_sound )
/* generic init */
generic_init(machine, demon_sound_w);
/* initialize the CTC interface */
demon_z80ctc_interface.baseclock = cpunum_get_clock(1);
z80ctc_init(0, &demon_z80ctc_interface);
/* reset the FIFO */
sound_fifo_in = sound_fifo_out = 0;
last_portb_write = 0xff;
@ -1543,15 +1540,15 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( demon_sound_ports, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x1c, 0x1f) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x00, 0x03) AM_DEVWRITE(Z80CTC, "ctc", z80ctc_w)
AM_RANGE(0x1c, 0x1f) AM_DEVWRITE(Z80CTC, "ctc", z80ctc_w)
ADDRESS_MAP_END
static const struct z80_irq_daisy_chain daisy_chain[] =
static const z80_daisy_chain daisy_chain[] =
{
{ z80ctc_reset, z80ctc_irq_state, z80ctc_irq_ack, z80ctc_irq_reti, 0 },
{ 0,0,0,0,-1 }
{ Z80CTC, "ctc" },
{ NULL }
};
@ -1562,6 +1559,8 @@ MACHINE_DRIVER_START( demon_sound )
MDRV_CPU_CONFIG(daisy_chain)
MDRV_CPU_PROGRAM_MAP(demon_sound_map,0)
MDRV_CPU_IO_MAP(demon_sound_ports,0)
MDRV_Z80CTC_ADD("ctc", demon_z80ctc_interface)
MDRV_MACHINE_RESET(demon_sound)

55
src/mame/audio/senjyo.c
View File

@ -13,46 +13,25 @@
static INT16 *_single;
static int single_rate = 1000;
static int single_volume = 0;
static const device_config *z80pio;
static void senjyo_z80pio_reset(int which)
const z80_daisy_chain senjyo_daisy_chain[] =
{
z80pio_reset( z80pio );
}
static int senjyo_z80pio_irq_state(int which)
{
return z80pio_irq_state( z80pio );
}
static int senjyo_z80pio_irq_ack(int which)
{
return z80pio_irq_ack( z80pio );
}
static void senjyo_z80pio_irq_reti(int which)
{
z80pio_irq_reti( z80pio );
}
const struct z80_irq_daisy_chain senjyo_daisy_chain[] =
{
{ z80ctc_reset, z80ctc_irq_state, z80ctc_irq_ack, z80ctc_irq_reti , 0 }, /* device 0 = CTC_0 , high priority */
{ senjyo_z80pio_reset, senjyo_z80pio_irq_state, senjyo_z80pio_irq_ack, senjyo_z80pio_irq_reti , 0 }, /* device 1 = PIO_0 , low priority */
{ 0,0,0,0,-1} /* end mark */
{ Z80CTC, "z80ctc" },
{ Z80PIO, "z80pio" },
{ NULL }
};
/* z80 pio */
static void pio_interrupt(running_machine *machine, int state)
static void daisy_interrupt(const device_config *device, int state)
{
cpunum_set_input_line(machine, 1, 0, state);
cputag_set_input_line(device->machine, "sub", 0, state);
}
const z80pio_interface senjyo_pio_intf =
{
pio_interrupt,
daisy_interrupt,
NULL,
NULL,
NULL,
@ -62,17 +41,13 @@ const z80pio_interface senjyo_pio_intf =
};
/* z80 ctc */
static void ctc_interrupt (running_machine *machine, int state)
{
cpunum_set_input_line(machine, 1, 0, state);
}
static z80ctc_interface ctc_intf =
const z80ctc_interface senjyo_ctc_intf =
{
"sub", /* clock from sub CPU */
0, /* clock (filled in from the CPU 0 clock */
NOTIMER_2, /* timer disables */
ctc_interrupt, /* interrupt handler */
z80ctc_0_trg1_w, /* ZC/TO0 callback */
daisy_interrupt, /* interrupt handler */
z80ctc_trg1_w, /* ZC/TO0 callback */
0, /* ZC/TO1 callback */
0 /* ZC/TO2 callback */
};
@ -88,7 +63,7 @@ WRITE8_HANDLER( senjyo_volume_w )
static TIMER_CALLBACK( senjyo_sh_update )
{
/* ctc2 timer single tone generator frequency */
attotime period = z80ctc_getperiod (0, 2);
attotime period = z80ctc_getperiod (devtag_get_device(machine, Z80CTC, "z80ctc"), 2);
if (attotime_compare(period, attotime_zero) != 0 )
single_rate = ATTOSECONDS_TO_HZ(period.attoseconds);
else
@ -102,12 +77,6 @@ void senjyo_sh_start(void)
{
int i;
/* z80 ctc init */
ctc_intf.baseclock = cpunum_get_clock(1);
z80ctc_init (0, &ctc_intf);
z80pio = device_list_find_by_tag( Machine->config->devicelist, Z80PIO, "z80pio" );
_single = (INT16 *)auto_malloc(SINGLE_LENGTH*2);
for (i = 0;i < SINGLE_LENGTH;i++) /* freq = ctc2 zco / 8 */

28
src/mame/drivers/astrocde.c
View File

@ -490,14 +490,15 @@ static WRITE8_HANDLER( demndrgn_sound_w )
*
*************************************/
static void ctc_interrupt(running_machine *machine, int state)
static void ctc_interrupt(const device_config *device, int state)
{
cpunum_set_input_line(machine, 1, 0, state);
cputag_set_input_line(device->machine, "sub", 0, state);
}
static z80ctc_interface ctc_intf =
{
"sub", /* clock comes from sub CPU */
0, /* clock (filled in from the CPU 0 clock) */
0, /* timer disables */
ctc_interrupt, /* interrupt handler */
@ -518,19 +519,10 @@ static const ay8910_interface ay8912_interface =
};
static MACHINE_START( tenpindx )
{
/* initialize the CTC */
ctc_intf.baseclock = cpunum_get_clock(0);
z80ctc_init(0, &ctc_intf);
MACHINE_START_CALL(astrocde);
}
static WRITE8_HANDLER( tenpindx_sound_w )
{
soundlatch_w(machine, offset, data);
cpunum_set_input_line(machine, 1, INPUT_LINE_NMI, PULSE_LINE);
cputag_set_input_line(machine, "sub", INPUT_LINE_NMI, PULSE_LINE);
}
@ -714,7 +706,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( tenpin_sub_io_map, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x90, 0x93) AM_READWRITE(z80ctc_0_r, z80ctc_0_w)
AM_RANGE(0x90, 0x93) AM_DEVREADWRITE(Z80CTC, "ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x97, 0x97) AM_READ(soundlatch_r)
AM_RANGE(0x98, 0x98) AM_WRITE(ay8910_control_port_0_w)
AM_RANGE(0x98, 0x98) AM_READ(ay8910_read_port_0_r)
@ -1243,10 +1235,10 @@ static const samples_interface gorf_samples_interface =
*
*************************************/
static const struct z80_irq_daisy_chain tenpin_daisy_chain[] =
static const z80_daisy_chain tenpin_daisy_chain[] =
{
{ z80ctc_reset, z80ctc_irq_state, z80ctc_irq_ack, z80ctc_irq_reti, 0 }, /* CTC number 0 */
{ 0, 0, 0, 0, -1 } /* end mark */
{ Z80CTC, "ctc" },
{ NULL }
};
@ -1469,8 +1461,8 @@ static MACHINE_DRIVER_START( tenpindx )
MDRV_CPU_CONFIG(tenpin_daisy_chain)
MDRV_CPU_PROGRAM_MAP(tenpin_sub_map,0)
MDRV_CPU_IO_MAP(tenpin_sub_io_map,0)
MDRV_MACHINE_START(tenpindx)
MDRV_Z80CTC_ADD("ctc", ctc_intf)
/* sound hardware */
MDRV_SPEAKER_STANDARD_MONO("mono")

15
src/mame/drivers/cchasm.c
View File

@ -54,7 +54,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_portmap, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_READWRITE(z80ctc_0_r,z80ctc_0_w)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE(Z80CTC, "ctc", z80ctc_r, z80ctc_w)
ADDRESS_MAP_END
static void cchasm_6840_irq(running_machine *machine, int state)
@ -134,10 +134,10 @@ static MACHINE_START( cchasm )
*
*************************************/
static const struct z80_irq_daisy_chain daisy_chain[] =
static const z80_daisy_chain daisy_chain[] =
{
{ z80ctc_reset, z80ctc_irq_state, z80ctc_irq_ack, z80ctc_irq_reti, 0 }, /* CTC number 0 */
{ 0,0,0,0,-1 } /* end mark */
{ Z80CTC, "ctc" },
{ NULL }
};
@ -148,9 +148,10 @@ static const struct z80_irq_daisy_chain daisy_chain[] =
*
*************************************/
extern z80ctc_interface cchasm_ctc_intf;
static MACHINE_DRIVER_START( cchasm )
MDRV_MACHINE_START(cchasm)
/* basic machine hardware */
MDRV_CPU_ADD("main", M68000,CCHASM_68K_CLOCK) /* 8 MHz (from schematics) */
MDRV_CPU_PROGRAM_MAP(memmap,0)
@ -160,6 +161,10 @@ static MACHINE_DRIVER_START( cchasm )
MDRV_CPU_PROGRAM_MAP(sound_memmap,0)
MDRV_CPU_IO_MAP(sound_portmap,0)
MDRV_Z80CTC_ADD("ctc", cchasm_ctc_intf)
MDRV_MACHINE_START(cchasm)
/* video hardware */
MDRV_SCREEN_ADD("main", VECTOR)
MDRV_SCREEN_REFRESH_RATE(40)

28
src/mame/drivers/dlair.c
View File

@ -82,9 +82,9 @@ static const UINT8 led_map[16] =
*
*************************************/
static void dleuro_interrupt(running_machine *machine, int state)
static void dleuro_interrupt(const device_config *device, int state)
{
cpunum_set_input_line(machine, 0, 0, state);
cpunum_set_input_line(device->machine, 0, 0, state);
}
@ -106,7 +106,8 @@ static int serial_receive(int ch)
static z80ctc_interface ctc_intf =
{
0, /* clock (filled in from the CPU 0 clock) */
"main", /* clock comes from main CPU's clock */
0, /* clock (filled in from the CPU clock) */
0, /* timer disables */
dleuro_interrupt, /* interrupt handler */
0, /* ZC/TO0 callback */
@ -118,7 +119,7 @@ static z80ctc_interface ctc_intf =
static z80sio_interface sio_intf =
{
0, /* clock (filled in from the CPU 3 clock) */
dleuro_interrupt, /* interrupt handler */
0,// dleuro_interrupt, /* interrupt handler */
0, /* DTR changed handler */
0, /* RTS changed handler */
0, /* BREAK changed handler */
@ -127,11 +128,11 @@ static z80sio_interface sio_intf =
};
static const struct z80_irq_daisy_chain dleuro_daisy_chain[] =
static const z80_daisy_chain dleuro_daisy_chain[] =
{
{ z80sio_reset, z80sio_irq_state, z80sio_irq_ack, z80sio_irq_reti, 0 },
{ z80ctc_reset, z80ctc_irq_state, z80ctc_irq_ack, z80ctc_irq_reti, 0 },
{ 0, 0, 0, 0, -1 } /* end mark */
// { Z80SIO, "sio" },
{ Z80CTC, "ctc" },
{ NULL }
};
@ -195,9 +196,7 @@ static MACHINE_START( dleuro )
laserdisc = device_list_find_by_tag(machine->config->devicelist, LASERDISC, "laserdisc");
/* initialize the CTC and SIO peripherals */
ctc_intf.baseclock = cpunum_get_clock(0);
sio_intf.baseclock = cpunum_get_clock(0);
z80ctc_init(0, &ctc_intf);
z80sio_init(0, &sio_intf);
}
@ -225,8 +224,9 @@ static INTERRUPT_GEN( vblank_callback )
/* also update the speaker on the European version */
if (sndti_exists(SOUND_BEEP, 0))
{
const device_config *ctc = devtag_get_device(machine, Z80CTC, "ctc");
beep_set_state(0, 1);
beep_set_frequency(0, ATTOSECONDS_TO_HZ(z80ctc_getperiod(0, 0).attoseconds));
beep_set_frequency(0, ATTOSECONDS_TO_HZ(z80ctc_getperiod(ctc, 0).attoseconds));
}
}
@ -431,7 +431,7 @@ ADDRESS_MAP_END
/* complete memory map derived from schematics */
static ADDRESS_MAP_START( dleuro_io_map, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_MIRROR(0x7c) AM_READWRITE(z80ctc_0_r, z80ctc_0_w)
AM_RANGE(0x00, 0x03) AM_MIRROR(0x7c) AM_DEVREADWRITE(Z80CTC, "ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x80, 0x83) AM_MIRROR(0x7c) AM_READWRITE(sio_r, sio_w)
ADDRESS_MAP_END
@ -710,7 +710,7 @@ static MACHINE_DRIVER_START( dlair_base )
MDRV_CPU_PROGRAM_MAP(dlus_map,0)
MDRV_CPU_VBLANK_INT("main", vblank_callback)
MDRV_CPU_PERIODIC_INT(irq0_line_hold, (double)MASTER_CLOCK_US/8/16/16/16/16)
MDRV_MACHINE_START(dlair)
MDRV_MACHINE_RESET(dlair)
@ -752,6 +752,8 @@ static MACHINE_DRIVER_START( dleuro )
MDRV_CPU_IO_MAP(dleuro_io_map,0)
MDRV_CPU_VBLANK_INT("main", vblank_callback)
MDRV_Z80CTC_ADD("ctc", ctc_intf)
MDRV_WATCHDOG_TIME_INIT(UINT64_ATTOTIME_IN_HZ(MASTER_CLOCK_EURO/(16*16*16*16*16*8)))
MDRV_MACHINE_START(dleuro)

19
src/mame/drivers/mcr.c
View File

@ -624,7 +624,7 @@ static ADDRESS_MAP_START( cpu_90009_portmap, ADDRESS_SPACE_IO, 8 )
SSIO_INPUT_PORTS
AM_RANGE(0xe0, 0xe0) AM_WRITE(watchdog_reset_w)
AM_RANGE(0xe8, 0xe8) AM_WRITE(SMH_NOP)
AM_RANGE(0xf0, 0xf3) AM_READWRITE(z80ctc_0_r, z80ctc_0_w)
AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE(Z80CTC, "ctc", z80ctc_r, z80ctc_w)
ADDRESS_MAP_END
@ -651,7 +651,7 @@ static ADDRESS_MAP_START( cpu_90010_portmap, ADDRESS_SPACE_IO, 8 )
SSIO_INPUT_PORTS
AM_RANGE(0xe0, 0xe0) AM_WRITE(watchdog_reset_w)
AM_RANGE(0xe8, 0xe8) AM_WRITE(SMH_NOP)
AM_RANGE(0xf0, 0xf3) AM_READWRITE(z80ctc_0_r, z80ctc_0_w)
AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE(Z80CTC, "ctc", z80ctc_r, z80ctc_w)
ADDRESS_MAP_END
@ -679,7 +679,7 @@ static ADDRESS_MAP_START( cpu_91490_portmap, ADDRESS_SPACE_IO, 8 )
SSIO_INPUT_PORTS
AM_RANGE(0xe0, 0xe0) AM_WRITE(watchdog_reset_w)
AM_RANGE(0xe8, 0xe8) AM_WRITE(SMH_NOP)
AM_RANGE(0xf0, 0xf3) AM_READWRITE(z80ctc_0_r, z80ctc_0_w)
AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE(Z80CTC, "ctc", z80ctc_r, z80ctc_w)
ADDRESS_MAP_END
@ -701,10 +701,10 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( ipu_91695_portmap, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_UNMAP_HIGH
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_MIRROR(0xe0) AM_DEVREADWRITE(Z80PIO, "z80pio_0", z80pio_r,z80pio_w)
AM_RANGE(0x00, 0x03) AM_MIRROR(0xe0) AM_DEVREADWRITE(Z80PIO, "ipu_pio0", z80pio_r,z80pio_w)
AM_RANGE(0x04, 0x07) AM_MIRROR(0xe0) AM_READWRITE(mcr_ipu_sio_r, mcr_ipu_sio_w)
AM_RANGE(0x08, 0x0b) AM_MIRROR(0xe0) AM_READWRITE(z80ctc_1_r, z80ctc_1_w)
AM_RANGE(0x0c, 0x0f) AM_MIRROR(0xe0) AM_DEVREADWRITE(Z80PIO, "z80pio_1", z80pio_r, z80pio_w)
AM_RANGE(0x08, 0x0b) AM_MIRROR(0xe0) AM_DEVREADWRITE(Z80CTC, "ipu_ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x0c, 0x0f) AM_MIRROR(0xe0) AM_DEVREADWRITE(Z80PIO, "ipu_pio1", z80pio_r, z80pio_w)
AM_RANGE(0x10, 0x13) AM_MIRROR(0xe0) AM_WRITE(mcr_ipu_laserdisk_w)
AM_RANGE(0x1c, 0x1f) AM_MIRROR(0xe0) AM_READWRITE(mcr_ipu_watchdog_r, mcr_ipu_watchdog_w)
ADDRESS_MAP_END
@ -1514,6 +1514,8 @@ static MACHINE_DRIVER_START( mcr_90009 )
MDRV_CPU_IO_MAP(cpu_90009_portmap,0)
MDRV_CPU_VBLANK_INT_HACK(mcr_interrupt,2)
MDRV_Z80CTC_ADD("ctc", mcr_ctc_intf)
MDRV_WATCHDOG_VBLANK_INIT(16)
MDRV_MACHINE_START(mcr)
MDRV_MACHINE_RESET(mcr)
@ -1602,8 +1604,9 @@ static MACHINE_DRIVER_START( mcr_91490_ipu )
MDRV_CPU_IO_MAP(ipu_91695_portmap,0)
MDRV_CPU_VBLANK_INT_HACK(mcr_ipu_interrupt,2)
MDRV_Z80PIO_ADD( "z80pio_0", nflfoot_pio_intf )
MDRV_Z80PIO_ADD( "z80pio_1", nflfoot_pio_intf )
MDRV_Z80CTC_ADD("ipu_ctc", nflfoot_ctc_intf)
MDRV_Z80PIO_ADD("ipu_pio0", nflfoot_pio_intf)
MDRV_Z80PIO_ADD("ipu_pio1", nflfoot_pio_intf)
MACHINE_DRIVER_END

6
src/mame/drivers/mcr3.c
View File

@ -470,7 +470,7 @@ static ADDRESS_MAP_START( mcrmono_portmap, ADDRESS_SPACE_IO, 8 )
AM_RANGE(0x04, 0x04) AM_MIRROR(0x78) AM_READ_PORT("MONO.IP4")
AM_RANGE(0x05, 0x05) AM_MIRROR(0x78) AM_WRITE(mcrmono_control_port_w)
AM_RANGE(0x07, 0x07) AM_MIRROR(0x78) AM_WRITE(watchdog_reset_w)
AM_RANGE(0xf0, 0xf3) AM_MIRROR(0x0c) AM_READWRITE(z80ctc_0_r, z80ctc_0_w)
AM_RANGE(0xf0, 0xf3) AM_MIRROR(0x0c) AM_DEVREADWRITE(Z80CTC, "ctc", z80ctc_r, z80ctc_w)
ADDRESS_MAP_END
@ -500,7 +500,7 @@ static ADDRESS_MAP_START( spyhunt_portmap, ADDRESS_SPACE_IO, 8 )
AM_RANGE(0x84, 0x86) AM_WRITE(mcr_scroll_value_w)
AM_RANGE(0xe0, 0xe0) AM_WRITE(watchdog_reset_w)
AM_RANGE(0xe8, 0xe8) AM_WRITE(SMH_NOP)
AM_RANGE(0xf0, 0xf3) AM_READWRITE(z80ctc_0_r, z80ctc_0_w)
AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE(Z80CTC, "ctc", z80ctc_r, z80ctc_w)
ADDRESS_MAP_END
@ -1055,6 +1055,8 @@ static MACHINE_DRIVER_START( mcr3_base )
MDRV_CPU_ADD("main", Z80, MASTER_CLOCK/4)
MDRV_CPU_CONFIG(mcr_daisy_chain)
MDRV_CPU_VBLANK_INT_HACK(mcr_interrupt,2)
MDRV_Z80CTC_ADD("ctc", mcr_ctc_intf)
MDRV_WATCHDOG_VBLANK_INIT(16)
MDRV_MACHINE_START(mcr)

40
src/mame/drivers/meritm.c
View File

@ -747,16 +747,16 @@ static const ay8910_interface ay8910_config =
*
*************************************/
static void meritm_audio_pio_interrupt(running_machine *machine, int state)
static void meritm_audio_pio_interrupt(const device_config *device, int state)
{
//logerror( "PIO(0) interrupt line: %d, V = %d, H = %d\n", state, video_screen_get_vpos(0), video_screen_get_hpos(0) );
cpunum_set_input_line(machine, 0, 0, state);
cpunum_set_input_line(device->machine, 0, 0, state);
}
static void meritm_io_pio_interrupt(running_machine *machine, int state)
static void meritm_io_pio_interrupt(const device_config *device, int state)
{
//logerror( "PIO(1) interrupt line: %d, V = %d, H = %d\n", state, video_screen_get_vpos(0), video_screen_get_hpos(0) );
cpunum_set_input_line(machine, 0, 0, state);
cpunum_set_input_line(device->machine, 0, 0, state);
}
@ -828,37 +828,17 @@ static void meritm_pio1_portb_input_changed_callback(void *param, UINT32 oldval,
}
#endif
static void meritm_z80pio_reset(int which)
static const z80_daisy_chain meritm_daisy_chain[] =
{
z80pio_reset( meritm_z80pio[which] );
}
static int meritm_z80pio_irq_state(int which)
{
return z80pio_irq_state( meritm_z80pio[which] );
}
static int meritm_z80pio_irq_ack(int which)
{
return z80pio_irq_ack( meritm_z80pio[which] );
}
static void meritm_z80pio_irq_reti(int which)
{
z80pio_irq_reti( meritm_z80pio[which] );
}
static const struct z80_irq_daisy_chain meritm_daisy_chain[] =
{
{ meritm_z80pio_reset, meritm_z80pio_irq_state, meritm_z80pio_irq_ack, meritm_z80pio_irq_reti, 1 }, /* PIO number 1 */
{ meritm_z80pio_reset, meritm_z80pio_irq_state, meritm_z80pio_irq_ack, meritm_z80pio_irq_reti, 0 }, /* PIO number 0 */
{ 0, 0, 0, 0, -1 } /* end mark */
{ Z80PIO, "z80pio_1" },
{ Z80PIO, "z80pio_0" },
{ NULL }
};
static MACHINE_START(merit_common)
{
meritm_z80pio[0] = device_list_find_by_tag( machine->config->devicelist, Z80PIO, "z80pio_0" );
meritm_z80pio[1] = device_list_find_by_tag( machine->config->devicelist, Z80PIO, "z80pio_1" );
meritm_z80pio[0] = devtag_get_device( machine, Z80PIO, "z80pio_0" );
meritm_z80pio[1] = devtag_get_device( machine, Z80PIO, "z80pio_1" );
//input_port_set_changed_callback(port_tag_to_index("PIO1_PORTB"), 0xff, meritm_pio1_portb_input_changed_callback, NULL);
};

150
src/mame/drivers/nbmj9195.c
View File

@ -489,25 +489,27 @@ static WRITE8_HANDLER( tmpz84c011_1_dir_pd_w ) { pio_dir[8] = data; }
static WRITE8_HANDLER( tmpz84c011_1_dir_pe_w ) { pio_dir[9] = data; }
static void ctc0_interrupt(running_machine *machine, int state)
static void ctc0_interrupt(const device_config *device, int state)
{
cpunum_set_input_line(machine, 0, 0, state);
cpunum_set_input_line(device->machine, 0, 0, state);
}
static void ctc1_interrupt(running_machine *machine, int state)
static void ctc1_interrupt(const device_config *device, int state)
{
cpunum_set_input_line(machine, 1, 0, state);
cpunum_set_input_line(device->machine, 1, 0, state);
}
/* CTC of main cpu, ch0 trigger is vblank */
static INTERRUPT_GEN( ctc0_trg1 )
{
z80ctc_0_trg1_w(machine, 0, 1);
z80ctc_0_trg1_w(machine, 0, 0);
const device_config *ctc = devtag_get_device(machine, Z80CTC, "main_ctc");
z80ctc_trg1_w(ctc, 0, 1);
z80ctc_trg1_w(ctc, 0, 0);
}
static z80ctc_interface ctc_intf_1 =
static z80ctc_interface ctc_intf_main =
{
"main", /* clock from main CPU */
0, /* clock */
0, /* timer disables */
ctc0_interrupt, /* interrupt handler */
@ -516,25 +518,17 @@ static z80ctc_interface ctc_intf_1 =
0, /* ZC/TO2 callback */
};
static z80ctc_interface ctc_intf_2 =
static z80ctc_interface ctc_intf_audio =
{
1, /* clock */
"audio", /* clock from audio CPU */
0, /* clock */
0, /* timer disables */
ctc1_interrupt, /* interrupt handler */
z80ctc_1_trg3_w, /* ZC/TO0 callback ctc1.zc0 -> ctc1.trg3 */
z80ctc_trg3_w, /* ZC/TO0 callback ctc1.zc0 -> ctc1.trg3 */
0, /* ZC/TO1 callback */
0 /* ZC/TO2 callback */
};
static void tmpz84c011_init(running_machine *machine)
{
// initialize the CTC
ctc_intf_1.baseclock = cpunum_get_clock(0);
ctc_intf_2.baseclock = cpunum_get_clock(1);
z80ctc_init(0, &ctc_intf_1);
z80ctc_init(1, &ctc_intf_2);
}
static MACHINE_RESET( sailorws )
{
int i;
@ -554,9 +548,6 @@ static DRIVER_INIT( nbmj9195 )
// sound program patch
ROM[0x0213] = 0x00; // DI -> NOP
// initialize TMPZ84C011 PIO and CTC
tmpz84c011_init(machine);
// initialize sound rom bank
nbmj9195_soundbank_w(machine, 0);
}
@ -656,7 +647,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_mjuraden, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -673,7 +664,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_mjuraden, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -698,7 +689,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_koinomp, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -716,7 +707,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_koinomp, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -744,7 +735,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_patimono, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -762,7 +753,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_patimono, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -789,7 +780,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_mmehyou, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -806,7 +797,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_mmehyou, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -831,7 +822,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_gal10ren, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -849,7 +840,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_gal10ren, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -876,7 +867,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_renaiclb, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -894,7 +885,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_renaiclb, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -921,7 +912,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_mjlaman, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -939,7 +930,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_mjlaman, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -966,7 +957,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_mkeibaou, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -984,7 +975,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_mkeibaou, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1011,7 +1002,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_pachiten, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1029,7 +1020,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_pachiten, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1056,7 +1047,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_sailorws, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1074,7 +1065,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_sailorws, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1101,7 +1092,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_sailorwr, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1119,7 +1110,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_sailorwr, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1146,7 +1137,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_psailor1, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1164,7 +1155,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_psailor1, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1191,7 +1182,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_psailor2, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1209,7 +1200,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_psailor2, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1236,7 +1227,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_otatidai, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1254,7 +1245,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_otatidai, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1281,7 +1272,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_yosimoto, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1299,7 +1290,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_yosimoto, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1326,7 +1317,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_jituroku, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1344,7 +1335,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_jituroku, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1371,7 +1362,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_ngpgal, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1388,7 +1379,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_ngpgal, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1413,7 +1404,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_mjgottsu, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1430,7 +1421,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_mjgottsu, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1455,7 +1446,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_cmehyou, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1472,7 +1463,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_cmehyou, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1497,7 +1488,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_mjkoiura, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1514,7 +1505,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_mjkoiura, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1539,7 +1530,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_mkoiuraa, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1556,7 +1547,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_mkoiuraa, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1581,7 +1572,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_mscoutm, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1602,7 +1593,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_mscoutm, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1628,7 +1619,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_imekura, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1649,7 +1640,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_imekura, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1675,7 +1666,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( readport_mjegolf, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_0_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "main_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_0_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_0_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_0_pc_r)
@ -1696,7 +1687,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( writeport_mjegolf, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "main_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_0_pc_w)
@ -1722,7 +1713,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_readport, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READ(z80ctc_1_r)
AM_RANGE(0x10, 0x13) AM_DEVREAD(Z80CTC, "audio_ctc", z80ctc_r)
AM_RANGE(0x50, 0x50) AM_READ(tmpz84c011_1_pa_r)
AM_RANGE(0x51, 0x51) AM_READ(tmpz84c011_1_pb_r)
AM_RANGE(0x52, 0x52) AM_READ(tmpz84c011_1_pc_r)
@ -1737,7 +1728,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_writeport, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_WRITE(z80ctc_1_w)
AM_RANGE(0x10, 0x13) AM_DEVWRITE(Z80CTC, "audio_ctc", z80ctc_w)
AM_RANGE(0x50, 0x50) AM_WRITE(tmpz84c011_1_pa_w)
AM_RANGE(0x51, 0x51) AM_WRITE(tmpz84c011_1_pb_w)
AM_RANGE(0x52, 0x52) AM_WRITE(tmpz84c011_1_pc_w)
@ -3639,16 +3630,16 @@ static INPUT_PORTS_START( mjegolf )
INPUT_PORTS_END
static const struct z80_irq_daisy_chain daisy_chain_main[] =
static const z80_daisy_chain daisy_chain_main[] =
{
{ z80ctc_reset, z80ctc_irq_state, z80ctc_irq_ack, z80ctc_irq_reti, 0 }, /* device 0 = CTC_0 */
{ 0, 0, 0, 0, -1 } /* end mark */
{ Z80CTC, "main_ctc" },
{ NULL }
};
static const struct z80_irq_daisy_chain daisy_chain_sound[] =
static const z80_daisy_chain daisy_chain_sound[] =
{
{ z80ctc_reset, z80ctc_irq_state, z80ctc_irq_ack, z80ctc_irq_reti, 1 }, /* device 0 = CTC_1 */
{ 0, 0, 0, 0, -1 } /* end mark */
{ Z80CTC, "audio_ctc" },
{ NULL }
};
@ -3665,6 +3656,9 @@ static MACHINE_DRIVER_START( NBMJDRV1 )
MDRV_CPU_CONFIG(daisy_chain_sound)
MDRV_CPU_PROGRAM_MAP(sound_readmem, sound_writemem)
MDRV_CPU_IO_MAP(sound_readport, sound_writeport)
MDRV_Z80CTC_ADD("main_ctc", ctc_intf_main)
MDRV_Z80CTC_ADD("audio_ctc", ctc_intf_audio)
MDRV_MACHINE_RESET(sailorws)

29
src/mame/drivers/niyanpai.c
View File

@ -184,28 +184,22 @@ static WRITE8_HANDLER( tmpz84c011_0_dir_pd_w ) { pio_dir[3] = data; }
static WRITE8_HANDLER( tmpz84c011_0_dir_pe_w ) { pio_dir[4] = data; }
static void ctc0_interrupt(running_machine *machine, int state)
static void ctc0_interrupt(const device_config *device, int state)
{
cpunum_set_input_line(machine, 1, 0, state);
cputag_set_input_line(device->machine, "audio", 0, state);
}
static z80ctc_interface ctc_intf =
{
1, /* clock */
"audio", /* clock from the audio CPU */
0, /* clock */
0, /* timer disables */
ctc0_interrupt, /* interrupt handler */
z80ctc_0_trg3_w, /* ZC/TO0 callback ctc1.zc0 -> ctc1.trg3 */
z80ctc_trg3_w, /* ZC/TO0 callback ctc1.zc0 -> ctc1.trg3 */
0, /* ZC/TO1 callback */
0, /* ZC/TO2 callback */
};
static void tmpz84c011_init(running_machine *machine)
{
// initialize the CTC
ctc_intf.baseclock = cpunum_get_clock(1);
z80ctc_init(0, &ctc_intf);
}
static MACHINE_RESET( niyanpai )
{
int i;
@ -232,9 +226,6 @@ static DRIVER_INIT( niyanpai )
// sound program patch
SNDROM[0x0213] = 0x00; // DI -> NOP
// initialize TMPZ84C011 PIO and CTC
tmpz84c011_init(machine);
// initialize sound rom bank
niyanpai_soundbank_w(machine, 0);
@ -494,7 +485,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_io_map, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_READWRITE(z80ctc_0_r, z80ctc_0_w)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE(Z80CTC, "ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w)
@ -866,10 +857,10 @@ static INTERRUPT_GEN( niyanpai_interrupt )
cpunum_set_input_line(machine, 0, 1, HOLD_LINE);
}
static const struct z80_irq_daisy_chain daisy_chain_sound[] =
static const z80_daisy_chain daisy_chain_sound[] =
{
{ z80ctc_reset, z80ctc_irq_state, z80ctc_irq_ack, z80ctc_irq_reti, 0 }, /* device 0 = CTC_1 */
{ 0, 0, 0, 0, -1 } /* end mark */
{ Z80CTC, "ctc" },
{ NULL }
};
@ -884,6 +875,8 @@ static MACHINE_DRIVER_START( niyanpai )
MDRV_CPU_CONFIG(daisy_chain_sound)
MDRV_CPU_PROGRAM_MAP(sound_readmem, sound_writemem)
MDRV_CPU_IO_MAP(sound_io_map,0)
MDRV_Z80CTC_ADD("ctc", ctc_intf)
MDRV_MACHINE_RESET(niyanpai)
MDRV_NVRAM_HANDLER(generic_0fill)

27
src/mame/drivers/pipeline.c
View File

@ -232,7 +232,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_port, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_READ(z80ctc_0_r) AM_WRITE(z80ctc_0_w)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE(Z80CTC, "ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x06, 0x07) AM_NOP
ADDRESS_MAP_END
@ -285,14 +285,15 @@ static GFXDECODE_START( pipeline )
GFXDECODE_ENTRY( "gfx2", 0, layout_8x8x3, 0x100, 32 ) // 3bpp tiles
GFXDECODE_END
static void ctc0_interrupt(running_machine *machine, int state)
static void ctc0_interrupt(const device_config *device, int state)
{
cpunum_set_input_line(machine, 1, 0, state);
cputag_set_input_line(device->machine, "audio", 0, state);
}
static z80ctc_interface ctc_intf =
static const z80ctc_interface ctc_intf =
{
1, // clock
"audio", // clock from audio CPU
0, // clock
0, // timer disables
ctc0_interrupt, // interrupt handler
0, // ZC/TO0 callback
@ -300,10 +301,10 @@ static z80ctc_interface ctc_intf =
0, // ZC/TO2 callback
};
static const struct z80_irq_daisy_chain daisy_chain_sound[] =
static const z80_daisy_chain daisy_chain_sound[] =
{
{ z80ctc_reset, z80ctc_irq_state, z80ctc_irq_ack, z80ctc_irq_reti, 0 }, /* device 0 = CTC_1 */
{ 0, 0, 0, 0, -1 } /* end mark */
{ Z80CTC, "ctc" },
{ NULL }
};
static const ppi8255_interface ppi8255_intf[3] =
@ -363,12 +364,6 @@ static PALETTE_INIT(pipeline)
}
}
static MACHINE_RESET( pipeline )
{
ctc_intf.baseclock = cpunum_get_clock(0);
z80ctc_init(0, &ctc_intf);
}
static MACHINE_DRIVER_START( pipeline )
/* basic machine hardware */
@ -383,6 +378,8 @@ static MACHINE_DRIVER_START( pipeline )
MDRV_CPU_ADD("mcu", M68705, 7372800/2)
MDRV_CPU_PROGRAM_MAP(mcu_mem, 0)
MDRV_Z80CTC_ADD( "ctc", ctc_intf )
MDRV_DEVICE_ADD( "ppi8255_0", PPI8255 )
MDRV_DEVICE_CONFIG( ppi8255_intf[0] )
@ -403,8 +400,6 @@ static MACHINE_DRIVER_START( pipeline )
MDRV_GFXDECODE(pipeline)
MDRV_MACHINE_RESET(pipeline)
MDRV_PALETTE_INIT(pipeline)
MDRV_PALETTE_LENGTH(0x100+0x100)

6
src/mame/drivers/senjyo.c
View File

@ -98,7 +98,7 @@ VIDEO_UPDATE( senjyo );
extern int is_senjyo, senjyo_scrollhack;
/* in audio/senjyo.c */
extern const struct z80_irq_daisy_chain senjyo_daisy_chain[];
extern const z80_daisy_chain senjyo_daisy_chain[];
extern const z80pio_interface senjyo_pio_intf;
void senjyo_sh_start(void);
@ -300,7 +300,7 @@ static READ8_DEVICE_HANDLER( pio_r )
static ADDRESS_MAP_START( sound_io_map, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE(Z80PIO, "z80pio", pio_r, pio_w)
AM_RANGE(0x08, 0x0b) AM_READWRITE(z80ctc_0_r, z80ctc_0_w)
AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE(Z80CTC, "z80ctc", z80ctc_r, z80ctc_w)
ADDRESS_MAP_END
@ -623,6 +623,7 @@ static const samples_interface senjyo_samples_interface =
};
extern const z80ctc_interface senjyo_ctc_intf;
static MACHINE_DRIVER_START( senjyo )
@ -639,6 +640,7 @@ static MACHINE_DRIVER_START( senjyo )
MDRV_MACHINE_RESET(senjyo)
MDRV_Z80PIO_ADD( "z80pio", senjyo_pio_intf )
MDRV_Z80CTC_ADD( "z80ctc", senjyo_ctc_intf )
/* video hardware */
MDRV_SCREEN_ADD("main", RASTER)

6
src/mame/includes/mcr.h
View File

@ -21,8 +21,10 @@ WRITE8_HANDLER( mcr_ipu_sio_transmit );
extern attotime mcr68_timing_factor;
extern const struct z80_irq_daisy_chain mcr_daisy_chain[];
extern const struct z80_irq_daisy_chain mcr_ipu_daisy_chain[];
extern const z80_daisy_chain mcr_daisy_chain[];
extern const z80_daisy_chain mcr_ipu_daisy_chain[];
extern const z80ctc_interface mcr_ctc_intf;
extern const z80ctc_interface nflfoot_ctc_intf;
extern const z80pio_interface nflfoot_pio_intf;
extern UINT8 mcr_cocktail_flip;

96
src/mame/machine/mcr.c
View File

@ -71,8 +71,6 @@ static attotime m6840_internal_counter_period; /* 68000 CLK / 10 */
static emu_timer *ipu_watchdog_timer;
static const device_config *nflfoot_z80pio[2];
/*************************************
*
@ -189,68 +187,50 @@ static const pia6821_interface zwackery_pia_4_intf =
*
*************************************/
static void ctc_interrupt(running_machine *machine, int state)
static void ctc_interrupt(const device_config *device, int state)
{
cpunum_set_input_line(machine, 0, 0, state);
cputag_set_input_line(device->machine, "main", 0, state);
}
static void ipu_ctc_interrupt(running_machine *machine, int state)
static void ipu_ctc_interrupt(const device_config *device, int state)
{
cpunum_set_input_line(machine, 3, 0, state);
cputag_set_input_line(device->machine, "ipu", 0, state);
}
const struct z80_irq_daisy_chain mcr_daisy_chain[] =
const z80_daisy_chain mcr_daisy_chain[] =
{
{ z80ctc_reset, z80ctc_irq_state, z80ctc_irq_ack, z80ctc_irq_reti, 0 }, /* CTC number 0 */
{ 0, 0, 0, 0, -1 } /* end mark */
{ Z80CTC, "ctc" },
{ NULL }
};
static void nflfoot_z80pio_reset(int which)
const z80_daisy_chain mcr_ipu_daisy_chain[] =
{
z80pio_reset( nflfoot_z80pio[which] );
}
static int nflfoot_z80pio_irq_state(int which)
{
return z80pio_irq_state( nflfoot_z80pio[which] );
}
static int nflfoot_z80pio_irq_ack(int which)
{
return z80pio_irq_ack( nflfoot_z80pio[which] );
}
static void nflfoot_z80pio_irq_reti(int which)
{
z80pio_irq_reti( nflfoot_z80pio[which] );
}
const struct z80_irq_daisy_chain mcr_ipu_daisy_chain[] =
{
{ z80ctc_reset, z80ctc_irq_state, z80ctc_irq_ack, z80ctc_irq_reti, 1 }, /* CTC number 1 */
{ nflfoot_z80pio_reset, nflfoot_z80pio_irq_state, nflfoot_z80pio_irq_ack, nflfoot_z80pio_irq_reti, 1 }, /* PIO number 1 */
{ z80sio_reset, z80sio_irq_state, z80sio_irq_ack, z80sio_irq_reti, 0 }, /* SIO number 0 */
{ nflfoot_z80pio_reset, nflfoot_z80pio_irq_state, nflfoot_z80pio_irq_ack, nflfoot_z80pio_irq_reti, 0 }, /* PIO number 0 */
{ 0, 0, 0, 0, -1 } /* end mark */
{ Z80CTC, "ipu_ctc" },
{ Z80PIO, "ipt_pio1" },
// { Z80SIO, "ipt_sio" },
{ Z80PIO, "ipt_pio0" },
{ NULL }
};
static z80ctc_interface ctc_intf =
const z80ctc_interface mcr_ctc_intf =
{
"main", /* clock from the main CPU */
0, /* clock (filled in from the CPU 0 clock) */
0, /* timer disables */
ctc_interrupt, /* interrupt handler */
z80ctc_0_trg1_w, /* ZC/TO0 callback */
z80ctc_trg1_w, /* ZC/TO0 callback */
0, /* ZC/TO1 callback */
0 /* ZC/TO2 callback */
};
static z80ctc_interface nflfoot_ctc_intf =
const z80ctc_interface nflfoot_ctc_intf =
{
"ipu", /* clock from the IPU cpu */
0, /* clock (filled in from the CPU 3 clock) */
0, /* timer disables */
ipu_ctc_interrupt, /* interrupt handler */
@ -275,7 +255,7 @@ const z80pio_interface nflfoot_pio_intf =
static z80sio_interface nflfoot_sio_intf =
{
0, /* clock (filled in from the CPU 3 clock) */
ipu_ctc_interrupt, /* interrupt handler */
0,// ipu_ctc_interrupt, /* interrupt handler */
0, /* DTR changed handler */
0, /* RTS changed handler */
ipu_break_changed, /* BREAK changed handler */
@ -292,26 +272,12 @@ static z80sio_interface nflfoot_sio_intf =
MACHINE_START( mcr )
{
/* initialize the CTC */
ctc_intf.baseclock = cpunum_get_clock(0);
z80ctc_init(0, &ctc_intf);
state_save_register_global(mcr_cocktail_flip);
}
MACHINE_START( nflfoot )
{
/* initialize the CTC */
ctc_intf.baseclock = cpunum_get_clock(0);
z80ctc_init(0, &ctc_intf);
nflfoot_ctc_intf.baseclock = cpunum_get_clock(3);
z80ctc_init(1, &nflfoot_ctc_intf);
nflfoot_z80pio[0] = device_list_find_by_tag( machine->config->devicelist, Z80PIO, "z80pio_0" );
nflfoot_z80pio[1] = device_list_find_by_tag( machine->config->devicelist, Z80PIO, "z80pio_1" );
nflfoot_sio_intf.baseclock = cpunum_get_clock(3);
z80sio_init(0, &nflfoot_sio_intf);
@ -447,29 +413,33 @@ MACHINE_RESET( zwackery )
INTERRUPT_GEN( mcr_interrupt )
{
const device_config *ctc = devtag_get_device(machine, Z80CTC, "ctc");
/* CTC line 2 is connected to VBLANK, which is once every 1/2 frame */
/* for the 30Hz interlaced display */
z80ctc_0_trg2_w(machine, 0, 1);
z80ctc_0_trg2_w(machine, 0, 0);
z80ctc_trg2_w(ctc, 0, 1);
z80ctc_trg2_w(ctc, 0, 0);
/* CTC line 3 is connected to 493, which is signalled once every */
/* frame at 30Hz */
if (cpu_getiloops() == 0)
{
z80ctc_0_trg3_w(machine, 0, 1);
z80ctc_0_trg3_w(machine, 0, 0);
z80ctc_trg3_w(ctc, 0, 1);
z80ctc_trg3_w(ctc, 0, 0);
}
}
INTERRUPT_GEN( mcr_ipu_interrupt )
{
const device_config *ctc = devtag_get_device(machine, Z80CTC, "ipu_ctc");
/* CTC line 3 is connected to 493, which is signalled once every */
/* frame at 30Hz */
if (cpu_getiloops() == 0)
{
z80ctc_1_trg3_w(machine, 0, 1);
z80ctc_1_trg3_w(machine, 0, 0);
z80ctc_trg3_w(ctc, 0, 1);
z80ctc_trg3_w(ctc, 0, 0);
}
}
@ -988,10 +958,10 @@ WRITE8_HANDLER( mcr_ipu_laserdisk_w )
static TIMER_CALLBACK( ipu_watchdog_reset )
{
logerror("ipu_watchdog_reset\n");
cpunum_set_input_line(machine, 3, INPUT_LINE_RESET, PULSE_LINE);
z80ctc_reset(1);
z80pio_reset( nflfoot_z80pio[0] );
z80pio_reset( nflfoot_z80pio[1] );
cputag_set_input_line(machine, "ipu", INPUT_LINE_RESET, PULSE_LINE);
devtag_reset(machine, Z80CTC, "ipu_ctc");
devtag_reset(machine, Z80PIO, "ipu_pio0");
devtag_reset(machine, Z80PIO, "ipu_pio1");
z80sio_reset(0);
}