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(mess) pc hardware: cleanup the end-of-dma notifications [O. Galibert]

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This commit is contained in:
Olivier Galibert 2012-09-08 21:27:33 +00:00
parent 417f123e8e
commit f4f21579fe
11 changed files with 137 additions and 54 deletions
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20
src/emu/machine/8237dma.c
View File

@ -127,7 +127,7 @@ void i8237_device::device_start()
void i8237_device::device_reset()
{
m_status = 0x0F;
m_eop = 1;
m_eop = ASSERT_LINE;
m_state = DMA8237_SI;
m_last_service_channel = 3;
m_service_channel = 0;
@ -269,10 +269,10 @@ void i8237_device::i8237_timerproc()
case DMA8237_SI:
{
/* Make sure EOP is high */
if ( !m_eop )
if ( m_eop == CLEAR_LINE )
{
m_eop = 1;
m_out_eop_func(m_eop ? ASSERT_LINE : CLEAR_LINE);
m_eop = ASSERT_LINE;
m_out_eop_func(m_eop);
}
/* Check if a new DMA request has been received. */
@ -363,8 +363,8 @@ void i8237_device::i8237_timerproc()
/* Check if EOP output needs to be asserted */
if ( m_status & ( 0x01 << m_service_channel ) )
{
m_eop = 0;
m_out_eop_func(m_eop ? ASSERT_LINE : CLEAR_LINE);
m_eop = CLEAR_LINE;
m_out_eop_func(m_eop);
}
break;
@ -413,7 +413,7 @@ void i8237_device::i8237_timerproc()
{
case DMA8237_DEMAND_MODE:
/* Check for terminal count or EOP signal or DREQ begin de-asserted */
if ( ( m_status & ( 0x01 << channel ) ) || !m_eop || !( m_drq & ( 0x01 << channel ) ) )
if ( ( m_status & ( 0x01 << channel ) ) || m_eop == CLEAR_LINE || !( m_drq & ( 0x01 << channel ) ) )
{
m_hrq = 0;
m_hlda = 0;
@ -435,7 +435,7 @@ void i8237_device::i8237_timerproc()
case DMA8237_BLOCK_MODE:
/* Check for terminal count or EOP signal */
if ( ( m_status & ( 0x01 << channel ) ) || !m_eop )
if ( ( m_status & ( 0x01 << channel ) ) || m_eop == CLEAR_LINE )
{
m_hrq = 0;
m_hlda = 0;
@ -452,8 +452,8 @@ void i8237_device::i8237_timerproc()
/* Check if EOP output needs to be asserted */
if ( m_status & ( 0x01 << channel ) )
{
m_eop = 0;
m_out_eop_func(m_eop ? ASSERT_LINE : CLEAR_LINE);
m_eop = CLEAR_LINE;
m_out_eop_func(m_eop);
}
}

6
src/emu/machine/am9517a.c
View File

@ -350,7 +350,7 @@ inline void am9517a_device::end_of_process()
}
// signal end of process
set_eop(0);
set_eop(ASSERT_LINE);
set_hreq(0);
m_current_channel = -1;
@ -454,7 +454,7 @@ void am9517a_device::device_reset()
m_last_channel = 3;
set_hreq(0);
set_eop(1);
set_eop(ASSERT_LINE);
set_dack();
}
@ -471,7 +471,7 @@ void am9517a_device::execute_run()
switch (m_state)
{
case STATE_SI:
set_eop(1);
set_eop(CLEAR_LINE);
if (!COMMAND_DISABLE)
{

3
src/mess/includes/at.h
View File

@ -159,6 +159,7 @@ public:
UINT8 m_at_spkrdata;
UINT8 m_at_speaker_input;
int m_dma_channel;
bool m_cur_eop;
UINT8 m_dma_offset[2][4];
UINT8 m_at_pages[0x10];
UINT16 m_dma_high_byte;
@ -176,6 +177,8 @@ public:
DECLARE_DRIVER_INIT(atcga);
DECLARE_DRIVER_INIT(atvga);
void pc_set_dma_channel(int channel, int state);
};

4
src/mess/includes/genpc.h
View File

@ -56,6 +56,7 @@ public:
UINT8 m_dma_offset[4];
UINT8 m_pc_spkrdata;
UINT8 m_pc_input;
bool m_cur_eop;
UINT8 m_nmi_enabled;
@ -102,6 +103,9 @@ public:
DECLARE_WRITE_LINE_MEMBER( pc_speaker_set_spkrdata );
const char *m_cputag;
private:
void pc_select_dma_channel(int channel, bool state);
};

48
src/mess/machine/at.c
View File

@ -163,6 +163,8 @@ WRITE_LINE_MEMBER( at_state::pc_dma_hrq_changed )
READ8_MEMBER(at_state::pc_dma_read_byte)
{
if(m_dma_channel == -1)
return 0xff;
UINT8 result;
offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16) & 0xFF0000;
@ -173,6 +175,8 @@ READ8_MEMBER(at_state::pc_dma_read_byte)
WRITE8_MEMBER(at_state::pc_dma_write_byte)
{
if(m_dma_channel == -1)
return;
offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16) & 0xFF0000;
space.write_byte(page_offset + offset, data);
@ -181,6 +185,8 @@ WRITE8_MEMBER(at_state::pc_dma_write_byte)
READ8_MEMBER(at_state::pc_dma_read_word)
{
if(m_dma_channel == -1)
return 0xff;
UINT16 result;
offs_t page_offset = (((offs_t) m_dma_offset[1][m_dma_channel & 3]) << 16) & 0xFE0000;
@ -193,6 +199,8 @@ READ8_MEMBER(at_state::pc_dma_read_word)
WRITE8_MEMBER(at_state::pc_dma_write_word)
{
if(m_dma_channel == -1)
return;
offs_t page_offset = (((offs_t) m_dma_offset[1][m_dma_channel & 3]) << 16) & 0xFE0000;
space.write_word(page_offset + ( offset << 1 ), m_dma_high_byte | data);
@ -215,23 +223,35 @@ WRITE8_MEMBER( at_state::pc_dma8237_5_dack_w ){ m_isabus->dack16_w(5, m_dma_high
WRITE8_MEMBER( at_state::pc_dma8237_6_dack_w ){ m_isabus->dack16_w(6, m_dma_high_byte | data); }
WRITE8_MEMBER( at_state::pc_dma8237_7_dack_w ){ m_isabus->dack16_w(7, m_dma_high_byte | data); }
WRITE_LINE_MEMBER( at_state::at_dma8237_out_eop ) { m_isabus->eop_w(state == ASSERT_LINE ? 0 : 1 ); }
static void set_dma_channel(device_t *device, int channel, int state)
WRITE_LINE_MEMBER( at_state::at_dma8237_out_eop )
{
at_state *st = device->machine().driver_data<at_state>();
if (!state)
st->m_dma_channel = channel;
m_cur_eop = state == ASSERT_LINE;
if(m_dma_channel != -1)
m_isabus->eop_w(m_dma_channel, ASSERT_LINE );
}
WRITE_LINE_MEMBER( at_state::pc_dack0_w ) { set_dma_channel(m_dma8237_1, 0, state); }
WRITE_LINE_MEMBER( at_state::pc_dack1_w ) { set_dma_channel(m_dma8237_1, 1, state); }
WRITE_LINE_MEMBER( at_state::pc_dack2_w ) { set_dma_channel(m_dma8237_1, 2, state); }
WRITE_LINE_MEMBER( at_state::pc_dack3_w ) { set_dma_channel(m_dma8237_1, 3, state); }
void at_state::pc_set_dma_channel(int channel, int state)
{
if(!state) {
m_dma_channel = channel;
if(m_cur_eop)
m_isabus->eop_w(channel, ASSERT_LINE );
} else if(m_dma_channel == channel) {
m_dma_channel = -1;
if(m_cur_eop)
m_isabus->eop_w(channel, CLEAR_LINE );
}
}
WRITE_LINE_MEMBER( at_state::pc_dack0_w ) { pc_set_dma_channel(0, state); }
WRITE_LINE_MEMBER( at_state::pc_dack1_w ) { pc_set_dma_channel(1, state); }
WRITE_LINE_MEMBER( at_state::pc_dack2_w ) { pc_set_dma_channel(2, state); }
WRITE_LINE_MEMBER( at_state::pc_dack3_w ) { pc_set_dma_channel(3, state); }
WRITE_LINE_MEMBER( at_state::pc_dack4_w ) { m_dma8237_1->hack_w(state ? 0 : 1); } // it's inverted
WRITE_LINE_MEMBER( at_state::pc_dack5_w ) { set_dma_channel(m_dma8237_2, 5, state); }
WRITE_LINE_MEMBER( at_state::pc_dack6_w ) { set_dma_channel(m_dma8237_2, 6, state); }
WRITE_LINE_MEMBER( at_state::pc_dack7_w ) { set_dma_channel(m_dma8237_2, 7, state); }
WRITE_LINE_MEMBER( at_state::pc_dack5_w ) { pc_set_dma_channel(5, state); }
WRITE_LINE_MEMBER( at_state::pc_dack6_w ) { pc_set_dma_channel(6, state); }
WRITE_LINE_MEMBER( at_state::pc_dack7_w ) { pc_set_dma_channel(7, state); }
I8237_INTERFACE( at_dma8237_1_config )
{
@ -343,4 +363,6 @@ MACHINE_RESET( at )
st->m_poll_delay = 4;
st->m_at_spkrdata = 0;
st->m_at_speaker_input = 0;
st->m_dma_channel = -1;
st->m_cur_eop = false;
}

33
src/mess/machine/genpc.c
View File

@ -69,6 +69,8 @@ WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dma_hrq_changed )
READ8_MEMBER( ibm5160_mb_device::pc_dma_read_byte )
{
if(m_dma_channel == -1)
return 0xff;
address_space *spaceio = m_maincpu->space(AS_PROGRAM);
offs_t page_offset = (((offs_t) m_dma_offset[m_dma_channel]) << 16) & 0x0F0000;
return spaceio->read_byte( page_offset + offset);
@ -77,6 +79,8 @@ READ8_MEMBER( ibm5160_mb_device::pc_dma_read_byte )
WRITE8_MEMBER( ibm5160_mb_device::pc_dma_write_byte )
{
if(m_dma_channel == -1)
return;
address_space *spaceio = m_maincpu->space(AS_PROGRAM);
offs_t page_offset = (((offs_t) m_dma_offset[m_dma_channel]) << 16) & 0x0F0000;
@ -127,13 +131,29 @@ WRITE8_MEMBER( ibm5160_mb_device::pc_dma8237_0_dack_w )
WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dma8237_out_eop )
{
return m_isabus->eop_w(state == ASSERT_LINE ? 0 : 1 );
m_cur_eop = state == ASSERT_LINE;
if(m_dma_channel != -1 && m_cur_eop)
m_isabus->eop_w(m_dma_channel, m_cur_eop ? ASSERT_LINE : CLEAR_LINE );
}
WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack0_w ) { if (!state) m_dma_channel = 0; }
WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack1_w ) { if (!state) m_dma_channel = 1; }
WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack2_w ) { if (!state) m_dma_channel = 2; }
WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack3_w ) { if (!state) m_dma_channel = 3; }
void ibm5160_mb_device::pc_select_dma_channel(int channel, bool state)
{
if(!state) {
m_dma_channel = channel;
if(m_cur_eop)
m_isabus->eop_w(channel, ASSERT_LINE );
} else if(m_dma_channel == channel) {
m_dma_channel = -1;
if(m_cur_eop)
m_isabus->eop_w(channel, CLEAR_LINE );
}
}
WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack0_w ) { pc_select_dma_channel(0, state); }
WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack1_w ) { pc_select_dma_channel(1, state); }
WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack2_w ) { pc_select_dma_channel(2, state); }
WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack3_w ) { pc_select_dma_channel(3, state); }
I8237_INTERFACE( pc_dma8237_config )
{
@ -651,7 +671,8 @@ void ibm5160_mb_device::device_reset()
m_out1 = 2; // initial state of pit output is undefined
m_pc_spkrdata = 0;
m_pc_input = 0;
m_dma_channel = 0;
m_dma_channel = -1;
m_cur_eop = false;
memset(m_dma_offset,0,sizeof(m_dma_offset));
m_ppi_portc_switch_high = 0;
m_ppi_speaker = 0;

8
src/mess/machine/isa.c
View File

@ -394,12 +394,10 @@ void isa8_device::dack_w(int line,UINT8 data)
return m_dma_device[line]->dack_w(line,data);
}
void isa8_device::eop_w(int state)
void isa8_device::eop_w(int channel, int state)
{
for (int i=0;i<8;i++) {
if (m_dma_eop[i]==TRUE && m_dma_device[i])
m_dma_device[i]->eop_w(state);
}
if (m_dma_eop[channel] && m_dma_device[channel])
m_dma_device[channel]->eop_w(state);
}
void isa8_device::nmi()

2
src/mess/machine/isa.h
View File

@ -173,7 +173,7 @@ public:
UINT8 dack_r(int line);
void dack_w(int line,UINT8 data);
void eop_w(int state);
void eop_w(int channels, int state);
void nmi();
void set_nmi_state(bool enabled) { m_nmi_enabled = enabled; }

18
src/mess/machine/isa_gus.c
View File

@ -1181,15 +1181,17 @@ void gf1_device::dack_w(int line,UINT8 data)
void gf1_device::eop_w(int state)
{
// end of transfer
m_dmatimer->reset();
//m_drq1(0);
if(m_dma_dram_ctrl & 0x20)
{
m_dma_dram_ctrl |= 0x40;
m_dma_irq_func(1);
if(state == ASSERT_LINE) {
// end of transfer
m_dmatimer->reset();
//m_drq1(0);
if(m_dma_dram_ctrl & 0x20)
{
m_dma_dram_ctrl |= 0x40;
m_dma_irq_func(1);
}
logerror("GUS: End of transfer. (%05x)\n",m_dma_current);
}
logerror("GUS: End of transfer. (%05x)\n",m_dma_current);
}

46
src/mess/machine/southbridge.c
View File

@ -221,6 +221,8 @@ void southbridge_device::device_reset()
m_poll_delay = 4;
m_at_spkrdata = 0;
m_at_speaker_input = 0;
m_dma_channel = -1;
m_cur_eop = false;
}
@ -336,6 +338,8 @@ WRITE_LINE_MEMBER( southbridge_device::pc_dma_hrq_changed )
READ8_MEMBER(southbridge_device::pc_dma_read_byte)
{
if(m_dma_channel == -1)
return 0xff;
UINT8 result;
offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16) & 0xFF0000;
@ -346,6 +350,8 @@ READ8_MEMBER(southbridge_device::pc_dma_read_byte)
WRITE8_MEMBER(southbridge_device::pc_dma_write_byte)
{
if(m_dma_channel == -1)
return;
offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16) & 0xFF0000;
space.write_byte(page_offset + offset, data);
@ -354,6 +360,8 @@ WRITE8_MEMBER(southbridge_device::pc_dma_write_byte)
READ8_MEMBER(southbridge_device::pc_dma_read_word)
{
if(m_dma_channel == -1)
return 0xff;
UINT16 result;
offs_t page_offset = (((offs_t) m_dma_offset[1][m_dma_channel & 3]) << 16) & 0xFF0000;
@ -366,6 +374,8 @@ READ8_MEMBER(southbridge_device::pc_dma_read_word)
WRITE8_MEMBER(southbridge_device::pc_dma_write_word)
{
if(m_dma_channel == -1)
return;
offs_t page_offset = (((offs_t) m_dma_offset[1][m_dma_channel & 3]) << 16) & 0xFF0000;
space.write_word(page_offset + ( offset << 1 ), m_dma_high_byte | data);
@ -389,16 +399,36 @@ WRITE8_MEMBER( southbridge_device::pc_dma8237_5_dack_w ){ m_isabus->dack_w(5, da
WRITE8_MEMBER( southbridge_device::pc_dma8237_6_dack_w ){ m_isabus->dack_w(6, data); }
WRITE8_MEMBER( southbridge_device::pc_dma8237_7_dack_w ){ m_isabus->dack_w(7, data); }
WRITE_LINE_MEMBER( southbridge_device::at_dma8237_out_eop ) { m_isabus->eop_w(state == ASSERT_LINE ? 0 : 1 ); }
WRITE_LINE_MEMBER( southbridge_device::at_dma8237_out_eop )
{
m_cur_eop = state == ASSERT_LINE;
if(m_dma_channel != -1)
m_isabus->eop_w(m_dma_channel, ASSERT_LINE );
}
WRITE_LINE_MEMBER( southbridge_device::pc_dack0_w ) { if (!state) m_dma_channel = 0; }
WRITE_LINE_MEMBER( southbridge_device::pc_dack1_w ) { if (!state) m_dma_channel = 1; }
WRITE_LINE_MEMBER( southbridge_device::pc_dack2_w ) { if (!state) m_dma_channel = 2; }
WRITE_LINE_MEMBER( southbridge_device::pc_dack3_w ) { if (!state) m_dma_channel = 3; }
void southbridge_device::pc_select_dma_channel(int channel, bool state)
{
if(!state) {
m_dma_channel = channel;
if(m_cur_eop)
m_isabus->eop_w(channel, ASSERT_LINE );
} else if(m_dma_channel == channel) {
m_dma_channel = -1;
if(m_cur_eop)
m_isabus->eop_w(channel, CLEAR_LINE );
}
}
WRITE_LINE_MEMBER( southbridge_device::pc_dack0_w ) { pc_select_dma_channel(0, state); }
WRITE_LINE_MEMBER( southbridge_device::pc_dack1_w ) { pc_select_dma_channel(1, state); }
WRITE_LINE_MEMBER( southbridge_device::pc_dack2_w ) { pc_select_dma_channel(2, state); }
WRITE_LINE_MEMBER( southbridge_device::pc_dack3_w ) { pc_select_dma_channel(3, state); }
WRITE_LINE_MEMBER( southbridge_device::pc_dack4_w ) { i8237_hlda_w( m_dma8237_1, state ? 0 : 1); } // it's inverted
WRITE_LINE_MEMBER( southbridge_device::pc_dack5_w ) { if (!state) m_dma_channel = 5; }
WRITE_LINE_MEMBER( southbridge_device::pc_dack6_w ) { if (!state) m_dma_channel = 6; }
WRITE_LINE_MEMBER( southbridge_device::pc_dack7_w ) { if (!state) m_dma_channel = 7; }
WRITE_LINE_MEMBER( southbridge_device::pc_dack5_w ) { pc_select_dma_channel(5, state); }
WRITE_LINE_MEMBER( southbridge_device::pc_dack6_w ) { pc_select_dma_channel(6, state); }
WRITE_LINE_MEMBER( southbridge_device::pc_dack7_w ) { pc_select_dma_channel(7, state); }
READ8_MEMBER( southbridge_device::at_portb_r )
{

3
src/mess/machine/southbridge.h
View File

@ -132,6 +132,7 @@ protected:
UINT8 m_at_spkrdata;
UINT8 m_at_speaker_input;
int m_dma_channel;
bool m_cur_eop;
UINT8 m_dma_offset[2][4];
UINT8 m_at_pages[0x10];
UINT16 m_dma_high_byte;
@ -142,6 +143,8 @@ protected:
UINT8 m_channel_check;
UINT8 m_nmi_enabled;
void pc_select_dma_channel(int channel, bool state);
};
#endif /* __SOUTHBRIDGE_H__ */