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New working software list additions

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-----------------------------------
ibm5170: The Final ChessCard [hap]
This commit is contained in:
hap 2019-05-23 23:23:28 +02:00
parent 874a6f94a4
commit f560cef0a4
8 changed files with 150 additions and 102 deletions
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6
hash/c64_cart.xml
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@ -6664,7 +6664,7 @@
<software name="fcc">
<description>The Final ChessCard (Eng, v0.9/v1.0)</description>
<year>1989</year>
<publisher>Tasc</publisher>
<publisher>TASC</publisher>
<part name="cart" interface="c64_cart">
<feature name="slot" value="fcc" />
@ -6685,7 +6685,7 @@
<software name="fccg">
<description>The Final ChessCard (Ger, v1.3/v1.5)</description>
<year>1990</year>
<publisher>Tasc</publisher>
<publisher>TASC</publisher>
<part name="cart" interface="c64_cart">
<feature name="slot" value="fcc" />
@ -6706,7 +6706,7 @@
<software name="fccgo">
<description>The Final ChessCard (Ger, v0.9/v1.0)</description>
<year>1989</year>
<publisher>Tasc</publisher>
<publisher>TASC</publisher>
<part name="cart" interface="c64_cart">
<feature name="slot" value="fcc" />

2
hash/c64_flop.xml
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@ -152,7 +152,7 @@
<software name="fcc"> <!-- optional -->
<description>The Final ChessCard</description>
<year>1990</year>
<publisher>Tasc</publisher>
<publisher>TASC</publisher>
<sharedfeat name="requirement" value="c64_cart:fcc"/>
<part name="flop1" interface="floppy_5_25">

12
hash/ibm5170.xml
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@ -9559,6 +9559,18 @@
</part>
</software>
<software name="finalchs">
<!-- needs finalchs ISA card to work -->
<description>The Final ChessCard</description>
<year>1989</year>
<publisher>TASC</publisher>
<part name="flop1" interface="floppy_3_5">
<dataarea name="flop" size="1474560">
<rom name="finalchs.img" size="1474560" crc="3428d309" sha1="ea345d6828ffd9ff9be3ac4e037e80491bb7ce74"/>
</dataarea>
</part>
</software>
<software name="krustyfh">
<description>Krusty's Fun House</description>
<year>1993</year>

2
src/devices/bus/c64/fcc.cpp
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@ -2,7 +2,7 @@
// copyright-holders:Curt Coder, hap
/**********************************************************************
Tasc Final ChessCard cartridge emulation
TASC Final ChessCard cartridge emulation
It expects a mouse in port 2, and/or joystick in port 1.

2
src/devices/bus/c64/fcc.h
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@ -2,7 +2,7 @@
// copyright-holders:Curt Coder, hap
/**********************************************************************
Tasc Final ChessCard cartridge emulation
TASC Final ChessCard cartridge emulation
**********************************************************************/

197
src/devices/bus/isa/finalchs.cpp
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@ -1,96 +1,34 @@
// license:BSD-3-Clause
// copyright-holders:Jonathan Gevaryahu
/***************************************************************************
// copyright-holders:hap
/*
Final Chess Card by TASC
Final ChessCard by TASC
TODO:
- skeleton, just boots the CPU
8-bit ISA card, comes with its own CPU (G65SC02P-4 @ 5MHz), and chess engine on 32KB ROM.
It is similar to the C64 version, actually not as impressive since a PC from around 1989
should be able to run a good chess game by itself.
***************************************************************************/
*/
#include "emu.h"
#include "finalchs.h"
#include "cpu/m6502/m65sc02.h"
WRITE8_MEMBER( isa8_finalchs_device::io7ff8_write )
{
m_FCH_latch_data = data;
}
READ8_MEMBER( isa8_finalchs_device::io7ff8_read )
{
static unsigned char table[] = { 0xff, 0xfd, 0xfe };
static int i = -1;
i++;
if (i == 3) i = 0;
return table[i]; // exercise the NMI handler for now with known commands
}
READ8_MEMBER( isa8_finalchs_device::io6000_read )
{
return 0x55;
}
WRITE8_MEMBER( isa8_finalchs_device::io6000_write )
{
m_FCH_latch_data = data;
}
void isa8_finalchs_device::finalchs_mem(address_map &map)
{
map(0x0000, 0x1fff).ram();
map(0x7ff8, 0x7ff8).r(FUNC(isa8_finalchs_device::io7ff8_read));
map(0x7ff8, 0x7ff8).w(FUNC(isa8_finalchs_device::io7ff8_write));
map(0x6000, 0x6000).r(FUNC(isa8_finalchs_device::io6000_read));
map(0x6000, 0x6000).w(FUNC(isa8_finalchs_device::io6000_write));
map(0x8000, 0xffff).rom();
}
ROM_START(finalchs)
ROM_REGION(0x10000,"maincpu",0)
ROM_LOAD("finalchs.bin", 0x8000, 0x8000, CRC(c8e72dff) SHA1(f422b19a806cef4fadd580caefaaf8c32b644098))
ROM_END
READ8_MEMBER( isa8_finalchs_device::finalchs_r )
{
return 0;
}
WRITE8_MEMBER( isa8_finalchs_device::finalchs_w )
{
}
//**************************************************************************
// GLOBAL VARIABLES
//**************************************************************************
DEFINE_DEVICE_TYPE(ISA8_FINALCHS, isa8_finalchs_device, "isa_finalchs", "Final Chess Card")
DEFINE_DEVICE_TYPE(ISA8_FINALCHS, isa8_finalchs_device, "isa_finalchs", "Final ChessCard")
//-------------------------------------------------
// device_add_mconfig - add device configuration
// constructor
//-------------------------------------------------
void isa8_finalchs_device::device_add_mconfig(machine_config &config)
{
m65sc02_device &cpu(M65SC02(config, "maincpu", 5_MHz_XTAL));
cpu.set_addrmap(AS_PROGRAM, &isa8_finalchs_device::finalchs_mem);
}
isa8_finalchs_device::isa8_finalchs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
device_t(mconfig, ISA8_FINALCHS, tag, owner, clock),
device_isa8_card_interface(mconfig, *this),
m_maincpu(*this, "maincpu"),
m_mainlatch(*this, "mainlatch"),
m_sublatch(*this, "sublatch")
{ }
//**************************************************************************
// LIVE DEVICE
//**************************************************************************
//-------------------------------------------------
// isa8_finalchs_device - constructor
//-------------------------------------------------
isa8_finalchs_device::isa8_finalchs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, ISA8_FINALCHS, tag, owner, clock)
, device_isa8_card_interface(mconfig, *this)
, m_FCH_latch_data(0)
{
}
//-------------------------------------------------
// device_start - device-specific startup
@ -99,25 +37,120 @@ isa8_finalchs_device::isa8_finalchs_device(const machine_config &mconfig, const
void isa8_finalchs_device::device_start()
{
set_isa_device();
//the included setup program allows any port from 0x100 to 0x1F0 to be selected, at increments of 0x10
//picked the following at random until we get dips hooked up
m_isa->install_device(0x160, 0x0161, read8_delegate(FUNC(isa8_finalchs_device::finalchs_r), this), write8_delegate(FUNC(isa8_finalchs_device::finalchs_w), this));
m_installed = false;
}
//-------------------------------------------------
// device_reset - device-specific reset
//-------------------------------------------------
void isa8_finalchs_device::device_reset()
{
m_FCH_latch_data = 0;
if (!m_installed)
{
// MAME doesn't allow reading ioport at device_start
u16 port = ioport("DSW")->read() * 0x10 + 0x100;
m_isa->install_device(port, port+1, read8_delegate(FUNC(isa8_finalchs_device::finalchs_r), this), write8_delegate(FUNC(isa8_finalchs_device::finalchs_w), this));
m_installed = true;
}
}
//-------------------------------------------------
// rom_region - device-specific ROM region
//-------------------------------------------------
ROM_START( finalchs )
ROM_REGION( 0x10000, "maincpu", 0 )
ROM_LOAD("finalchs.bin", 0x8000, 0x8000, CRC(c8e72dff) SHA1(f422b19a806cef4fadd580caefaaf8c32b644098) )
ROM_END
const tiny_rom_entry *isa8_finalchs_device::device_rom_region() const
{
return ROM_NAME( finalchs );
}
//-------------------------------------------------
// input_ports - device-specific input ports
//-------------------------------------------------
static INPUT_PORTS_START( finalchs )
PORT_START("DSW") // DIP switch on the ISA card PCB
PORT_DIPNAME( 0x0f, 0x07, "I/O Port Address" ) PORT_DIPLOCATION("SW1:!1,!2,!3,!4")
PORT_DIPSETTING( 0x00, "0x100" )
PORT_DIPSETTING( 0x01, "0x110" )
PORT_DIPSETTING( 0x02, "0x120" )
PORT_DIPSETTING( 0x03, "0x130" )
PORT_DIPSETTING( 0x04, "0x140" )
PORT_DIPSETTING( 0x05, "0x150" )
PORT_DIPSETTING( 0x06, "0x160" )
PORT_DIPSETTING( 0x07, "0x170" )
PORT_DIPSETTING( 0x08, "0x180" )
PORT_DIPSETTING( 0x09, "0x190" )
PORT_DIPSETTING( 0x0a, "0x1A0" )
PORT_DIPSETTING( 0x0b, "0x1B0" )
PORT_DIPSETTING( 0x0c, "0x1C0" )
PORT_DIPSETTING( 0x0d, "0x1D0" )
PORT_DIPSETTING( 0x0e, "0x1E0" )
PORT_DIPSETTING( 0x0f, "0x1F0" )
INPUT_PORTS_END
ioport_constructor isa8_finalchs_device::device_input_ports() const
{
return INPUT_PORTS_NAME(finalchs);
}
//-------------------------------------------------
// device_add_mconfig - add device configuration
//-------------------------------------------------
void isa8_finalchs_device::device_add_mconfig(machine_config &config)
{
M65SC02(config, m_maincpu, 5_MHz_XTAL);
m_maincpu->set_addrmap(AS_PROGRAM, &isa8_finalchs_device::finalchs_mem);
GENERIC_LATCH_8(config, m_mainlatch);
GENERIC_LATCH_8(config, m_sublatch);
m_sublatch->data_pending_callback().set_inputline(m_maincpu, INPUT_LINE_NMI);
}
/******************************************************************************
I/O
******************************************************************************/
// External handlers
READ8_MEMBER(isa8_finalchs_device::finalchs_r)
{
if (offset == 0)
return m_mainlatch->read();
else
return !m_mainlatch->pending_r();
}
WRITE8_MEMBER(isa8_finalchs_device::finalchs_w)
{
if (offset == 0)
m_sublatch->write(data);
}
// internal (on-card CPU)
void isa8_finalchs_device::finalchs_mem(address_map &map)
{
map(0x0000, 0x1fff).ram();
map(0x7f00, 0x7f00).mirror(0x00ff).r(m_sublatch, FUNC(generic_latch_8_device::read)).w(m_mainlatch, FUNC(generic_latch_8_device::write));
//map(0x6000, 0x6000).noprw(); // ?
map(0x8000, 0xffff).rom();
}

30
src/devices/bus/isa/finalchs.h
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@ -1,17 +1,20 @@
// license:BSD-3-Clause
// copyright-holders:Jonathan Gevaryahu
// copyright-holders:hap
/*
Final ChessCard by TASC
*/
#ifndef MAME_BUS_ISA_FINALCHS_H
#define MAME_BUS_ISA_FINALCHS_H
#pragma once
#include "isa.h"
#include "cpu/m6502/m65sc02.h"
#include "machine/gen_latch.h"
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
// ======================> isa8_finalchs_device
class isa8_finalchs_device :
public device_t,
@ -29,24 +32,23 @@ protected:
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
virtual const tiny_rom_entry *device_rom_region() const override;
virtual ioport_constructor device_input_ports() const override;
private:
// internal state
uint8_t m_FCH_latch_data;
required_device<m65sc02_device> m_maincpu;
required_device<generic_latch_8_device> m_mainlatch;
required_device<generic_latch_8_device> m_sublatch;
bool m_installed;
DECLARE_READ8_MEMBER(finalchs_r);
DECLARE_WRITE8_MEMBER(finalchs_w);
DECLARE_WRITE8_MEMBER( io7ff8_write );
DECLARE_READ8_MEMBER( io7ff8_read );
DECLARE_READ8_MEMBER( io6000_read );
DECLARE_WRITE8_MEMBER( io6000_write );
void finalchs_mem(address_map &map);
};
// device type definition
DECLARE_DEVICE_TYPE(ISA8_FINALCHS, isa8_finalchs_device)
#endif // MAME_BUS_ISA_FINALCHS_H

1
src/devices/bus/isa/isa_cards.cpp
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@ -159,6 +159,7 @@ void pc_isa16_cards(device_slot_interface &device)
device.option_add("dectalk", ISA8_DECTALK);
device.option_add("pds", ISA8_PDS);
device.option_add("lba_enhancer", ISA8_LBA_ENHANCER);
device.option_add("finalchs", ISA8_FINALCHS);
// 16-bit
device.option_add("ide", ISA16_IDE);
device.option_add("ne2000", NE2000);