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netlist: Added 4316 bilateral switch pack.

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This commit is contained in:
Vas Crabb 2016-12-23 14:54:54 +11:00
parent 87e810cad4
commit f5bc78c211
5 changed files with 140 additions and 25 deletions
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2
scripts/src/netlist.lua
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@ -99,6 +99,8 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_4020.h",
MAME_DIR .. "src/lib/netlist/devices/nld_4066.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_4066.h",
MAME_DIR .. "src/lib/netlist/devices/nld_4316.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_4316.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7448.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7448.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7450.cpp",

2
src/lib/netlist/devices/nld_4066.h
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@ -15,7 +15,7 @@
* VSS |7 8| INOUTC
* +--------------+
*
* FIXME: These devices are slow (~125 ns). THis is currently not reflected
* FIXME: These devices are slow (~125 ns). This is currently not reflected
*
* Naming conventions follow National semiconductor datasheet
*

49
src/lib/netlist/devices/nld_4316.cpp Normal file
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@ -0,0 +1,49 @@
// license:BSD-3-Clause
// copyright-holders:Vas Crabb
/*
* nld_4316.c
*
*/
#include <devices/nlid_cmos.h>
#include "analog/nld_twoterm.h"
#include "nld_4316.h"
namespace netlist { namespace devices {
NETLIB_OBJECT(CD4316_GATE)
{
NETLIB_CONSTRUCTOR(CD4316_GATE)
NETLIB_FAMILY("CD4XXX")
, m_supply(*this, "PS")
, m_R(*this, "R")
, m_S(*this, "S")
, m_E(*this, "E")
, m_base_r(*this, "BASER", 45.0)
{
}
NETLIB_RESETI() { }
NETLIB_UPDATEI();
public:
NETLIB_SUB(vdd_vss) m_supply;
NETLIB_SUB(R) m_R;
logic_input_t m_S, m_E;
param_double_t m_base_r;
};
NETLIB_UPDATE(CD4316_GATE)
{
m_R.update_dev();
if (m_S() && !m_E())
m_R.set_R(m_base_r());
else
m_R.set_R(NL_FCONST(1.0) / netlist().gmin());
m_R.m_P.schedule_after(NLTIME_FROM_NS(1));
}
NETLIB_DEVICE_IMPL(CD4316_GATE);
} } // namesapce netlist::devices

33
src/lib/netlist/devices/nld_4316.h Normal file
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@ -0,0 +1,33 @@
// license:BSD-3-Clause
// copyright-holders:Vas Crabb
/*
* nld_4136.h
*
* CD4066: Quad Analog Switch with Level Translation
*
* +--------------+
* 1Z |1 ++ 16| VCC
* 1Y |2 15| 1S
* 2Y |3 14| 4S
* 2Z |4 4066 13| 4Z
* 2S |5 12| 4Y
* 3S |6 11| 3Y
* /E |7 10| 3Z
* GND |8 9| VEE
* +--------------+
*
* FIXME: These devices are slow (can be over 200 ns in HC types). This is currently not reflected
*
* Naming conventions follow Texas Instruments datasheet
*
*/
#ifndef NLD_4316_H_
#define NLD_4316_H_
#include "nl_setup.h"
#define CD4316_GATE(name) \
NET_REGISTER_DEV(CD4316_GATE, name)
#endif /* NLD_4316_H_ */

79
src/lib/netlist/macro/nlm_cd4xxx.cpp
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@ -6,6 +6,7 @@
#include "devices/nld_system.h"
#include "devices/nld_4020.h"
#include "devices/nld_4066.h"
#include "devices/nld_4316.h"
/*
* CD4001BC: Quad 2-Input NOR Buffered B Series Gate
@ -31,14 +32,14 @@ static NETLIST_START(CD4001_DIP)
DUMMY_INPUT(VSS)
DUMMY_INPUT(VDD)
DIPPINS( /* +--------------+ */
s1.A, /* A1 |1 ++ 14| VCC */ VSS.I,
s1.B, /* B1 |2 13| A6 */ s4.B,
s1.Q, /* A2 |3 12| Y6 */ s4.A,
s2.Q, /* Y2 |4 4001 11| A5 */ s4.Q,
s2.A, /* A3 |5 10| Y5 */ s3.Q,
s2.B, /* Y3 |6 9| A4 */ s3.B,
VDD.I, /* GND |7 8| Y4 */ s3.A
DIPPINS( /* +--------------+ */
s1.A, /* A1 |1 ++ 14| VCC */ VSS.I,
s1.B, /* B1 |2 13| A6 */ s4.B,
s1.Q, /* A2 |3 12| Y6 */ s4.A,
s2.Q, /* Y2 |4 4001 11| A5 */ s4.Q,
s2.A, /* A3 |5 10| Y5 */ s3.Q,
s2.B, /* Y3 |6 9| A4 */ s3.B,
VDD.I, /* GND |7 8| Y4 */ s3.A
/* +--------------+ */
)
@ -115,14 +116,14 @@ static NETLIST_START(CD4066_DIP)
PARAM(C.BASER, 270.0)
PARAM(D.BASER, 270.0)
DIPPINS( /* +--------------+ */
A.R.1, /* INOUTA |1 ++ 14| VDD */ A.PS.VDD,
A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL,
B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL,
B.R.2, /* INOUTB |4 4066 11| INOUTD */ D.R.1,
B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2,
C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1,
A.PS.VSS, /* VSS |7 8| INOUTC */ C.R.2
DIPPINS( /* +--------------+ */
A.R.1, /* INOUTA |1 ++ 14| VDD */ A.PS.VDD,
A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL,
B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL,
B.R.2, /* INOUTB |4 4066 11| INOUTD */ D.R.1,
B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2,
C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1,
A.PS.VSS, /* VSS |7 8| INOUTC */ C.R.2
/* +--------------+ */
)
NETLIST_END()
@ -141,18 +142,47 @@ static NETLIST_START(CD4016_DIP)
PARAM(C.BASER, 1000.0)
PARAM(D.BASER, 1000.0)
DIPPINS( /* +--------------+ */
A.R.1, /* INOUTA |1 ++ 14| VDD */ A.PS.VDD,
A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL,
B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL,
B.R.2, /* INOUTB |4 4016 11| INOUTD */ D.R.1,
B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2,
C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1,
A.PS.VSS, /* VSS |7 8| INOUTC */ C.R.2
DIPPINS( /* +--------------+ */
A.R.1, /* INOUTA |1 ++ 14| VDD */ A.PS.VDD,
A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL,
B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL,
B.R.2, /* INOUTB |4 4016 11| INOUTD */ D.R.1,
B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2,
C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1,
A.PS.VSS, /* VSS |7 8| INOUTC */ C.R.2
/* +--------------+ */
)
NETLIST_END()
static NETLIST_START(CD4316_DIP)
CD4316_GATE(A)
CD4316_GATE(B)
CD4316_GATE(C)
CD4316_GATE(D)
NET_C(A.E, B.E, C.E, D.E)
NET_C(A.PS.VDD, B.PS.VDD, C.PS.VDD, D.PS.VDD)
NET_C(A.PS.VSS, B.PS.VSS, C.PS.VSS, D.PS.VSS)
PARAM(A.BASER, 45.0)
PARAM(B.BASER, 45.0)
PARAM(C.BASER, 45.0)
PARAM(D.BASER, 45.0)
DIPPINS( /* +--------------+ */
A.R.2, /* 1Z |1 ++ 16| VCC */ A.PS.VDD,
A.R.1, /* 1Y |2 15| 1S */ A.S,
B.R.1, /* 2Y |3 14| 4S */ D.S,
B.R.2, /* 2Z |4 4316 13| 4Z */ D.R.2,
B.S, /* 2S |5 12| 4Y */ D.R.1,
C.S, /* 3S |6 11| 3Y */ C.R.1,
A.E, /* /E |7 10| 3Z */ C.R.2,
A.PS.VSS, /* GND |8 9| VEE */ VEE
/* +--------------+ */
)
NETLIST_END()
NETLIST_START(CD4XXX_lib)
TRUTHTABLE_START(CD4001_NOR, 2, 1, "")
@ -169,5 +199,6 @@ NETLIST_START(CD4XXX_lib)
LOCAL_LIB_ENTRY(CD4020_DIP)
LOCAL_LIB_ENTRY(CD4016_DIP)
LOCAL_LIB_ENTRY(CD4066_DIP)
LOCAL_LIB_ENTRY(CD4316_DIP)
NETLIST_END()