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some pedantic fixes (nw)

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This commit is contained in:
Cowering 2015-10-09 10:25:44 -05:00
parent 93d9d28df9
commit f5d247d7b8
2 changed files with 9 additions and 9 deletions
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14
src/devices/machine/68230pit.c
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@ -109,9 +109,9 @@ void pit68230_device::execute_run ()
} while (m_icount > 0);
}
LOG (static INT32 ow_cnt = 0);
LOG (static INT32 ow_data = 0);
LOG (static INT32 ow_ofs = 0);
LOG (static INT32 ow_cnt = 0)
LOG (static INT32 ow_data = 0)
LOG (static INT32 ow_ofs = 0)
WRITE8_MEMBER (pit68230_device::write){
switch (offset) {
@ -171,7 +171,7 @@ WRITE8_MEMBER (pit68230_device::write){
break;
default:
LOG (logerror ("unhandled register %02x", offset));
LOG (logerror ("unhandled register %02x", offset))
}
LOG (if (offset != ow_ofs || data != ow_data || ow_cnt >= 1000) {
@ -185,9 +185,9 @@ WRITE8_MEMBER (pit68230_device::write){
ow_cnt++; )
}
LOG (static INT32 or_cnt = 0);
LOG (static INT32 or_data = 0);
LOG (static INT32 or_ofs = 0);
LOG (static INT32 or_cnt = 0)
LOG (static INT32 or_data = 0)
LOG (static INT32 or_ofs = 0)
READ8_MEMBER (pit68230_device::read){
UINT8 data = 0;

4
src/devices/machine/z80sio.h
View File

@ -208,7 +208,7 @@ protected:
{
REG_RR0_STATUS = 0,
REG_RR1_SPEC_RCV_COND = 1,
REG_RR2_INTERRUPT_VECT = 2,
REG_RR2_INTERRUPT_VECT = 2
};
// Write registers
@ -221,7 +221,7 @@ protected:
REG_WR4_RX_TX_MODES = 4,
REG_WR5_TX_CONTROL = 5,
REG_WR6_SYNC_OR_SDLC_A = 6,
REG_WR7_SYNC_OR_SDLC_F = 7,
REG_WR7_SYNC_OR_SDLC_F = 7
};
enum