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https://github.com/holub/mame
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New machines market as NOT_WORKING
---------------------------------- Waldorf Electronics MiniWorks 4-Pole [DBWBP]
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334120cd95
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f5d61ddcbe
@ -4713,6 +4713,7 @@ files {
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MAME_DIR .. "src/mame/drivers/mstation.cpp",
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MAME_DIR .. "src/mame/drivers/mt735.cpp",
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MAME_DIR .. "src/mame/drivers/mtd1256.cpp",
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MAME_DIR .. "src/mame/drivers/mw4pole.cpp",
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MAME_DIR .. "src/mame/drivers/mx2178.cpp",
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MAME_DIR .. "src/mame/drivers/mycom.cpp",
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MAME_DIR .. "src/mame/drivers/myvision.cpp",
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@ -47,6 +47,7 @@ static const int div_tab[4] = { 1, 4, 8, 16 };
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DEFINE_DEVICE_TYPE(MC68HC11A1, mc68hc11a1_device, "mc68hc11a1", "Motorola MC68HC11A1")
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DEFINE_DEVICE_TYPE(MC68HC11D0, mc68hc11d0_device, "mc68hc11d0", "Motorola MC68HC11D0")
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DEFINE_DEVICE_TYPE(MC68HC11E1, mc68hc11e1_device, "mc68hc11e1", "Motorola MC68HC11E1")
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DEFINE_DEVICE_TYPE(MC68HC811E2, mc68hc811e2_device, "mc68hc811e2", "Motorola MC68HC811E2")
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DEFINE_DEVICE_TYPE(MC68HC11F1, mc68hc11f1_device, "mc68hc11f1", "Motorola MC68HC11F1")
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DEFINE_DEVICE_TYPE(MC68HC11K1, mc68hc11k1_device, "mc68hc11k1", "Motorola MC68HC11K1")
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@ -107,6 +108,11 @@ mc68hc11d0_device::mc68hc11d0_device(const machine_config &mconfig, const char *
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{
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}
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mc68hc11e1_device::mc68hc11e1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: mc68hc11_cpu_device(mconfig, MC68HC11E1, tag, owner, clock, 512, 64, 0, 512, 0x01, 0x0f, 0xfb)
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{
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}
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mc68hc811e2_device::mc68hc811e2_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: mc68hc11_cpu_device(mconfig, MC68HC811E2, tag, owner, clock, 256, 64, 0, 2048, 0x01, 0xf5, 0xfb)
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{
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@ -511,6 +517,40 @@ void mc68hc11d0_device::mc68hc11_reg_map(memory_view::memory_view_entry &block,
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block(base + 0x3f, base + 0x3f).rw(FUNC(mc68hc11d0_device::config_r), FUNC(mc68hc11d0_device::config_w)); // CONFIG
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}
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void mc68hc11e1_device::mc68hc11_reg_map(memory_view::memory_view_entry &block, offs_t base)
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{
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block(base + 0x00, base + 0x00).rw(FUNC(mc68hc11e1_device::port_r<0>), FUNC(mc68hc11e1_device::port_w<0>)); // PORTA
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block(base + 0x02, base + 0x02).r(FUNC(mc68hc11e1_device::pioc_r)); // PIOC
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block(base + 0x03, base + 0x03).rw(FUNC(mc68hc11e1_device::port_r<2>), FUNC(mc68hc11e1_device::port_w<2>)); // PORTC
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block(base + 0x04, base + 0x04).rw(FUNC(mc68hc11e1_device::port_r<1>), FUNC(mc68hc11e1_device::port_w<1>)); // PORTB
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block(base + 0x05, base + 0x05).nopw(); // PORTCL
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block(base + 0x07, base + 0x07).rw(FUNC(mc68hc11e1_device::ddr_r<2>), FUNC(mc68hc11e1_device::ddr_w<2>)); // DDRC
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block(base + 0x08, base + 0x08).rw(FUNC(mc68hc11e1_device::port_r<3>), FUNC(mc68hc11e1_device::port_w<3>)); // PORTD
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block(base + 0x09, base + 0x09).rw(FUNC(mc68hc11e1_device::ddr_r<3>), FUNC(mc68hc11e1_device::ddr_w<3>)); // DDRD
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block(base + 0x0a, base + 0x0a).r(FUNC(mc68hc11e1_device::port_r<4>)); // PORTE
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block(base + 0x0e, base + 0x0f).rw(FUNC(mc68hc11e1_device::tcnt_r), FUNC(mc68hc11e1_device::tcnt_w)); // TCNT
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block(base + 0x16, base + 0x1f).rw(FUNC(mc68hc11e1_device::toc_r), FUNC(mc68hc11e1_device::toc_w)); // TOC1-TOC4, TI4/O5
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block(base + 0x20, base + 0x20).rw(FUNC(mc68hc11e1_device::tctl1_r), FUNC(mc68hc11e1_device::tctl1_w)); // TCTL1
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block(base + 0x21, base + 0x21).rw(FUNC(mc68hc11e1_device::tctl2_r), FUNC(mc68hc11e1_device::tctl2_w)); // TCTL2
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block(base + 0x22, base + 0x22).rw(FUNC(mc68hc11e1_device::tmsk1_r), FUNC(mc68hc11e1_device::tmsk1_w)); // TMSK1
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block(base + 0x23, base + 0x23).rw(FUNC(mc68hc11e1_device::tflg1_r), FUNC(mc68hc11e1_device::tflg1_w)); // TFLG1
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block(base + 0x24, base + 0x24).rw(FUNC(mc68hc11e1_device::tmsk2_r), FUNC(mc68hc11e1_device::tmsk2_w)); // TMSK2
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block(base + 0x25, base + 0x25).rw(FUNC(mc68hc11e1_device::tflg2_r), FUNC(mc68hc11e1_device::tflg2_w)); // TFLG2
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block(base + 0x26, base + 0x26).rw(FUNC(mc68hc11e1_device::pactl_ddra_r), FUNC(mc68hc11e1_device::pactl_ddra_w)); // PACTL
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block(base + 0x28, base + 0x28).r(FUNC(mc68hc11e1_device::spcr_r<0>)).nopw(); // SPCR
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block(base + 0x29, base + 0x29).r(FUNC(mc68hc11e1_device::spsr_r<0>)).nopw(); // SPSR
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block(base + 0x2a, base + 0x2a).rw(FUNC(mc68hc11e1_device::spdr_r<0>), FUNC(mc68hc11e1_device::spdr_w<0>)); // SPDR
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block(base + 0x2c, base + 0x2c).r(FUNC(mc68hc11e1_device::sccr1_r)).nopw(); // SCCR1
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block(base + 0x2d, base + 0x2d).r(FUNC(mc68hc11e1_device::sccr2_r)).nopw(); // SCCR2
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block(base + 0x30, base + 0x30).rw(FUNC(mc68hc11e1_device::adctl_r), FUNC(mc68hc11e1_device::adctl_w)); // ADCTL
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block(base + 0x31, base + 0x34).r(FUNC(mc68hc11e1_device::adr_r)); // ADR1-ADR4
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block(base + 0x39, base + 0x39).rw(FUNC(mc68hc11e1_device::option_r), FUNC(mc68hc11e1_device::option_w)); // OPTION
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block(base + 0x3a, base + 0x3a).nopw(); // COPRST (watchdog)
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block(base + 0x3b, base + 0x3b).nopw(); // PPROG (EEPROM programming)
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block(base + 0x3d, base + 0x3d).rw(FUNC(mc68hc11e1_device::init_r), FUNC(mc68hc11e1_device::init_w)); // INIT
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block(base + 0x3f, base + 0x3f).rw(FUNC(mc68hc11e1_device::config_r), FUNC(mc68hc11e1_device::config_w)); // CONFIG
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}
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void mc68hc811e2_device::mc68hc11_reg_map(memory_view::memory_view_entry &block, offs_t base)
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{
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block(base + 0x00, base + 0x00).rw(FUNC(mc68hc811e2_device::port_r<0>), FUNC(mc68hc811e2_device::port_w<0>)); // PORTA
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@ -893,6 +933,16 @@ void mc68hc11d0_device::device_reset()
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m_config = 0x00;
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}
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void mc68hc11e1_device::device_reset()
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{
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mc68hc11_cpu_device::device_reset();
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m_port_data[0] &= 0x8f;
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m_port_data[1] = 0x00;
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ddr_w<0>(0x70);
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ddr_w<1>(0xff);
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}
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void mc68hc811e2_device::device_reset()
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{
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mc68hc11_cpu_device::device_reset();
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@ -14,6 +14,7 @@ enum {
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DECLARE_DEVICE_TYPE(MC68HC11A1, mc68hc11a1_device)
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DECLARE_DEVICE_TYPE(MC68HC11D0, mc68hc11d0_device)
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DECLARE_DEVICE_TYPE(MC68HC11E1, mc68hc11e1_device)
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DECLARE_DEVICE_TYPE(MC68HC811E2, mc68hc811e2_device)
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DECLARE_DEVICE_TYPE(MC68HC11F1, mc68hc11f1_device)
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DECLARE_DEVICE_TYPE(MC68HC11K1, mc68hc11k1_device)
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@ -573,6 +574,18 @@ private:
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uint8_t reg01_r();
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};
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class mc68hc11e1_device : public mc68hc11_cpu_device
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{
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public:
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// construction/destruction
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mc68hc11e1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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protected:
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virtual void device_reset() override;
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virtual void mc68hc11_reg_map(memory_view::memory_view_entry &block, offs_t base) override;
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};
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class mc68hc811e2_device : public mc68hc11_cpu_device
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{
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public:
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53
src/mame/drivers/mw4pole.cpp
Normal file
53
src/mame/drivers/mw4pole.cpp
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@ -0,0 +1,53 @@
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// license:BSD-3-Clause
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// copyright-holders:AJR
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/****************************************************************************
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Skeleton driver for Waldorf MiniWorks 4-Pole analog filter module.
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****************************************************************************/
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#include "emu.h"
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#include "cpu/mc68hc11/mc68hc11.h"
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namespace {
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class mw4pole_state : public driver_device
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{
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public:
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mw4pole_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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{
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}
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void mw4pole(machine_config &config);
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private:
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void mem_map(address_map &map);
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required_device<mc68hc11_cpu_device> m_maincpu;
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};
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void mw4pole_state::mem_map(address_map &map)
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{
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map(0x8000, 0xffff).rom().region("eprom", 0);
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}
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static INPUT_PORTS_START(mw4pole)
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INPUT_PORTS_END
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void mw4pole_state::mw4pole(machine_config &config)
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{
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MC68HC11E1(config, m_maincpu, 8_MHz_XTAL);
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m_maincpu->set_addrmap(AS_PROGRAM, &mw4pole_state::mem_map);
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}
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ROM_START(mw4pole)
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ROM_REGION(0x8000, "eprom", 0)
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ROM_LOAD("4-pole v1.48 001eaf32.bin", 0x0000, 0x8000, CRC(51be6962) SHA1(20e793573a49002c854b012280aed13058ba0b63)) // TMS27C256
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ROM_END
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} // anonymous namespace
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SYST(1995, mw4pole, 0, 0, mw4pole, mw4pole, mw4pole_state, empty_init, "Waldorf Electronics", "MiniWorks 4-Pole", MACHINE_IS_SKELETON)
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@ -31736,6 +31736,9 @@ mvme162 // (c) 1993 Motorola
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18w // 653 (c) 1979 Midway
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18w2 // 653 (c) 1979 Midway
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@source:mw4pole.cpp
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mw4pole // (c) 1995 Waldorf Electronics GmbH Germany
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@source:mw8080bw.cpp
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280zzzap // 610 [1976]
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blueshrk // 742 [1978]
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@ -691,6 +691,7 @@ multi8.cpp
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mupid2.cpp
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mvme147.cpp
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mvme162.cpp
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mw4pole.cpp
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mx2178.cpp
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myb3k.cpp
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mycom.cpp
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