Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-10-06 09:00:04 +03:00
Code Issues Actions 3 Packages Projects Releases Wiki Activity

5% performance improvement for breakout from a single device. (nw)

Browse Source
This commit is contained in:
couriersud 2019-01-10 23:16:39 +01:00
parent 68f25519fd
commit f73eca0c7f
1 changed files with 46 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

65
src/lib/netlist/devices/nld_82S16.cpp
View File

@ -15,19 +15,55 @@ namespace netlist
NETLIB_OBJECT(82S16) NETLIB_OBJECT(82S16)
{ {
NETLIB_CONSTRUCTOR(82S16) NETLIB_CONSTRUCTOR(82S16)
, m_A(*this, {{"A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7" }}) , m_A(*this, {{"A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7" }}, NETLIB_DELEGATE(82S16, addr))
, m_CE1Q(*this, "CE1Q") , m_CE1Q(*this, "CE1Q", NETLIB_DELEGATE(82S16, enq))
, m_CE2Q(*this, "CE2Q") , m_CE2Q(*this, "CE2Q", NETLIB_DELEGATE(82S16, enq))
, m_CE3Q(*this, "CE3Q") , m_CE3Q(*this, "CE3Q", NETLIB_DELEGATE(82S16, enq))
, m_WEQ(*this, "WEQ") , m_WEQ(*this, "WEQ")
, m_DIN(*this, "DIN") , m_DIN(*this, "DIN")
, m_DOUTQ(*this, "DOUTQ") , m_DOUTQ(*this, "DOUTQ")
, m_ram(*this, "m_ram", 0) , m_ram(*this, "m_ram", 0)
, m_addr(*this, "m_addr", 0)
, m_enq(*this, "m_enq", 0)
{ {
} }
NETLIB_RESETI(); NETLIB_RESETI();
NETLIB_UPDATEI(); NETLIB_UPDATEI();
NETLIB_HANDLERI(addr)
{
uint8_t adr = 0;
for (std::size_t i=0; i<8; i++)
{
//m_A[i].activate();
adr |= (m_A[i]() << i);
}
m_addr = adr;
NETLIB_NAME(82S16)::update();
}
NETLIB_HANDLERI(enq)
{
const auto last = m_enq;
m_enq = m_CE1Q() || m_CE2Q() || m_CE3Q();
if (!last && m_enq)
{
// FIXME: Outputs are tristate. This needs to be properly implemented
m_DOUTQ.push(1, NLTIME_FROM_NS(20));
for (int i=0; i<8; i++)
m_A[i].inactivate();
m_WEQ.inactivate();
m_DIN.inactivate();
}
else if (last && !m_enq)
{
for (int i=0; i<8; i++)
m_A[i].activate();
m_WEQ.activate();
m_DIN.activate();
NETLIB_NAME(82S16)::update();
}
}
protected: protected:
object_array_t<logic_input_t, 8> m_A; object_array_t<logic_input_t, 8> m_A;
@ -39,6 +75,8 @@ namespace netlist
logic_output_t m_DOUTQ; logic_output_t m_DOUTQ;
state_var<uint64_t[4]> m_ram; // 256 bits state_var<uint64_t[4]> m_ram; // 256 bits
state_var_u8 m_addr; // 256 bits
state_var_sig m_enq;
}; };
NETLIB_OBJECT_DERIVED(82S16_dip, 82S16) NETLIB_OBJECT_DERIVED(82S16_dip, 82S16)
@ -69,22 +107,9 @@ namespace netlist
// FIXME: optimize device (separate address decoder!) // FIXME: optimize device (separate address decoder!)
NETLIB_UPDATE(82S16) NETLIB_UPDATE(82S16)
{ {
if (m_CE1Q() || m_CE2Q() || m_CE3Q()) if (!m_enq)
{ {
// FIXME: Outputs are tristate. This needs to be properly implemented const auto adr(m_addr);
m_DOUTQ.push(1, NLTIME_FROM_NS(20));
//for (int i=0; i<8; i++)
//m_A[i].inactivate();
}
else
{
unsigned int adr = 0;
for (std::size_t i=0; i<8; i++)
{
//m_A[i].activate();
adr |= (m_A[i]() << i);
}
if (!m_WEQ()) if (!m_WEQ())
{ {
m_ram[adr >> 6] = (m_ram[adr >> 6] m_ram[adr >> 6] = (m_ram[adr >> 6]
@ -101,6 +126,8 @@ namespace netlist
{ {
m_ram[i] = 0; m_ram[i] = 0;
} }
m_addr = 0;
m_enq = 0;
} }
NETLIB_DEVICE_IMPL_DEPRECATED(82S16) NETLIB_DEVICE_IMPL_DEPRECATED(82S16)